SPD5108 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1.1 Pin Assignments
  • 1.2 Pin Descriptions
  • 2.1 Device Standard
  • 2.2 Device Functional Diagram
  • 2.3 Device Power Up
  • 2.4 Device Reset and Initialization
  • 2.5 I2C and I3C Operation
  • 2.6 Device Interface - IO Voltage Configuration
  • 2.7 Management Bus Protocol
  • 2.8 HSA Pin Resistor Values and ID
  • 2.9 SPD5 Family Device - Write and Read Access
  • 2.10 Write Protection of Non-Volatile Memory (For SPD5 Family Devices Only)
  • 2.11 AC Timing Definition
  • 2.12 Parametric Characteristics
  • 3.1 Access Mechanism
  • 3.2 Registers

Features

  • SPD5 Hub Device
  • Two-wire programmable I2C or I3C Basic bus serial interface
  • Single device load on the Host bus
  • Up to 12.5MHz transfer rate
  • 1.8V power supply input
  • 1.0V LDO output at VIO pin; Optionally can take 1.0V input power supply on VIO pin
  • Supports 1.0V, 1.1V, 1.2V, and 1.8V Push-Pull IO levels Open-drain IO levels
  • 16 blocks of non-volatile memory; 64 bytes per block
  • Hub Function (a.k.a. Transparent Mode of operation) with 3 address bit translation
  • Integrated Temperature Sensor; 0.5°C Accuracy with 0.25°C resolution
  • Packet Error Check (PEC) Function
  • Parity Error Check Function
  • Bus Reset Function
  • Up to 8 unique addressing
  • Programmable I2C, I3C Basic Bus Addressing Scheme
  • In Band Interrupt (IBI) (Transparent Mode of Operation)
  • Write protection for each block of NVM
  • 9-pin thermally enhanced DFN package
  • Temperature: Industrial range of -40°C to 125°C

Figure 1. SPD5118 Block Diagram Table 1. Device Part Numbers and Feature

1.1 Pin Assignments

package size is 2.0mm x 3.0mm. The DFN package pinouts for SPD5118 and SPD5108 are shown in Figure 2. The pinouts are bottom view.

1.2 Pin Descriptions

Figure 2. 9 Pin Thermally Enhanced DFN Package Pinouts - Bottom View Table 2. Pin Description

6 VSS GND GND

3 HSCL I Host Bus - I2C/I3C Basic Input Clock

2 HSDA IO Host Bus - I2C/I3C Basic Data

8 HSA I Host Bus - I2C/I3C Basic Address Pin. See Table 98 for ID definition.

4 LSCL/RFU O Local Bus - I2C/I3C Basic Output Clock

1 LSDA/RFU IO LSDA - Local Bus - I2C/I3C Basic Data

7 VIO I/Power Connect minimum of 1.0µF capacitor for 1.0V LDO output to filter the noise. LDO is not used. External capacitor must be still present.

9 Thermal Pad, GND GND Connected to GND Plane

1.2.1 Pin Definitions

Table 3. Pin Definitions

5 VDDSPD Power Yes Yes

6 VSS GND Yes Yes

3 HSCL I Yes Yes

2 HSDA IO Yes Yes

8 HSA I Yes Yes

4 LSCL/RFU O LSCL LSCL

1 LSDA/RFU IO LSDA LSDA

7 VIO I/Power Yes Yes

9 Thermal Pad, GND GND Yes Yes

  1. Definition of SPD5118/5108 Hub Devices

2.1 Device Standard

a master host bus. The designations are SPD5118 and SPD5108. elimination of confusion, ease of device specification, and ease of use. for some uses and EE only for other uses. parts common in the industry.

2.2 Device Functional Diagram

2.2.1 SPD5 Hub Device

2.3 Device Power Up

The SPD5 device has one VDDSPD supply input and one optional VIO supply input. Figure 3. SPD5 Hub Device

2.3.1 SPD5 Hub Device

  1. Within t1.0V_Ready time, sense its VIO pin to determine if the SPD5 device has 1.0V input supply present. If not
  2. Within tSense_HSA time, sense its HSA pin to determine if SPD5 Hub device is in application environment or in

may optionally disable the HSA pin and associated sensing circuit.

  1. Enable I2C interface within tINIT time and be ready to receive the command from the host. The SPD5 Hub

device is ready for operation after tINIT time. HSCL signal is high and remains high with no leakage path or damage to the SPD Hub device. Figure 4. Device Power Up Sequence

2.3.2 DDR5 DIMM Power Up and Bus Readiness

Figure 5 and Figure 6 provide the holistic view of DDR5 RDIMM/LRDIMM power up as reference. Figure 5. DIMM Power and Bus Topology Figure 6. DIMM Power Sequence and Bus Interface Activity

SPD5108/SPD5118 Datasheet 2. Definition of SPD5118/5108 Hub Devices R10DS0299EU0111 Rev.1.11 Page 8 Sep 15, 2021

2.4 Device Reset and Initialization

At power down (phase during which VDDSPD input supply decreases continuously), as soon as VDDSPD input supply drops below the VDDSPDmin, the device does not guarantee the operation. On warm power cycling, the VDDSPD and VIO input supply must remain below VPOFF for tPOFF and must meet cold power on reset timing when restoring the power.

2.5 I2C and I3C Operation

At power on, by default, the SPD5 Hub device comes up in I2C mode of operation. Following applies in I2C mode: 1. The maximum operation speed is limited to 1MHz 2. In-band interrupts are not supported 3. Bus reset is supported. 4. Parity check is not supported except for supported CCCs. 5. Packet Error check is not supported. The SPD5 devices shall operate in the I2C mode until placed into I3C Basic mode via command. The host may put the SPD5 Hub device in I3C Basic mode by issuing SETAASA CCC. The following applies in I3C Basic mode: 1. The maximum operation speed is up to 12.5MHz 2. In-band interrupts are supported 3. Bus reset is supported. 4. Parity check is always enabled by default. 5. Packet error check is supported and by default is disabled.

2.6 Device Interface - IO Voltage Configuration

The SPD5 Hub device supports configurable Open Drain and Push Pull IO levels to accommodate broad range of DDR5 platform and applications.

2.6.1 Open Drain Interface with Internal On Die Pull-up Resistor

The configuration options shown in Figure 7 and Figure 8 are supported when device is in I2C mode or in I3C Basic mode. Figure 7 shows the SPD5 Hub device configuration options for Open Drain interface for both Host side and local side of the device. In this configuration, the SPD5 Hub device supports Open Drain IO levels on both Host and Local side. However, the IO voltage levels on Host side and Local side are independent and can be different. On Host side, the SPD5 device can support IO levels from 1.0 V to 3.3 V depending on the supply rail Host may have pulled up the resistor to. The host side pull-up resistor can be on motherboard or on die inside the host logic device. On local side, the SPD5 device can support IO levels from 1.0 V to 1.2V and is configurable through MR14[4:2]. For DDR5 DIMM application, DIMM vendor typically sets this register based on the DIMM design and the component selected on the local side of the interface. DIMM vendor also sets the MR14[5] = 0. If the VIO is applied externally, the level should be the same as the setting. If VIO is not applied on the board, the internal LDO of the SPD5 Hub device regulates the VIO output based on the setting of MR14[4:2]. The pull-up resistor selection is configurable and DIMM vendor also sets the register MR15 appropriately.

independent and can be different. internal pull-up connects to the VIO rail, and only works if the local side IO voltage setting is 000, 001, 010, or 011. The pull-up resistor selection is configurable and DIMM vendor also sets the register MR15 appropriately.

2.6.2 Open Drain Interface with External Pull-up Resistor

The configuration options shown in Figure 9 is supported when device is in I2C mode or in I3C Basic mode. side. However, the IO voltage levels on Host side and Local side are independent and can be different. On local side, the SPD5 device can support IO levels from 1.0V to 3.3V and is configurable through MR14 [4:2]. should be set to 1.8V. If VIO is not applied, it will be set to 1.8V internally. Figure 7. Open Drain Interface; On Die Pull-up to LDO Output Figure 8. Open Drain Interface; MR14[4:2] = 011

MR15 [7:0] is not applicable. The internal LDO of the SPD5 device regulation is design specific.

2.6.3 Push Pull Interface with Internal On Die Pull-up Resistor

The configuration option shown in Figure 10 is only supported when device is in I3C Basic mode. side. However, the IO voltage levels on Host side and Local side are independent and can be different. can be on motherboard or on die inside the host logic device.

2.7 Management Bus Protocol

Basic mode of operation identically.

2.7.1 Serial Address of the SPD5 Hub Device

The SPD5 Hub device type ID is 4-bit binary value of 1010b. Figure 9. Open Drain Interface; External On Board Pull-up Resistor Figure 10. Push Pull Interface; On Die Pull-up to LDO Output

  • If local OD IO voltage is higher than 1.8V, VIO just needs to set to 1.8V.

Table 4. For example, if the value sensed on HSA pin identifier 2 (010 binary), then the unique address for this

2.7.2 Serial Address of the Local Devices

PMIC local device type ID is 4-bit binary value of 1001b. the PMIC local device behind the SPD Hub has 7-bit address of 1001 111b.

2.7.3 Switch from I2C Mode to I3C Basic Mode

mode until put into I3C Basic mode via command. issue DEVCTRL and SETHID CCC first (if required) followed by SETAASA CCC. device as explained in Local Device Selection Through the SPD5 Hub Device (Before SETHID CCC). The Host puts the SPD5 Hub device in I3C mode by issuing SETAASA CCC.

2.7.4 Switch from I3C Basic Mode to I2C Mode

The Host can put the SPD5 Hub back in I2C mode from I3C Basic mode at any time by issuing RSTDAA CCC.

2.7.5 SPD5 Hub Device Selection

bits represent the HID bits. Table 4. 7-Bit Address of the SPD5 Hub Device Table 5. 7-Bit Address of the Local Devices (e.g. PMIC Device)

2.7.6 Local Device Selection Through the SPD5 Hub Device (Before SETHID CCC)

behind SPD5 Hub on each DIMM. HID bits as anything other than 111 which is not a valid code as shown in Table 5.

  1. Host issues Start followed by 7’h7E with W = 0 (or Host issues Start followed by 0xFC).
  2. After SPD5 Hub executes SETHID CCC command that Host issues. See Local Device Selection Through the

SPD5 Hub Device (After SETHID CCC). Table 6. 7-Bit Address of Each Hub Devices on I2C/I3C Basic Bus Table 7. 7-Bit Address of Local Devices on I2C/I3C Basic Bus

2.7.7 Local Device Selection Through the SPD5 Hub Device (After SETHID CCC)

sends SETHID CCC, the Host still accesses all the slave devices behind the SPD5 Hub as shown in Table 7. device before or after SETHID CCC.

2.7.8 I2C Slave Protocol - Host to SPD5 Hub Device

conditions when it may passively assert a NACK. NACKs the subsequent write or read operation if MemReg = 1 and sets the MR52 [7] = 1. busy with internal write operation to non-volatile memory. Figure 12. Example: Host Accessing Temperature Sensor 0 on DIMM 3

volatile register MR11 [2:0] to address the entire 1024 bytes of non-volatile memory.

2.7.8.1 Write Operation - Data Packet

treated simply Upper Address bits. Table 8. Write Command Data Packet; MR11 [3] = 0

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any other

operation including another Repeat Start is considered an illegal operation.

  1. All write transactions to NVM location (MemReg = 1) shall terminate with STOP operation (i.e. no Repeat Start is allowed for NVM

Table 9. Write Command Data Packet; MR11 [3] = 1

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

  1. The memory size of SPD hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  2. All write transactions to NVM location (MemReg = 1) shall terminate with STOP operation (i.e. no Repeat Start is allowed for NVM

2.7.8.2 Read Operation - Data Packet

treated simply Upper Address bits.

2.7.8.3 Default Read Address Pointer Mode

default read address pointer mode is only applicable to volatile register space (i.e. MemReg = 0). Table 10. Read Command Data Packet; MR11 [3] = 0

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any other

operation including another Repeat Start is considered an illegal operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

Table 11. Read Command Data Packet; MR11 [3] = 1

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

  1. The memory size of SPD hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  2. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

The Default Read Address Pointer mode can be used in conjunction with other normal Write and Read operation. followed by read and read followed by write transactions. the device returns the data from where the previous address pointer was left which is at address 0x18. Table 14 gives an example of write followed by Stop operation followed by a read transaction with Start operation. STOP operation as default read address pointer mode is enabled, it returns the data from address 0x08. Table 12. Read Command Data Packet with Default Address Pointer Mode Table 13. Write Command followed by Read Command Data Packet Table 14. Write Command followed by Read Command Data Packet

previous address pointer was left which is at address 0x17. Table 17 gives an example of default read pointer mode followed repeat start operation followed read operation. from the address 0x0A, 0x0B. Table 15. Read Command followed by Read Command Data Packet Table 16. Read Command followed by Default Read Pointer Mode Command Data Packet Table 17. Read Command followed by Read Command Data Packet

0x34. The host then performs Stop operation.

2.7.9 I2C Slave Protocol - Host to Local Device Through SPD5 Hub Device

2.7.9.1 Write Operation - Data Packet

Table 18. Consecutive Default Read Pointer Mode Command Data Packets Table 19. Write Command Data Packet (e.g. TS0)

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

stable input clock (DCK_t, DCK_c), Reset_n and DCS_n to allow any read or write access on its I2C interface. Table 20. Write Command Data Packet (e.g. PMIC)

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation. Table 21. Write Command Data Packet (e.g. RCD; PEC Disabled)

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

2.7.9.2 Read Operation - Data Packet

Table 22. Write Command Data Packet (e.g. RCD; PEC Enabled)

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation. Table 23. Read Command Data Packet (e.g. TS0)

  1. In I2C mode, Start or Repeat Start operation followed by 7’h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

like any other data. The SPD Hub device does not check for the PEC. Table 24. Read Command Data Packet (e.g. PMIC)

  1. In I2C mode, Start or Repeat Start operation followed by 7’7h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

  1. If slave device NACKs during Repeat Start for any reason, the host my retry Repeat Start again. The host can do the Repeat Start as

Table 25. Read Command Data Packet (e.g. RCD; PEC Disabled; Legacy Format)

  1. In I2C mode, Start or Repeat Start operation followed by 7’7h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

Table 26. Read Command Data Packet (e.g. RCD; PEC Enabled; Legacy Format)

  1. In I2C mode, Start or Repeat Start operation followed by 7’7h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

2.7.10 I3C Basic Slave Protocol - Host to SPD5 Hub Device

2.7.10.1 Write Operation Data Packet

conditions when it may passively assert a NACK. The T bit carries Parity information from the Host for each byte. to do the read operation with Repeat Start, the SPD5 Hub device NACKs. busy with internal write operation to non-volatile memory. The Packet Error Code (PEC) function is disabled by default when the SPD5 Hub device is put in I3C Basic mode. CMD field. In other words, the host must not interrupt the burst length prematurely for Write operation. treated simply Upper Address bits. Table 27. Read Command Data Packet (e.g. RCD; PEC Disabled; Optimized Format)

  1. In I2C mode, Start or Repeat Start operation followed by 7’7h7E with W = 0 is only allowed for CCCs that are allowed in I2C mode. Any

other operation including another Repeat Start is considered an illegal operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

PEC calculation does not include IBI header byte (7’h7E followed by W = 0). Table 28. Write Command Data Packet; PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD5 Hub device ignores Blk Addr [4] bit.
  2. Repeat Start or Repeat Start with 7’h7E.
  3. All write transactions to NVM location (MemReg = 1) shall terminate with STOP operation (i.e. no Repeat Start is allowed for NVM

Table 29. Write Command Data Packet; PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity error or PEC error in a previous transaction when host performs consecutive transactions with
  3. The SPD5 Hub device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued
  4. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD5 Hub device ignores Blk Addr [4] bit.
  5. Repeat Start or Repeat Start with 7’h7E.
  6. All write transactions to NVM location (MemReg = 1) shall terminate with STOP operation (i.e. no Repeat Start is allowed for NVM

Table 30. Write Command Data Packet with IBI Header; PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (Repeat Start).
  2. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK) and Figure 13 shows how the

transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD5 Hub device ignores Blk Addr [4] bit.
  2. Repeat Start or Repeat Start with 7’h7E.
  3. All write transactions to NVM location (MemReg = 1) shall terminate with STOP operation (i.e. no Repeat Start is allowed for NVM

2.7.10.2 Read Operation Data Packet

SPD5 Hub device to Host indicating Continuous (1) or Stop (0) whether it is transmitting the last byte or not. The Packet Error Code (PEC) function is disabled by default when SPD5 Hub device is put in I3C Basic mode. treated simply Upper Address bits. Table 31. Write Command Data Packet with IBI Header; PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (Repeat Start).
  2. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK) and Figure 13 shows how the

transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).

  1. The SPD5 Hub NACKs if there is a parity error or PEC error in a previous transaction when host performs consecutive transactions with
  2. The SPD5 Hub device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued
  3. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD5 Hub device ignores Blk Addr [4] bit.
  4. Repeat Start or Repeat Start with 7’h7E.
  5. All write transactions to NVM location (MemReg = 1) shall terminate with STOP operation (i.e. no Repeat Start is allowed for NVM

Table 32. Read Command Data Packet; PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. The memory size of SPD hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  2. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

the Host tries Repeat Start. If there were no parity errors, the SPD Hub may eventually ACK.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 16 shows how the Host ends slave device operation.

the operation followed by Host STOP operation.

  1. Repeat Start or Repeat Start with 7’h7E.

PEC calculation (from Host to SPD5 Hub) does not include IBI header byte (7’h7E followed by W = 0). Table 33. Read Command Data Packet; PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. The SPD5 Hub device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued
  4. The memory size of SPD Hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  5. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

calculation and all other NACK responses of the device select code of the Repeat Start are not included in PEC calculation.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.
  3. Repeat Start or Repeat Start with 7’h7E.

Table 34. Read Command Data Packet with IBI Header; PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (Repeat Start).
  2. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK) and Figure 13 shows how the

transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. The memory size of SPD Hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  2. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  3. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

the Host tries Repeat Start. If there were no parity errors, the SPD Hub may eventually ACK.

  1. Figure 16 shows how the Host ends slave device operation.

the operation followed by Host STOP operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 35. Read Command Data Packet with IBI Header; PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (Repeat Start).
  2. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK) and Figure 13 shows how the

transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. The SPD5 Hub device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued
  3. The memory size of SPD Hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  4. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  5. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

calculation and all other NACK responses of the device select code of the Repeat Start are not included in PEC calculation.

  1. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.
  2. Repeat Start or Repeat Start with 7’h7E.

2.7.10.3 Default Read Address Pointer Mode

pointer mode is only applicable to volatile register space (i.e. MemReg = 0). Table 36. Read Command Data Packet with Read Address Pointer Mode; PEC Disabled

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. Figure 16 shows how the Host ends slave device operation.
  3. When last byte (i.e. MR255) is reached (extreme rare case), the slave device sends T = 0. Figure 17 shows how the slave device ends

the operation followed by Host STOP operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 37. Read Command Data Packet with Read Address Pointer Mode; PEC Enabled

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. Figure 17 shows how the slave device ends the operation followed by STOP operation
  3. Repeat Start or Repeat Start with 7’h7E.

2.7.11 I3C Basic Slave Protocol - Host to Local Device (Through SPD5 Hub Device)

2.7.11.1 Write Operation - Data Packet

devices behind SPD5 Hub device also supports the IBI header byte similar to as shown in Table 30 and Table 31. See the device specific datasheet. Table 38. Read CMD Data Packet with Read Address Pointer Mode and IBI Header; PEC Disabled

  1. Figures 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (Repeat Start).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  4. Figure 16 shows how the Host ends slave device operation.
  5. When last byte (i.e. MR255) is reached (extreme rare case), the slave device sends T = 0. Figure 17 shows how the slave device ends

the operation followed by Host STOP operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 39. Read CMD Data Packet with Read Address Pointer Mode and IBI Header; PEC Enabled

  1. Figures 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (Repeat Start).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  4. Figure 17 shows how the slave device ends the operation followed by STOP operation
  5. Repeat Start or Repeat Start with 7’h7E.

Table 40. Write Command Data Packet (e.g. TS); PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr; bit [7]).
  2. The NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The TS device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the host

does not match with its own device code. The TS device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 41. Write Command Data Packet (e.g. TS); PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr, bit [7]).
  2. The NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The TS device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The TS device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 42. Write Command Data Packet (e.g. PMIC); PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr, bit [7]).
  2. The NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The TS device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The TS device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 43. Write Command Data Packet (e.g. PMIC); PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr, bit [7]).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions Repeat
  3. The PMIC device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued by

the host does not match with its own device code. The PMIC device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 44. Write Command Data Packet (e.g. RCD); PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Data, bit [7]).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The RCD device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the host

does not match with its own device code. The RCD device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

2.7.11.2 Read Operation - Data Packet

devices behind SPD5 Hub device also supports the IBI header byte similar to as shown in Table 34 and Table 35. Refer the device specific data sheet. Table 45. Write Command Data Packet (e.g. RCD); PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Data, bit [7]).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. The RCD device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued by

the host does not match with its own device code. The RCD device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 46. Read Command Data Packet (e.g. TS); PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr, bit [7]).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The TS device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the host

does not match with its own device code. The TS device ignores the entire packet until STOP or next Repeat Start operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

the Host tries Repeat Start. If there were no parity errors, the device may eventually ACK.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 16 shows how the Host ends slave device operation.
  3. For volatile register access, when last byte (MR TBD from TS Spec) is reached (extreme rare case), the slave device sends T = 0.

Figure 17 shows how the Host ends slave device operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 47. Read Command Data Packet (e.g. TS); PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr, bit [7]).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. The TS device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The TS device ignores the entire packet until STOP or next Repeat Start operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

calculation and all other NACK responses of the device select code of the Repeat Start are not included in PEC calculation.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.
  3. Repeat Start or Repeat Start with 7’h7E.

Table 48. Read Command Data Packet (e.g. PMIC); PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr, bit [7]).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The PMIC device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the host

does not match with its own device code. The PMIC device ignores the entire packet until STOP or next Repeat Start operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

the Host tries Repeat Start. If there were no parity errors, the device may eventually ACK.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 16 shows how the Host ends slave device operation.
  3. For volatile register access, when last byte is reached within the region (either Host region or DIMM Vendor region), it will continue to

address counter reaches R255, it resets to address R00 and it continues to return the data. Only Host can perform the STOP operation.

  1. Repeat Start or Repeat Start with 7’h7E.

allow any read or write access on its I3C interface. Table 49. Read Command Data Packet (e.g. PMIC); PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Addr, bit [7]).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. The PMIC device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued by

the host does not match with its own device code. The PMIC device ignores the entire packet until STOP or next Repeat Start operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

calculation and all other NACK responses of the device select code of the Repeat Start are not included in PEC calculation.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.
  3. Repeat Start or Repeat Start with 7’h7E.

Table 50. Read Command Data Packet (e.g. RCD); PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Data).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The RCD device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the host

does not match with its own device code. The RCD device ignores the entire packet until STOP or next Repeat Start operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

the Host tries Repeat Start. If there were no parity errors, the device may eventually ACK.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.
  3. Repeat Start or Repeat Start with 7’h7E.

Table 51. Read Command Data Packet (e.g. RCD); PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (1st bit of Data).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. The RCD device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the host

does not match with its own device code. The RCD device ignores the entire packet until STOP or next Repeat Start operation.

  1. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

all other NACK responses of the device select code of the Repeat Start are not included in PEC calculation.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.
  3. Repeat Start or Repeat Start with 7’h7E.

Figure 15. Master Push Pull to Slave Open Drain Hand Off Operation

SPD5108/SPD5118 Datasheet 2. Definition of SPD5118/5108 Hub Devices R10DS0299EU0111 Rev.1.11 Page 44 Sep 15, 2021

2.7.12 In Band Interrupt (IBI)

In I2C mode, in band interrupt function is not supported. Only I3C Basic mode supports in band interrupt function.

2.7.12.1 Enabling and Disabling In Band Event Interrupt Function

By default, all interrupt sources are disabled (i.e. set to 0). The host may enable following interrupts in the SPD5 Hub device. Once enabled, the SPD5 Hub device sends an IBI when that event occurs. 1. Error Interrupt Enable in MR27 [4]: a. When MR27 [4] = 1, the device sends the IBI at next available opportunity when any of the register bit in MR52 [7:5, 1:0] is set to 1 and sets MR48 [7] = 1 and updates Pending Interrupt Bits [3:0] = 0001 for GETSTATUS CCC. b. When MR27 [4] = 0, the device does not send the IBI regardless of the register bit status in MR52 [7:5, 1:0]. However, the device does set MR48 [7] = 1 and updates Pending Interrupt Bits [3:0] = 0001 for GETSTATUS CCC. 2. Temp Sensor Interrupt Enable in MR27 [3:0]: The host can set any combination of register bits to 1. a. When any of the register bits in MR27 [3:0] = 1 and if MR27 [4] = 1, the device sends the IBI at next available opportunity when the corresponding register bit in MR51 [3:0] is set to 1 and sets MR48 [7] = 1 and updates Pending Interrupt Bits [3:0] = 0001 for GETSTATUS CCC. b. When any of the register bits in MR27 [3:0] = 0 or MR27 [4] = 0, the device does not send the interrupt regardless of the corresponding register bit status in MR51 [3:0]. However, the device does set MR48 [7] = 1 and updates Pending Interrupt Bits [3:0] = 0001 for GETSTATUS CCC if any of the bits in MR27 [3:0] = 1 and MR27 [4] = 0.

2.7.12.2 Mechanics of Interrupt Generation - SPD5 Hub Device

Event interrupts may be generated by the SPD5 Hub device if IBI is enabled. When there is a pending interrupt (i.e.MR48 [7] = 1 and MR27 [4] = 1), the SPD5 Hub requests an interrupt after detecting START condition by transmitting its 7-bit binary address (LID bits followed by HID bits) followed by R/W = 1 on the SDA bus serially (synchronized by SCL falling transitions). If the SPD5 Hub detects no START condition but if the Host to the SPD5 Hub device bus (HSDA and HSCL) has been inactive (no edges seen) for tAVAL period, then the SPD5 Hub device may assert HSDA low by tIBI_ISSUE time to request an interrupt. When the SPD5 Hub device requests an interrupt, the Host toggles the HSCL. The SPD5 Hub device transmits its 7-bit binary address; 1010 followed by 3 HID bits and then sets the R/W bit = 1. When the SPD5 Hub device requests an interrupt, the host may take one of the following two actions:

  • The Host sends ACK on 9th bit to accept the interrupt request. At this point, if the SPD5 Hub confirms that it has won the arbitration, the SPD5 Hub device transmits the IBI payload as shown in Table 52 and Table 53 for PEC disabled and PEC enabled configuration respectively. See Figure 18. Figure 18 just shows only first two data bits of the first payload byte (MDB Byte) to illustrate the timing. The interrupt payload contains MDB followed by MR51 and MR52 in order. The host then issues the STOP command. Note The timing waveform in Figure 18. The host then accepts the IBI payload if it sends an ACK on 9th bit to accept the interrupt request. The host can interrupt the IBI payload at T. If host stops the IBI payload at T bit in the middle of payload, the SPD5 Hub device retains the IBI status flag MR48 [7] = 1 and Pending Interrupt Bits [3:0] internally and waits for the next opportunity to request an interrupt. If the SPD5 Hub device successfully transmits the entire IBI payload, it then clears IBI status flag MR48 [7] = 0 and Pending Interrupt Bits [3:0] = 0000 on its own and does not request for an IBI again unless there is another different event occurs; for another same event, the device does not request for an IBI.
  • The Host sends NACK on the 9th bit as shown in Figure 19 followed by a STOP command. In this case, the SPD5 Hub device does not transmit the IBI payload and waits for the next opportunity to request an interrupt. At this point, though Host sent an NACK, it does have a knowledge of which SPD5 Hub device sent the IBI request. The SPD5 Hub retains the IBI status flag MR48 [7] = 1 and Pending Interrupt Bits [3:0] = 0001.

2.7.12.3 Mechanics of Interrupt Generation - Local Slave Device

(synchronized by SCL falling transitions). Figure 20 bottom waveform. The SPD5 Hub device forwards the R/W bit = 1 to the Host.

  • The Host sends ACK on 9th bit to accept the interrupt request. At this point, if the local device confirms that it has won the arbitration, the local device transmits the IBI payload as shown in Table 54 and Table 55 for PEC disabled and PEC enabled configuration respectively. See Figure 20. Figure 20 just shows only first two data bits of the first payload byte (MDB Byte) to illustrate the timing. The interrupt payload contains MDB Byte followed by appropriate slave device error register contents. The host then issues the STOP command. Note the timing waveform in Figure 20. The host then accepts the IBI payload if it sends an ACK on 9th bit to accept the interrupt request. The host can interrupt the IBI payload at T bit. If host stops the IBI payload at T bit in the middle of payload, the local device retains the IBI status flag and Pending Interrupt Bits [3:0] internally and waits for the next opportunity to request an interrupt. If the local device successfully transmits the entire IBI payload, it then clears IBI status flag and Pending Interrupt Bits [3:0] = 0000 on its own and does not request for an IBI again unless there is another different event occurs; for another same event, the device does not request for an IBI.
  • The Host sends NACK on the 9th bit as shown in Figure 21 followed by a STOP command. In this case, the local device does not transmit the IBI payload and waits for the next opportunity to request an interrupt. At this point, though Host sent an NACK, it does have a knowledge of which local device sent the IBI request. The local device retains the IBI status flag and Pending Interrupt Bits [3:0] = 0001.

Table 54. Slave Device IBI Payload Packet; PEC is Disabled

  1. Figure 14 shows how the transition occurs from Host Open Drain (ACK) to Slave Push Pull Operation (1st bit of Byte bit [7]).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.

Table 55. Slave Device IBI Payload Packet; PEC is Enabled

  1. Figure 14 shows how the transition occurs from Host Open Drain (ACK) to Slave Push Pull Operation (1st bit of Byte bit [7]).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.

Figure 20. Local Device Interrupt, Host Ack Followed by Slave Device IBI Payload

2.7.12.4 Interrupt Arbitration; SETHID CCC is Not Issued By Host;

based on the HID code for the SPD5 Hub device. Figure 21. Local Device Interrupt; Host NACK Followed by STOP

14 local devices behind the SPD5 Hub. devices that will be on a standard DDR5 RDIMM or DDR5 LRDIMM. The Olive color cells in Table 57 do not apply. time that it receives from the local slave devices to the Host. it won the arbitration. See Figure 22. Table 56. Interrupt Arbitration - Among SPD5 Hub Devices Figure 22. SPD5 Hub Function During Arbitration from Local Slave Device

Hub. There are up to 13 local devices behind each SPD5 Hub. has the lowest priority for winning the interrupt arbitration. process. The HID code for that lowest LID code represents the SPD5 Hub device code. among all devices (either SPD Hub device or local slave devices) during the arbitration phase. Example 1: There are total 5 devices (4 local slave devices and 1 Hub device) that are requesting an interrupt. LID code of 0010 is the lowest among three other local slave device code and its HID code is 111. Example 2: There are total 4 devices (2 local slave devices and 2 Hub device) that are requesting an interrupt. Table 57. Interrupt Arbitration - Among Local Slave Devices

LID code of 1001 is the lowest among one other local slave device code and its HID code is 100. Example 3: There are total of 3 devices (2 local slave devices and 1 Hub device) that are requesting an interrupt. because LID code 1010 is lower than two other local slave device code and its HID code is 000. Among Local Slave Devices behind one SPD5 Hub Devices section. Figure 23. Arbitration Between Two Local Identical Slave Devices

device waits for next opportunity to send an interrupt.

  • Host sends an ACK to accept the interrupt and hence accepts the IBI payload from the winning Hub or local slave device. After the IBI payload, the host issues STOP operation.
  • Host sends an NACK followed by STOP operation.

Table 58. Interrupt Arbitration - Among Local Slave and SPD5 Hub Devices

SPD5108/SPD5118 Datasheet 2. Definition of SPD5118/5108 Hub Devices R10DS0299EU0111 Rev.1.11 Page 53 Sep 15, 2021 In a rare but still possible scenario would be that at the exact same time as when the Hub or local slave device is requesting an interrupt, the host is starting an operation to that same exact hub or local slave devices. When this happens, neither Host or nor the hub or local slave device knows it is a winner until the 8th bit and Host always wins. This is because, the hub or local slave device sends R = 1 (8th bit) during the interrupt. The host sets W = 0 (8th bit) during the operation. As a result, the host wins and the hub or slave device must let go of the bus and wait for the next opportunity to send an interrupt. This is shown as example 3 in Table 59. The Table 59 shows three examples. In each example, the Host is targeting an operation to the device cod. The slave LID code column represent local slave device behind hub which has HID code value of 111; the Hub HID code column represents the SPD5 Hub device which has LID code of 1010 followed by its own unique HID code; the winning device column represent the final winner among all devices (either Host or SPD Hub device or local slave devices) during the arbitration phase. In example 1, there are total of 5 devices (1 Hub device and 4 local slave devices) are requesting an interrupt at exactly same time as when the Host is starting an operation to hub device on DIMM 3 (1010 011). The winning device is local slave device 0010 111 because it has the lower 4-bit LID code. In example 2, there are total of 4 devices (2 Hub devices 2 local slave devices) are requesting an interrupt at exactly same time as when the Host is requesting an operation to the local slave device on DIMM5 (0110 101). The host is the winner because its intended target device has the lower 4-bit LID code than devices that are requesting an interrupt. In example 3, there are is one 1 hub device on DIMM 2 is requesting an interrupt at exactly the same time as when Host is requesting an operation to the same exact Hub device on DIMM2. In this case, the host is the winner because the 8-bit will be driven low by the Host (W = 0) while the Hub device drives it high (R = 1) during the interrupt. In an extreme rare but still possible scenario would be that at the exact same time as when the Hub or local slave device is requesting an interrupt, the host is requesting a read operation with default read address pointer mode to the same exact hub or local slave device. When this happens, there is no winning device. This is the only time there is no winning device. This is because, the hub or local slave device sends R = 1 (8th bit) during the interrupt and Host also sends R = 1 for read request with default read address pointer mode. As a result, there is no winner because all devices, i.e. the Host or the hub or the local slave device, is waiting for other device to ACK. In this case, no device will ACK. Since there is no ACK by any device, the Host must time out and repeats the read request with Repeat Start. When it repeats the read request with Repeat Start, the hub or local slave device does not send an interrupt because it sees Repeat Start.

2.7.12.5 Interrupt Arbitration; SETHID CCC is Issued by Host;

has the same 3-bit HID code. back to the local device interface. devices on the DIMM has same 3-bit HID code. Table 59. Interrupt Arbitration -Best Host and Local Slave and SPD5 Hub Devices

010 Host

101 Host

SPD5108/SPD5118 Datasheet 2. Definition of SPD5118/5108 Hub Devices R10DS0299EU0111 Rev.1.11 Page 55 Sep 15, 2021 Interrupt Arbitration - Between Host and All Devices In an uncommon but possible scenario would be that at the exact same time as when the slave device is requesting an interrupt, the host is starting an operation to the slave device. When this happens, Host also gets involved in the arbitration process along with the slave devices. During the arbitration phase, there will be always only one winning device and it could be either Host or the slave device. If the host wins during the arbitration phase, it continues with normal operation. The losing slave device waits for next opportunity to send an interrupt. If the host lose during the arbitration phase, it host must let go of the bus. When Host looses during the arbitration, the host must let the slave device finish sending their 4-bit LID code followed by 3-bit HID code followed by R/W = 1. At this point, during the 9th bit, the host has two options to take the action as noted:

  • Host sends an ACK to accept the interrupt and hence accepts the IBI payload from the winning slave device. After the IBI payload, the host issues STOP operation.
  • Host sends an NACK followed by STOP operation. In a rare but still possible scenario would be that at the exact same time as when the SPD5 Hub device is requesting an interrupt, the host is starting an operation to that same SPD5 Hub device. When this happens, neither Host or nor the SPD5 Hub device knows it is a winner until the 8th bit and Host always wins. This is because, the SPD5 hub device sends R = 1 (8th bit) during the interrupt. The host sets W = 0 (8th bit) during the operation. As a result, the host wins and the SPD5 Hub device must let go of the bus and wait for the next opportunity to send an interrupt. In an extreme rare but still possible scenario would be that at the exact same time as when the SPD5 Hub device is requesting an interrupt, the host is requesting a read operation with default read address pointer mode to the SPD5 Hub device. When this happens, there is no winning device. This is the only time there is no winning device. This is because, the SPD5 Hub device sends R = 1 (8th bit) during the interrupt and Host also sends R = 1 for read request with default read address pointer mode. As a result, there is no winner because all devices, i.e. the Host or the SPD5 Hub device, is waiting for other device to ACK. In this case, no device will ACK. Since there is no ACK by any device, the Host must time out and repeats the read request with Repeat Start. When it repeats the read request with Repeat Start, the SPD5 Hub device does not send an interrupt because it sees Repeat Start.

2.7.12.6 Clearing Device Status and IBI Status Registers

The SPD5 Hub device provides the IBI status in MR48 [7] by setting it to 1. The SPD5 Hub device clears the IBI status register MR48 [7] to 0 automatically when it sends a complete IBI (including payload and without interruption) and it also clears Pending Interrupt Bits [3:0] to 0000. Once IBI status register is cleared, the SPD5 Hub does not request for an IBI again unless another event occurs. The SPD5 Hub device provides the device status in MR51 and MR52 registers. The status information in MR51 and MR52 are latched and remains set even after the SPD5 Hub device sends IBI payload and clears the IBI status register MR48 [7] to 0. The host must explicitly clear the status register through Clear command by writing 1 for appropriate status or by issuing a Global clear command. After Host issues clear command, if the condition is no longer present, the SPD5 Hub device clears the appropriate status register, clears the IBI status register to 0 and Pending Interrupt Bits [3:0] to 0000 even if the SPD5 Hub device has not sent the IBI. After Host issues clear command, if the condition is still present, the device will again set the appropriate status register, sets the IBI status register to 1 and Pending Interrupt Bits [3:0] to 0001 even if the device has already sent the IBI and entire IBI payload.

2.7.13 Packet Error Check (PEC) Function

In I2C mode, packet error checking is not supported. Only I3C Basic mode supports packet error checking. The SPD5 Hub device implements an 8-bit Packet Error Code (PEC) which is appended at the end of all transactions if PECs is enabled through DEVCTRL CCC or by directly writing 1 to MR18 [7]. The PEC is a CRC-8

ACK and NACK and IBI header (7’h7E followed by W = 0) bits. The seed value for PEC function is all zero. When Host calculates PEC for SPD5 Hub device, it includes LID and HID bits followed by R/W bit.

2.7.14 Parity Error Check Function

drive static low or high in T bit.

2.7.15 Packet Error Check and Parity Error Handling

error is calculated for each byte. The host sends parity error information in T bit. supported by the SPD5 Hub for parity checking. All other errors are not supported and not applicable.

2.7.15.1 Write Command Data Packet Error Handling - PEC Disabled

that it receives from the host as shown in Table 60. Table 60. Write Command Data Packet; PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  2. Repeat Start or Repeat Start with 7’h7E.
  • The SPD5 Hub device executes the command. Write command - if parity error:
  • The SPD5 Hub device discards the byte in the packet that had a parity error.
  • The SPD5 Hub device discards all subsequent bytes in that packet until the STOP operation. The SPD5 Hub device may or may not check parity for all sub-sequent bytes in that packet.
  • Note that as the packet contains more than one byte, if first byte had no parity error but the second byte had a parity error, the SPD5 Hub device may or may not execute the first byte operation but second byte and all subsequent bytes operations are discarded.
  • The SPD5 Hub device sets the MR52 [0], MR48 [7] and P_Err in GETSTATUS CCC to 1; updates Pending Interrupt Bits [3:0] to 0001 and waits for the next opportunity to send an in band interrupt if IBI is enabled.

2.7.15.2 Read Command Data Packet Error Handling - PEC Disabled

it receives from the host prior to Repeat Start as shown in Table 61.

  • The SPD5 Hub sends ACK back to the host when Host perform Start Repeat operation.
  • The SPD5 Hub device executes the command and sends the data as shown in Table 61.

Table 61. Read Command Data Packet; PEC Disabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  3. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  2. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

the Host tries Repeat Start. If there were no parity errors, the device may eventually ACK.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 16 shows how the Host ends slave device operation.

ends slave device operation.

  1. Repeat Start or Repeat Start with 7’h7E.
  • The SPD5 Hub device discards the byte in the packet that had a parity error.
  • The SPD5 Hub device discards second byte in that packet if the parity error occurred in first byte. The SPD5 Hub device may or may not check the parity for second byte in that packet.
  • The SPD5 Hub sends NACK back to the host when Host performs a Start Repeat operation. This is shown in the RED color cell in Table 61. The NACK represents either a parity error in one of the two bytes or that SPD5 Hub is not able to start the read operation. The host may re-try Repeat Start again. The host may do the Repeat Start as many times as it may desire. If the SPD5 Hub device NACKs due to parity error in a previous byte from the host, it will always NACK regardless of how many times host tries Repeat Start.
  • The SPD5 Hub does not send the data shown in Table 61 and instead expects Host to perform STOP operation.
  • The SPD5 Hub device sets MR52 [0] and MR48 [7] and P_Err in GETSTATUS CCC to 1; updates Pending Interrupt Bits [3:0] to 0001 and waits for the next opportunity to send an in band interrupt if IBI is enabled.

2.7.15.3 Write Command Data Packet Error Handling - PEC Enabled

the entire packet (from Start condition until last byte of Data) that it receives from the host as shown in Table 62.

  • The SPD5 Hub device waits for the entire packet. If no error in packet, the SPD5 Hub device executes the command. If there is an error in the packet, the SPD5 Hub device discards the entire packet and does not execute that packet and waits for STOP, sets the MR52 [1] and MR48 [7] to 1 and PEC_Err in GETSTATUS CCC to 1; updates Pending Interrupt Bits [3:0] to 0001 in GETSTATUS CCC and waits for the next opportunity to send in band interrupt if IBI is enabled. Write command - if parity error:
  • The SPD5 Hub device discards that byte and the entire packet until STOP operation.

Table 62. Write Command Data Packet; PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. The SPD5 Hub device does not check for parity or PEC errors in subsequent bytes when it determines the 7-bit device select code issued
  4. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD Hub device ignores Blk Addr [4] bit.
  5. Repeat Start or Repeat Start with 7’h7E.
  • The SPD5 Hub device sets MR52 [0] and MR48 [7] and P_Err in GETSTATUS CCC to 1; updates Pending Interrupt Bits [3:0] in GETSTATUS CCC to 0001 and waits for the next opportunity to send in band interrupt if IBI is enabled.
  • The SPD5 Hub device may or may not check the error for the packet. If the SPD5 Hub device checks for the packet error, likely it will detect an error in the packet and the device may also set MR52 [1] and PEC_Err in GETSTATUS CCC to 1 as well.

2.7.15.4 Read Command Data Packet Error Handling - PEC Enabled

that it receives from the host prior to Repeat Start as shown in Table 63. during T bit when SPD5 Hub device is sending the read data. Repeat Start condition (from first device select code followed by the address offset and CMD byte). Table 63. Read Command Data Packet; PEC Enabled

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation (MemReg bit).
  2. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  3. The SPD5 Hub device does not check for parity or PEC errors in subsequent bytes when it determines the 7-bit device select code issued
  4. The memory size of SPD5 Hub device is limited to 1024 Bytes. SPD5 Hub device ignores Blk Addr [4] bit.
  5. If slave device NACKs during Repeat Start for any reason, the host may retry Repeat Start again. The host can do the Repeat Start as

calculation and all other NACK responses of the device select code of the Repeat Start are not included in PEC calculation.

  1. Figure 15 shows how the transition occurs from Host Push Pull Operation to Slave Open Drain (ACK).
  2. Figure 17 shows how the slave device ends the operation followed by Host STOP operation.
  3. Repeat Start or Repeat Start with 7’h7E.

SPD5108/SPD5118 Datasheet 2. Definition of SPD5118/5108 Hub Devices R10DS0299EU0111 Rev.1.11 Page 60 Sep 15, 2021 Read command - If no parity error and no PEC error:

  • The SPD5 Hub sends ACK back to the host when Host perform a Start Repeat operation.
  • The SPD5 Hub device executes the command and sends the data as shown in Table 63.
  • The SPD5 Hub computes PEC for the bytes shown in Table 63. Read command - if parity error or PEC error:
  • The SPD5 Hub device discards the byte in the packet that had a parity error.
  • The SPD5 Hub device discards second byte in that packet if a parity error occurred in first byte. The SPD5 Hub device may or may not check parity for the second byte in that packet.
  • The SPD5 Hub device discards the packet if there is a PEC error.
  • The SPD5 Hub sends NACK back to the host when Host perform Start Repeat operation. This is shown in the RED color cell in Table 63. The NACK represents either PEC error or a parity error in one of the three bytes or that SPD5 Hub is not able to start the read operation. The host may re-try Repeat Start again. The host may do the Repeat Start as many times as required. The PEC calculation by SPD5 Hub device only includes device select code of the ACK responses of the Repeat Start operation. In other words, if there are more than one Repeat Start operation, the SPD5 Hub device includes the device select of only the last Repeat Start from the Host when it ACKs in PEC calculation and other NACK responses of the device select codes of the Repeat Start are not included in PEC calculation. If the SPD5 Hub device NACKs due to PEC error or a parity error in a previous bytes from Host, it will always NACK regardless of how many times Host tries Repeat Start.
  • The SPD5 Hub does not send any data shown in Table 63 and instead expects Host to perform STOP operation.
  • The SPD5 Hub device sets MR52 [0] and MR48 [7] and P_Err in GESTATUS CCC to 1 for parity error and MR52 [1] and MR48 [7] and PEC_Err in GETSTATUS CCC to 1 for PEC error. Further, the SPD5 Hub updates Pending Interrupt Bits [3:0] in GETSTATUS CCC to 0001 and waits for the next opportunity to send an in band interrupt if IBI is enabled.

2.7.16 CCC Packet Error Handling

Parity error and PEC error detected in a CCC packet are handled the same way as described for normal Read/Write operation.

2.7.17 Error Reporting

All error conditions including PEC error check and Parity error check detected by the SPD5 Hub devices are captured in MR52 registers. There are three different possible ways error information can be communicated to the host. 1. The Host makes the read request to MR51 and MR52 registers. 2. The Host starts any transaction with 7’h7E IBI header. (Only applicable in I3C Basic Mode) 3. The SPD5 Hub device sends in band interrupt if enabled, when its SCL and SDA input has been idle for tAVAL time. (Only applicable in I3C Basic Mode).

2.7.18 I3C Basic Common Command Codes (CCC)

The I3C Basic spec lists large number of Common Command Codes (CCC). Not all CCC are required to be supported. The SPD5 Hub device NACKs for all unsupported CCC. The SPD5 Hub supports CCC as listed in Table 64. The SPD5 Hub device requires STOP operation in between when switching from CCC operation to private device specific Write or Read or Default Read Address Pointer mode operation and vice versa. In other words, any CCC operation must be followed by STOP operation before continuing to any device specific Write or Read or Default Read Address Pointer mode operation. Similarly, any device specific Write or Read or Default Read Address

Hub device also requires STOP operation between any direct CCC to broadcast CCC.

2.7.18.1 ENEC CCC

next Start operation (i.e. after STOP operation). Table 65 to Table 68 shows an example of a single ENEC CCC. Table 69 shows the encoding definition for ENEC CCC. but does not include 7’h7E with W = 0 byte in PEC calculation. Table 64. SPD5 Hub CCC Support Requirement Table 65. ENEC CCC - Broadcast

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. Repeat Start or Repeat Start with 7’h7E.

Table 66. ENEC CCC - Broadcast with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. Repeat Start or Repeat Start with 7’h7E.

Table 67. ENEC CCC - Direct

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 68. ENEC CCC - Direct with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. The SPD5 Hub device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued
  3. Repeat Start or Repeat Start with 7’h7E.

2.7.18.2 DISEC CCC

Start operation (i.e. after STOP operation). Table 70 to Table 73 shows an example of a single DISEC CCC. Table 74 shows the encoding definition for DISEC CCC. but does not include 7’h7E with W = 0 byte in PEC calculation. Table 69. ENEC CCC Byte Encoding Table 70. DISEC CCC - Broadcast

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. Repeat Start or Repeat Start with 7’h7E.

Table 71. DISEC CCC - Broadcast with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. Repeat Start or Repeat Start with 7’h7E.

Table 72. DISEC CCC - Direct

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

2.7.18.3 RSTDAA CCC

  1. Further it disables IBI and PEC function (MR27 [4] = 0, MR18 [7] = 0 respectively) and clears parity function

MR18 [6] = 0) and it takes in effect at the next Start operation (i.e. after STOP operation). Table 75 to Table 78 shows an example of a single RSTDAA CCC. but does not include 7’h7E with W = 0 byte in PEC calculation. Table 73. DISEC CCC - Direct with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. The SPD5 Hub device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued
  3. Repeat Start or Repeat Start with 7’h7E.

Table 74. DISEC CCC Byte Encoding Table 75. RSTDAA CCC - Broadcast

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.

Table 76. RSTDAA CCC - Broadcast with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat

2.7.18.4 SETAASA CCC

an example of a single SETAASA CCC.

2.7.18.5 GETSTATUS CCC

must do STOP operation. Table 80 to Table 81 shows an example of a single GETSTATUS CCC. but does not include 7’h7E with W = 0 byte in PEC calculation. Table 77. RSTDAA CCC - Direct

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. The SPD5 Hub device does not check for parity error in subsequent bytes when it determines the 7-bit device select code issued by the

host does not match with its own device code. The SPD5 Hub device ignores the entire packet until STOP or next Repeat Start operation. Table 78. RSTDAA CCC - Direct with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. The SPD5 Hub device does not check for parity or PEC error in subsequent bytes when it determines the 7-bit device select code issued

Table 79. SETAASA CCC - Broadcast

Table 80. GETSTATUS CCC - Direct

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. Repeat Start or Repeat Start with 7’h7E.

Table 81. GETSTATUS CCC - Direct with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. Repeat Start or Repeat Start with 7’h7E.

Pending Interrupt Bits [3:0] gets cleared. register, sets the IBI status register to 1 and Pending Interrupt Bits [3:0] to 0001.

2.7.18.6 DEVCAP CCC

issue this CCC. Table 83 to Table 84 shows an example of a single DEVCAP CCC. but does not include 7’h7E with W = 0 byte in PEC calculation. Table 82. GETSTATUS CCC Byte Encoding Table 83. DEVCAP CCC - Direct

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. Repeat Start or Repeat Start with 7’h7E.

2.7.18.7 SETHID CCC

The SPD5118 and SPD5108 supports SETHID CCC. The device behavior is as defined below. for host to issue this CCC. When SETHID CCC is registered by the SPD5 Hub, it stops 3-bit HID translation. Table86 shows an example of a single SETHID CCC. The host must send all 0 in the data byte followed by T bit. bit. As the device is in I2C mode when SETHID CCC is issued, the PEC function is not supported. The Host may issue SETHID CCC more than one time. See Figure 24 and Figure 25 for examples. Table 84. DEVCAP CCC - Direct with PEC

  1. The SPD5 Hub NACKs if there is a parity or PEC error in a previous transaction when host performs consecutive transactions with Repeat
  2. Repeat Start or Repeat Start with 7’h7E.

Table 85. DEVCAP CCC Byte Encoding Table 86. SETHID CCC - Broadcast

2.7.18.8 DEVCTRL CCC

protocol depending on how it may access the device until all devices are configured identically. does not include 7’h7E with W = 0 byte in PEC calculation. access device specific register.

  • DEVCTRL CCC must be followed by STOP operation before starting a device specific register access. In other words, host shall avoid DEVCTRL CCC followed by Repeat Start to do a device specific register operation. Note that host is allowed to do multiple DEVCTRL CCC with Repeat Start in between to the same device or across multiple devices.
  • DEVCTRL CCC must be followed by STOP operation before starting Default Read Address Pointer Mode even across different devices.
  • In I2C mode, DEVCTRCL CCC must be limited to 1 byte addressing mode for SPD5 Hub device (i.e. MR11 [3] = 0.

Table 87. DEVCTRL CCC - Broadcast

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. An exception is made for DEVCTRL CCC where device does report a parity error when it determines the 7-bit device select code issued

not check for parity error in subsequent bytes; ignores the entire packet and waits until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 88. DEVCTRL CCC - Broadcast with PEC

  1. The SPD5 Hub NACKs if there is a parity error in a previous transaction when host performs consecutive transactions with Repeat Start.
  2. An exception is made for DEVCTRL CCC where device does report a parity error when it determines the 7-bit device select code issued

subsequent bytes; ignores the entire packet and waits until STOP or next Repeat Start operation.

  1. Repeat Start or Repeat Start with 7’h7E.

Table 89. DEVCTRL CCC Command Definition reached, the host is responsible for applying STOP operation. PEC BL[1:0] Only applicable if RegMod = 0 and PEC function is enabled. when the PEC byte is expected after the data bytes. specific address offset register. 1 = Device Specific Offset Address (i.e. StartOffset[1:0] and PECBL[1:0] is a don’t care and does not apply). DevID[6:0] Identifies 7-bit device address. Device responds to DEVCTRL CCC data packet depending on AddrMask[2:0]. If AddrMask[2:0] = 111, DevID[6:0] is a don’t care and device always responds. If AddrMask[2:0] = 011, DevID[6:3] must match for device to respond. DevID[2:0] is don’t care. For any other codes for AddrMask[2:0], the device always NACKs.

on I3C Basic bus to do VR Enable followed by all devices with 4-bit LID code of 0110 to disable parity function. disable the parity function. Broadcast command; StartOffset = 00 to indicate starting Byte 0 and RegMod = 0 to indicates general register. Upon receiving this command, all devices will enable PEC function. Table 90. DEVCTRL CCC Data Payload Definition SPD5 Hub device always ignores this bit.

  1. After slave device clears the event, the device can still have certain registers set to 1 if the event is still present in which case, the device

will generate an IBI again at the next opportunity. Table 91. DEVCTRL CCC Example - Multicast Command to 1001 and 0110 Devices

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation.

receiving this command, PMIC on DIMM5 will enable its regulator. followed by all devices with 4-bit LID of 1001 on the I3C bus to write to address offset of 0x15 with data 0x78. Table 92. DEVCTRL CCC Example - Broadcast Command to all Devices

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation.

Table 93. DEVCTRL CCC Example - Unicast Command to PMIC on DIMM5

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation.

Table 94. DEVCTRL CCC Example - Multicast Command to 0010 and 1001 Devices

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation.

Table 95. DEVCTRL CCC Example - Multicast Command to 1001 Devices

  1. Figure 13 shows how the transition occurs from Slave Open Drain (ACK) to Host Push Pull Operation.

2.7.19 Host Flow Diagram Examples of DDR5 DIMM

reference and can be ignored from PMIC design point of view. Figure 24. Host Flow Diagram Examples 1 and 2 But RCD does not have VDDQ yet. But RCD does not have VDDQ yet.

2.7.20 IO Operation

either Open Drain mode or Push Pull can also be independently configurable. may always drive the HSCL clock input using a Push-Pull output driver. Figure 25. Host Flow Diagram Example 3 But RCD does not have VDDQ yet.

by the SPD5 device for each cycle.

2.7.21 Bus Clear

2.7.22 Bus Reset

operation works same way regardless of whether device is operating in I2C or I3C Basic mode. guarantee and it may or may not reset the I2C bus or I3C Basic bus.

  1. Interface and any pending command or transactions are cleared
  2. All internal register values are preserved unless noted otherwise in item # 3.

Table 96. SPD5 Hub Device Dynamic IO Operation Mode Switching

  1. Device always returns to I2C mode of operation; MR18 [7:5] = 000; MR27 [4] resets to 0; MR52 [1:0] resets to

00; INF_SEL bit in GETSTATUC CCC to 0.

  1. Device does not re-sample HSA pin.
  2. Device floats the HSDA pin such that it gets pulled High by the external pull-up. The device pulls the LSDA pin
  3. Device treats bus reset as STOP operation.

2.7.23 Command Truth Table

and I3C Basic mode with PEC disabled, the command truth table does not apply. Figure 26. I2C or I3C Basic Bus Reset - SPD5 Hub Device Table 97. For I3C Mode Only with PEC Enabled - Command Truth Table

2.8 HSA Pin Resistor Values and ID

2.8.1 SPD5 Family Devices

Table 98 shows the HSA pin resistor values and corresponding ID for the SPD5118 and SPD5108.

2.9 SPD5 Family Device - Write and Read Access

STOP operation (i.e. not Repeat Start) before launching new transactions to SPD5 Hub volatile memory registers. Conversely, any read or write to SPD5 Hub volatile memory registers must be followed by STOP operation (i.e. not Repeat Start) before launching new transactions to SPD5 Hub EEPROM.

2.9.1 Write and Read Access - NVM Memory

any register to inform this to the host and does not generate any interrupt to the host. Hub device does not set any register to inform this to the host and does not generate any interrupt to the host. not return any data. In I2C mode and I3C Basic mode with PEC disabled, the host must do the STOP operation.

2.9.2 Write and Read Access - Register Memory

MemReg = 0 by the SPD5 Hub device. memory is continuous address space even if it appears crossing 16 byte boundary or “Block Address” boundary. any data. In I2C mode and I3C Basic mode with PEC disabled, the host must do the STOP operation. Table 98. HSA Pin Resistor Value and ID - SPD5 Family

2.10 Write Protection of Non-Volatile Memory (For SPD5 Family Devices Only)

2.10.1 Normal Run Time Operation (HSA Pin is tied to GND via a resistor value)

that corresponding block of NVM are ignored and MR52 [6] bit is set to 1. attempt to clear the bit in MR12 and MR13 is ignored and MR52 [5] bit is set to 1.

2.10.2 Offline Tester Operation (HSA Pin is tied directly to GND, no resistor value)

allows to modify the corresponding block of NVM memory.

2.10.3 Suggested Steps to Program SPD5 Devices

  1. Connect HSA Pin directly to GND (without a resistor).
  2. Power up the device. The device senses HSA pin. It sets MR48 [2] = 1 and enables write protection override.
  3. Program MR12 and MR13 to enable desired NVM blocks to be written.
  4. Program desired NVM blocks.
  5. Program MR12 and MR13 to set the write protection as desired.

2.11 AC Timing Definition

2.11.1 I2C or I3C Basic Bus Timing

timing diagram for Data bus Input and Data Output parameters. Figure 27. I2C or I3C Basic Bus AC Input Timing Parameter Definition Figure 28. I3C Basic Bus AC Data Output Timing Parameter Definition

2.11.2 Hub Propagation Delay

local interface LSCL/LSDA signals, respectively. Figure 33. Propagation Delay Through the SPD5 Device

2.12 Parametric Characteristics

2.12.1 Absolute Maximum Ratings

Maximum Rating conditions for extended periods may affect device reliability.

2.12.2 ESD Requirements

2.12.3 Operating Condition, Measurement Condition and DC and AC Characteristics

the Measurement Conditions summarized in the relevant tables. Table 99. Absolute Maximum Ratings Table 100. ESD Requirement Table 101. Operating Conditions Table 102. Write Endurance and Data Retention

Table 103. AC Measurement Conditions (Note 1)

  1. This AC measurement condition (Table 103 and Table 34) is only for the test purpose in lab.

Figure 34. AC Measurement Waveform Table 104. Input Parameters

  1. Verified by design and characterization, not necessarily tested on all devices.

Table 105. Output Ron Spec

  1. Pull-down Ron = Vout/Iout; Pull-up Ron = (VIO - Vout)/Iout.

Table 106. DC Characteristics

  1. Thermal sensor is active.
  2. Output slew rate is guaranteed by design and/or characterization. The output slew rate reference load is shown in Figure 30 and Figure 31

Table 107. AC Characteristics Table 106. DC Characteristics (Continued)

2.12.4 Temperature Sensor Performance

  1. I3C Basic mode with Open Drain operation follows timing values as shown in I2C Mode - Open Drain column.
  2. See Figure 27 for input timing parameter definition.
  3. See Figure 32 for voltage threshold definition for rise and fall times.
  4. If PEC is enabled, tWR_RD_DELAY_PEC_EN timing parameter also applies.
  5. See Figure 30 for output timing parameter measurement reference load definition. See Figure 33 for propagation delay definition.
  6. See Figure 29 for output timing parameter definition
  7. The Hub device must be configured in I3C Basic mode to guarantee tDOUT value. The input path filter setting is 0 ns. See Figure 28 for

timing parameter measurement reference load definition.

  1. The Hub device must be configured in I3C Basic mode to guarantee tDOFFS value. See Figure 13. See Figure 30 for output timing

parameter measurement reference load definition.

  1. The Hub device must be configured in I3C Basic mode. The Host guarantees tDOFFM value. See Figure 14. See Figure 30 for output

timing parameter measurement reference load definition.

  1. From STOP condition of DEVCTRL CCC to START condition for Register Read or Register Write Command Data Packet delay.
  2. The device sends NACK if Host does not satisfy tDEVCTRLCCC_DELAY_PEC_DIS timing parameter.
  3. This timing parameter restriction is only applicable when PEC function is disabled in SPD5 Hub. If PEC is enabled, this timing parameter
  4. From STOP condition for Register Write Command Data Packet to START condition for Register Read Command Data Packet delay.
  5. This timing parameter restriction is only applicable when PEC function is enabled in SPD5 Hub. If PEC is disabled, this timing parameter
  6. The SPD5 Hub sends NACK if Host does not satisfy tWR_RD_DELAY_PEC_EN timing parameter.

Table 108. Temperature Sensor Performance, Table 107. AC Characteristics (Continued)

3.1 Access Mechanism

3.1.1 Register Attribute Definition

with Attribute Modifiers, as defined in Table 110. concept of “Block” memory in volatile register space. When writing to and reading from volatile register space (i.e. MemReg = 0), the “Block Address bits” are treated simply as Upper address bits.

3.2 Registers

3.2.1 Register Map

Table 109. Register Base Attributes Read Only R This bit can be read by software. Writes have no effect. Read/Write RW This bit can be read or written by software. Write Only W This bit can only be written by software. Table 110. Register Attribute Modifier code has been written into the password registers. Table 111. Register Map

3.2.2 Thermal Sensor Registers Read Out Mechanism

All thermal registers are sixteen bit quantities stored in two consecutive registers; low byte first and then high byte. low byte and high byte. The device always returns 0 in Reserved bits when Host reads from the low and high byte. 255.75. Units for all thermal registers are oC. The format of each pair of thermal registers is shown in Table 112. The examples (reserved bits in grey, sign bit highlighted in cyan) is shown in Table 113. Table 112. Thermal Register - Low Byte and High Byte Table 113. Thermal Register Examples

3.2.3 Register Description

Table 114. MR0 Device Type - These are hard coded. Once programmed by Renesas, it cannot be changed.

  1. The code in this register is used in conjunction with any device type in MR1 register.

Table 115. MR1

  1. The code in this register is used in conjunction with any device type in MR0 register.

Table 116. MR2

0 RV 0 MR2[0]: Reserved

Table 113. Thermal Register Examples (Continued)

Table 117. MR3 The JEDEC standard Renesas Code. Table 118. MR4 The JEDEC standard Renesas Code. Table 119. MR5

1 ROE - MR6[1]: TS_SUPPORT

0 ROE - MR6[0]: HUB_SUPPORT

Table 120. MR6

Table 121. MR11

3 RW 0 MR11[3]: I2C_LEGACY_MODE_ADDR

  1. This register is only applicable if bit [3] = 0 and MR18 [5] = 0. The SPD5 Hub device does not incur any delay to switch from one page to
  2. This register only applies to non-volatile memory (1024 Bytes) access of SPD5 Hub device. For volatile memory access, this register
  3. See Write and Read Access - NVM Memory for the NVM Write and Read operation when device reaches the last byte of the 16 byte

Table 122. MR12

7 RWE 0 MR12[7]: WP_BLK_7

6 RWE 0 MR12[6]: WP_BLK_6

5 RWE 0 MR12[5]: WP_BLK_5

4 RWE 0 MR12[4]: WP_BLK_4

3 RWE 0 MR12[3]: WP_BLK_3

2 RWE 0 MR12[2]: WP_BLK_2

1 RWE 0 MR12[1]: WP_BLK_1

0 RWE 0 MR12[0]: WP_BLK_0

  1. Once any register bit is set to 1, it can only be cleared when the SPD5 device is in offline tester mode of operation.
  2. The write (or update) transaction to this register must be followed by STOP operation to allow the SPD Hub device to update the setting.

Table 123. MR13

7 RWE 0 MR13[7]: WP_BLK_15

6 RWE 0 MR13[6]: WP_BLK_14

5 RWE 0 MR13[5]: WP_BLK_13

4 RWE 0 MR13[4]: WP_BLK_12

3 RWE 0 MR13[3]: WP_BLK_11

2 RWE 0 MR13[2]: WP_BLK_10

1 RWE 0 MR13[1]: WP_BLK_9

0 RWE 0 MR13[0]: WP_BLK_8

  1. Once any register bit is set to 1, it can only be cleared when the SPD5 device is in offline tester mode of operation.
  2. The write (or update) transaction to this register must be followed by STOP operation to allow the SPD Hub device to update the setting.

Table 124. MR14

5 RWE 0 MR14[5]: LOCAL_INF_PULLUP_CONF

Table 122. MR12 (Continued)

  1. DIMM Vendor configures this register during assembly based on the DIMM design. After SPD Hub device is powered up, the Host can

alter the setting through this register.

  1. The write (or update) transaction to this register must be followed by STOP operation to allow the SPD Hub device to update the setting.
  2. The pull-up resistor value is configured in MR15 [7:0] for relevant output.
  3. The register setting in MR14 [4:2] must be either 000 or 001 or 010 or 011. The internal LDO of the device regulates to either 1.0V or 1.1V

input to the VIO pin internally on die.

  1. External pull-up resistor on board to the rail is configured appropriately in register MR14 [4:2]. The device allows any combination of

setting in MR14 [4:2] register.

  1. This register is configured by the DIMM vendor for the local interface. But it may also be used by the SPD5 Hub device internally for the

Table 125. MR15

  1. This register is only applicable if MR14 [5] = 0.
  2. DIMM Vendor can configure this register during assembly based on the DIMM design. After SPD5 Hub device is powered up, the Host

can alter the setting through this register.

  1. The write (or update) transaction to this register must be followed by STOP operation to allow the SPD Hub device to update the setting.
  2. The resistor tolerance is + 25%

Table 126. MR18

7 RW 0 MR18[7]: PEC_EN

6 RW 0 MR18[6]: PAR_DIS

5 RO 0 MR18[5]: INF_SEL

4 RW 0 MR18[4]: DEF_RD_ADDR_POINT_EN

1 RW 0 MR18[1]: DEF_RD_ADDR_POINT_BL

0 RV 0 MR18[0]: Reserved

  1. The write (or update) transaction to this register must be followed by STOP operation to allow the SPD Hub device to update the setting.
  2. This register is only applicable if MR18 [5] = 1.
  3. This register is updated when RSTDAA CCC is registered by the SPD5 Hub device or when SPD5 Hub device goes through the bus reset
  4. This register is only applicable if MR18 [5] = 1. When Parity function is disabled, the SPD5 Hub device simply ignores the T bit information
  5. This register is automatically updated when SETAASA CCC or RSTDAA CCC is registered by the SPD5 Hub device or when SPD5 Hub

when there is a next START operation (i.e. after STOP operation).

  1. The setting in registerMR18 [3:1] is a don’t care.
  2. This register is only applicable if MR18 [4] = 1.
  3. This register is only applicable if MR18 [7, 4] = 11.

Table 127. MR19

  1. This entire register is self clearing register after corresponding register is cleared.

Table 128. MR20

  1. This entire register is self clearing register after corresponding register is cleared.

Table 129. MR26

0 RW 0 MR26[0]: DIS_TS

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. If this bit is set to 1 and then reset to 0, the host must wait minimum of tINIT before accessing samples on the thermal sensor.

Table 130. MR27

4 RO 0 MR27 [4]: IBI_ERROR_EN

3 RW 0 MR27 [3]: IBI_TS_CRIT_LOW_EN

2 RW 0 MR27[2]: IBI_TS_CRIT_HIGH_EN

1 RW 0 MR27[1]: IBI_TS_LOW_EN

0 RW 0 MR27[0]: IBI_TS_HIGH_EN

  1. This register is a self clearing register after corresponding registers are cleared. Writing 0 in this register has no effect.
  2. After this command is issued, the device does not generate an IBI for any pending event. But if new event occurs, the device does
  3. This register is automatically updated when ENEC CCC or DISEC CCC or RSTDAA CCC is registered by the SPD5 Hub device or when

is a next START operation (i.e. after STOP operation).

  1. This register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.

Table 131. MR28 MR28 and MR29 - 16 bit thermal registers define the high limit for thermal sensor.

  1. This entire register is only applicable ifMR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature High Limit value must have a higher value than temperature High Limit (MR28 [7:0] and MR29 [7:0].
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 132. MR29 MR28 and MR29 - 16 bit thermal registers define the high limit for thermal sensor.

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature High Limit value must have a higher value than temperature High Limit (MR28 [7:0] and MR29 [7:0].
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 133. MR30 MR30 and MR31 - 16 bit thermal registers define the low limit for thermal sensor.

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature Low Limit value must have a lower value than temperature Low Limit (MR30 [7:0] and MR31 [7:0]
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 134. MR31 MR30 and MR31 - 16 bit thermal registers define the low limit for thermal sensor.

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature Low Limit value must have a lower value than temperature Low Limit (MR30 [7:0] and MR31 [7:0].
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 135. MR32

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature High Limit value must have a higher value than temperature High Limit (MR28 [7:0] and MR29 [7:0].
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 136. MR33

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature High Limit value must have a higher value than temperature High Limit (MR28 [7:0] and MR29 [7:0].
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 137. MR34

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature Low Limit value must have a lower value than temperature Low Limit (MR30 [7:0] and MR31 [7:0].
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 138. MR35

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. Critical temperature High Limit value must have a higher value than temperature High Limit (MR30 [7:0] and MR31 [7:0].
  3. The Reserved bits are Read Only bits. The Host must write 0 in reserved bits when writing and device always returns 0 when host reads

Table 139. MR48

7 RO 0 MR48[7]: IBI_STATUS

3 RO 0 MR48[3]: WR_OP_STATUS

2 RO - MR48[2]: WP_OVERRIDE_STATUS

The default state of this register reflects the sensing of HSA pin during power on. This bit is set to 1 if HSA pin is directly tied to GND. Table 140. MR49

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. The device always returns 0 from reserved bits when host reads this byte.

Table 141. MR50

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.
  2. The device always returns 0 from reserved bits when host reads this byte.

Table 142. MR51

3 RO 0 MR51 [3:]: TS_CRIT_LOW_STATUS

2 RO 0 MR51[2]: TS_CRIT_HIGH_STATUS

1 RO 0 MR51[1]: TS_LOW_STATUS

0 RO 0 MR51[0]: TS_HIGH_STATUS

  1. This entire register is only applicable if MR1 [7:0] programmed value is either 0x18 or 0x14 or 0x12.

Table 139. MR48 (Continued)

Table 143. MR52

7 RO 0 MR52[7]: BUSY_ERROR_STATUS

6 RO 0 MR52[6]: WR_NVM_BLK_ERROR_STATUS

5 RO 0 MR52[5]: WR_NVM_PRO_REG_ERROR_STATUS

1 RO 0 MR52[1]: PEC_ERROR_STATUS

0 RO 0 MR52[0]: PAR_ERROR_STATUS

  1. SPD device busy status is only for accessing EEPROM memory. For any access to volatile register space, this bit definition does not
  2. When SPD device is busy with EEPROM write/read, it sends NACK to the host requests within write recovery time.
  3. Only applicable MR18 [5] = 1 and if PEC function is enabled.
  4. This register is updated to 0 when SPD5 Hub device goes through bus reset as described in Bus Reset.
  5. Only applicable in MR18 [5] = 1 and if Parity function is not disabled or for supported CCC in I2C mode.

Figure 35. Top Marking Table 144. Ordering Information 1.11 Sep 15, 2021 Updated high/low bytes for -40°C in Thermal Register Examples table.

1.10 Aug 3, 2021 Updated Open Drain Interface with Internal On Die Pull-up Resistor

1.00 Jun 8, 2021 Initial release.

  1. The parameters in this datasheet are defined in accordance with JEDEC Standard.

© Renesas Electronics Corporation

Package Revision HistoryRev No.Date CreatedDescriptionJune 4, 2021Rev 02Update to Renesa LogoJune 26, 2018Rev 01Add Component Outline for Foot Print in Green© Renesas Electronics Corporation

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