SPCR02A ETC | Alldatasheet

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SSoouunndd CCoonnttrroolllleerr wwiitthh 4400KKBB MMRROOMM aanndd SSeerriiaall RRAAMM IInntteerrffaaccee SEP. 19, 2001 Version 1.5 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLO GY CO. makes no warranty for any errors which may appear i n this document. Contact SUNPLUS TECHNOLOGY CO. to obt ain the lat est v ersion of dev ice s pecifications bef ore plac ing your order. No res ponsibility is assume d by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.

© Sunplus Technology Co., Ltd. Proprietary & Confidential 2 SEP. 19, 2001 Version: 1.5

40KB MROM AND SERIAL RAM INTERFACE 1. GENERAL DESCRIPTION The SPCR02A is a CPU based device for recording (one channel) and pla yback (t wo chann el) that includes a CM OS 8 -bit microprocessor, 40K-byte MROM (speech is com pressed by 4-bit ADPCM with ap prox. 12sec. spe ech duration @ 7KHz sampling rate). It also includes Serial SRAM Inter face and 1 28-byte working SRAM. It includes t wo Timer/Counters, 20 sof tware selectable I/Os, tw o 8 -bit audio current out put D/A, MIC (microphone) input, and A GC f unction. For a udio processing, melody and spe ech can be mixed into one output. It operates over a single power voltage range of 2.4V - 5.5V. In addition, the SPCR02A has a Clock Stop mode for power savings. The power savings mode saves the SRAM contents, but freezes the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 6.0MHz. It has an instruction cy cle rate of 2 clock cy cles ( min.) - 6 cloc k cycles (max. ). The SPCR02A includes, not only the latest technology, b ut also the full commitment and technical support of Sunplus. 2. BLOCK DIAGRAM 8-bit microprocessor 40K-byte MROM 128-byte SRAM INT control Two 8-bit D/A (current)

20 PINS GENERAL I/O PORT

IOB3-0, 6,7 IOC3-0,6,7 IOD7-0 (I/O) AUD1 AUD2 MIC Input Two Timers TimeBase MIC AGC OPIN OPOUT Rosc Serial RAM Interface CSB SCL SDA (I/O)(I/O) 3. FEATURES ! 8-bit microprocessor ! Software-based audio processing ! Provides 40K-byte MROM for program and audio data with approx. 12 sec. speech @ 7KHz sampling rate with ADPCM ! 128-bytes working SRAM ! Operating voltage (single power): 2.4V - 3.6V 3 .6V - 5.5V ! Supports Rosc ! Max. CPU clock speed: 6.0MHz @ 5.0V ! Serial SRAM Interface ! Standby mode (Clock Stop mode) for power savings. M ax. 5µA @ 5.0V ! Below 1000ns instruction cycle time @ 4.0MHz CPU clock ! Provides 20 general I/Os ! Two 12-bit timer/counters ! Two 8-bit audio current output (D/A) ! 6 INT sources ! Sunplus Serial SRAM Chip-Set Options ― SPRS256 A (10sec @ 6.4KHz sampling rate) ― SPRS512C (20sec @ 6.4KHz sampling rate) ― SPRS1024C (40sec @ 6.4 Sampling Rate) ! Key wake -up function ! MIC input with AGC and Comparator 4. APPLICATION FIELD ! Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) S pelling (English or Chinese) M ath ! High end toy controller ! Talking instrument controller ! General speech recorder ! Interactive games ! Industrial controller © Sunplus Technology Co., Ltd. Proprietary & Confidential 3 SEP. 19, 2001 Version: 1.5

  1. SIGNAL DESCRIPTIONS* Mnemonic PIN No. Type Description VDD 10 I Positive supply for logic and I/O pins. VSS 3 I Ground reference for logic and I/O pins. RESET 4 I RESET input (This pin is active low reset for the chip) ROSC 11 I ROSC input SDA SCL CSB I/O O O External SRAM interface with the following Serial SRAM Chip-Set Options: SPRS256A, SPRS512C, and SPRS1024C. AUD1 MIC OPIN OPOUT ALC AUD2 O I I O I O AUDIO output A Microphone input Preamplifier Input Preamplifier Output Automatic Gain Control AUDIO output B IOB0 IOB1 IOB2 IOB3 IOB6 IOB7 I/O I/O I/O I/O I/O I/O Port B is an 8- bit bi-directional programm able Input / Output port with Pull-low o r Open-drain option. As inputs, Port B can be in either the Pure or Pull-low states. As outputs, Port B can be either Buffer or Open-drain NMOS types (Sink current). See note 1 and 2 below. IOC0 IOC1 IOC2 IOC3 IOC6 IOC7 I/O I/O I/O I/O I/O I/O Port C is an 8- bit bi-directional progra mmable Input / Output port w ith Pull-high or Open-drain option. As inputs, Port C can be in either the P ure or Pull-high st ates. As outputs Port C can be a Buffer or Open-drain type. Port C3 - C0 are Open-drain NMOS type (Sink current) and Port C7 - C6 are Open-drain NMOS (Sink current). IOC1: EXT INT IN IOC2: EXT COUNT IN See note 1 and 2 below. IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 I/O I/O I/O I/O I/O I/O I/O I/O Port D is an 8-bit bi-directional Input / Output port with Pull-low or Open-drain option. As inputs, Port D c an be eithe r Pure or Pull-lo w states. As outputs, Port D can b e either Buffer or Ope n-drain PMOS (sen d current). Also, Port D can be sof tware programmed for wake-up I/O pins. (Key change, Wake up I/O) **See note 1 and 2 below. * Refer to SPC Programming Guide for complete information. **Note: 1.) Three input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified as Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output (sink). © Sunplus Technology Co., Ltd. Proprietary & Confidential 4 SEP. 19, 2001 Version: 1.5
  1. FUNCTIONAL DESCRIPTIONS 6.1. CPU The SPCR0 2A 8-bit micropro cessor is a high perfo rmance processor equipped with Accumulator , Progr am Counter , X Register, Stack pointer and Processor S tatus Register (this is the same as the 65 02 instruction structure). SPCR 02A is able to perform with 6 .0MHz (ma x.) depending on the application specifications. 6.2. ROM Area The SPCR02A provides a 40K-byte MROM that can be defined as the program area, audio data area, or both. 6.3. RAM Area The SPCR02A total RAM consist s of 128 bytes (including Stack) at locations from $80 through $FF. 6.4. Map of Memory and I/Os HW register, I/Os USER RAM and STACK USER'S PROGRAM & DATA AREA $00000 $00080 $00100 $06000 $0FFFF *I/O PORT: - PORT IOB $0003 IOC $0004 IOD $0005 *NMI SOURCE: - I/O CONFIG $0000 $0001 - INTA (from TIMER A) *INT SOURCE: - INTA (from TIMER A) - INTB (from TIMER B) - CPU CLK / 1024 - CPU CLK / 8192 - CPU CLK / 65536 - EXT INT *MEMORY MAP (From ROM view) DUMMY for ice debug 6.5. I/O Port Configurations* Input/Output IOB port : IOB3 - 0 60K OD : Open Drain input data logic_1 control output data OD-NMOS or buffer Input/Output IOB port : IOB7,6 60K OD : Open Drain input data logic_2 control output data OD-NMOS or buffer Input/Output IOC port : IOC3 - 0 input data output data logic_3 control 90K VDD OD-NMOS buffer or OD : Open Drain Input/Output IOC port : IOC7,6 input data output data logic_4 control VDD OD-NMOS buffer or OD : Open Drain 90K Input/Output IOD port : IOD3 - 0 60K OD : Open Drain input data logic_5 control output data OD-PMOS or buffer © Sunplus Technology Co., Ltd. Proprietary & Confidential 5 SEP. 19, 2001 Version: 1.5

Input/Output IOD port : IOD7 - 4 60K OD : Open Drain input data logic_6 control output data OD-PMOS or buffer *Values shown are for VDD = 5.0V test conditions only. 6.6. Timer/Counter The SPCR02A contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be spe cified as a t imer or a counter , but TMB can onl y be used as a tim er. In the timer mode, TMA and TMB ar e r e-loaded up -counters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user ’s pre-set valu e and be up-counted again. At the same time, t he carry signal w ill generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset b y loa ding #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time. The r ead instr uction w ill not r eset or af fect the value of the counter. Clock source of Timer/Counter can be selected as follows: Timer/Counter Clock Source 12-BIT TIMER CPU CLOCK (T) or T/4 TMA 12-BIT COUNTER T/64, T /8192, T/65536 o r EX T CLK TMB 12-BIT TIMER T or T/4 MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4 6.7. Speech and Melody Since the SPC R02A provides a large R OM a nd wide range of CPU operation speeds, it is most suitable for spe ech and melod y synthesis. For speech synthesis, the SPCR02A can provide NMI for accurate sampling frequenc y. For reco rding users can record the sound and digitize it into the external Serial SRAM. The sound data can be pla yed back in the sequence of the control functions a s designed b y the user's prog ram. For pre- recorded data several algorithms are r ecommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM. For melody synthesis, the SPCR02A provides the dual tone mode. After selecting the dual tone mo de, users onl y n eed to fill either TMA or TMB, or both TMA a nd TMB to ge nerate e xpected frequency for ea ch channel. The hard ware will toggle the ton e wave automatic ally without ent ering into an interrupt service routine. Users are able to simulate musical instruments or sound effects by simply controlling the envelope of tone output. 6.8. Power Savings Mode The SPCR02A provides a pow er savings mode (S tandby mode) for those ap plications that require very low stand-by current. To enter st andby m ode, the W ake-Up Register should be enabled and then stop the CPU clock b y writing the ST OP CLOCK Register. The CPU will then go to the stand-by mode. In such a mode, RAM and I/Os will remain in their previous states until being awakened. Po rt IOD7-0 is th e onl y wake-up source in the SPCR02A. After the SPCR02A is aw akened, th e internal CPU will go to the RESET State (Tw ≧ 65536 x T1) and then continue processing the program. Wakeup Reset will not af fect RAM or I/Os. (See FIG.1) Tw CPU CLK Sleep Wake-up Reset FIG. 1 T1 = 1 / ( FCPU ), Tw ≧ 655 36 x T1 © Sunplus Technology Co., Ltd. Proprietary & Confidential 6 SEP. 19, 2001 Version: 1.5

  1. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA -10℃ to +70℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 7.2. DC/AC Characteristics Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 2.4 - 5.5 V Operating Current IOP - 4.0 10 mA FOSC = 4.0MHz @ 5.0V, no load Standby Current ISTBY - - 2.0 µA VDD = 5.0V OSC frequency FOSC - 3.0 6.0 MHz VDD = 5.0V Audio output current IAUD - -1.2 - mA VDD = 5.0V Input high level VIH 3.0 - - V VDD = 5.0V Input Low level VIL - - 0.8 V VDD = 5.0V Output high I IOB, IOC, IOD IOH -1.0 - - mA VDD = 5.0V VOH = 4.2V Output sink I IOB, IOC, IOD IOL 4.0 - - mA VDD = 5.0V VOL = 0.8V Input resistor IOB, IOC, IOD RIN - 30 - Kohm Pull Low or Pull High OSC frequency FCPU - - 4.0 MHz VDD = 3.0V 7.3. The Relationship between the ROSC and the FCPU SPCR02A 0 200 400 600 800 Rosc ( K ohms ) Fosc ( MHz ) SP C R 0 2 A 0 2 0 0 40 0 6 00 8 0 0 R o sc ( K o hm s ) Fosc ( MHz ) © Sunplus Technology Co., Ltd. Proprietary & Confidential 7 SEP. 19, 2001 Version: 1.5
  1. APPLICATION CIRCUIT VDD ROSC RESET VSS MIC OPIN OPOUT ALC IOD0 IOD7 AUD1 AUD2 VDD R3C3 SPCR02A VDD 8050 8050 IOD0 IOD7 Q1Q2 MIC SDA SCL CSB IOC0 IOC3 IOC0 IOC3 IOB0 IOB3 IOB0 IOB3 R4C4 SDA SCL CSB VDD VSS VDDSPRS512C Input SpeakerSpeaker 4.7K0.1µ0.1µ 47µ 43K 0.1µ 100K 68p 200K0.22µ IOC6 IOC7 IOC6 IOC7 IOB6 IOB7 IOB6 IOB7 © Sunplus Technology Co., Ltd. Proprietary & Confidential 8 SEP. 19, 2001 Version: 1.5
  1. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment Chip Size: 2220µm x 2120µm This IC substrate should be connected to VSS Note1: Chip size included scribe line. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type SPCR02A-nnnnV-C Chip form Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z). © Sunplus Technology Co., Ltd. Proprietary & Confidential 9 SEP. 19, 2001 Version: 1.5

9.3. PAD Locations PAD No. PAD Name X Y

1 IOB6 -915 518

2 IOB7 -917 288

3 VSS -897 63

4 RESET -833 -807

5 IOD7 -669 -825

6 IOD6 -502 -825

7 IOD5 -345 -825

8 IOD4 -175 -825

9 IOD3 -14 -825

10 VDD 152 -832

11 ROSC 304 -821

12 AUD2 465 -821

13 MIC 614 -821

14 ALC 775 -821

15 OPIN 925 -821

16 OPOUT 908 -620

17 AUD1 891 -451

18 IOD2 904 -290

19 IOD1 904 -121

20 IOD0 935 106

21 SDA 937 333

22 SCL 937 557

23 CSB 613 893

24 IOC0 474 892

25 IOC1 313 895

26 IOC2 176 894

27 IOC3 15 893

28 IOC6 -119 894

29 IOC7 -278 893

30 IOB0 -437 898

31 IOB1 -569 897

32 IOB2 -742 903

33 IOB3 -908 901

© Sunplus Technology Co., Ltd. Proprietary & Confidential 10 SEP. 19, 2001 Version: 1.5

  1. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no w arranty, exp ress, st atutory imp lied or b y descri ption regarding t he information in this publicati on o r regarding the f reedom of the d escribed chip(s) from p atent infringement. FURTHERMORE, S UNPLUS MAKES NO W ARRANTY OF MERCHANTABILITY OR FITNESS FOR AN Y PURPOSE. SUNPLUS reserves the right to halt p roduction or alter the specifications and prices at an y time w ithout noti ce. Accordingly , the reade r is cautioned to ver ify t hat the da ta sheet s and oth er information i n t his publication are current befor e placing orders. Products descr ibed herein are intended for use in normal co mmercial application s. Applications involving unusual e nvironmental or reliability require ments, e.g. milit ary equipment o r medical l ife su pport equip ment, ar e specifically not recommended without additional processing b y S UNPLUS fo r such applications. Please note that application cir cuits illustrated in this document are for reference purposes only. © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 SEP. 19, 2001 Version: 1.5
  1. REVISION HISTORY Date Revision # Description Page NOV. 28, 1997 1.0 Original DEC. 27, 1997 1.1 Modify error. IOB4 -> IOB6, IOB5 -> IOB7, IOC4 -> IOC6, IOC5 -> IOC7 FEB. 06, 1998 1.2 Modify error. IOB4 -> IOB6, IOB5 -> IOB7, IOC4 -> IOC6, IOC5 -> IOC7 2, 3, 7 AUG. 18, 1998 1.3 Correction error. DEC. 15, 1999 1.4 1. Modify Format 2. Add PIN No. 3. Add “DISCLAIMER” 2. Correct chip size 3. Add Note1 and Note2 in the “9.1 PAD Assignment” 4. Renew to a new document format © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 SEP. 19, 2001 Version: 1.5