DSP56857PB MOTOROLA | Alldatasheet
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Technical content
The 56857 offers a rich feature set and on-chip memory in a 100-pin LQFP . It includes 80 KB of on-chip program SRAM and 48 KB of on-chip data SRAM. With two enhanced serial synchronous serial interfaces (ESSIs), this device can provide outputs for 5.1-channel surround sound. The 56857 can be designed into multi-processor systems to provide internet audio and speech processing functionalities. JTAG/EOnCE PLL 16-Bit Quad Timer Up to 47 GPIO COP/Watchdog (2) SCI Data Memory 56800E Core
120 MIPS
2 KB Boot ROM
80 KB SRAM
48 KB SRAM
(2) ESSI SPI 8-Bit Host BENEFITS
- Easy to program with flexible application development tools
- Supports multiple processor connections
- 16-bit quad timer module (with four external pins) that allows capture/compare functionality, and can be cascaded
- Quad timer module can also be used for simple digital-to-analog conversion functionality
- Enhanced synchronous serial interface with enhanced network and audio modes
- T ime of Day for applications requiring clock display
- Flexible 6-Channel Direct Memory Access (DMA) allows both internal and external memory transfers with almost no CPU interruption
- Serial peripheral interface with master and slave mode supporting connection to other processors or serial memory devices
- T wo enhanced synchronous serial interfaces with three transmitters per module provide support for 5.1 channel surround sound for audio
applications
56857 16-BIT DIGITAL SIGNAL PROCESSORS
- 120 MIPS at 120MHz
- 80 KB Program SRAM
- 48 KB Data SRAM
- 2 KB Boot ROM
- Six independent channels of DMA
- T wo Enhanced Synchronous Serial Interfaces (ESSI)
- T wo Serial Communication Interfaces (SCI)
- Serial Peripheral Interface (SPI)
- Four dedicated GPIO
- 8-bit parallel Host Interface
- General purpose 16-bit Quad Timer
- J TAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
- Computer Operating Properly (COP)/Watchdog Timer
- T ime of Day (TOD)
- 100-pin LQFP package
- Up to 47 GPIO ENERGY INFORMATION
- Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
- W ait and Stop modes available TARGET APPLICATIONS HYBRID MCU/DSP 56857
120 MIPS Hybrid Processor
- Multi-processor Telephony Systems
- Stand-alone MP3 player
- D T A D
- Feature phone
- V oice recognition and command
- Embedded modem/data pump
- LCD and keypad support
- General purpose devices
- Automotive hands-free Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST . All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56857PB/D REV 3
ORDERING INFORMATION
- Processor Expert™ (PE) technology provides a rapid application design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system.
- The CodeWarrior™ Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling and debugging. A comprehensive set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, the CodeWarrior tool suite and EVMs create a comprehensive, scalable tools solution for easy, fast and efficient development. HYBRID MCU/DSP 56857 PRODUCT DOCUMENTATION
56857 PERIPHERAL CIRCUIT FEATURES
- General Purpose 16-bit Quad Timer*
- T wo Serial Communication Interfaces (SCI)*
- Serial Peripheral Interface (SPI) Port*
- T wo Enhanced Synchronous Serial Interface (ESSI) modules*
- Computer Operating Properly (COP)/Watchdog Timer
- J T AG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
- Six independent channels of DMA
- 8-bit parallel Host Interface*
- T ime of Day (TOD)
- Four dedicated GPIO
- Up to 47 GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O
56857 MEMORY FEATURES
- On-chip Memory – 80 KB Program RAM – 48 KB Data RAM –2 KB Boot ROM – Chip Select Logic used as GPIO
- Harvard architecture permits up to three simultaneous accesses to program and data memory 56800E CORE FEATURES
- Efficient 16-bit hybrid controller engine with dual Harvard architecture
- 120 Million Instructions Per Second (MIPS) at 120MHz core frequency
- Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC)
- Four (4) 36-bit accumulators, including extension bits
- 16-bit bidirectional shifter
- Parallel instruction set with unique addressing modes
- Hardware DO and REP loops
- Three internal address buses and one external address bus
- Four internal data buses and one external data bus
- Instruction set supports both DSP and controller functions
- Four hardware interrupt levels
- Five software interrupt levels
- Controller-style addressing modes and instructions for compact code
- Efficient C compiler and local variable support
- Software subroutine and interrupt stack with depth limited only by memory
- J T AG/Enhanced OnCE debug programming interface The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers, enabling rapid development of optimized control applications. Features of the 56800E core include: DSP56800E Detailed description of the 56800E Reference Manual architecture, 16-bit DSP core processor and the instruction set Order Number: DSP56800ERM/D DSP5685x Detailed description of memory, User’s Manual peripherals, and interfaces of the 56853, 56854, 56855, 56857, and 56858 Order Number: DSP5685xUM/D Technical Data pin descriptions, and package Sheet descriptions Order Number: DSP56857/D DSP56857 Summary description and block diagram Product Brief of the core, memory, peripherals and interfaces Order Number: DSP56857PB/D PART SUPPLY P ACKAGE TYPE PIN COUNT FREQUENCY ORDER NUMBER VOLTAGE (MHz) DSP56857 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 100 120 DSP56857BU120 DSP56857 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 100 120 SPAK56857BU120 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...