SP973T8

SP973T8 ZARLINK | Alldatasheet

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Technical content

30MHz 8-BIT FLASH ADC (TTL/CMOS OUTPUTS) DS2465 - 2.3 Fig.1 Pin connections - top view Fig.2 Internal block diagram The SP973T8 is a wideband, full flash analog-to-digital converter that requires no preceding sample and hold. The device contains a full 8-bit D-type latch which ensures that the

8 TTL/CMOS outputs are accurately registered and have a

good data valid time at high clock speeds. Operating from a single +5 volt supply the device is capable of conversion rates well in excess of 30MHz and its wideband input allows signals with frequencies up to the Nyquist limit to be digitised with high accuracy. An internal bandgap voltage regulator gives low DC drift over a wide operating temperature range. The SP973T8 is designed for applications where power consumption and package size is at a premium.

FEATURES

n Flash Converter, No Sample and Hold Required n Wideband Analog Input 70MHz, 3dB (Typ.) n Low Power Consumption (600mW Typ.) n Latched TTL/CMOS Compatible Outputs n No Missing Codes - Guaranteed n Designed for Wideband Operation n Single 5V Supply n Production Tested at 30MHz

ORDERING INFORMATION

SP973T8 C DP (Commercial - Plastic DIL package)

APPLICATIONS

Supply voltage, VCC 7V Output Current 10mA Input Voltage, VIN VCC Operating Temperature 0°C to +70°C Storage Temperature -65°C to +150°C D3 D4 D2 D5 D1 D6 D0 (LSB) D7 (MSB) CLK DGND CLK OR BIAS DVCC VRB VRT AVCC VIN AGND VRM SP973T8 LSB 4 MSB 15

14 DGND

R R R R R x 256 256 8 8 CLK VRT VRM VIN VRB AVCC AGND CLK OR BIAS TTL/CMOS OUTPUTS ENCODER D LATCH TTL OUTPUT STAGE LATCH DP18

ELECTRICAL CHARACTERISTICS

These characteristics are guaranteed over the following conditions (unless otherwise stated): Tamb = 25°C, VCC = +5V ± 0.25V Full temperature range = 0°C to +70°C DC CHARACTERISTICS Full Full Full Full Full Full Full Full Full Full Full Full ICC PD VIN IIN f3db CIN RD VRT VRB VRT0 VRB0 RTC VIH IIH VIL IIL VOH VOL DNL INL 100 110 475 520 1.8 150 325 1.8 2.75 1.75 3.3 3.5 120 600 390 440 4.3 2.3 1.5 4.3 3.3 3.8 0.1 140 130 735 680 VCC-0.7 1100 550 VCC-0.7 VCC VCC-1.0 0.4 0.4 ±0.5 mA mA mW mW V mA MHz pF W V V mV mV W/°C V mA V mA V V V V LSB LSB LSB LSB Units ConditionsTemp.Symbol Test levelCharacteristic Value Min. Typ. Max. AC CHARACTERISTICS (Refer to Fig.7) Units ConditionsTemp.Symbol Test levelCharacteristic Value Min. Typ. Max. Power Supply Supply current Power dissipation Analog Input Input range Input bias current 3dB bandwidth Input capacitance Reference Ladder Ladder resistance Ladder voltage (top) Ladder voltage (bottom) Ladder offset (top) Ladder offset (bottom) Ladder temp. coeff. Clock Input Logic '1' voltage Logic '1' current Logic '0' voltage Logic '0' current Digital Outputs Logic '1' voltage Logic '0' voltage Static performance Differential non-linearity Integral non-linearity Clock min. high Clock min. low Max. conversion rate Aperture delay Output data delay Output rise time output fall time Dynamic Performance Differential non-linearity Integral non-linearity S/N ratio Effective No. of bits Bit Error Rate Full tPW1 tPW0 tAD tD tR tF DNL INL SNR ENOB BER -0.85 40.9 6.5 ±0.5 44.5 44.1 43.3 7.1 7.0 6.9 1 in 109 ns ns MHz ns ns ns ns LSB LSB dBc dBc dBc bits bits bits AIN = 15MHz at FS With FCLK = 30MHz AIN MAX = 10MHz at FS AIN MAX = 10MHz at FS AIN MAX = 1MHz at FS AIN MAX = 5MHz at FS AIN MAX = 10MHz at FS AIN MAX = 1MHz at FS AIN MAX = 5MHz at FS AIN MAX = 10MHz at FS VIN = VRT A swing of 1V centred on the voltage applied to the CLK pin Into Standard LS TTL Load

ELECTRICAL CHARACTERISTICS DEFINITIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency, as determined by Fast Fourier Transform analysis is 3dB down on the DC level. Aperture Delay The delay between the falling edge of the CLOCK signal and the instant at which the analog input is sampled. Bit Error Rate (BER) The number of spurious code errors produced for any given input sinewave frequency. In this case it is the number of codes occuring outside the histogram cusp for a 3/4 F.S. sinewave. Differential Non-Linearity (DNL) The deviation of any code width from an ideal 1LSB step. Effective Number of Bits (ENOB) This is a measure of the dynamic performance and is calculated from the following expression. ENOB = SNR-1.76 6.02 SNR is the signal-to-noise ratio, in decibels, at the test frequency. Integral Non-Linearity (INL) The deviation of the centre of each code from a reference line which has been determined by a least squares curve fit. Output Data Delay The delay between the 50% point of the falling edge of the clock signal and the 50% point of any data output change. Reference Ladder Offset The voltage error at the ends of the resistor chain caused by the lead frame and bond wire. Signal-to-Noise Ratio (SNR) The ratio of the RMS signal amplitude to the RMS value of 'noise' which is defined as the sum of all other spectral components including harmonics but excluding DC with a full scale analog input signal. Test Levels Level 1 - 100% production tested Level 2 - 100% production tested at 25 °C and sample tested at specified temperatures Level 3 - Sample tested only Level 4 - Parameter is guaranteed by design and characteristics testing Level 5 - Parameter is a typical value only

Description

Output data bits 3, 2, 1, 0 Clock input pin Clock threshold level pin Bottom of reference resistor chain Function D3, D2, D1, D0 CLK CLK VRB AVCC AGND VRM VIN VRT DVCC DGND D6, D5, D4 Pin No. 1, 2, 3, 4 16, 17, 18

5 Volt power to all circuitry except the TTL output

Middle of reference resistor chain Analog input voltage pin Top of reference resistor chain

5 Volt power supply to the TTL output stage

Most significant bit (output data bit 7) Output data bits 6, 5, 4 THERMAL CHARACTERISTICS DP Thermal resistance, chip-to-case qjc 20 °C/W Thermal resistance, chip-to-ambient qjA 75 °C/W RECOMMENDED OPERATING CONDITIONS Supply Voltage VCC +5.0V Reference VRT +4.3V Reference VRB +2.3V AVCC to DVCC 0mV AGND to DGND 0mV Analog Input VIN 2 Vp-p max PIN DESCRIPTIONS

Analog Input Pin (Fig.3) The analog input of the SP973T8 is connected to 256 comparators which have a combined capacitance of about 30pF. The sample/latch operation of the comparators causes the input capacitance to vary slightly as the comparator input transistors turn on/off. For this reason the input driver circuit should provide a low impedance signal to keep the harmonic distortion levels of the driver to a minimum. The maximum amplitude of the analog input is defined by the setting of the two reference voltages VRT and VRB. Opti- mum performance will be obtained with the input signal biased midway between VRT and VRB with a peak to peak amplitude of VRT-VRB. The SP973T8 has excellent overload tracking of input signals with amplitudes greater than V RT-VRB, and will not be damaged if the absolute maximum ratings are adhered to. Voltage Reference Pins (Fig.4) The SP973T8 converts analog signals in the range VRB<VIN<VRT into digital format, where VRB produces code 0 and VRT produces code 255. Between the pins VRT and VRB are a series of 256 resistors forming a reference chain with a total resistance of 425 W (typically). The centre point of the reference chain is also connected to an external pin named VRM by which it is possible to provide precision trimming of the integral linearity of the device. The maximum value of VRT is VCC-0.7 volts since values above this figure will start to saturate the comparator, resulting in noticeable distortion. Optimum performance from a +5 Volt power supply is obtained with VRT<+4.3V and VRB a further 2 volts below VRT. In addition the VRT, VRB and VRM pins should be decoupled to ground close to the device pins using good quality 10nf capacitors. A simple method for providing the reference voltages is shown in Fig.4, and further information may be found in applications note AN72. With a reference ladder voltage of less than 2V the reduced LSB size causes a larger differential linearity error. Operation of the device below 1.5V may therefore cause missing codes. Fig.3 One of 255 analog inputs connected to pin 11 ANALOG INPUT REF CHAIN 200µA VRB VRT 1.5W AVCC +5V DGND DATA OUTPUT 50W +5V DVCC Fig,5 TTL output stage TTL/CMOS Outputs (Fig.5) The data output levels of the SP973T8 are TTL/CMOS compatible and switch from 0V to +4V. The output circuit is capable of operation at clock frequencies in excess of 60MHz when driving into a standard LSTTL load. ADC INTERNAL RESISTOR CHAIN ADC PIN 7 ADC PIN 12 2.45V ZN458 PRECISION REFERENCE 4.3V 18k 1.5k CLAMP LEVEL FOR VIDEO Fig.4 Simple reference voltage generation

Clock Input (Fig.6) The SP973T8 will operate at clock frequencies up to and above 30MHz. The clock input has been designed to accept a 1Vpp signal, in either differential or single-ended mode, between the V IH(MAX) and V IL(MIN) levels indicated in the electrical specification. At VIH(MAX) or VIL(MIN) the CLK input will sink 800mA or source 3.2mA of current, respectively. (See Fig.6). When used in single-ended operation, CLK may be decoupled to ground so that this input will then self-bias at approximately 1.2V below the supply VCC. It may then be used to bias the CLK input, through a termination resistor, for AC- coupled applications as shown in Fig.8. Alternatively a TTL level clock may be used by inserting an appropriate value resistor in series with the coupling capacitor. TIMING (Fig.7) The analog input is sampled by the SP973T8 approximately 3ns (tAD) after the falling edge of the clock. Due to the pipeline operation of the device, a further one clock cycle is required to produce the output data. As shown in Fig.7, the output has a good data valid time, enabling the data to be latched at both the rising and falling edges of the clock. However, for clock frequencies above 25MHz the clock-to- output delay time may lead to an inadequate data set up time relative to the rising clock edge and it is therefore recommended that the output data is latched on the falling clock edge. SAMPLE N SAMPLE N+1 SAMPLE N+2 SAMPLE N+3 VIN tAD DATA VALID N DATA VALID N+1DATA VALID N-1DATA VALID N-2 PIPELINE DELAY DATA OUTPUT tD CLOCK tpw0 tpw1 tCYC Fig.7 Timing diagram 800µA 800µA CLOCK INPUT 450 450 600 +5V DIFF CLOCK 3.8V AGND CLOCK OR BIAS DECOUPLE AVCC Fig.6 Clock input stage

Circuit Board Construction (Fig.8) Excellent performance can be obtained from this ADC using only one solid ground plan for both analog and digital signals. With all flash ADCs it is important to restrict digital crosstalk into the input, not only within the wanted signal bandwidth but also at frequencies between Nyquist and clock, as such signals will be aliased down into the wanted signal bandwidth. We can give the designer two useful suggestions to reduce the above. First, due to the on-chip clock regeneration circuit, a low level clock can be fed to the ADC 1V p-p is recommended. The second suggestion is the addition of a small bead inductor in series with and close to the device analog input. Supply line decoupling is very important when dealing with a mix of analog and digital signals as they can provide a source of digital feedback from the digital output currents. It is wise, therefore, to decouple the SP973T8 close to the device supply pins with good quality, high frequency, low inductance capacitors. Due to the high clock rates involved, long clock lines to the device should be avoided to reduce the noise pick up. Fig.8 Test/application circuit S P T 172 163 154 145 136 127 118 0.1µ 10n 10n 10n 0.1µ 10n 10nF MID REF VRM NOTE: DECOUPLE CLOSE TO PINS +VE REF VRT DVCC DGND ANALOG INPUT D7 (MSB) D0 (LSB) DATA OUTPUTS (TTL/CMOS COMPATIBLE) CLOCK -VE REF VRB AVCC AGND

GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017

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• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. © GEC Plessey Semiconductors 1994 Publication No. DS2465 Issue No. 2.3 January 1994 This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.