SP705

SP813LCN-L EXAR | Alldatasheet

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Technical content

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss June 2010 Rev. 2.0.0 Exar Corporation www.exar.com 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 – Fax. +1 510 668-7001 GENERAL DESCRIPTION The SP705-708/813L series is a family of microprocessor (µP) supervisory circuits that integrate myriad comp onents involved in discrete solutions which monitor power-supply and battery in mP and digital systems. The SP705-708/813L series will significantly improve system reliability and operational efficiency when compared to solutions obtained with discr ete components. The features of the SP705-708/813L series include a watchdog timer, a µP reset, a Power Fail Comparator, and a manual-reset input. The SP705-708/813L series is ideal for applications in automotive systems, computers, controllers, and intelligent instruments. The SP705-708/813L series is an ideal solution for systems in which critical monitoring of the power supply to the µP and related digital components is demanded.

APPLICATIONS

• Processors & DSPs Based Systems
• Industrial & Medical Instruments

FEATURES

• Precision Voltage Monitor − SP705/SP707/SP813L: 4.65V − SP706/SP708: 4.40V
• 200ms RESET Pulse Width
• Independent Watchdog Timer − 1.6s Timeout (SP705/SP706/SP813L)
• 60µA Maximum Supply Current
• Debounced TTL/CMOS Manual Reset Input
• RESET Asserted Down to VCC=1.1V
• Voltage Monitor for Power Failure or Low Battery Warning
• 8-Pin PDIP, NSOIC and MSOP Packages
• Pin Compatible with Industry Standards 705-708-813L Series
• Functionally Compatible to Industry Standard 1232 Series Part Number RESET Threshold RESET Active Manual RESET Watchdog PFI Accuracy SP705 4.65V Low Yes Yes 4% SP706 4.40V Low Yes Yes 4% SP707 4.65V Low and High Yes No 4% SP708 4.40V Low and High Yes No 4% SP813L 4.65V High Yes Yes 4%

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 2/17 Rev. 2.0.0 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. V Input Current Continuous Power Dissipation ELECTRICAL SPECIFICATIONS Unless otherwise indicated, V CC = 4.75V to 5.5V (SP705-SP707-SP813L), V CC = 4.50V to 5.5V (SP706-SP708), T A= TMIN to TMAX, typical at 25°C. Parameter Min. Typ. Max. Units Conditions Operating Voltage Range VCC 1.1 5.5 V Supply Current ISUPPLY 40 60 µA MR=VCC or floating, WDI floating Reset Threshold 4.50 4.65 4.75 V SP705, SP707, SP813L 4.25 4.40 4.50 SP706, SP708 (Note 2) Reset Threshold Hysteresis 40 mV Note 2 Reset Pulse Width tRS 140 200 280 ms Note 2 RESET Output Voltage VCC-1.5 V ISOURCE=800µA, Note 2 0.8 ISOURCE=4µA, VCC=1.1V, Note 2 0.4 ISINK=3.2mA, Note 2 0.3 ISINK=100µA, VCC=1.2V, Note 2 Watchdog Timeout Period tWD 1.00 1.60 2.25 s SP705, SP707, SP813L WDI Pulse Width tWP 1 µs VIL=0.4V, VIH=0.8xVCC WDI Input Threshold Low 0.8 V SP705, SP707, SP813L VCC=5V WDI Input Threshold High 3.5 V WDI Input Current 30 75 µA SP705, SP707, SP813L, WDI=VCC -75 -20 µA SP705, SP707, SP813L, WDI=0V WDO Output Voltage VCC-1.5 V ISOURCE=800µA 0.4 ISINK=3.2mA MR Pull-up Current 100 250 600 µA MR = 0V MR Pulse Width tMR 150 ns MR Input Threshold Low 0.8 V MR Input Threshold High 2.0 MR to Reset Out Delay tMD 250 ns Note 2 PFI Input Threshold 1.20 1.25 1.30 V VCC=5V PFI Input Current -25.00 0.01 25.00 nA PFO Output Voltage VCC-1.5 V ISOURCE=800µA 0.4 ISINK=3.2mA Note 1: The input voltage limits on PFI and MR can be exceeded if the input current is less than 10mA. Note 2: Applies to both RESET in the SP705-SP708 and RESET in the SP707/708/813L/813M.

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 3/17 Rev. 2.0.0 BLOCK DIAGRAM Fig. 1: SP705-SP706-SP813L Block Diagram Fig. 2: SP707-SP708 Block Diagram

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 4/17 Rev. 2.0.0 PIN ASSIGNMENT Fig. 3: Pin Assignment PIN DESCRIPTION Name Pin Number Description SP705-SP706 SP707-SP708 SP813L SOIC MSOP SOIC MSOP DIP SOIC MR 1 3 1 3 1 Manual Reset This input triggers a reset pulse when pulled below 0.8V. This active LOW input has an internal 250µA pull-up current. It can be driven from a TTL or CMOS logic line or shorted to ground with a switch. VCC 2 4 2 4 2 +5V power supply GND 3 5 3 5 3 Ground reference for all signals PFI 4 6 4 6 4 Power-Fail Input When this voltage monitor input is less than 1.25V, PFO goes LOW. Connect PFI to ground or VCC when not in use. PFO 5 - 5 7 5 Power-Fail Output This output is LOW until PFI is less then 1.25V WDI 6 8 - - 6 Watchdog Input If this input remains HIGH or LOW for 1.6s, the internal watchdog timer times out and WDO goes LOW. Floating WDI or connecting WDI to a high-impedance tri-state buffer disables the watchdog feature. The internal watchdog timer clears whenever RESET is asserted, WDI is tri-stated, or whenever WDI sees a rising or falling edge. N.C. - - 6 8 - No Connect RESET 7 1 7 1 - Active-LOW RESET Output This output pulses LOW for 200ms when triggered and stays LOW whenever V CC is below the reset threshold (4.65V for the SP705/707/813L and 4.40V for the SP706/708). It remains LOW for 200ms after V cc rises above the reset threshold or MR goes from LOW to HIGH. A watchdog timeout will not trigger RESET unless WDO is connected to MR.

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 5/17 Rev. 2.0.0 Name Pin Number Description SP705-SP706 SP707-SP708 SP813L SOIC MSOP SOIC MSOP DIP SOIC WDO 8 2 - - 8 Watchdog Output This output pulls LOW when the internal watchdog timer finishes its 1.6s count and does not go HIGH again until the watchdog is cleared. WDO also goes LOW during low-line conditions. Whenever V CC is below the reset threshold, WDO stays LOW. However, unlike RESET, WDO does not have a minimum pulse width. As soon as VCC is above the reset threshold, WDO goes HIGH with no delay. RESET - - 8 2 7 Active-HIGH RESET Output This output is the complement of RESET. Whenever RESET is HIGH, RESET is LOW and vice-versa. Note that the SP813L has a reset output only.

ORDERING INFORMATION

Range Marking Package Packing Quantity Note 1 Note 2 SP705CN-L 0°C≤TA≤+70°C SP705C YYWWL 8-pin NSOIC Bulk Lead Free SP705CN-L/TR 0°C≤TA≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP705EN-L -40°C≤TA≤+85°C SP705E YYWWL 8-pin NSOIC Bulk Lead Free SP705EN-L/TR -40°C≤TA≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP705CU-L 0°C≤TA≤+70°C 705C YWW 8-pin MSOP Bulk Lead Free SP705CU-L/TR 0°C≤TA≤+70°C 8-pin MSOP 2.5K/Tape & Reel Lead Free SP706CN-L 0°C≤TA≤+70°C SP706C YYWWL 8-pin NSOIC Bulk Lead Free SP706CN-L/TR 0°C≤TA≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP706EN-L -40°C≤TA≤+85°C SP706E YYWWL 8-pin NSOIC Bulk Lead Free SP706EN-L/TR -40°C≤TA≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP706CU-L 0°C≤TA≤+70°C 706C YWW 8-pin MSOP Bulk Lead Free SP706CU-L/TR 0°C≤TA≤+70°C 8-pin MSOP 2.5K/Tape & Reel Lead Free SP707CN-L 0°C≤TA≤+70°C SP707C YYWWL 8-pin NSOIC Bulk Lead Free SP707CN-L/TR 0°C≤TA≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP707EN-L -40°C≤TA≤+85°C SP707E YYWWL 8-pin NSOIC Bulk Lead Free SP707EN-L/TR -40°C≤TA≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP707CU-L 0°C≤TA≤+70°C 707C YWW 8-pin MSOP Bulk Lead Free SP707CU-L/TR 0°C≤TA≤+70°C 8-pin MSOP 2.5K/Tape & Reel Lead Free SP708CN-L 0°C≤TA≤+70°C SP708C YYWWL 8-pin NSOIC Bulk Lead Free SP708CN-L/TR 0°C≤TA≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP708EN-L -40°C≤TA≤+85°C SP708E YYWWL 8-pin NSOIC Bulk Lead Free SP708EN-L/TR -40°C≤TA≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP813LCN-L 0°C≤TA≤+70°C SP813LC YYWWL 8-pin NSOIC Bulk Lead Free SP813LCN-L/TR 0°C≤TA≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP813LEN-L -40°C≤TA≤+85°C SP813LE YYWWL 8-pin NSOIC Bulk Lead Free SP813LEN-L/TR -40°C≤TA≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free SP813LCP-L 0°C≤TA≤+70°C SP813LC YWWL# 8-pin PDIP Bulk Lead Free SP813LEP-L -40°C≤TA≤+85°C SP813LE YWWL# 8-pin PDIP Bulk Lead Free “YY” = Year – “WW” = Work Week – “#” = Lot Number

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 6/17 Rev. 2.0.0 TYPICAL PERFORMANCE CHARACTERISTICS All data taken at V IN = 2.7V to 5.5V, T J = TA = 25°C, unless otherwise specified - Schematic and BOM from Application Information section of this datasheet. Fig. 4: Power-Fail Comparator De-Assertion Response Time Fig. 5: Power-Fail Comparator De-Assertion Response Time Circuit Fig. 6: Power-Fail Comparator Assertion Response Time Fig. 7: Power-Fail Comparator Assertion Response Time Circuit Fig. 8: SP705/707 RESET Output Voltage vs. Supply Voltage Fig. 9: SP705/707 RESET Output Voltage vs. Supply Voltage Circuit

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 7/17 Rev. 2.0.0 Fig. 10: SP705/707 RESET Response Time Fig. 11: SP705/707 RESET Response Time Circuit Fig. 12: SP707 RESET and RESET Assertion Fig. 13: SP707 RESET and RESET De-Assertion Fig. 14: SP707 RESET and RESET Assertion and De-Assertion Circuit

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 8/17 Rev. 2.0.0 Fig. 15: SP707/708/813L RESET Output Voltage vs. Supply Voltage Fig. 16: SP813L RESET Response Time Fig. 17: SP707/708/813L RESET Output Voltage vs. Supply Voltage and SP813L RESET Response Time Circuit

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 9/17 Rev. 2.0.0 The SP705-708/813L series provides four key functions: 1. A reset output during power-up, power- down and brownout conditions. 2. An independent watchdog output that goes LOW if the watchdog input has not been toggled within 1.6 seconds. 3. A 1.25V threshold detector for power-fail warning, low battery dete ction, or monitoring a power supply other than +5V. 4. An active-LOW manual-reset that allows RESET to be triggered by a pushbutton switch. The SP707/708 devices are the same as the SP705/706 devices except for the active-HIGH RESET substitution of the watchdog timer. The SP813L is the same as the SP705 except an active-HIGH RESET is provided rather than an active-LOW RESET. The SP705/707/813L devices generate a reset when the supply voltage drops below 4.65V. The SP706/708 devices generate a reset below 4.40V. The SP705-708/813L series is ideally suited for applications in automotive systems, intelligent instruments, and battery-powered computers and controllers. The SP705- 708/813L series is ideally applied in environments where monitoring of power supply to a µP and its related components is critical. THEORY OF OPERATION The SP705-708/813L series is a microprocessor (µP) supervisory circuit that monitors the power supplied to digital circuits such as microprocessors, microcontrollers, or memory. The series is an ideal solution for portable, battery-powered equipment that requires power supply monitoring. Implementing this series will reduce the number of components and overall complexity. The watchdog func tions of this product family will continuously oversee the operational status of a system. Th e operational features and benefits of the SP705-708/813L series are described in more detail below. RESET OUTPUT A microprocessor's reset input starts the µP in a known state. The SP705-708/813L series asserts reset during power-up and prevents code execution errors during power down or brownout conditions. On power-up, once V CC reaches 1.1V, RESET is a guaranteed logic LOW of 0.4V or less. As V CC rises, RESET stays LOW. When VCC rises above the reset threshold, an internal timer releases RESET after 200ms. RESET pulses LOW whenever VCC dips below the reset threshold, such as in a brownout condition. When a brownout condition occurs in the middle of a previously initiated reset pulse, the pulse continues for at least another 140ms. On power down, once V CC falls below the reset threshold, RESET stays LOW and is guaranteed to be 0.4V or less until V CC drops below 1.1V. The SP707/708/813L active-HIGH RESET output is simply the complement of the RESET output and is guaranteed to be valid with V CC down to 1.1V. Some µPs, such as Intel's 80C51, require an active-HIGH reset pulse. WATCHDOG TIMER The SP705/706/813L watchdog circuit monitors the µP's activity. If the µP does not toggle the watchdog input (WDI) within 1.6 seconds and WDI is not tri-stated, WDO goes LOW. As long as RESET is asserted or the WDI input is tri-stated, the watchdog timer will stay cleared and will not count. As soon as RESET is released and WDI is driven HIGH or LOW, the timer will start counting. Pulses as short as 50ns can be detected. Typically, WDO will be connected to the non- maskable interrupt input (NMI) of a µP. When V CC drops below the reset threshold, WDO will go LOW whether or not the watchdog timer had timed out. Normally this would trigger an NMI but RESET goes LOW simultaneously and thus overrides the NMI. If WDI is left unconnected, WDO can be used as a low-line output. Since floating WDI disables the internal timer, WDO goes LOW only when V CC falls below the reset threshold, thus functioning as a low-line output.

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 10/17 Rev. 2.0.0 Fig. 18: SP705/706/813L Watchdog Timing Waveforms Fig. 19: SP705/706 Timing Diagrams with WDI tri-stated. POWER-FAIL COMPARATOR The power-fail comparator can be used for various purposes because its output and non inverting input are not internally connected. The inverting input is internally connected to a 1.25V reference. To build an early-warning circuit for power failure, connect the PFI pin to a voltage divider as shown in Figure 20. Choose the voltage divider ratio so that the voltage at PFI falls below 1.25V just before the +5V regulator drops out. Use PFO t o i n t e r r u p t t h e µ P s o i t can prepare for an orderly power-down. Fig. 20: Typical Operating Circuit MANUAL RESET The manual-reset input ( MR) allows RESET to be triggered by a pushbutton switch. The switch is effectively debounced by the 140ms minimum RESET pulse width. MR is TTL/CMOS logic compatible, so it can be driven by an external logic line. MR can be used to force a watchdog timeout to generate a RESET pulse in the SP705/706/813L. Simply connect WDO to MR. Ensuring a Valid Reset Output Down to VCC=0V When V CC falls below 1.1V, the SP705/706/707/708 RESET output no longer sinks current, it becomes an open circuit. High-impedance CMOS logic inputs can drift to undetermined voltages if left undriven. If a pull-down resistor is added to the RESET pin, any stray charge or leakage currents will be shunted to ground, holding RESET LOW. The resistor value is not critical. It should be about 100KW, large enough not to load RESET and small enough to pull RESET to ground.

falls below approximately 11V. (where RESET = LOW and RESET = HIGH). Figure 23. Buffer the RESET output to other

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 12/17 Rev. 2.0.0 Fig. 23: Interfacing to Microprocessors with Bidirectional REST I/O (SP705/706/708) The SP705-708/813L series offers unmatched performance and the lowest power consumption for these industry standard devices. Refer to Figures 24 and 25 for supply current performance characteristics rated against temperature and supply voltages. Table 2 shows how the SP705-708/813L series can be used instead of the Dallas Semiconductor DS1232LP/LPS. Table 2 illustrates to a designer the advantages and tradeoffs of the SP705-708/813L series compared to the Dallas Semiconductor device. While the names of the pin descriptions may differ, the functions are the same or very similar. Unlike the DS1232, the SP705- 708/813L series has a separate watchdog output pin WDO which can be simply connected to the MR input to generate a Reset signal. The DS1232 ha s pin selectable features, while the SP705-708/813L series has more fixed functions of reset threshold and watchdog time-out delay. For most applications, the fixed functions will be preferred, with the benefit of reduced cost due to a less complex part. In addition, the SP705- 708/ 813L series has a power fail input and output function not available with the DS1232 that is useful for monitoring systems with unregulated supply voltages. The SP705- 708/813L series is avai lable in one of the industry's smallest space-saving package sizes, the MSOP. Fig. 24: Supply Current vs. Temperature Fig. 25: Supply Current vs. Supply Voltage

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 13/17 Rev. 2.0.0 Fig. 26: Device Overviw on Maxim/Dallas Semiconductor

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 14/17 Rev. 2.0.0 PACKAGE SPECIFICATION 8-PIN NSOIC

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 15/17 Rev. 2.0.0 8-PIN MSOP

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 16/17 Rev. 2.0.0 8-PIN PDIP

SSPP770055--SSPP770088--SSPP881133LL LLooww PPoowweerr MMiiccrroopprroocceessssoorr SSuuppeerrvviissoorryy CCiirrccuuiittss © 2010 Exar Corporation 17/17 Rev. 2.0.0

REVISION HISTORY

2.0.0 06/03/2010 Reformat of datasheet FOR FURTHER ASSISTANCE Email: customersupport@exar.com Exar Technical Documentation: http://www.exar.com/TechDoc/default.aspx? EXAR CORPORATION HEADQUARTERS AND SALES OFFICES

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Fremont, CA 94538 – USA Fax: +1 (510) 668-7030 www.exar.com NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and make s no representation that the circuits are free of patent infringement. Charts and schedules contai ned herein are only for illustration pu rposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the us e of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause fa ilure of the life support system or to significantly affect it s safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.