SP693ACT/TR

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Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation Low Power Microprocessor Supervisory with Battery Switch-Over SP691A/693A/800L/800M The SP691A/693A/800L/800M is a microprocessor (µP) supervisory circuit that integrates a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in µP and digital systems. The SP691A/693A/800L/800M offers complete µP monitoring and watchdog functions. The SP691A/693A/800L/800M is ideal for a low-cost battery management solution and is well suited for portable, battery-powered applications with its supply current of 35µA. The 6ns chip-enable propagation delay, the 25mA current output in battery-backup mode, and the 250mA current output in standard operation also makes the SP691A/693A/800L/800M suitable for larger scale, high-performance equipment. ■ Precision 4.65V/4.40V Voltage Monitoring ■ 200ms Or Adjustable Reset Time ■ 100ms, 1.6s Or Adjustable Watchdog Time ■ 60µA Maximum Operating Supply Current ■ 2.0µA Maximum Batter y Backup Current ■ 0.1µA Maximum Batter y Standby Current ■ Power Switching 250mA Output in Vcc Mode (0.6Ω) 25mA Output in Batter y Mode (5Ω) ■ On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 6ns CE Gate Propagation Delay ■ Voltage Monitor for Power-Fail or Low Batter y ■ Backup-Battery Monitor ■ RESET Valid to Vcc=1V ■ 1% Accuracy Guaranteed ( SP800L/800M) ■ Pin Compatible Upgrade to MAX691A/693A/ 800L/800M r e b m u N t r a P d l o h s e r h T T E S E R y c a r u c c A T E S E R y c a r u c c A I F P h c t i w S y r e t t a B -p u k c a B A 1 9 6 P S V 5 6 . 4 + V m 5 2 1 + %4 S E Y A 3 9 6 P S V 0 4 . 4 + V m 5 2 1 + %4 S E Y L 0 0 8 P S V 5 6 . 4 + V m 0 5 + %1 S E Y M 0 0 8 P S V 0 4 . 4 + V m 0 5 + %1 S E Y

DESCRIPTION

FEATURES

Now Available in Lead Free Packaging

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Terminal Voltages (with respect to GND) Input Currents noted. Typical values apply at TAMB=+25OC. S R E T E M A R A P .N I M .P Y T .X A M ST I N U SN O I T I D N O C , e g n a R e g a t l o V g n i t a r e p O V CC V r o TT A B 1E T O N , 0 5 . 5 V V , e g a t l o V t u p t u O TU O e d o M g n i t a r e p O l a m r o N n i V CC 50 . 0 - V CC 3. 0 - V CC 2. 0 - V CC 51 0 . 0 - V CC 51 . 0 - V CC 90 . 0 - V V CC I,V5.4= TUO Am52= V CC I,V5.4= TUO Am052= V CC V,V0.3= TTAB I,V8.2= TUO Am001= V CC V-ot- TUO ecnatsiseR-nO 6.0 9.0 2.1 0.2 Ω V CC V5.4= V CC V0.3= V TUO edoMpukcaB-yrettaBni V TTAB 3.0- V TTAB 52.0- V TTAB 51.0- V TTAB 1.0- V TTAB 70.0- V TTAB 50.0- V V TTAB I,V5.4= TUO Am02= V TTAB I,V8.2= TUO Am01= V TTAB I,V0.2= TUO Am5= V TTAB V-ot- TUO ecnatsiseR-nO 5 Ω V TTAB V5.4= V TTAB V8.2= V TTAB V0.2= lamroNnitnerruCylppuS I,edoMgnitarepO ccV 53 06 µA V CC V(> TTAB Ignidulcxe,)V1- TUO -yrettaBnitnerruCylppuS I,edoMpukcaB TTAB 2ETON, 100.0 0.2 µA V CC V(< TTAB V,)V2.1- TTAB Ignidulcxe,V8.2= TUO V TTAB I,tnerruCybdnatS TTAB , 3ETON 1.0- 20.0 µA V CC > V( TTAB Ignidulcxe,)V2.0+ TUO dlohserhTrevohctiwSyrettaB V TTAB 30.0+ V TTAB 30.0- V pu-rewop nwod-rewop siseretsyHrevohctiwSyrettaB 06 Vm kaePotkaeP ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

Power Dissipation Per Package

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation S R E T E M A R A P .N I M .P Y T .X A M ST I N U S N O I T I D N O C w o L t u p t u O N O T T A B e g a t l o V 1 . 0 7 . 0 4 . 0 5 . 1 V I KN I S A m 2 . 3 = I KN I S A m 5 2 = t r o h S t u p t u O N O T T A B t n e r r u C t i u c r i C 1 0 6 5 1 001 A m µA t n e r r u c k n i s t n e r r u c e c r u o s R E M I T G O D H C T A W D N A , E N I L W O L , T E S E R e g a t l o V d l o h s e r h T t e s e R 0 5 . 4 5 2 . 4 0 6 . 4 5 3 . 4 5 6 . 4 0 4 . 4 5 6 . 4 0 4 . 4 5 7 . 4 0 5 . 4 0 7 . 4 5 4 . 4 V A 1 9 6 P S A 3 9 6 P S L 0 0 8 P S M 0 0 8 P S s i s e r e t s y H d l o h s e r h T t e s e R 5 1 V m k a e p -o t -r e t n e c V CC y a l eD T E S E R o t 0 8 µs n w o d r e w o p y a l e D T E S E R o t E N I L W O L 0 0 8 s n n w o d r e w o p d o i r e P t u o e m i T e v i t c A t e s e R r o t a l l i c s O l a n r e t n I e h t r o f 0 4 1 00 2 08 2 s m p u -r e w o p d o i r e P t u o e m i T e v i t c A t e s e R , k c o l C l a n r e t x E e h t r o f

4 E T O N

s e l c y c p u -r e w o p r o f d o i r e P t u o e m i T g o d h c t a W r o t a l l i c s O l a n r e t n I e h t 0 . 1 0 7 6 . 1 0 0 1 5 2 . 2 0 4 1 c e s s m d o i r e p g n o l d o i r e p t r o h s r o f d o i r e P t u o e m i T g o d h c t a W

4 E T O N , k c o l C l a n r e t x E e h t

t u p n I g o d h c t a W m u m i n i M h t d i W e s l u P 0 0 1 s n V LI V , V 8 . 0 = HI V x 5 7 . 0 = CC e g a t l o V t u p t u O T E S E R 5 . 3 4 0 0 . 0 1 . 0 3 . 0 4 . 0 V I KN I S 05 = µ V , A CC V, V 1 = CC g n i l l a f I KN I S V, A m 2 . 3 = CC V5 2 . 4 = I EC R U O S V, A m 6 . 1 = CC V5 = t i u c r i C -t r o h S t u p t u O T E S E R t n e r r u C 7 02 A m t n e r r u c e c r u o s t u p t u o , w o L e g a t l o V t u p t u O T E S E R 5 E T O N 1 . 0 4. 0 V I KN I S A m 2 . 3 = e g a t l o V t u p t u O E N I L W O L 5 . 3 1 . 0 4. 0 V I KN I S V, A m 2 . 3 = CC V5 2 . 4 = I EC R U O S 1= µ V , A CC V5 = t r o h S t u p t u O E N I L W O L t n e r r u C t i u c r i C 5 1 001 µA t n e r r u c e c r u o s t u p t u o e g a t l o V t u p t u O O D W 5 . 3 1 . 0 4. 0 V I KN I S A m 2 . 3 = I EC R U O S 00 5 = µ V, A CC V5 = t i u c r i C -t r o h S t u p t u O O D W t n e r r u C 3 01 A m t n e r r u c e c r u o s t u p t u o noted. Typical values apply at TAMB=+25OC.

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation S R E T E M A R A P .N I M .P Y T .X A M ST I N U SN O I T I D N O C , e g a t l o V d l o h s e r h T I D W

6 E T O N

V x 5 7 . 0 CC 8 . 0 V V H I V L I t n e r r u C t u p n I I D W 0 5 - 01 - 0 2 05 µA V 0 =I D W V =I D W TU O R O T A R A P M O C L I A F -R E W O P d l o h s e r h T t u p n I I F P 0 0 2 . 1 5 2 2 . 1 5 2 . 1 5 2 . 1 0 0 3 . 1 5 7 2 . 1 V A 3 9 6 /A 1 9 6 P S V, CC V5 = M 0 0 8 /L 0 0 8 P S V, C C V5 = t n e r r u C e g a k a e L I F P + 10 . 0 + 52 A n e g a t l o V t u p t u O O F P 5 . 3 1 . 0 4. 0 V I KN I S A m 2 . 3 = I EC R U O S 1= µ V, A CC V5 = t n e r r u C t i u c r i C t r o h S O F P 0 6 5 1 001 A m µA t n e r r u c k n i s t u p t u o t n e r r u c e c r u o s t u p t u o y a l e D O F P -o t -I F P 5 2 0 6 µs V DO V m 5 1 = V D O V m 5 1 = G N I T A G E L B A N E -P I H C E C NI t n e r r uC e g a k a e L + 50 0 . 0 +1 µA e d o m e l b a s i d E C NI EC o t TU O , e c n a t s i s e R

7 E T O N 56 05 1 Ω e d om e l b a n e

E C TU O t n e r r u C t i u c r i C -t r o h S ) e v i t c A T E S E R ( 1 . 0 57 . 0 0. 2 A m E C , e d o m e l b a s i d TU O V0 = E C NI EC o t TU O n o i t a g a p o r P

8 E T O N , y a l e D 6 01 s n 05 Ω C , r e v i r d e c n a d e p m i e c r u o s D A O L F p 0 5 =

E C TU O h g i H e g a t l o V t u p t u O ) e v i t c A T E S E R ( 5 . 3 7 . 2 V V CC I, V 5 = TU O 00 1 = µA V CC V, V 0 = TT A B I, V 8 . 2 = TU O 1= µA E C o t T E S E R TU O y a l e D 2 1 µs n w o d -r e w o p R O T A L L I C S O L A N R E T N I C S O NI t n e r r uC e g a k a e L 0 1 . 0 + 0. 5 µA C S O LE S V0 = C S O NI t n e r r u C p U -l l u P t u p n I 01 001 µA C S O LE S V= TU O CS O , g n i t a o l f r o NI V0 = C S O LE S t n e r r u C p U -l l u P t u p n I 01 001 µA C S O LE S V0 = C S O NI e g n aR y c n e u q e r F 0 0 2 zH k CS O LE S V0 = C S O NI r o t a l l i c sO l a n r e t x E e g a t l o V d l o h s e r h T V TU O 3. 0 - V TU O 6. 0 - 5 6 . 3 0. 2 V V H I V LI C S O NI h t iw y c n e u q e r F r o t i c a p a C l a n r e t x E 2 zH k CS O LE S C, V 0 = CS O F p 7 4 = noted. Typical values apply at TAMB=+25OC. 1.237 1.263

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation Pin 1 — VBATT — Battery-Backup Input. Con- nect to the external battery supply or super- charging capacitor and charging circuit. If a backup battery is not provided, connect this pin to ground. Pin 2 —V OUT — Output Supply Voltage. V OUT connects to V CC when V CC is greater than V BATT and VCC is above the reset threshold. When V CC falls below V BATT and V CC is below the reset threshold, V OUT connects to V BATT . Connect a 0.1µF capacitor from V OUT to GND. Pin 3 — VCC — +5V Input Supply Voltage. Pin 4 — GND — Ground reference for all signals. Pin 5 — BATT ON — Battery On Output. Goes high when V OUT switches to V BATT . Goes low when V OUT switches to V CC . Connect the base of a PNP through a current-limiting resistor to BATT ON for V OUT current requirements greater than 250mA. Pin 6 — LOWLINE — Low Line Output. This output pin goes LOW when VCC falls below the reset threshold voltage. This output pin returns to its HIGH output as soon as VCC rises above the reset threshold voltage. PINOUT Pin 7 — OSC IN — External Oscillator Input. When OSC SEL is unconnected or driven HIGH, a 10µA pull-up connects from VOUT to this input pin, the internal oscillator sets the reset and watchdog timeout periods, and this input pin selects between fast and slow watchdog timeout periods. When OSC SEL is driven LOW, the reset and watchdog timeout periods may be set either by a capacitor from this input pin to ground or by an external clock at this pin (refer to Figure 21). Pin 8 — OSC SEL — Oscillator Select. When OSC SEL is unconnected or driven HIGH, the internal oscillator sets the reset delay and watchdog timeout period. When OSCSEL is driven LOW, the external oscillator input pin, OSC IN, is enabled (refer to Table 1). This input pin has a 10µA internal pull-up. Pin 9 — PFI — Power-Fail Input. This is the noninverting input to the pow er-fail comparator. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or V OUT when not used. Pin 10 — PFO — Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry. Pin 11 — WDI — Watchdog Input. This is a three-level input pin. If WDI remains either HIGH or LOW for longer than the watchdog timeout period, WDO goes LOW and RESET is asserted for the reset timeout period. WDO remains LOW until the next transition at this input pin. Leaving this input pin unconnected disables the watchdog function. This input pin connects to an internal voltage divider between V OUT and ground, which sets it to mid-supply when left unconnected. VBATT VOUT Vcc GND BATT ON PFO PFI OSCIN RESET WDO CEIN CEOUT WDILOWLINE DIP/SO TOP VIEW Corporation RESET OSCSEL PIN ASSIGNMENTS

input pin to the chip-enable gating circuit. H IG H on the next transition at W D I. Pin 15 — RESET — Active LOW Reset Output. Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M

Figure 17. Typical Application Circuit of the SP691A/693A/800L/800M toggled within a specified time.

RESET will generate 200ms pulses every 1.6s. WDO has a 2 x TTL output characteristic. period and 200m s reset tim out period. period remains 200ms. Refer to Figure 20. be found in Figure 21 and Table 1. gate is enabled and passes all CE transitions. gate from CEIN to CEOUT . Refer to Figure 16. 800M devices to be used with most µPs. while RESET and/or RESET are asserted. whichever occurs first. Refer to Figure 19. impedance until RESET is deasserted. currents into CEIN are <1µA over temperature. Figure 22. For minimum propagation delay, a low output-impedance driver. Table 1. Reset Pulse Width and Watchdog Timeout Selections

transmission gate is enabled. reset threshold comparator. Refer to Figure 16. threshold, LOWLINE is pulled to V OUT . is easily accessible as shown in Figure 17. input leakage of +25nA max over temperature. input to ground if PFI is not used. applications. Refer to Figure 17.

4 CLOAD

Figure 22. Chip Enable Propagation Delay Test Circuit Figure 23. Low-Battery Indicator Circuit

via a parallel diode and a large PMOS switch. power-on transients may reach a maximum of 1A. diode are much smaller. Refer to Figure 24. the switch are each approximately 10Ω. Table 2. Input and Output Status in Battery-Backup Mode; to enter the Battery-Backup Mode, VCC must be less than the reset threshold and less than VBATT . Figure 24. VCC and VBATT to VOUT Switch

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation PACKAGE: 16 PIN NSOIC TOP VIEW b Gauge Plane L1 L Ø Ø1 Ø Seating Plane VIEW C A A1 SEE VIEW C B B SECTION B-B WITH PLATING c BASE METAL b SYMBOL MIN NOM MAX A 1.35 - 1.75 A1 0.1 - 0.25 A2 1.25 - 1.65 b 0.31 - 0.51 c 0.17 - 0.25 D E e L 0.4 - 1.27 ø 0º - 8º ø1 5º - 15º Note: Dimensions in (mm)

1.27 BSC

1.04 REF

0.25 BSC

16 Pin NSOIC JEDEC MO-012 (AC) Variation

9.90 BSC

6.00 BSC

3.90 BSC

E E/2 INDEX AREA (D/2 X E1/2) E1/2 D e SIDE VIEW Seating Plane

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation PACKAGE: 16 PIN WSOIC A A2 A1 SIDE VIEW Seating Plane SYMBOL MIN NOM MAX A 2.35 - 2.65 A1 0.1 - 0.3 A2 2.05 - 2.55 b 0.31 - 0.51 c 0.2 - 0.33 D E e L 0.4 - 1.27 ø 0º - 8º ø1 5º - 15º Note: Dimensions in (mm)

16 Pin SOIC JEDEC MS-013 (AA) Variation

10.30 BSC

10.30 DSC

7.50 BSC

L Ø Ø1 Seating Plane Gauge Plane VIEW C TOP VIEW e E E/2 bINDEX AREA (D/2 X E1/2) E1/2 D 1 2 3 B B SEE VIEW C c WITH PLATING BASE METAL b SECTION B-B

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation PACKAGE: 16 PIN PDIP eA eB E D L b b2eb3 N 1 2 3 INDEX AREA N/2 E E1 C b SYMBOL MIN NOM MAX A - - 0.21 A1 0.15 - - A2 0.115 0.13 0.195 b 0.014 0.018 0.022 b2 0.045 0.06 0.07 b3 0.3 0.039 0.045 c 0.008 0.01 0.014 D 0.735 0.75 0.755 D1 0.005 - - E 0.3 0.31 0.325 E1 0.24 0.25 0.28 e eA eB - - 0.43 L 0.115 0.13 0.15 Note: Dimensions in (mm) .100 BSC .300 BSC

16 PIN PDIP JEDEC MS-001 (BB) Variation

A c

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation Part Number Temperature Range Package Type Corporation ANALOG EXCELLENCE Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Sipex Corporation Headquarters and Sales Office

233 South Hillview Drive

Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

ORDERING INFORMATION

Available in lead free packaging. To order add “-L” suffix to part number. Example: SP691AEN/TR = standard; SP691AEN-L/TR = lead free /TR = Tape and Reel Pack quantity is 2500 for NSOIC and WSOIC. CLICK HERE TO ORDER SAMPLES

Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation Part Number Temperature Range Package Type Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Available in lead free packaging. To order add “-L” suffix to part number. Example: SP800MEN/TR = standard; SP800MEN-L/TR = lead free /TR = Tape and Reel Pack quantity is 2500 for NSOIC and WSOIC.