SP6654 EXAR | Alldatasheet
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Technical content
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation SP6654
FEATURES
■ Ultra-low 20µA Quiescent Current ■ 98% Efficiency Possible ■ 800mA Output Current ■ 2.7V to 5.5V Input Voltage Range ■ Output Adjustable Down to 1.0V ■ No External FET’s Required ■ 1.25A Inductor Peak Current Limit ■ 100% Duty Ratio Low Dropout Operation ■ 80µA Light Load Quiescent Current in Dropout ■ Logic Shutdown Control ■ Programmable UVLO ■ Small 10 pin MSOP Package ■ Power Good Indicator ■ Industry Standard 10 Pin MSOP and and Small DFN Package High Efficiency 800mA Synchronous Buck Regulator
APPLICATIONS
■ PDA's ■ DSC's ■ MP3 Players ■ USB Devices ■ Point of Use Power The SP6654 is a 800mA synchronous buck regulator which is ideal for portable applications that use a Li-Ion or 3 cell alkaline/NiCD/NiMH input. The SP6654’s proprietary control loop, 20µA light load quiescent current, and 0.3Ω power switches provide excellent efficiency across a wide range of output currents. As the input battery supply decreases towards the output voltage the SP6654 seamlessly transitions into 100% duty ratio operation further extending useful battery life. The SP6654 is protected against overload and short circuit conditions with a precise inductor peak current limit. Other features include programmable under voltage lockout, externally pro- grammed output voltage down to 1.0V, logic level shutdown control, and an open drain power good indicator when V OUT is above 94% of its programmed value. PWR GD VI VO 22µF 10µH VOUT 800mA 2.7V to 5.5V Input 10Ω 1µF SP6654 PVIN PWR GD LX GND VOUT FB PGNDVIN 22µF C IN CV IN C OUT R VIN R F CF 22pF R I 200K Ideal for portable designs powered with Li Ion battery TYPICAL APPLICATION SCHEMATIC
DESCRIPTION
10 Pin DFN
P GND GND V OUT FB Now Available in Lead Free Packaging
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation VIN=PV IN=VSDN =3.6V, VOUT =VFB , IO = 0mA, TAMB = -40°C to +85°C, The ♦ denotes the specifications which apply over the full operating temperature range, unless otherwise specified. ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
ELECTRICAL CHARACTERISTICS
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Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation V IN=PV IN=V SDN =3.6V, VOUT =V FB , IO = 0mA, TAMB = -40°C to +85°C, The ♦ denotes the specifications wich apply over the full operating temperature range, unless otherwise specified. RETEMARAPN IMP YTX AMS TINUS NOITIDNOC tuokcoLegatlovrednUOLVU V,dlohserhT NI gnillaf 55.20 7.25 8.2 V ♦ V=0D,V0=1D NI 07.25 8.20 0.3 ♦ V=1D NI V0=0D, 58.20 0.35 1.3 ♦ V=1D NI V=0D, NI siseretsyhOLVU0 4V mT BMA C°72= egatloVtuptuOwoLDGRWP4 .0V ♦ V NI I,V3.3= KNIS Am1= tnerruCegakaeLDGRWP1 A µ ♦ V6.3=DGRWPV dlohserhTgnisiRDGRWP6 -% ,%6-egatloVteSBF T BMA C°72= sisiretsyHDGRWP0 8V mT BMA C°72= tnerruCegakaeL0D,1D1 0 05A n ♦ egatloVdlohserhTtupnI0D,1D 06.00 9.0 V ♦ noitisnarTwoLothgiH 52.18 .1 ♦ noitisnarThgiHotwoL tnerruCegakaeLBF1 0 01A nV 1=BF D1 D0 00 Shutdown. All internal circuitry is disabled and the power switches are opened. 01 Device enabled, falling UVLO threshold =2.70V 10 Device enabled, falling UVLO threshold =2.85V 11 Device enabled, falling UVLO threshold =3.00V Table 1. Operating Mode Definition
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation PIN DESCRIPTION PIN NUMBER PIN NAME DESCRIPTION 1P V IN Input voltage power pin. Inductor charging current passes through this pin. 2V IN Internal supply voltage. Control circuitry powered from this pin. 3 PWR GD Open drain Power Good indicator. If VFB is less than 750mV this pin is pulled to ground. When VFB is above 750mV this pin is open. Connect a resistor from this pin to VIN or VOUT to create a logic signal. 4D 1 Digital mode control input. See table I for definition. 5D 0 Digital mode control input. See table I for definition. 6F B External feedback network input connection. Connect a resistor from FB to ground and FB to VOUT to set the output voltage. This pin regulates to the internal bandgap reference voltage of 0.8V. 7V OUT Output voltage sense pin. Used by the timing circuit to set minimum on and off times. 8 GND Internal ground pin. Control circuitry returns current to this pin. 9P GND Power ground pin. Synchronous rectifier current returns through this pin. 10 LX Inductor switching node. Inductor tied between this pin and the output capacitor to create regulated output voltage. FUNCTIONAL DIAGRAM FB Zero_X DRVON QR QS Min Ton PWRGD PVIN OVR_I MIN Ton OVR_IKOFF/VOUT Vin LX TOFF = UVLO BLANK = Tblank(=100ns) or Toff = Koff/Vout ILIM/M REF VOLOW FB +- VRAMP RST PGND TSD BLANK 750mV - C UVLO TONOVER Internal Supply REF' OVR_I VOUT - C DRVON BLANK ILIM/M VOLOW - C TONOVER Min Ton = KON/(VIN -VOUT) Ref One-Shot DRVON - C Block FB' GND REF M Vos DRIVER DRVON =100ns
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation OPERATION The SP6654 is a high efficiency synchronous buck regulator with an input voltage range of +2.7V to +5.5V and an output that is adjustable between +1.0V and V IN. The SP6654 features a unique on-time control loop that runs in discon- tinuous conduction mode (DCM) or continuous conduction mode (CCM) using synchronous rectification. Other features include, over-cur- rent protection, digitally controlled enable and under-voltage lockout, an external feedback pin, and a power good indicator. The SP6654 operates with a light load quiescent current of 20µA using a 0.3Ω PMOS main switch and a 0.3Ω NMOS synchronous switch. It operates with excellent efficiency across the entire load range, making it an ideal solution for battery powered applications and low current step-down conversions. The part smoothly tran- sitions into a 100% duty cycle under heavy load/ low input voltage conditions. On-Time Control - Charge Phase The SP6654 uses a precision comparator and a minimum on-time to regulate the output voltage and control the inductor current under normal load conditions. As the feedback pin drops be- low the regulation point, the loop comparator output goes high and closes the main switch. The minimum on-timer is triggered, setting a logic high for the duration defined by: T ON = KON V IN - VOUT where: K ON = 2.25V*µsec constant V IN = VIN pin voltage V OUT = VOUT pin voltage To accommodate the use of ceramic and other low ESR capacitors, an open loop ramp is added to the feedback signal to mimic the inductor current ripple. The following waveforms de- scribe the ideal ramp operation in both CCM and DCM operation. In either CCM or DCM, the negative going ramp voltage (V RAMP in the functional diagram) is added to FB and this creates the FB's signal. This FB signal is applied to the negative termi- nal of the loop comparator. To the positive terminal of the loop comparator is applied the REF voltage of 0.8V plus an offset voltage Vos to compensate for the DC level of V RAMP ap- plied to the negative terminal. The result is an internal ramp with enough negative going offset (approximately 50mV) to trip the loop com- parator whenever FB falls below regulation. The output of the loop comparator, a rising VOLOW, causes a SET if BLANK = 0 and OVR_I = 0. This starts inductor charging (DRVON = 1) and starts the minimum on-timer. The minimum on-timer times out and indicates DRVON can be reset if the voltage loop is satisfied. If V OUT is still below the regulation point RESET is held low until VOUT is above DRVON REF, FB VOSREF’ FB’ I(L1) RAMP: DCM OPERATION DRVON REF, FB VOS REF’FB’ I(L1) RAMP: CCM OPERATION
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation regulation. Once RESET occurs TON minimum is reset, and the TOFF one-shot is triggered to blank the loop comparator from starting a new charge cycle for a minimum period. This blank- ing period occurs during the noisy LX transition to discharge, where spurious comparator states may occur. For T OFF > TBLANK the loop is in a discharge or wait state until the loop comparator starts the next charge cycle by DRVON going high. If an over current occurs during charge the loop is interrupted and DRVON is RESET. The off- time one-shot pulse width is widened to TOFF = K OFF / VOUT , which holds the loop in discharge for that time. At the end of the off-time the loop is released and controlled by VOLOW. In this manner maximum inductor current is controlled on a cycle-by-cycle basis. An assertion of UVLO (undervoltage lockout) or TSD (thermal shut- down) holds the loop in no-charge until the fault has ended. On-Time Control - Discharge Phase The discharge phase follows with the high side PMOS switch opening and the low side NMOS switch closing to provide a discharge path for the inductor current. The decreasing inductor current and the load current cause the output voltage to drop. Under normal load conditions when the inductor current is below the pro- grammed limit, the off-time will continue until the output voltage falls below the regulation threshold, which initiates a new charge cycle via the loop comparator. The inductor current “floats” in continuous con- duction mode. During this mode the inductor peak current is below the programmed limit and the valley current is above zero. This is to satisfy load currents that are greater than half the mini- mum current ripple. The current ripple, I LR , is defined by the equation: ILR ≈ K ON * VIN - VOUT - IOUT * R CH L VIN - VOUT where: L = Inductor value IOUT = Load current R CH = PMOS on resistance, 0.3Ω typ. If the IOUT * RCH term is negligible compared with (VIN - VOUT ), the above equation simplifies to: ILR ≈ KON L For most applications, the inductor current ripple controlled by the SP6654 is constant regardless of input and output voltage. Because the output voltage ripple is equal to: V OUT (ripple) = ILR * RESR where: R ESR = ESR of the output capacitor the output ripple of the SP6654 regulator is independent of the input and output voltages. For battery powered applications, where the battery voltage changes significantly, the SP6654 provides constant output voltage ripple through- out the battery lifetime. This greatly simplifies the LC filter design. The maximum loop frequency in CCM is de- fined by the equation: F LP ≈ (VIN - VOUT ) * (VOUT + IOUT * RDC ) KON * [VIN + IOUT * (RDC - RCH )] where: FLP = CCM loop frequency R DC = NMOS on resistance, 0.3Ω typ. Ignoring conduction losses simplifies the loop frequency to: FLP ≈ 1 * VOUT * (VIN - VOUT ) KON VIN AND’ing the loop comparator and the on-timer reduces the switching frequency for load cur- rents below half the inductor ripple current. This increases light load efficiency. The minimum on-time insures that the inductor current ripple is a minimum of K ON /L, more than the load OPERATION: Continued
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation current demands. The converter goes in to a standard pulse frequency modulation (PFM) mode where the switching frequency is propor- tional to the load current. Low Dropout and Load Transient Operation AND’ing the loop comparator also increases the duty ratio past the ideal D= VOUT /VIN up to and including 100%. Under a light to heavy load transient, the loop comparator will hold the main switch on longer than the minimum on timer until the output is brought back into regu- lation. Also, as the input voltage supply drops down close to the output voltage, the main MOSFET resistance loss will dictate a much higher duty ratio to regulate the output. Eventually as the input voltage drops low enough, the output voltage will follow, causing the loop compara- tor to hold the converter at 100% duty cycle. This mode is critical in extending battery life when the output voltage is at or above the minimum usable input voltage. The dropout voltage is the minimum (V IN -VOUT ) below which the output regulation cannot be main- tained. The dropout voltage of SP6654 is equal to IL* (0.3Ω+ RL1) where 0.3Ω is the typical R DS(ON) of the P-Channel MOSFET and RL is the DC resistance of the inductor. The SP6654 has been designed to operate in dropout with a light load Iq of only 80µA. The on-time control circuit seamlessly operates the converter between CCM, DCM, and low drop- out modes without the need for compensation. The converter’s transient response is quick since there is no compensated error amplifier in the loop. Inductor Over-Current Protection To reduce the light load dropout Iq, the SP6654 over-current system is only enabled when IL1 > 400mA. The inductor over-current protection circuitry is programmed to limit the peak induc- tor current to 1.25A. This is done during the on- time by comparing the source to drain voltage drop of the PMOS passing the inductor current with a second voltage drop representing the maximum allowable inductor current. As the two voltages become equal, the over-current comparator triggers a minimum off-time one shot. The off-time one shot forces the loop into the discharge phase for a minimum T OFF time causing the inductor current to decrease. At the end of the off-time, loop control is handed back to the AND’d on-time signal. If the output voltage is still low, charging begins until the output is in regulation or the current limit has been reached again. During startup and over- load conditions, the converter behaves like a current source at the programmed limit minus half the current ripple. The minimum T OFF is controlled by the equation: TOFF (MIN) = K OFF V OUT Under-Voltage Lockout The SP6654 is equipped with a programmable under-voltage lockout to protect the input bat- tery source from excessive currents when sub- stantially discharged. When the input supply is below the UVLO threshold both power switches are open to prevent inductor current from flow- ing. The three levels of falling input voltage UVLO threshold are shown in Table 1, with a typical hysteresis of 120mV to prevent chatter- ing due to the impedance of the input source. During UVLO, PWR GD is forced low. Under-Current Detection The synchronous rectifier is comprised of an inductor discharge switch, a voltage compara- tor, and a driver latch. During the off-time, positive inductor current flows into the PGND pin 9 through the low side NMOS switch to LX pin 10, through the inductor and the output capacitor, and back to pin 9. The comparator monitors the voltage drop across the discharge NMOS. As the inductor current approaches zero, the channel voltage sign goes from negative to positive, causing the comparator to trigger the driver latch and open the switch to prevent OPERATION
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation For the typical SP6654 application circuit with inductor size of 10µH, and KON of 2V*µsec, the SP6654 current ripple would be about 200mA, and inductor current reversal. This circuit along with the on-timer puts the converter into PFM mode and improves light load efficiency when the load current is less than half the inductor ripple current defined by K ON /L. Shutdown/Enable Control The D0, D1 pins 4,5 of the device are logic level control pins that according to Table 1 shut down the converter when both are a logic low, or enables the converter when either are a logic high. When the converter is shut down, the power switches are opened and all circuit bias- ing is extinguished leaving only junction leak- age currents on supply pins 1 and 2. After pins 4 or 5 are brought high to enable the converter, there is a turn on delay to allow the regulator circuitry to reestablish itself. Power conversion begins with the assertion of the internal refer- ence ready signal which occurs approximately 150µs after the enable signal is received. Power Good Indicator A power good indicator looks at the voltage on the feedback node. When this voltage is below 0.75V, the open drain NMOS on pin 3 sinks current to ground. Tying a resistor from pin 3 to V IN or VOUT creates a logic level power good indicator. PWRGD is forced low when in UVLO. External Feedback Pin The FB pin 6 is compared to an internal refer- ence voltage of 0.8V to regulate the SP6654 output. The output voltage can be externally programmed within the range +1.0V to +5.0V by tying a resistor from FB to ground and FB to V OUT (pin7). See the applications section for resistor selection information. Inductor Selection The SP6654 uses a specially adapted minimum on-time control of regulation utilizing a preci- sion comparator and bandgap reference. This adaptive minimum on-time control has the ad- vantage of setting a constant current ripple for a given inductor size. From the operations section it has been shown: Inductor Current Ripple, I LR ≈ K ON L OPERATION: Continued
APPLICATION INFORMATION
would be fairly constant for different input and output voltages, simplifying the selection of com- ponents for the SP6654 power circuit. Other inductor values could be selected, as shown in Table 2 Components Selection. Using a larger value than 10µH in an attempt to reduce output voltage ripple would reduce inductor current ripple and may not produce as stable an output ripple. For larger inductors with the SP6654, which has a peak inductor current of 1.25A, most 15µH or 22µH inductors would have to be larger physi- cal sizes, limiting their use in small portable applications. Smaller values like 6.8µH would more easily meet the 1.25A limit and come in small case sizes, and the increased inductor
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation For the 22µF POSCAP with 0.04Ω ESR, and a 10µH inductor yielding 200mA inductor current ripple ILR , the VOUT ripple would be 8mVpp. Since 8mV is a very small signal level, the actual value would probably be larger due to noise and layout issues, but this illustrates that the SP6654 output ripple can be very low indeed. To improve stability, a small ceramic capacitor, C F = 22pF should be paralleled with the feedback voltage divider RF, as shown on the typical application schematic on page 1. Another function of the output capacitance is to hold up the output voltage during the load transients and prevent excessive overshoot and undershoot. The typical perfor- mance characteristics curves show very good load step transient response for the SP6654 with the recommended output capacitance of 22µF ce- ramic. The input capacitor will reduce the peak current drawn from the battery, improve efficiency and significantly reduce high frequency noises in- duced by a switching power supply. The typical input capacitor for the SP6654 is 22µF ceramic, POSCAP or Aluminum Polymer. These capaci- tors will provide good high frequency bypassing and their low ESR will reduce resistive losses for higher efficiency. An RC filter is recommended for the V IN pin 2 to effectively reduce the noise for the ICs analog supply rail which powers sensitive circuits. This time constant needs to be at least 5 times greater than the switching period, which is calculated as 1/FLP during the CCM mode. The typical application schematic uses the values of R VIN = 10Ω and CVIN = 1µF to meet these require- ments. current ripple of almost 300mA would produce very stable regulation and fast load transient response at the expense of slightly reduced efficiency. Other inductor parameters are important: the in- ductor current rating and the DC resistance. When the current through the inductor reaches the level of I SAT , the inductance drops to 70% of the nominal value. This non-linear change can cause stability problems or excessive fluctuation in in- ductor current ripple. To avoid this, the inductor should be selected with saturation current at least equal to the maximum output current of the con- verter plus half the inductor current ripple. To provide the best performance in dynamic condi- tions such as start-up and load transients, inductors should be chosen with saturation current close to the SP6654 inductor current limit of 1.25A. DC resistance, another important inductor charac- teristic, directly affects the efficiency of the con- verter, so inductors with minimum DC resistance should be chosen for high efficiency designs. Recommended inductors with low DC resistance are listed in table 2. Preferred inductors for on board power supplies with the SP6654 are mag- netically shielded types to minimize radiated mag- netic field emissions. Capacitor Selection The SP6654 has been designed to work with very low ESR output capacitors (listed in Table 2 Component Selection) which for the typical appli- cation circuit are 22µF ceramic, POSCAP or Alu- minum Polymer. These capacitors combine small size, low ESR and good value. To regulate the output with low ESR capacitors of 0.01Ω or less, an internal ramp voltage V RAMP has been added to the FB signal to reliably trip the loop comparator (as described in the Operations section). Output ripple for a buck regulator is determined mostly by output capacitor ESR, which for the SP6654 with a constant inductor current ripple can be expressed as: V OUT (ripple) = ILR * R ESR
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation The output voltage is programmed by the external divider, as shown in the typical application circuit on page 1. First pick a value for RI that is no larger than 300K. Too large a value of RI will reduce the AC voltage seen by the loop comparator since the internal FB pin capacitance can form a low pass filter with RF in parallel with RI. The formula for R F with a given RI and output voltage is: R F = ( V OUT - 1 ) • RI 0.8V Output Voltage Ripple Frequency An important consideration in a power supply application is the frequency value of the output ripple. Given the control technique of the SP6654 (as described in the operations section), the frequency of the output ripple will vary when in light to moderate load in the discontinuous or PFM mode. For moderate to heavy loads greater than about 100mA inductor current ripple, (for the typical 10µH inductor application on 100mA is half the 200mA inductor current ripple), the output ripple frequency will be fairly constant. From the operations section, this maximum loop frequency in continuous conduction mode is: 1 V OUT (V IN - VOUT )FLP ≈ K ON V IN Data for loop frequency, as measured from output voltage ripple frequency, can be found in the typical performance curves. Layout Considerations Proper layout of the power and control circuits is necessary in a switching power supply to obtain good output regulation with stability and a mini- mum of output noise. The SP6654 application circuit can be made very small and reside close to the IC for best performance and solution size, as long as some layout techniques are taken into consideration. To avoid excessive interference between the SP6654 high frequency converter and INDUCTORS SURFACE MOUNT Inductor Specification Inductance Manufacturer/Part No. Series R Ω ISAT (A) Size Inductor Type Manufacturer (µH) LxW(mm) Ht. (mm) Website CAPACITORS - SURFACE MOUNT Capacitor Specification Capacitance Manufacturer/Part No. ESR RippleCurrent Si ze Voltage Capacitor Type Manufacturer (µF) Ω (max) (A) @ 45°C LxW(mm) Ht. (mm) (V) Website Table 2 Component Selection Note: Components highlighted in bold are those used on the SP6654 Evaluation Board.
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation PACKAGE: 10 PIN MSOP e Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2) L ØØ1 R Seating Plane Gauge PlaneL2 B B SYMBOL MIN NOM MAX A- - 1.1 A1 0 - 0.15 A2 0.75 0.85 0.95 b 0.17 - 0.27 c 0.08 - 0.23 D E e L 0.4 0.6 0.8 N- 1 0 - R 0.07 - - R1 0.07 - - ø0 º - 8 º ø1 0º - 15º Note: Dimensions in (mm)
10 Pin MSOP JEDEC MO-187 (BA) Variation
3.00 BSC
4.90 BSC
0.50 BSC
2.00 BSC
0.95 REF
0.25 BSC
E D c WITH PLATING BASE METAL b Section B-B A2 A b
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation PACKAGE: 10 PIN DFN SYMBOL MIN NOM MAX A 0.8 0.9 1 A1 0 0.02 0.05 A2 0.55 0.65 0.8 b 0.18 0.25 0.3 D D2 2.2 2.7 e E E2 1.4 - 1.75 K 0.2 - - L 0.3 0.4 0.5 Note: Dimensions in (mm) 3x3 10 Pin DFN JEDEC MO-229 (VEED-5) VARIATION
0.20 REF
0.5 PITCH
L K 1 2 Top View D E E/2 D/2 A Side View
Date: 2/1/05 SP6654 High Efficiency 800mA Synchronous Buck Regulator © Copyright 2005 Sipex Corporation Corporation ANALOG EXCELLENCE Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Sipex Corporation Headquarters and Sales Office
233 South Hillview Drive
Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
ORDERING INFORMATION
Part Number Operating Temperature Range Top Mark Package Type /TR = Tape and Reel Pack quantity is 2,500 for MSOP and 3,000 for DFN Available in lead free packaging. To order add "-L" suffix to part number. Example: SP6654EU/TR = standard; SP6654EU-L/TR = lead free