SP6136ER1

SP6136 EXAR | Alldatasheet

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Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation

FEATURES

■ 5V to 24V Input step down converter ■ Up to 7A output in a small form factor ■ Highly integrated design, minimal components ■ UVLO Detects Both VCC and VIN ■ Overcurrent circuit protection with auto-restart ■ Power Good Output, ENABLE Input ■ Maximum Controllable Duty Cycle Ratio up to 92% ■ Wide BW amp allows Type II or III compensation ■ Programmable Soft Start ■ Fast Transient Response ■ Available in Lead Free, RoHS Compliant 6-Pin QFN package ■ External Driver Enable/Disable ■ U.S. Patent #6,922,04 The SP636 is a synchronous step-down switching regulator controller optimized for high efficiency. The part is designed to be especially attractive for single supply step down con- version from 5V to 24V. The SP636 is designed to drive a pair of external NFETs using a fixed 600 KHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown, output short circuit protection, and overcurrent protection with auto restart. The device also features a PWRGD output and an enable input. The SP636 is available in a space saving 6-pin QFN and offers excellent thermal performance. TYPICAL APPLICATION CIRCUIT

DESCRIPTION

16 Pin QFN

10KΩ CBST 0.1uF 68.1kΩ, 1% RZ3 1kΩ 21.5kΩ, 1% MT, Si4354DY 18.5 mΩ, 30V CZ3 270pF CP1 12 pF RZ2 30.9kΩ CZ2 560pF MB, Si4886DY 13.5 mΩ, 30V CF1 22pF 12V CIN 22uF CSP 6.8nF VIN GND VOUT GND SS VCC POWERGOOD CSS 47nF ISP ISN EN PGND GND PWRGD VFB COMP VIN B ST GH SWN UVIN GL 3.3V 0-7A DBST SD101AWS CVCC 4.7uF 0.1uF R5 10kΩ SP6136NC CS 0.1uF RS2 5.11KΩ RS1 5.11KΩ Inter-Technical SC7232-2R2 2.2uH, 13A, 10.4mΩ COUT 100uF ENABLE Note: Die attach paddle is internally connected to GND. SP6136 Synchronous Buck Controller

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation PARAMETER MIN TYP MAX UNITS CONDITIONS QUIESCENT CURRENT VIN Supply Current .5 3.0 mA VFB = V (no switching) VCC Supply Current .5 3.0 mA VFB = V (no switching) BST Supply Current 0.2 0.4 mA VFB = V (no switching) PROTECTION: UVLO VCC UVLO Start Threshold 4.00 4.25 4.5 V VCC UVLO Hysteresis 50 200 250 mV UVIN Start Threshold 2.35 2.50 2.65 V Apply voltage to UVIN pin UVIN Hysteresis 200 300 400 mV Apply voltage to UVIN pin VIN Start Threshold 9.0 9.5 0.0 V UVIN Floating VIN Hysteresis 300 mV UVIN Floating Enable Pullup Current 0.4 µA Apply voltage to EN pin ERROR AMPLIFIER REFERENCE Error Amplifier Reference 0.792 0.800 0.808 V 2X Gain Config. Error Amplifier Reference Over Line and Tempera- ture 0.788 0.800 0.82 V COMP Sink Current 70 50 230 µA COMP Source Current -230 -50 -70 µA VFB Input Bias Current 50 00 nA COMP Common Mode Output Range .9 3.0 3.2 V COMP Pin Clamp Voltage 3.2 3.5 3.8 V VFB = 0.7V ELECTRICAL SPECIFICATIONS Unless otherwise specified: -40°C < TAMB < 85°C, 4.5V < VCC < 5.5V, BST=VCC, SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC = 0µF, CCOMP = 0.µF, CGH = CGL = 3.3nF, CSS = 50nF, RPWRGD = 10KΩ. These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maxi - mum rating conditions for extended periods of time may affect reliability. Peak Output Current < 10µs ABSOLUTE MAXIMUM RATINGS

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation ELECTRICAL SPECIFICATIONS Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC = 0.µF, CCOMP = 0.µF, CGH = CGL = 3.3nF, CSS = 50nF. PARAMETER MIN TYP MAX UNITS CONDITIONS CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH Ramp Offset .7 2.0 2.3 V TA = 25˚C Ramp Amplitude 0.80 .0 .20 V GH Minimum Pulse Width 50 00 ns Maximum Controllable Duty Ratio 92 % Maximum Duty Ratio 00 % Guaranteed by design Internal Oscillator Frequency 520 600 680 kHz TIMERS: SOFTSTART SS Charge Current: -6 -0 -4 µA SS Discharge Current: .0 2.0 3.0 mA Fault Present VCC LINEAR REGULATOR VCC Output Voltage 4.6 5.0 5.4 V VIN = 6 to 23V, ILOAD = 0mA to 30mA Dropout Voltage 250 500 750 mV IVCC = 30mA POWER GOOD OUTPUT Power Good Threshold -0 -7.5 -5 % Power Good Hysteresis 2.0 4.0 % Power Good Sink Current .0 0 mA VFB = 0.7V, VPWRGD = 0.2V PROTECTION: SHORT CIRCUIT & THERMAL Short Circuit Threshold Voltage 0.2 0.25 0.3 V Measured VREF (0.8V) - VFB Overcurrent Threshold Voltage 54 60 66 mV Measured ISP - ISN ISP, ISN Common Mode Range 0 3.3 V Hiccup Timeout 90 0 30 ms Thermal Shutdown Temperature 35 45 55 ˚C Thermal Hysteresis 0 3.3 ˚C

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation ELECTRICAL SPECIFICATIONS Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = PGND = GND = 0.0V, UVIN = 3.0V, CVCC = 0.µF, CCOMP = 0.µF, CGH = CGL = 3.3nF, CSS = 50nF. PARAMETER MIN TYP MAX UNITS CONDITIONS OUTPUT: NFET GATE DRIVERS GH & GL Rise Times 35 50 ns Measured 0% to 90% GH & GL Fall Times 30 40 ns Measured 90% to 0% GL to GH Non Overlap Time 45 70 ns GH & GL Measured at 2.0V SWN to GL Non Overlap Time 25 40 ns Measured SWN = 00mV to GL = 2.0V GH & GL Pull Down Resistance 5 50 85 KΩ Driver Pull Down Resistance .5 .9 Ω Driver Pull Up Resistance 2.5 3.9 Ω BLOCk DIAGRAM NON SYNCH. STARTUP 100ms Delay 600 kHZFAULT 0.1V 0.25V SOFTSTART INPUT 135ºC OFF 145ºC ON 50KΩ 140KΩ 1.0V OFF 1.7V ON

4.05 V OFF

4.25 V ON

R FAULT 6EN 1 uA VCC VCC

3 GND

1.6 V SS GL HOLD OFF CLK CLOCK PULSE GENERATOR Q S RESET DOMINANT QPWM SYNCHRONOUS DRIVER

2 PGND

2.8 V 1.3 V RAMP = 1V VFB Power Good PWRGD

0.72 V OFF

0.74 V ON

THERMAL AND OVER CURRENT PROTECTIONUVLO COMPARATORS VCC UVLO HICCUP FAULT REFOK COUNTER CLR CLK ISP ISN 60 mV OVER CURRENT DETECTION DETECTION VFBINT SHORTCIRCUIT Q DOMINANT R S SETSHUTDOWN THERMAL VIN REFOK CORE 0.8V UVIN VIN UVLO

2.50 V ON

2.20 V OFF

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation PIN DESCRIPTION THEORY OF OPERATION General Overview The SP6136 is a fixed frequency, voltage mode, synchronous PWM controller opti - mized for high efficiency. The part has been designed to be especially attractive for single supply input voltages ranging between 5V and 24V. The heart of the SP636 is a wide bandwidth transconductance amplifier designed to ac- commodate Type II and Type III compensa- tion schemes. A precision 0.8V reference present on the positive terminal of the error amplifier permits the programming of the output voltage down to 0.8V via the VFB pin. The output of the error amplifier, COMP, compared to a V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscillator that accurately sets the PWM frequency to 600kHz. PIN PIN NAME GL High current driver output for the low side NFET switch. It is always low if GH is high or during a fault. Resistor pull down ensures low state at low voltage. 2 PGND Ground Pin. The power circuitry is referenced to this pin. Return separately from other ground traces to the (-) terminal of Cout. 3 GND Ground pin. The control circuitry of the IC is referenced to this pin.

4 VFB

Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error Amplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode.

5 COMP

Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM comparator. An optimal filter combination is chosen and connected to this pin and either ground or VFB to stabilize the voltage mode loop. 6 EN Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is internally pulled to VCC with a µA current source. 7 PWRGD Power Good Output. This open drain output is pulled low when VOUT is outside of the regulation. Connect an external resistor to pull high. 8 SS Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft start rate based on the 0µA source current. The SS pin is held low via a mA (min) current during all fault conditions. 9 ISN Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE and NSENSE. Offset accuracy +0%. 0 ISP Positive Input for the Inductor Current Sense. SWN Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFET transistors. 2 GH High current driver output for the high side NFET switch. It is always low if GL is high or during a fault. 3 BST High side driver supply pin. Connect BST to the external boost diode and capacitor as shown in the Application Schematic of page . High side driver is connected between BST pin and SWN pin. 4 VIN Supply Input -- supplies power to the internal LDO. 5 UVIN Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground. Can be overridden with external resistors. 6 VCC Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an external 5V supply. Note: Die attach paddle is internally connected to GND.

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation THEORY OF OPERATION The SP6136 contains two unique control features that are very powerful in distributed applications. First, non-synchronous driver control is enabled during start up to prohibit the low side NFET from pulling down the out- put until the high side NFET has attempted to turn on. Second, a 00% duty cycle timeout ensures that the low side NFET is periodically enhanced during extended periods at 00% duty cycle. This guarantees the synchronized refreshing of the BST capacitor during very large duty ratios. The SP636 also contains a number of valu- able protection features. A programmable input UVLO allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal V CC UVLO ensures that the controller itself has enough voltage to properly operate. Other protection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected, the SP636 is forced into an idle state where the output drivers are held off for a finite period before a re-start is attempted. Soft Start “Soft Start” is achieved when a power con- verter ramps up the output voltage while controlling the magnitude of the input sup - ply source current. In a modern step down converter, ramping up the non-inverting input of the error amplifier controls soft start. As a result, excess source current can be defined as the current required to charge the output capacitor IVIN, X = Cout • ΔVout ΔTSoft-start The SP636 provides the user with the op- tion to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 0µA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, the excess current source can be redefined as: IVIN, X = COUT • ΔVOUT • 0µA (CSS X 0.8V) Hiccup Upon the detection of a power, thermal, or short-circuit fault, the SP636 is forced into an idle state for a minimum of 200ms. The SS and COMP pins are immediately pulled low, and the gate drivers are held off for the duration of the timeout period. Power and thermal faults have to be removed before a restart may be attempted, whereas, a short- circuit fault is internally cleared shortly after the fault latch is set. Therefore, a restart at- tempt is guaranteed every 200ms (typical) as long as the short-circuit condition persists. A short-circuit detection comparator has also been included in the SP636 to protect against the accidental short or severe build up of current at the output of the power con- verter. This comparator constantly monitors the inputs to the error amplifier, and if the VFB pin ever falls more than 250mV (typical) below the voltage reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP636 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation. Error Amplifier & Voltage Loop As stated before, the heart of the SP636 voltage error loop is a high performance, wide bandwidth transconductance ampli - fier. Because of the amplifier’s current limited ( +00µA) transconductance, there are many ways to compensate the voltage loop or to control the COMP pin externally. If a simple, single pole, single zero response is required, then compensation can be as simple as an RC circuit to ground. If a more complex compensation is required, then the amplifier has enough bandwidth (45° at 4

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation THEORY OF OPERATION MHz) and enough gain (60 dB) to run Type III compensation schemes with adequate gain and phase margins at crossover frequencies greater than 200 kHz. The common mode output of the error ampli- fier (COMP) is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between .0V and 2.0V to ensure proper 0% to 00% duty cycle capability. The voltage loop also includes two other very important features. One is a non-synchronous start up mode. Basically, the GL driver cannot turn on unless the GH driver has attempted to turn on or the SS pin has exceeded .7V. This feature prevents the controller from “dragging down” the output voltage during startup or in fault modes. The second feature is a 00% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the GH driver is on for 20 continuous clock cycles, a reset is given to the PWM flip flop half way through the 20th cycle. This forces GL to rise for the remainder of the cycle, in turn refreshing the BST capacitor. Gate Drivers The SP636 contains a pair of powerful 2W Pull-up and .5W Pull-down drivers. These state-of-the-art drivers are designed to drive an external NFET capable of handling up to 30A. Rise, fall, and non-overlap times have all been minimized to achieve maximum efficiency. All drive pins GH, GL, & SWN are monitored continuously to ensure that only one external NFET is ever on at any given time. Thermal & Short-Circuit Protection Because the SP636 is designed to drive large NFETs running at high current, there is a chance that either the controller or power converter will become too hot. Therefore, an internal thermal shutdown (145°C) has been included to prevent the IC from malfunction- ing at extreme temperatures. Over-Current Protection Over-current is detected by monitoring a differential voltage across the output in - ductor as shown in figure 1. Inputs to an over-current detection comparator, set to trigger at 60 mV nominal, are connected to the inductor as shown. Since the average voltage sensed by the comparator is equal to the product of in - ductor current and inductor DC resistance (DCR) then I max = 60mV / DCR. Solving this equation for the specific inductor in cir- cuit , Imax = 4.6A. When Imax is reached, a 220 ms time-out is initiated, during which top and bottom drivers are turned off. Fol - lowing the time-out, a restart is attempted. If the fault condition persists, then the time- out is repeated (referred to as hiccup). Figure 1: Over-current detection circuit ISN SP613X SWN ISP VoutL = 2.7uH, DCR = 4.mOhm RS 5.11K RS2 5.K CS 0.uF CSP 6.8nF

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation 20V rated MOSFET is sufficient. For convert- ers with 0-5Vin, as in the above example, select a 30V MOSFET. The calculation of Rds(on) for Top and Bottom MOSFETs is interrelated and can be done using the following procedure: ) Calculate the maximum permissible power dissipation P (dissipation) based on required efficiency. The converter in the above example should deliver an output power Pout = 3.3V•0A = 33W. For a target efficiency of 94%, input power P in is given by Pin = Pout/0.94 = 35.W. Maximum al - lowable power dissipation is then: P(dissipation) = Pin – Pout = 2. W 2) Calculate the total power dissipation in top and bottom MOSFETs P(mosFEt) by sub- tracting inductor losses from P (dissipation) calculated in step . To simplify, disregard core losses; then P L = I 2rms • DCR • .4, where .4 accounts for the increase in DCR at operating temperature. For the above example PL = 0.63W. Then: P(mosFEt) = 2.W – 0.63W = .47W. 3) Calculate Rds(on) of the bottom MOSFET by allocating 40% of calculated losses to it. 40% dissipation allocation reflects the fact that the the top MOSFET has essentially no switching loss. Then P(bottom) = 0.4X.47W = 0.59W. Rds(on) = P/(I2rms • .5) where Irms = Iout • {-(Vout/Vin)}0.5 and .5 accounts for the increase in Rds(on) at the operating temperature. Then: Rds(on) = P [{I2out • (-Vout/Vin)} • .5] = 5.4 W. 4) Allocate 60% of the calculated losses to the top MOSFET, P (top) = 0.6X.47 = 0.88W. Assume conduction losses equal to switching losses, then P = 0.5X0.88W = 0.44W. Since it operates at the duty cycle of D=Vin/Vout; then: Rds(on) = P [I2out • (Vout/Vin) • .5] = 0.7W. Gate-to-drain charge Qgd for the top MOS- FET needs to be specified. A simplified expression for switching losses is: where dv/dt and di/dt are the rates at which voltage and current transition across the top MOSFET respectively, and f is the switching frequency. Voltage switching time (Vin /dv/dt) is related to Qgd: where Ig is Current charging the gate-to-drain capacitance. It can be calculated from: where V drivE is the drive voltage of the SP636 top driver minus the drop across the boost diode (approximately 4.5V); VgatE is the top MOSFET’s gate voltage correspond- ing to Iout (assume 2.5V) and RdrivE is the internal resistance of the SP636 top driver (assume 2W average for turn-on and turn-off). Substituting these values in equation (5) we get Ig = A. Substituting for Ig in equation (4), we get (Vin /dv/dt) = Qgd. Substituting for (Vin /dv/dt) in equation (3) we have: Ps = Iout • Vin • f • {Qgd + (Iout / di/dt)} Solving for Qgd we get: Iout • Vin • f di/dt Di/dt is usually limited by parasitic DC-Loop Inductance (Lp) according to di/dt = Vin/Lp.

APPLICATION INFORMATION

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation Lp is due to wiring and PCB traces connecting input capacitors and switching MOSFETs. For typical Lp of 2nH and Vin of 2V, di/dt is 1A/ns. Substituting for di/dt in equation (6) we get Qgd = 2 nC. In selecting a package type, the main con- siderations are cost, power/current handling capability and space constraints. A larger package in general offers higher power and current handling at increased cost. Package selection can be narrowed down by calculat- ing the required junction-to-ambient thermal resistance θja: θja = {Tj(max) - Ta(max))} / P(max) Where: T j(max) is the die maximum tem - perature rating, Ta(max) is maximum ambient temperature, and P(max) is maximum power dissipated in the die. It is common practice to add a guard-band of 25˚C to the junction temperature rating. Following this convention, a 150˚C rated MOSFET will be designed to operate at 125˚C (i.e., Tj(max) = 125˚C). P(max) = 0.88W (from section 4) and Ta(max) = 40˚C as specified in the design example. Substituting in equation (7) we get θja = 96.6 ˚C/W. For the top MOSFET, we now have deter - mined the following requirements; BV dss = 30V, Rds(on) = 0.7mW, Qgd = 2 nC and θja < 96.6˚C/W. An SO-8 MOSFET that meets the requirements is Vishay-Siliconix’s Si4394DY; BVdss = 30V, Rds(on) = 9.75mW @ Vgs = 4.5V, Qgd = 2.nC and θja = 90 ˚C/W. The bottom MOSFET has the requirements of BVdss = 30V and R ds(on) = 5.4m W. Vishay- Siliconix’s Si4320DY meets the requirements; BVdss = 30V, Rds(on) = 4mW @ Vgs = 4.5V. Power Good Power Good (PWRGD) is an open drain output that is pulled low when V out is out- side regulation. The PWRGD pin can be connected to VCC with an external 10K W resistor. During startup, output regulates when Soft Start (SS) reaches 0.8V (the refer- ence voltage). PWRGD is enabled when SS reaches .6V. PWRGD output can be used as a “Power on Reset”. The simplest way to adjust delay of the “Power on Reset” signal with respect to Vout in regulation is with the Soft Start Capacitor (Css) and is given by: Css = (Iss • Tdelay)/0.8 where Iss is the Soft Start charge current (0µA nominal). Under Voltage Lock Out (UVLO) The SP636 has two separate UVLO com- parators to monitor the bias (Vcc) and Input (Vin) voltages independently. The Vcc UVLO is internally set to 4.25V. The V in UVLO is programmable through UV in pin. When UVIN pin is greater than 2.5V the SP636 is permitted to start up pending the removal of all other faults. A pair of internal resistors is connected to UVIN as shown in figure 4. Therefore without external biasing the V in start threshold is 9.5V. A small capacitor may be required between UVIN and GND to filter out noise. For applications with Vin of 5V or 3.3V, connect UVIN directly to Vin. Figure 4- Internal and external bias of UVIN To program the Vin start threshold, use a pair of external resistors as shown. If external resistors are an order of magnitude smaller SP613X 40K 50K 2.5V ON 2.2V OFF GND UVIN VIN

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation than internal resistors, then the V in start threshold is given by: For example, if it is required to have a V in start threshold of 7V, then let R5 = 5KW and using equation (9) we get R4 = 9.09KW. Inductor Selection There are many factors to consider in select- ing the inductor including cost, efficiency, size and EMI. In a typical SP636 circuit, the inductor is chosen primarily for value, saturation current and DC resistance. In - creasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple cur - rents, poor efficiency and need more output capacitance to smooth out the larger ripple current. The inductor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. The switching frequency and the inductor operating point determine the inductor value as follows: L = Vout • (Vin(max) - Vout) Vin(max) • Fs • Kr • Iout(max) where: Fs = switching frequency Kr = ratio of the ac inductor ripple current to the maximum output current The peak to peak inductor ripple current is: Ipp = Vout • (Vin(max) - Vout) Vin(max) • Fs • L Once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency re - quirements. The core must be large enough not to saturate at the peak inductor current IpEak = Iout(max) + Ipp/2 and provide low core loss at the high switch- ing frequency. Low cost powdered iron cores have a gradual saturation characteristic but can introduce considerable AC core loss, especially when the inductor value is relatively low and the ripple current is high. Ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. In general, ferrite or molypermalloy materials are the better choice for all but the most cost sensi- tive applications. The power dissipated in the inductor is equal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. Core losses have a more significant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output cur- rents where the copper losses dominate. Core loss information is usually available from the magnetic vendor. The copper loss in the inductor can be cal- culated using the following equation: PL(cu) = I2 L(rms) • Rwinding where IL(rms) is the RMS inductor current that can be calculated as follows:

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation IL(rms) = Iout(max) X + • Ipp

3 Iout(max)

Output Capacitor Selection The required ESR (Equivalent Series Re - sistance) and capacitance drive the selec - tion of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the ad- ditional current demanded by the load until the SP636 adjusts the inductor current to the new value. Therefore, the capacitance must be large enough so that the output voltage is held up while the inductor current ramps up or down to the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equal to the current. Because of the fast tran- sient response and inherent 00% and 0% duty cycle capability provided by the SP636 when exposed to output load transients, the output capacitor is typically chosen for ESR, not for capacitance value. The output capacitor’s ESR, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple can be calculated by: RESR < ΔVout ipk-pk where: ΔVout = Peak to Peak Output Voltage Ripple ipk-pk = Peak to Peak Inductor Ripple Current The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows: ΔVout =. . √(Ipp•REsr)2 + { Ipp • (1-d) } Cout • Fs where: Fs = Switching Frequency D = Duty Cycle Cout = Output Capacitance Value Input Capacitor Selection The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripple current requirement imposed by the switching current. In continuous conduction mode, the source current of the high-side MOSFET is approximately a square wave of duty cycle Vout/VIN. Most of this current is supplied by the input bypass capacitors. The RMS value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: Icin(rms) = Iout(max) X √ D • (-D) Schottky Diode Selection When paralleled with the bottom MOSFET, an optional Schottky diode can improve efficiency and reduce noise. Without this Schottky diode, the body diode of the bot - tom MOSFET conducts the current during the non-overlap time when both MOSFETs are turned off. Unfortunately, the body di -

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation ode has high forward voltage and reverse recovery problems. The reverse recovery of the body diode causes additional switching noise when the diode turns off. The Schottky diode alleviates these sources of noise and additionally improves efficiency thanks to its low forward voltage. The reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. The power dissipation of the Schottky diode is determined by: PDIODE = 2 • VF • Iout • TNOL • FS where: TNOL = non-overlap time between GH and GL. VF = forward voltage of the Schottky diode. Loop Compensation Design The open loop gain of the whole system can be divided into the gain of the error ampli - fier, PWM modulator, buck converter output stage, and feedback resistor divider. In or - der to cross over at the selected frequency FCO, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. The goal of loop compensation is to manipu- late loop frequency response such that its gain crosses over 0db at a slope of -20db/ dec. The first step of compensation design is to pick the loop crossover frequency. High crossover frequency is desirable for fast transient response, but often jeopardizes the system stability. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The ESR zero is contributed by the ESR associated with the output capacitors and can be determined by: ƒz(Esr) = 2π • Cout • REsr The next step is to calculate the complex conjugate poles contributed by the LC output filter, ƒp(Lc) = 2π • √L • Cout When the output capacitors are of a Ceramic Type, the SP6136 Evaluation Board requires a Type III compensation circuit to give a phase boost of 180° in order to counteract the effects of an under damped resonance of the output filter at the double pole frequency. (SRz2Cz2+1)(SR1Cz3+1) (SRESRCOUT+ 1) [S2LCOUT+S(RESR+RDC) COUT+1] VIN SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1) VRAMP_PP VOUT (Volts) VREF (Volts) Notes: RESR = Output Capacitor Equivalent Series Resistance. RDC = Output Inductor DC Resistance. VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 Output Load Resistance >> RESR & RDC R2 VREF (R1 + R2) or VOUTVFBK (Volts) Type III Voltage Loop Compensation GAMP (s) Gain Block PWM Stage GPWM Gain Block Output Stage GOUT (s) Gain Block Voltage Feedback GFBK Gain Block Figure 5: SP6136 Voltage Mode Control Loop with Loop Dynamic Definitions: REsr = Output Capacitor Equivalent Series Resistance Rdc = Output Inductor DC Resistance Vramp _ pp = SP636 internal RAMP Amplitude Peak to Peak Voltage

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation (Hz) Error Amplifier Gain Bandwidth Product Condition: C22 >> CP1, R1 >> RZ3

20 Log (RZ2/R1)

(dB) 1/6.28(R22) (CZ2) 1/6.28 (R1) (CZ3) 1/6.28 (R1) (CZ2) 1/6.28 (RZ2) (CP1) 1/6.28 (RZ3) (CZ3) Figure 6: Bode Plot of Type III Error Amplifier Compensation Table 1. Input and Output Stage Components Selection Charts

2.2 Inter-

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation SP6136 Efficiency versus Iout @ Vin=12V, Vout=3.3V Iout (A) Efficiency (%) SP6136 Load Regulation @ Vin=12V 3.340 3.342 3.344 3.346 3.348 3.350 Iout (A) Vout (V)

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation PACkAGE: 3MMX3MM 16 PIN QFN

Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation

ORDERING INFORMATION

Available in lead free packaging. To order add "-L" suffix to part number. Example: SP636ER/TR = standard; SP636ER-L/TR = lead free /TR = Tape and Reel Pack quantity is 3000 for QFN. Part Number Temperature Range Package Sipex Corporation Headquarters and Sales Office

233 South Hillview Drive

Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.