SP601 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Ability to Interface and Drive Standard and Current Sensing N-Channel Power MOSFET/IGBT Devices
  • Creation and Management of a Floating Power Supply for Upper Rail Drive
  • Simultaneous Conduction Lockout
  • Overcurrent Protection
  • Single Low Current Bias Supply Operation
  • Latch Immune CMOS Logic
  • Peak Drive in Excess of 0.5A Half Bridge 500VDC Driver The SP601 is a smart power high voltage integrated circuit (HVIC) optimized to drive MOS gated power devices in half- bridge topologies. It provides the necessary control and management for PWM motor drive, power supply, and UPS applications.

Ordering Information

SP601 -40 oC to +85oC 22 Lead Plastic DIP Pinout SP601 (PDIP) TOP VIEW Functional Block Diagram 1 22 CL1 G1L G2L D1L EN- D1U G1U G2U NC CL2 PHASE FAULT ITRIPSEL VBIAS VDD VSS TRIPL VDF UP/ TRIPU VBS VOUT DOWN ABLE FILTER Q S R CMOS TIMING AND CONTROL VOUT SENSE AND FILTER UV LOCK OUT LEVEL SHIFT UV LOCK OUT Q S R QS R QS R QS R VBIAS 10Ω RND 3.5Ω RBS VDD VDF UP/DN ENABLE FAULT 750Ω RF ITRIPSEL IONT IOFFT ITRIPSEL IONB IOFFB ITRIPSEL FAULT VSS CL1 TRIPL G2L G1L D1L VOUT13 LOWER UPPER 3.5Ω RO VBS D1U G1U G2U TRIPU CL2 PHASE PART WITHDRAWN PROCESS OBSOLETE NO NEW DESIGNS

Absolute Maximum Ratings Full Temperature Range, All Voltage Referenced to VSS Unless Otherwise Noted. Note 1, Note 2. Thermal Information Power Supply to Phase, VBS Low Voltage Signal Pins G1L, D1L, V DF, TOP, BOT High Voltage Pins (VBS, VOUT, TRIPU, CL2, G2U and D1U: 0V-18V Higher Than Phase) DVPHASE/DT Thermal Resistance, Junction-to-Ambient θJA Maximum Package Power Dissipation at T A = +85oC, PO NOTES: 1. Care must be taken in the application of VBIAS as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (RND). Prolonged high peak currents may result if +15VDC is applied abruptly and/or if the local bypass capacitor CDD is large. It is suggested that CDD be ≤ 10MFD. If it is desirable to switch the 15VDC source or if a CDD is larger, additional series impedance may be required. 2. Consult factory for additional package offerings. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. Electrical Specifications (VBIAS = 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to V SS Except TRIPU, CL2, G1U, D1U, and VBS Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE PARAMETER SYMBOL TEMP MIN TYP MAX UNITS DC CHARACTERISTICS Input Current (5V < VTOP, VBOT, VTRIPSEL < 15V) I IN +25oC - 20 30 µA -40oC to +85oC - 30 33 µA IBIAS Quiescent Current (All Inputs Low) I BIASL +25oC- 1 . 7 2 . 0 5 m A -40oC to +85oC- 1 . 72 . 1 m A IBIAS Quiescent Current (VOUT ≥ VBIAS, and All Inputs Low) IBIASH +25oC- 1 . 7 2 . 0 5 m A -40oC to +85oC- 1 . 72 . 1 m A IBS Quiescent Current Bootstrap Supply I BS +25oC - 875 1000 µA -40oC to +85oC - 900 1060 µA ENABLE Threshold Level V TOP +25oC 789 V -40oC to +85oC6 . 9 5 8 9 . 1 V UP/DN Threshold Level V BOT +25oC 789 V -40oC to +85oC6 . 9 5 8 9 . 1 V Current Trip Select Threshold Level V TRIPSEL +25oC 789 V -40oC to +85oC6 . 9 5 8 9 . 1 V Trip Lower and Upper Comparator Threshold Level - Normal (ITRIPSEL = VSS) VTRIP L/UN +25oC9 0 1 0 5 1 2 5 m V -40oC to +85oC9 0 1 0 5 1 2 7 m V Trip Lower and Upper Comparator Threshold Level - Boost (ITRIPSEL = VDD) % of Measured VTRIP L/UN VTRIP L/UB +25oC 110 130 150 % -40oC to +85oC 109 130 152 % Under Voltage Lockout Thresholds (V DD and VBS)V LOCK +25oC 9 10 11.5 V -40oC to +85oC 9.7 10.5 11.8 V Phase Out of Status Voltage Threshold (PHASE) V OSVT +25oC 579 V -40oC to +85oC 4.7 7 9.6 V Faultbar Impedance at IFBAR = 1mA RF +25 oC 500 760 1000 Ω -40oC to +85oC 450 760 1100 Ω SP601

Upper/Lower Source Impedances (ISOURCE = 10mA) R SO L/U +25oC1 2 1 7 2 3 Ω -40oC to +85oC 7 17 29 Ω Upper/Lower Sink Impedances (ISINK = 10mA) R SI L/U +25oC 8 12 16 Ω -40oC to +85oC 5 12 20 Ω Bootstrap Supply Current Limiting Impedance R BS +25oC2 3 . 5 5 Ω -40oC to +85oC 1.4 3.5 5.6 Ω Noise Dropping Resistor Impedance R ND +25oC 6 10 14 Ω -40oC to +85oC 5.4 10 14.6 Ω High Voltage Leakage (500V VBS, VOUT, PHASE, TRIPU, CL2, G1U, G2U, and D1U to VSS. All other Pins at VSS) ILK +25oC- 1 3 µA Miller Clamp Diodes; D1U and D1L (I D = 10mA) V D1U/L +25oC 0.4 0.9 1.4 V Noise Clamping Zeners; CL2 and CL1 (I Z = 10mA) V CL2/1-LOW +25oC 6.35 6.61 6.85 V -40oC to +85oC 6.15 6.61 7.15 V Noise Clamping Zeners; CL2 and CL1 (I Z = 50mA) V CL2/1- HIGH +25oC 7.0 8.5 8.0 V VOUT Limiting Resistance R O +25oC2 3 . 5 5 Ω -40oC to +85oC 1.4 3.5 5.6 Ω NOTE: Maximum Steady State ÷ 15VDC Supply Current = IBIASL ÷ IBS Switching Specifications (All Referenced to VSS, Except: TRIPU, Cl2, G1U, G2U, and D1U Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE) PARAMETER SYMBOL TEMP MIN TYP MAX UNITS Refresh One Shot Timer t REF +25oC 200 350 500 µs -40oC to +85oC 180 350 540 µs Delay Time of Trip I/U Voltage (ITRIPSEL low) to G2U/G2L Low (50% Overdrive tOFFTN +25oC 234 µs -40oC to +85oC 1.85 3 4.35 µs Delay Time of Trip I Voltage (ITRIPSEL low) to Faultbar Low tFN +25oC 234 µs -40oC to +85oC 1.85 3 4.35 µs Delay Time of Phase Out of Status to Faultbar Low (TOP High) tOSVF +25oC 500 700 900 ns -40oC to +85oC 400 700 1050 ns Minimum Logic Input Pulse Width: TOP and BOTTOM tMINIW +25oC 300 430 600 ns -40oC to +85oC 275 430 660 ns Minimum G1U/G1L On Time t ON +25oC 1.6 2.3 3.1 µs -40oC to +85oC 1.5 2.4 3.4 µs Minimum Pulsed Off Time, G2U/G2L t OFF +25oC 1.3 2.0 3.4 µs -40oC to +85oC 1.05 2.1 3.9 µs Turn On Delay Time of G1U (BISTATE MODE) t OND +25oC 2.5 3.2 4.5 µs -40oC to +85oC 2.1 3.3 5.2 µs Turn On Delay Time of G1L (BISTATE MODE) t OND +25oC 2.5 3.2 4.5 µs -40oC to +85oC 2.1 3.3 5.2 µs Turn On Delay Time of G1U (THREE-STATE MODE) tOND +25oC 0.75 1.0 1.5 µs -40oC to +85oC 0.60 1.1 1.75 µs Electrical Specifications (VBIAS = 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to V SS Except TRIPU, CL2, G1U, D1U, and VBS Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE (Continued) PARAMETER SYMBOL TEMP MIN TYP MAX UNITS SP601

(THREE-STATE MODE) tOND +25oC 0.75 1.0 1.5 µs -40oC to +85oC 0.60 1.1 1.75 µs Turn Off Delay Time of G2U and G2L t OFFD +25oC 0.75 1.0 1.45 µs -40oC to +85oC 0.60 1.1 1.75 µs Minimum Dead Time: G1U OFF to G1L ON, or G1L off to G1U on (BISTATE MODE) -40oC to +85oC1 . 2 2 . 6 4 µs -40oC to +85oC 3.15 4.8 7.4 µs Rise Time of Upper and Lower Driver (Load = 2000pF) tR U/L +25oC2 5 5 0 1 0 0 n s -40oC to +85oC1 5 5 0 1 1 5 n s Fall Time of Upper and Lower Driver (Load = 2000pF) tF U/L +25oC2 5 5 0 1 0 0 n s -40oC to +85oC1 5 5 0 1 1 5 n s Recommended Operating Conditions and Functional Pin Description (All Voltages Referenced to VSS, Unless Otherwise Noted. See Figure 1) PARAMETER CONDITION FAULTBAR Open Drain Fault Indicator Output ITRIPSELECT Digital Input Command to Increase TRIP L and TRIPU Threshold by 30% VBIAS 14.5V to 16.5V with 15V nominal, ≅ 1.5mA DC BIAS Current VDD CDD to VSS VSS COMMON TRIP I 100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output CL1 Lower Noise Clamp Zener G2L and G1L Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER) VDF Current Limiting Charging Resistor for Bootstrap Capacitor Power Supply VBS Bootstrap Supply, Normally a Diode Drop Below V DD Voltage with Respect to the Floating PHASE Reference VOUT Load Connection Node PHASE Floating Reference Point for High Side Control Circuitry: V BS, TRIPU, CL2, G1U, G2U and D1U TRIPU 100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive CL2 Upper Noise Clamp Zener G2U and G1U Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER) ENABLE Digital Input to ENABLE the UP/DN Command to Turn on Top/Bottom Devices UP/DN Digital Input to Top/Bottom Device (If ENABLE is High) D1U Miller Clamp UPPER to V BS D1L Miller Clamp LOWER to V DD Switching Specifications (All Referenced to VSS, Except: TRIPU, Cl2, G1U, G2U, and D1U Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE) (Continued) PARAMETER SYMBOL TEMP MIN TYP MAX UNITS SP601

THREE-STATE MODE SLOWER THAN REFRESH ONE SHOT TIMER NOTE: BOT switching not relevant. BISTATE MODE SLOWER THAN REFRESH ONE SHOT TIMER Typical Circuit Configuration TRUTH TABLE Applicable to Typical Circuit Configuration (Figure 1) INPUTS OUTPUTS UP/DN ENABLE TRIP L TRIPU PHASE V BIAS UPPER LOWER FAULT BAR 000XX100 1 11001110 1 11011100 0 110X0100 0 XX1XX100 0 010XX101 1 100XX100 1 XXXXX000 0 NOTE: 0 = False, 1 = True, X = Don’t Care ENABLE UP/DOWN REFRESH ONE SHOT IONB VALID BOTON IOFFT IONT IOFFB UPPER LOWER VOUT V DC COM ENABLE UP/DOWN REFRESH ONE SHOT IONB VALID BOTON IOFFT IONT IOFFB UPPER LOWER VOUT V DC COM SP601

FIGURE 1. TYPICAL CIRCUIT CONFIGURATION NOTE: Refer to ‘Additional Product Offerings’ for information concerning power output devices.

The SP601 provides a flexible, digitally controlled power function which is intended to be used as PWM drivers of N-Channel MOSFETs and/or IGBTs for up to 240VAC line rectified totem-pole applications. The CMOS driveable inputs are filtered and captured by the control logic to deter- mine the output state. The logic includes fixed timing to pro- hibit simultaneous conduction of the external power switches and, thru the V OUT sense detector, verifies the output volt- age state is in agreement with the controlled inputs. The > 11VDC floating power supply required to drive the upper rail external power device is created and managed by the HVIC through C F and D F. This capacitor is refreshed from the VDD supply each time VOUT goes low. If the upper chan- nel is commanded on for a long period of time, the bootstrap capacitor C F is automatically refreshed by bringing V OUT low. This is accomplished by turning off the upper rail MOS- FET/IGBT, momentarily turning on the lower rail output device, followed by returning control back to the upper switch. Otherwise, C F would gradually deplete its charge allowing the upper switch to come out of saturation. The upper and lower gate drivers allow for controlled charge and discharge rates as well as facilitate the use of nearly lossless current sensing power MOS devices. The over current trip level can be boosted 30% on a pulse by pulse basis by logic level ‘1’ applied to I TRIPSELECT . A FAULT output signal is generated when any of the following occurs: V bias is low Over current is detected V phase doesn’t agree with the input signal Reset of FAULT is provided by externally removing power or by holding the ENABLE input low for the required reset time (trtMAX). Each application can be individually optimized by the selec- tion of external components tailored to ensure proper overall system operation including: Determining the ratings and sizing of MOSFETs and IGBTs, mixed or matched, as well as flyback diodes (FBD). The selection of separate gate charge (R C) and discharge (RD) impedance chosen per the load capacitance, frequency of operation, and D I/DT dependent recovery characteristics of the associated FBDs. R D should also be sized to prevent simultaneous bridge conduction by ensuring gate discharge in the allotted turn off pulse width (t OFF MIN). The selection of over current detection resistors (R P), com- patible with current sense MOSFETs/IGBTs or shunt(s) may be used. For the floating bootstrap supply D F and C F must be deter- mined. DF must support the worse case system bus voltage and handle the charging currents of C F. Proper selection should take into consideration T RR and TFR per the desired operating frequency. Proper selection of C F is a trade off between the minimum tON time of the lower rail to charge up the capacitor, the amount of charge transfer required by the load, and cost. Due to automatic refresh the capacitor is replenished every 350 µs TYP (or even sooner if the UP/DN input switches at a faster repetition rate). The local filter capacitor (C DD) should be sized sufficiently large enough to transfer the charge to C F without causing a significant droop in V DD. As a rule of thumb it should be at least 10 times larger than C F and be located adjacent to the VDD and V SS pins to minimize series resistance and inductance. Refer to Application Note AN8829 for more details about module operation and selection of external components. SP601