SP5024SMP

SP5024 ZARLINK | Alldatasheet

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DS2452 - 2.1 December 1992 SP5024 3-Wire Bus Controlled Synthesiser The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I2C bus or 3-wire bus format depending on which device is inserted. The SP5024, when used with a TV varicap tuner, forms a complete phase locked loop tuning system. The circuit consists of a divide-by-8 prescaler with its own preamplifier and a 15 bit programmable divider controlled by a serially - loaded data register. Four open-collector outputs, each independently programmable, are included. The device has two modes of operation selected by the 'mode selected input'. In mode 1 the comparison frequency is 7.8125kHz and the programmable divider MSB is bypassed; mode 2 comparison frequency is 6.25kHz. The comparison frequencies are both obtained from a 4MHz crystal controlled on-chip oscillator. The comparator has a charge pump output with an output amplifier stage around which feedback may be applied. Only one external transistor is required for varicap line driving.

FEATURES

n Complete 1.3GHz Single Chip System n Dual Standard 50kHz or 62.5kHz Step Size n Low Power Consumption (5V 40mA) n Programming Compatible with Toshiba TD6380 and TD6381 * n Pin Compatible with SP5510 * n Low Radiation n Varactor Drive Amplifier Disable n Charge Pump Disable n Single Port 18/19 Bit Serial Data Entry n Four Controllable Outputs n ESD Protection † * See notes on pin compatibility † Normal ESD handling procedures should be observed

APPLICATIONS

n Satellite TV When Combined With SP4902 2.5GHz Prescaler n Cable Tuning Systems n VCRs Fig. 1 Pin connections – top view CHARGE PUMP CRYSTAL MODE SELECT DATA CLOCK PORT P4 PORT P3 PORT P2 PORT P1 DRIVE OUTPUT VEE RF INPUT RF INPUT V CC NC NC LOCK ENABLE CHARGE PUMP CRYSTAL MODE SELECT DATA CLOCK PORT P4 PORT P3 PORT P2 MP16 DRIVE OUTPUT V EE RF INPUT RF INPUT V CC LOCK ENABLE PORT P1 DP18

ORDERING INFORMATION

SP5024 DP - (18-lead plastic package) SP5024S MP - (16-lead miniature plastic package)

V CC VCC 0.6 -250 150 0.5 15,16 15, 16 15,16 4,5,10 3,4,5,10 4,5,10 4,10 Supply current Prescaler input voltage Prescaler input voltage Prescaler input impedance Input capacitance High level input voltage High level input voltage Low level input voltage High level input current Low level input current Low level input current High level input current Low level input current Clock input hysteresis Clock rate Data set up time Data hold time Enable set up time Enable hold time Clock-to-enable time Charge pump output current Charge pump output leakage current Drift due to leakage Charge pump drive output current Charge pump amplifier gain Oscillator temperature stability Oscillator stability with supply voltage Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator source impedance

ELECTRICAL CHARACTERISTICS

Tamb = -20°C to +80°C, VCC = +4·5V to +5·5V. Reference frequency = 4MHz. Pin numbers refer to SP5024 (DP package). These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Typ. Value Characteristic Pin 12.5 300 600 300 600 300 0.4 ±150 -400 Min. Max. Symbol ICC 6400 200 VCC = 5V 50MHz to 1GHz sinewave 1.3GHz, see Fig. 5 V IN = 5·5V, V CC = 5·5V VIN = 0V, VCC = 5·5V VIN = 0V, VCC = 5·5V VIN = 5·5V, V CC = 5·5V VIN = 0V, VCC = 5·5V See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 4 V pin 1 = 2·0V V pin 1 = 2·0V At collector of external varicap drive transistor V pin 18 = 0·7V Pin 18 Current 100µA "Parallel resonant" crystal Nominal spread = 615% ConditionsUnits ppm/°C ppm/V Ω mV p-p Ω mA mVRMS mVRMS Ω pF V V V µA µA µA µA µA V MHz ns ns ns ns ns µA nA mV/s mA

ELECTRICAL CHARACTERISTICS (continued) mA µA µA µA µA VOUT = 0.7V VOUT = 13.2V VOUT = VCC VIN = <0V VIN = <0V 6 - 9,11 6-9 Port and Lock sink current Port leakage current Lock leakage current Varactor Drive Amp Disable Charge Pump Disable Typ. Value ConditionsCharacteristic Pin -350 -350 Units Min. Max. Symbol Supply voltage Prescaler inputs Output ports Total port output current Prescaler DC offset Loop amplifier DC offset Crystal oscillator DC offset Data bus inputs Storage temperature Junction temperature DP 18 thermal resistance, chip-to-ambient DP 18 thermal resistance, chip-to-case MP 16 thermal resistance, chip-to-ambient MP 16 thermal resistance, chip-to-case Power consumption at 5V Value Parameter ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE = 0V Min. Pin SP5024 S Pin SP5024 15, 16 6-9 6-9 15, 16 1, 18 4, 5 ,10 13, 14 6-9 6-9 13, 14 1, 16 4, 5 ,10 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.7 -55 ConditionsUnits V Vp-p V V mA V V V V °C/W °C/W °C/W °C/W mW Port in off state Port in on state With V CC applied All ports off Max. 2.5 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 +125 +150 111 275 Fig.2 Block diagram PRESCALER RF IN RF IN CLOCK DATA ENABLE MODE SELECT DATA INPUT INTERFACE PRE AMP DATA CLOCK 14/15 BIT PROGRAMMABLE DIVIDER 14/15 BIT LATCH DIVIDER RATIO CONTROL OUTPUT BUFFER P4 P3 P2 P1 PHASE COMP F FPD CHARGE PUMP LOCK DETECT FCOMP 4640/ 512 OSC 4MHz MODE SELECT VCC CRYSTAL CHARGE PUMP VEE CPDIS VADIS LOCK AMP DRIVE/VARICAP OUTPUT

The SP5024 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor, to control a voltage controlled local oscillator, so forming a PLL frequency synthesised source. The system is controlled by a microprocessor via a standard data, clock, enable, three-wire data bus. The data load normally consists of a single word, which contains the frequency and port information, and is only transferred to the internal data shift register during an enable high period. The clock input is disabled during enable low periods. New data words are only accepted by the internal data buffers from the shift register on a negative transition of the enable, so giving improved fine tune facility for digital AFC etc. The data sequence and timing follows the format shown in Fig. 3. The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of this divider, F PD , is fed to the phase comparator where it is compared in phase and frequency domain to the internally generated comparison frequency, FCOMP . The FCOMP is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used is generally 4MHz, which gives an FCOMP of 6.25kHz/7.8125kHz and, when multiplied back up to the synthesised LO, gives a minimum step size of 50kHz/62.5kHz, respectively. The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The input sensitivity and impedance are shown in Figs. 5 and 7, respectively. The SP5024 contains an improved lock detect circuit which generates a flag when the loop has attained lock. ‘Out of lock’ is indicated by high impedance state. The SP5024 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least 10mA. These outputs are set by the remaining four bits within the normal data word. PIN COMPATIBILITY The SP5024 may be used in SP5510 applications which require 3-wire bus as opposed to I2C bus data format. In SP5510 applications where the reference crystal is connected to pin 3, a small modification is required to ground the crystal as shown in Fig. 4. Appropriate connections to the mode select input (pin 3) must also be made. In mode 1 (pin 3 'HIGH') the SP5024 is programming and step size compatible with the Toshiba TD6380, and in mode 2 (pin 3 'LOW') it is compatible with the TD6381. In both modes a 4MHz crystal is used to derive F COMP , unlike the TD6381 which requires a 3.2MHz crystal. Fig. 3 Data format and timing CLOCK P1 P2 P3 P4 MSB 217 216 215 214 213 212 202122 LSB FREQUENCY DATA (LSB = 62.5kHz, with 4MHz reference) FREQUENCY DATA (LSB = 50kHz, with 4MHz reference) P1 P2 P3 P4 MSB 218 217 216 215 214 213 202122 LSB t4 t2 t3 t5 t1 = ENABLE SET-UP TIME t2 = DATA SET-UP TIME t3 = DATA HOLD TIME t4 = CLOCK-TO ENABLE TIME t5 = ENABLE HOLD TIME CLOCK CHIP ENABLE DATA CHIP ENABLE DATA MODE 1 (PIN 3 HIGH) DATA MODE 2 (PIN 3 LOW)

Fig. 4 Typical application (F STEP = 50kHz) 300 37.5 12.5 500 1000 1500 FREQUENCY (MHz) VIN (mV RMS INTO 50 Ω ) OPERATING WINDOW Fig. 5 Typical input sensitivity VREF RF INPUTS VCC 170 CHARGE PUMP DRIVE OUTPUT RF input Loop amplifier 2 x 3k Fig.6a Input/Output interface circuits

Enable and data inputs Clock input Reference oscillator Output ports P1-P4 and Lock output OUTPUT Fig.6b Input/Output interface circuits Fig.7 Typical input impedance

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