SP43602 SIPAT | Alldatasheet
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Technical content
900 MHz
1800 MHz
2200 MHz
3800 MHz
5000 MHz
Table 1. Electrical Specifications @ +25°C, V
4 GHz ≤ 5 GHz
Figure 3. 0.5dB Step Error vs. Frequency* Figure 4. 1dB Attenuation vs. Attenuation State Note 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 3.
Figure 13. Pin Configuration (Top View) Table 2. Pin Descriptions
1 GND Ground
3 Serial/Parallel mode select
4 GND Ground
5 RF1 RF1 port
14 RF2 RF2 port
15 GND Ground
16 LE Serial interface Latch Enable input
17 CLK Serial interface Clock input
18 SI Serial interface Data input
19 C16 (D6) Parallel control bit, 16 dB
20 C8 (D5) Parallel control bit, 8 dB
21 C4 (D4) Parallel control bit, 4 dB
22 C2 (D3) Parallel control bit, 2 dB
23 C1 (D2) Parallel control bit, 1 dB
taken to avoid exceeding the specified rating. be grounded for proper device operation. devices are immune to latch-up. The SP43602 has a maximum 25 kHz switching rate. can be toggled across attenuation states. 24-lead 4x4 QFN package is MSL1. Figure 14. Maximum Power Handling Capability Table 3. Operating Ranges Table 4. Absolute Maximum Ratings
20 MHz ≤ 5 GHz
9 KHz ≤ 20 MHz
Note: Ground C0.5, C1, C2, C4, C8, C16 if not in use.
Table 5. Control Voltage Table 6. Latch and Clock Specifications L L L L L L L L Reference I.L. Table 8. Serial Attenuation Word Truth Table Table 9. Serial Register Map Table 7. Parallel Truth Table
50 Ω RF Digital Attenuator Tel: +86-23-62808818 Fax: +86-23-62805284 www.sipatsaw.com / sawmkt@sipat.com Page 6 of 10 Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the SP43602. The bit provides this selection, with =LOW selecting the parallel interface and =HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of six CMOS-compatible control lines that select the desired attenuation state, as shown in Table 7. The parallel interface timing requirements are defined by Fig. 16 (Parallel Interface Timing Diagram), Table 11 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 16) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial Interface The serial interface is a 8-bit serial-in, parallel-out shift register buffered by a transparent latch. The 8-bits make up the Attenuation Word that controls the DSA. Fig. 15 illustrates a example timing diagram for programming a state. The serial-interface is controlled using three CMOS- compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Attenuation Word truth table is listed in Table 8. A programming example of the serial register is illustrated in Table 9. The serial timing diagram is illustrated in Fig. 15. It is required that all parallel pins be grounded when the DSA is used in serial mode. Power-up Control Settings The SP4602 will always initialize to the maximum attenuation setting (31.5 dB) on power-up for both the serial and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the 31.5 dB range by pre- setting the parallel control pins prior to power-up. In this mode, there is a 400-µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.5 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between serial and parallel programming modes is possible. If the DSA powers up in serial mode ( = HIGH), all the parallel control inputs DI[6:1] must be set to logic low. Prior to toggling to parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic low. If the DSA powers up in either latched or direct-parallel mode, all parallel pins DI[6:1] must be set to logic low prior to toggling to serial mode ( = HIGH), and held low until the DSA has been programmed serially to ensure bit D[7] is set to logic low. The sequencing is only required once on power-up. Once completed, the DSA may be toggled between serial and parallel programming modes at will. SP / SP / SP / SP / SP /
( ) select switch to the Parallel (or left) position. the parallel programming timing diagram. procedure is identical to the direct-parallel method. Figure 17. Evaluation Board Layout low prior to programming the next word. attenuation state is enabled or disabled.
Figure 19. Package Drawing Figure 18. Evaluation Board Schematic