SP43503 SIPAT | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
Features
HaRP™-enhanced UltraCMOS™ device Attenuation: 1 dB steps to 31 dB High Linearity: Typical +58 dBm IP3 Excellent low-frequency performance 3.3 V or 5.0 V Power Supply Voltage Fast switch settling time Programming Modes: Direct Parallel Latched Parallel Serial High-attenuation state @ power-up (PUP) CMOS Compatible No DC blocking capacitors required Packaged in a 24-lead 4x4x0.85 mm QFN Figure 1. Package Type
900 MHz
2200 MHz
3800 MHz
5800 MHz
Table 1. Electrical Specifications @ +25°C, V
4 GHz ≤ 6 GHz
Figure 3. 1dB Step Error vs. Frequency * Figure 4. 1dB Attenuation vs. Attenuation State Figure 5. 1dB Major State Bit Error Figure 6. 1dB Attenuation Error vs. Frequency Note 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 3.
Table 2. Pin Descriptions Figure 13. Pin Configuration (Top View)
1 NC No Connect
3 P̅/S Serial/Parallel mode select
4 GND Ground
5 RF1 RF1 port
6 GND Ground
13 GND Ground
14 RF2 RF2 port
15 GND Ground
16 LE Serial interface Latch Enable input
17 CLK Serial interface Clock input
18 SI Serial interface Data input
19 C16 (D6) Parallel control bit, 16 dB
20 C8 (D5) Parallel control bit, 8 dB
21 C4 (D4) Parallel control bit, 4 dB
22 C2 (D3) Parallel control bit, 2 dB
23 C1 (D2) Parallel control bit, 1 dB
24 GND Ground
Note: Ground C1, C2, C4, C8, C16 if not in use. devices are immune to latch-up. The SP43503 has a maximum 25 kHz switching rate. DSA can be toggled across attenuation states. maximum for extended periods may reduce reliability. the 24-lead 4x4 QFN package is MSL1. Figure 14. Maximum Power Handling Capability Table 3. Operating Ranges Table 4. Absolute Maximum Ratings
20 MHz ≤ 6 GHz
Table 5. Control Voltage Table 6. Latch and Clock Specifications Table 8. Attenuation Word Truth Table Table 7. Parallel Truth Table L L L L L L L L Reference I.L. Table 9. Serial Register Map
Either a parallel or serial interface can be used to control the SP43503. The P̅/S bit provides this selection, with P̅/S=LOW selecting the parallel interface and P̅/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of five CMOS- compatible control lines that select the desired attenuation state, as shown in Table 7. The parallel interface timing requirements are defined by Fig. 16 (Parallel Interface Timing Diagram), Table 11 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 16) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial Interface The serial interface is a 8-bit serial-in, parallel-out shift register buffered by a transparent latch. The 8- bits make up the Attenuation Word that controls the DSA. Fig. 15 illustrates a example timing diagram for programming a state. When the DSA is used in serial mode, ground all parallel control pins (pins 19- 23). The serial-interface is controlled using three CMOS- compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Attenuation Word truth table is listed in Table 8. A programming example of the serial register is illustrated in Table 9. The serial timing diagram is illustrated in Fig. 15. It is required that all parallel pins be grounded when the DSA is used in serial mode. Power-up Control Settings The SP43503 will always initialize to the maximum attenuation setting (31 dB) on power-up for both the serial and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the 31 dB range by pre-setting the parallel control pins prior to power-up. In this mode, there is a 400-µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between serial and parallel programming modes is possible. If the DSA powers up in serial mode (P̅/S = HIGH), all the parallel control inputs DI[6:2] must be set to logic low. Prior to toggling to parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic low. If the DSA powers up in either latched or direct- parallel mode, all parallel pins DI[6:2] must be set to logic low prior to toggling to serial mode (P̅/S = HIGH), and held low until the DSA has been programmed serially to ensure bit D[7] is set to logic low. The sequencing is only required once on power- up. Once completed, the DSA may be toggled between serial and parallel programming modes at will. Tel: +86-23-62808818 Fax: +86-23-62805284 www.sipatsaw.com / sawmkt@sipat.com
SP43503 Digital Step Attenuator. software is set to program in Direct-Parallel mode. attenuation state is enabled or disabled. Parallel is selected in the software. Figure 17. Evaluation Board Layout attenuation state is enabled or disabled.
Figure 19. Package Drawing Figure 18. Evaluation Board Schematic Note: Capacitors C1-C8, C13, & C14 may be omitted.