SP43404 SIPAT | Alldatasheet
Document overview
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Technical content
Features
Attenuation: 1.0 dB steps to 15 dB Flexible parallel and serial programming interfaces Parallel latched or direct mode High attenuation accuracy and linearity over temperature and frequency Unique power-up state selection Very low power consumption Single-supply operation Positive CMOS control logic 75 Ω impedance Packaged in a 20 Lead 4x4 mm QFN Table 1. Electrical Specifications @ +25°C, V
- Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency.
- Note Absolute Maximum in Table 3.
- Measured in a 50 Ω system.
Figure 2. Package Type
20 Lead 4x4 mm QFN
Table 2. Pin Descriptions exceeding the rate specified in Table 3. an external series capacitor.
- Latch Enable (LE) has an internal 100 kΩ resistor to V
- Connect pin 12 to GND to enable internal negative
bypass and disable internal negative voltage generator.
- Place a 10 kΩ resistor in series, as close to pin as
Figure 15. Pin Configuration (Top View) devices are immune to latch-up. The SP43404 has a maximum 25 kHz switching rate.
1 N/C No connect
3 Data Serial interface data input (Note 4). 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2).
7 N/C No connect
8 PUP2 Power-up selection bit. 13 P/S Parallel/Serial mode select. 15 C8 Attenuation control bit, 8 dB. 16 C4 Attenuation control bit, 4 dB. 17 C2 Attenuation control bit, 2 dB. 19 C1 Attenuation control bit, 1 dB.
20 GND Ground for proper operation
Table 3. Absolute Maximum Ratings Table 4. Operating Ranges to the limits in the Operating Ranges table.
2 RFI N
3 DATA
4 CL K
6 VDD
7 PUP1
8 PUP2
9 VDD_D
10 GN D
ease customer evaluation of the SP43404 DSA. settings to be specified as the power-up state. Figure 4. Evaluation Board Layout Figure 5. Evaluation Board Schematic specifications over frequency.
attenuation state, as shown in Table 5. Characteristics), and switching speed (Table 1). Table 5. Truth Table is independent of the state of the LE input. brought LOW, data in the shift register is latched. present on the four parallel data inputs (C1 to C8). be specified as the power-up state. Table 6. Power-Up Truth Table, Parallel with C1-C8, and PUP2 is not active.
Table 7. 4-Bit Attenuator Serial Programming Table 9. Parallel Interface AC Characteristics Figure 19. Parallel Interface Timing Diagram Table 8. Serial Interface AC Characteristics Figure 18. Serial Interface Timing Diagram prevent an unknown state in the device . at 10 MHz to verify fclk specification.
0 C 8C 4C 2C 1 0
Figure 20. Package Drawing
0.20 REF
- Dimension applies to metallized terminal and is measured
between 0.25 and 0.30 from terminal tip.
- Coplanarity applies to the exposed heat sink slug as well as
- Dimensions are in millimeters.