SP431

HSP43124 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 17

Technical content

Features

• 45MHz Clock Rate
• 256 Tap Programmable FIR Filter
• 24-Bit Data, 32-Bit Coefficients
• Cascade of up to 5 Half Band Filters
• Decimation from 1 to 256
• Two Pin Interface for Down Conversion by F S/4
• Multiplier for Mixing or Scaling Input with an External Source
• Serial I/O Compatible with Most DSP Microprocessors

Applications

• Low Cost FIR Filter
• Filter Co-Processor
• Digital Tuner Block Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HSP43124PC-45 0 to 70 28 Ld PDIP E28.6 HSP43124PC-33 0 to 70 28 Ld PDIP E28.6 HSP43124SC-45 0 to 70 28 Ld SOIC M28.3 HSP43124SC-33 0 to 70 28 Ld SOIC M28.3 HSP43124SI-40 -40 to 85 28 Ld SOIC M28.3 PROGRAMMABLE FIR FILTER INPUT FORMATTER DIN SCLK SYNCIN MXIN SYNCMX OUTPUT FORMATTER DOUT SYNCOUT CLKOUT A0-2 C0-7 WR CONTROL INTERFACE RD FSYNC FCLK HALF BAND FILTER HALF BAND FILTER HALF BAND FILTER Data Sheet May 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

28 LEAD PDIP, SOIC

V CC DIN SYNCOUT CLKOUT VCC GND DOUT SYNCMX MXIN HSP43124

DIN I Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A “HIGH” on this input represents a “1”, and a low on this input represents “0”. The word format and operation of serial interface are con- tained in the Data Input Section. SYNCIN I Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples SYN- CIN “HIGH” one SCLK before the first bit of the new word. NOTE: SYNCIN should not maintain a “HIGH” state for longer than one SCLK cycle. SCLK I Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the part. The following signals are synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX. MXIN I Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A “HIGH” on this input represents a “1”, and a low on this input represents “0”. Also used to specify the Weaver Modulator ROM output as a part of the two pin F S/4 down conversion interface. Details on word format and operation are contained in the Mix Factor Section. SYNCMX I Mix F actor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples SYNCMX “HIGH” one SCLK before the first bit of the new mix factor.NOTE: SYNCMX should only pulse “HIGH” for one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin FS/4 down con- version interface. FCLK I Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate require- ments on FCLK for particular filter configurations is discussed in the Filter Compute Engine Section. This clock may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock. FSYNC I Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is currently being input, the current sum of products and the input data are “canceled” and the DIN pin is ignored until the next SYNCIN cycle occurs. WR I Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by the address on A0-2. TheWR signal is asynchronous to all other clocks.NOTE: WR should not be low when RD is low. RD I Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places the contents of that memory location on C0-7. WhenRD returns “HIGH” the C0-7 bus functions as an input bus. The RD pin is asynchronous to all other clocks.NOTE: RD should not be low whenWR is low. A0-2 I Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address map for the control registers. C0-7 I/O Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM. CLKOUT O Output Clock. Programmable bit clock for serial output. NOTE: Assertion ofFSYNC initializes CLKOUT to a high state. SYNCOUT O Output Data Sync. SYNYOUT is asserted HIGH for one CLKOUT cycle before the first bit of a new output sample is available on DOUT. DOUT O Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter section for additional details.) HSP43124

significant byte (LSB) to most significant byte (MSB). TABLE 1. CONFIGURATION CONTROL REGISTER FUNCTIONAL DESCRIPTION HBF must be enabled to get an output). 7-5 FIR Decimation Rate. Range is 1-8 (8 = 000). side the range of 8 - 24 are invalid. 5 Number System. 0 = Two’s Complement, 1 = Offset Binary. 6 Serial Format. 1 = MSB First, 0 = LSB First.

7 Unused

5 1 = MSB First, 0 = LSB First. by 00000, and values from 1 to 7 are invalid. 5 Round Select. 1 = Round to Selected Number of Bits, 0 = Truncate. 6 Number System. 0 = Two’s Complement, 1 = Offset Binary. 7 Gain Correction. 1 = Apply scale factor of 2 to data. 0 = No Scaling.

110 Filter Symmetry 1-0 00 = Even Symmetric FIR Coefficients

the range of 8 - 24 are invalid. 5 Serial Format. 1 = MSB First, 0 = LSB First. 6 Mix Factor Select. 1 = Serial Input, 0 = Weaver modulator look-up-table.

FIGURE 10A. BLOCK DIAGRAM OF FIXED COEFFICIENT HALFBAND FILTERS BITS2-0 100 0 1 11 1 101 1 1 11 1 010 0 0 01 1 011 0 0 11 1 000 0 0 00 0 001 0 0 00 1 MUX1 = (BIT2 AND BIT0) ANDBIT1 MUX2 = BIT2 MUX3 = (BIT1 AND BIT0) OR BIT2 MUX4 = BIT1 OR BIT2 MUX5 = BIT0 OR BIT1 OR BIT2 INVALID = BIT2 AND BIT1 MULTIPLEXERS’ DECODER TABLE AND EQUATIONS MUX5MUX4MUX3MUX2MUX1 HB5 HB4 HB3 HB2 HB1 INPUT TO FNORMALIZED = Fs Fs FHB1 = Fs or Fs/2 Fs/2 FHB1 /2 FHB2 = FHB1 or FHB1 /2 FNORMALIZED = FHB1 FHB3 = FHB2 or FHB2 /2 FHB2 /2 FNORMALIZED = FHB2 FHB3 /2 FNORMALIZED = FHB3 FHB4 = FHB3 or FHB3 /2 FHB4 /2 FNORMALIZED = FHB4 OUTPUT OF HALFBAND SECTION HALFBAND SECTION 01MUX5 MUX4 MUX3 MUX2 MUX1

35 TAP

23 TAP

19 TAP

11 TAP

7 TAP

FIGURE 10B. SPECTRAL COMPOSITION OF FIVE CASCADED HALFBANDS FIGURE 10C. COMPOSITE RESPONSE OF FIXED COEFFI- CIENT HALFBAND FILTERS WITH RESPECT TO THE NORMALIZED FREQUENCY SHOWN IN FIG- URE 10A FCLK FCLK 3FCLK FCLK FCLK FCLK FS FS FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK STAGE 1 STAGE 2 STAGE 3 STAGE 4 STAGE 5 POSITE FILTER FCLK COM- -120 -140 -160 -180 -200 0.125 0.25 0.375 0.5 MAGNITUDE (dB) -60 -40 -20 -80 -100 6dB BANDWIDTH HB1 TRANSITION BW NORMALIZED FREQUENCY HB2 HB3 HB4 HB5 (NORMALIZED TO OUTPUT FREQUENCY) HSP43124

Table 4. These values are the 32-bit, two’s complement, coefficients used to achieve unity gain in the Filter Processor. the programmable filter as an FIR filter. Thus, the Min FCLK is 19.6MHz. the FCLK rate must exceed 14FS. TAPS. The resulting expression is given below. plied by two in order to determine the correct FCLK. input to the filter structure. TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS

TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued)

TABLE 4. HALFBAND FILTER COEFFICIENTS (32 BITS, UN-NORMALIZED) TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued)

Absolute Maximum Ratings Thermal Information Operating Conditions oC to 70oC Thermal Resistance (Typical, Note 1) θJA (oC/W) (SOIC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, FCLK = SCLK = 45MHz Notes 2, 3 - 203 mA Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 µA Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 µA Clock Input High V IHC VCC = Max, FCLK and SCLK 3.0 - V Clock Input Low V ILC VCC = Min, FCLK and SCLK - 0.8 V Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -5mA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 5mA, VCC = Min - 0.4 V Input Capacitance C IN FCLK = SCLK = 1MHz All Measurements Referenced to GND. T A = 25oC, Note 4 -1 0 p F Output Capacitance C OUT -1 0 p F NOTES: 2. Power supply current is proportional to frequency. Typical rating is 4.5mA/MHz. 3. Output load per test circuit and C L = 40pF. 4. Not tested, but characterized at initial design and at major process/design changes. HSP43124

VCC = +4.75V to +5.25V, TA = -40oC to 85oC (Industrial) PARAMETER SYMBOL NOTES 45MHz 40MHz 33MHz UNITSMIN MAX MIN MAX MIN MAX FCLK, SCLK Period t CP 22 - 25 - 30 - ns FCLK, SCLK High t CH 8 - 10 - 12 - ns FCLK, SCLK Low t CL 8 - 10 - 12 - ns Setup Time DIN, MXIN, SYNCIN, SYNCMX to SCLK tDS 8-8-9-n s Hold Time DIN, MXIN, SYNCIN, SYNCMX from SCLK tDH 0-0-0-n s Setup Time FSYNC to FCLK t SS 8-8-8-n s Hold Time FSYNC from FCLK t SH 0-0-0-n s Setup Time C0-7, A0-2 to Falling Edge ofWR t WS 10 - 10 - 10 - ns Hold Time C0-7, A0-2 from Falling Edge ofWR t WH 3-3-3-n s Setup Time A0-2 to Falling Edge ofRD t RS 10 - 10 - 10 - ns Hold Time A0-2 from Rising Edge ofRD t RH 0-0-0-n s WR High t WRH 10 - 10 - 12 - ns WR Low t WRL 10 - 10 - 12 - ns RD High t RDH 10 - 10 - 10 - ns RD Low to Data Valid t RDO -2 5-2 5-2 5 n s RD High to Output Disable t OD -6-6-6 n s FCLK to CLKOUT t FOC -1 2-1 3-1 4 n s CLKOUT to SYNCOUT, DOUT t DO -8-9- 1 0 n s Output Rise, Fall Time t RF Note 6 - 3 - 3 - 3 ns NOTES: VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. EQUIVALENT CIRCUIT C L (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR I CCSB AND ICCOP NOTE: Test head capacitance. HSP43124