SP42450 SIPAT | Alldatasheet

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Technical content

Features

 Design method linearity enhanced Silicon-on -Sapphire device  Five symmetric, absorptive RF ports  High Isolation:  68 dB at 450 MHz  62 dB at 900 MHz  55 dB at 2100 MHz  53 dB at 2600 MHz  50 dB at 4000 MHz  IIP2 of 95 dBm, IIP3 of 58 dBm  High ESD tolerance of 3500 V HBM  Optional External Vss Control (VssEXT)  Three pin CMOS logic control  No blocking capacitors required  Small RoHS-Compliant 24-lead 4x4x0.85 mm QFN package The SP42450 is a linearity enhanced Absorptive SP5T RF Switch developed on the Silicon-on-Sapphire (SOS) process technology. This general purpose switch is comprised of five symmetric RF ports and has very high isolation. An on-chip CMOS decode logic facilitates a three-pin low voltage CMOS control interface and an optional external Vss feature (Vss EXT). High ESD tolerance and no blocking capacitor requirements make this the ultimate in integration and ruggedness. The design methodology, used to create the SP5T RF Switch, is a technology that enhances linearity and has exceptional harmonics performance. It is an innovative feature of the Silicon-on-Sapphire process, providing performance superior to GaAs with the economy and integration of conventional CMOS. Product Description RF2 RF4 RF5 CMOS Control/Driver and ESD V1 V2 ESD RF1 RF3 ESD 50 ESD 50 ESD 50 ESD 50 ESD 50 RFC VssEXT (optional)

Table 1. Electrical Specifications @ 25 °C, VDD = 3.0 V (ZS = ZL = 50 Ω )

450 MHz

900 MHz

2100 MHz

2600 MHz

4000 MHz

Table 2. Operating Ranges must be grounded when using internal Vss supply.

  1. Pull-down resistor in EVK schematic may increase control

Table 3. Pin Descriptions taken to avoid exceeding the specified rating. devices are immune to latch-up. Table 4. Absolute Maximum Ratings

  1. Machine Model ESD Voltage (JESD22-A115-A)

Table 5. Truth Table Figure 3. Pin Configuration (Top View) 24-lead 4x4 QFN package is MSL1.

  1. Pin 20 must be grounded wh en using internal Vss supply

2 RF54 RF I/O

5 RF44 RF I/O

8 RF34 RF I/O

11 RF24 RF I/O

14 RF14 RF I/O

16 VDD Supply

17 V1 Switch control input, CMOS logic level

18 V2 Switch control input, CMOS logic level

19 V3 Switch control input, CMOS logic level

20 VssEXT /

22 RFC4 RF Common

negative voltage generator to eliminate the spurs.

through a 50 Ω transmission line via the top SMA connector. Figure 4. Evaluation Board Layouts Figure 5. Evaluation Board Schematic

1 GND

2 RF5

3 GND

4 GND

5 RF4

6 GND

7 GND

8 RF3

9 GND

10 GND

11 RF2

12 GND

Figure 19. Nominal Linearity Performance (IIP2) Figure 18. Nominal Linearity Performance (IIP3)

Figure 20. Package Drawing