SP301

VSP3010 BURR-BROWN | Alldatasheet

Document overview

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Technical content

12-Bit, 12MHz CCD/CIS SIGNAL PROCESSOR

FEATURES

l 12-BIT, 12MHz A/D CONVERTER l GUARANTEED NO MISSING CODES l 3-CHANNEL, 4MHz COLOR SCAN MODE: Correlated Double Samplers 8-Bit Offset Adjustment DACs 0dB to +13dB PGAs l A/D INPUT MONITOR l INTERNAL VOLTAGE REFERENCE l SINGLE +5V SUPPLY l 3V OR 5V DIGITAL OUTPUT l LOW POWER: 500mW typ (CCD Mode)

DESCRIPTION

The VSP3010 is a complete, three-channel image signal processor for Charge Coupled Device (CCD) or Contact Image Sensor (CIS) systems. Each chan- nel contains sensor signal sampling, Black Level adjustment and a programmable gain amplifier. The three inputs are multiplexed into a high speed, 12-bit analog-to-digital converter. Input circuitry can be configured, by digital command, for CCD or CIS sensors. A Black Clamp and Correlated Double Samplers (CDS) are provided for CCD sensors. For CIS devices, the VSP3010 provides a single-ended sampler and a reference input. The VSP3010 is available in a 48-lead LQFP package and operates from 0°C to +85°C with a single +5V supply. TM © 1999 Burr-Brown Corporation PDS-1542A Printed in U.S.A. June, 1999

APPLICATIONS

l CCD AND CIS COLOR SCANNERS l FAX AND MULTI-FUNCTION MACHINES l INDUSTRIAL /MEDICAL IMAGING SYSTEMS VSP3010 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 For most current data sheet and other product information, visit www.burr-brown.com 8 5 RINP RINN Clamp 8 5 GINP GINN Clamp CDS CDS CDS PGA PGA PGA BINP BINN Clamp 8-Bit DAC 8-Bit DAC 8-Bit DAC MUX Timing Bandgap Reference R G B Offset Register R G B Gain Adjust Register Configuration Register Register Port 12-Bit A/D P/S WRT RD SCLK SD CM REFT REFB OE VDRV B0-B11 (D0-D7, A0-A2) VSP3010 CK1CLP CK2 STRT VREFADCCK TP0

At TA = full specified temperature range, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, and PGA gain = 1, unless otherwise specified. VSP3010Y PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Bits CONVERSION CHARACTERISTICS 3-Channel CCD Mode 12 MHz 3-Channel CIS Mode 12 MHz ANALOG INPUTS Full-Scale Input Range 0.5 3.5 Vp-p Input Capacitance 10 pF External Reference Voltage Range 0.25 1.75 V Reference Input Resistance 800 W Input Limits GND A – 0.3 V DDA + 0.3 V DYNAMIC CHARACTERISTICS Integral Non-Linearity (INL) –1 –2 LSB Differential Non-Linearity (DNL) 0.3 0.75 LSB No Missing Codes 12 Bits Input-Referred Noise 0.3 LSBs rms PSRR VDDA = +5V –0.25V 0.04 % FSR DIGITAL INPUTS Logic Family CMOS Convert Command Start Conversion Rising Edge of ADCCK High Level Input Current (VIN = VDDD ) 20 mA Low Level Input Current (VIN = 0V) 20 mA Positive-Going Threshold Voltage 3.00 3.40 3.80 V Negative-Going Threshold Voltage 1.25 1.65 2.05 V Input Capacitance 5p F DIGITAL OUTPUTS Logic Family CMOS Logic Coding Straight Binary VDRV Supply Range +2.7 +5.3 V Output Voltage, VDRV = +5V Low Level I OL = 50mA +0.1 V High Level I OH = 50mA +4.6 V Low Level I OL = 1.6mA +0.4 V High Level I OH = 0.5mA +2.4 V Output Voltage, VDRV = +3 Low Level I OL = 50mA +0.1 V High Level I OH = 50mA +2.5 V 3-State Enable Time OE = LOW 20 40 ns 3-State Enable Time OE = HIGH 2 10 ns Output Capacitance 5p F Data Latency 6 Clock Cycles Data Output Delay C L = 15pF 12 ns DC ACCURACY Zero Error 0.8 % FS Gain Error 1.5 % FS POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Operating 4.7 5 5.3 V Supply Current: +IS 3-Channel Mode 100 108 mA 1-Channel Mode 82 90 mA Power Dissipation 3-Channel Mode 500 540 mW 1-Channel Mode 410 450 mW Thermal Resistance, qJA 100 °C/W SPECIFIED TEMPERATURE RANGE 0 +85 °C

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The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER (1) RANGE MARKING NUMBER (2) MEDIA VSP3010Y LQFP-48 340 0 °C to +85°C VSP3010Y VSP3010Y 250-Piece Tray "" " " " VSP3010Y/2K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3010Y/2K” will get a single 2000- piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION

PIN DESIGNATOR TYPE DESCRIPTION PIN DESIGNATOR TYPE DESCRIPTION

1 CLP DI Clamp Enable

2 GND A P Analog Ground

3 RINP AI Red-Channel Analog Input

4 RINN AI Red-Channel Reference Input

5 GND A P Analog Ground

6 GINP AI Green-Channel Analog Input

7 GINN AI Green-Channel Reference Input

8 GND A P Analog Ground

9 BINP AI Blue-Channel Analog Input

10 BINN AI Blue-Channel Reference Input

11 GND A P Analog Ground

12 V DDA P Analog Power Supply, +5V

13 STRT DI Start Line Scanning

14 ADCCK DI A/D Converter Clock Input

15 CK1 DI Sample Reference Clock

16 CK2 DI Sample Data Clock

17 GND

18 RD DI Read Signal for Registers

19 WRT DI Write Signal for Registers

20 P/S DI Parallel/Serial Port Select;

HIGH = Parallel, LOW = Serial

21 SD DI Serial Data Input

22 SCLK DI Serial Data Clock

DDD P Digital Power Supply, +5V

24 OE DI A/D Converter Output Enable

25 B0 (D0) LSB DIO A/D Output (Bit 0) and Register Data Port (Bit 0)

26 B1 (D1) DIO A/D Output (Bit 1) and Register Data Port (Bit 1)

27 B2 (D2) DIO A/D Output (Bit 2) and Register Data Port (Bit 2)

28 B3 (D3) DIO A/D Output (Bit 3) and Register Data Port (Bit 3)

29 B4 (D4) DIO A/D Output (Bit 4) and Register Data Port (Bit 4)

30 B5 (D5) DIO A/D Output (Bit 5) and Register Data Port (Bit 5)

31 B6 (D6) DIO A/D Output (Bit 6) and Register Data Port (Bit 6)

32 B7 (D7) DIO A/D Output (Bit 7) and Register Data Port (Bit 7)

33 B8 (A0) DIO A/D Output (Bit 8) and Register Address (Bit 0)

34 B9 (A1) DIO A/D Output (Bit 9) and Register Address (Bit 1)

35 B10 (A2) DIO A/D Output (Bit 10) and Register Address (Bit 2)

36 B11 MSB DO A/D Output (Bit 11)

DRV P Output Driver Voltage Supply

38 V DDD P Digital Power Supply, +5V

39 GND D P Digital Ground

40 TP0 AO A/D Converter Input Monitor Pin

41 GND A P Analog Ground

42 V DDA P Analog Power Supply, +5V

43 V REF AIO Reference Input/Output

44 GND A P Analog Ground

45 REFB AO Bottom Reference

46 CM AO Common-Mode Voltage

47 REFT AO Top Reference

DDA P Analog Power Supply, +5V PIN CONFIGURATION B11 (MSB) B10 (A2) B9 (A1) B8 (A0) B7 (D7) B6 (D6) B5 (D5) B4 (D4) B3 (D3) B2 (D2) B1 (D1) B0 (D0, LSB) VDDA REFT CM REFB GND A VREF VDDA GND A TP0 GND D VDDD VDRV STRT ADCCK CK1 CK2 GND D RD WRT P/S SD SCLK VDDD OE CLP GND A RINP RINN GND A GINP GINN GND A BINP BINN GND A VDDA 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 VSP3010Y

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Timing specifications = tMIN to tMAX with +5V power supply. SYMBOL PARAMETER MIN TYP MAX UNITS tCK1AP 3-Channel Conversion Rate 200 250 ns tCK1A CK1 Pulse Width 15 70 ns tCK2A CK2 Pulse Width 15 70 ns tCCK ADCCK Pulse Width 35 42 ns tCKP ADCCK Period 83 ns tS Sampling Delay 10 ns tCK12A CK1 Falling Edge to CK2 Rising Edge 15 ns tCK21A CK2 Falling Edge to CK1 Rising Edge 50 ns tSET ADCCK Falling Edge to CK1 Rising Edge 10 ns tADCCK2 ADCCK Falling Edge to CK2 Falling Edge 20 ns tADCCK1 ADCCK Falling Edge to CK1 Falling Edge 20 ns tCNV Conversion Delay 22 ns tST Start Conversion Time 20 100 ns Timing for 3-Channel CCD/CIS Mode tCKP tCCK tCCK tCNV tCK12A tCK2A tCK21A tST tSET tCK1AP tCK1A tS tS tADCCK2 GRR 1 G 1 B 1 B R1, G1, B1CCD STRT CK1 CK2 ADCCK tCCK tADCCK1 tCNVtCCK tSET tCKP tS GRR 1 G 1 B 1 B tCK1A R1, G1, B1 tCK1AP tST CIS STRT CK1 ADCCK 3-Channel CCD Mode 3-Channel CIS Mode

TIMING DIAGRAMS (cont.) Timing specifications = tMIN to tMAX with +5V power supply. SYMBOL PARAMETER MIN TYP MAX UNITS tCK1BP 1-Channel Conversion Rate 66 83 ns tCK1B CK1 Pulse Width 15 20 ns tCK2B CK2 Pulse Width 15 20 ns tCCK ADCCK Pulse Width 35 42 ns tCKP ADCCK Period 83 ns tS Sampling Delay 10 ns tCK12B CK1 Falling Edge to CK2 Rising Edge 10 ns tCK21B CK2 Falling Edge to CK1 Rising Edge 30 ns tCK1SET ADCCK Rising Edge to CK1 Rising Edge 10 ns tCK1ADC CK1 Rising Edge to ADCCK Falling Edge 10 ns tADDCK2 ADDCK Falling Edge to CK2 Falling Edge 20 ns tCNV Conversion Delay 22 ns tTR Transmission Time 5 ns tSET ADCCK Falling Edge to CK1 Rising Edge 10 ns Timing for 1-Channel CCD/CIS Mode CCD Output 1-Channel CCD Mode STRT CK1 CK2 ADCCK 1-Channel CIS Mode tS tS tCK1BP tCK1SET tCK1ADC tADCCK2 tCK12B tCK21B tCK2B tTR tCCK tCKP tCCK tCK1B Pixel 1 Pixel 1 CIS STRT CK1 ADCCK tS tCK1BP tCK1B Pixel 1 tCCK tSET tCNV Pixel 1 tCCK tCKP

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TIMING DIAGRAMS (cont.) Timing for Parallel Port Writing Timing for Serial Port Writing SYMBOL PARAMETER MIN TYP MAX UNITS tPR Parallel Ready Time 20 ns tW WRT Pulse Width 30 50 ns tRW Address Setup Time 20 50 ns tDA Data Setup Time 30 50 ns SYMBOL PARAMETER MIN TYP MAX UNITS tW WRT Pulse Width 30 50 ns tWD Data Valid Time 30 ns tSD Data Ready Time 15 50 ns tSCK Serial Clock Pulse Width 30 50 ns tSCKP Serial Clock Period 60 100 ns tSS Serial Ready Time 100 200 ns tSW WRT Pulse Setup Time 50 ns Timing for Reading SYMBOL PARAMETER MIN TYP MAX UNITS tRW Address Setup Time 20 50 ns tDA Data Setup Time 30 50 ns tRD Readout Delay 20 ns tRH Readout Hold Time 1 ns tPR Parallel Ready Time 20 ns Valid Stable Stable D7-D0 A2-A0 P/S WRT Register tRW tPR tDA tW Valid Stable Valid tDA tRW tRD tRH Register A2-A0 RD D7-D0 P/S tPR NOTE: SCLK must be LOW before WRT goes HIGH. P/S SCLK (1) SD A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 WRT Data tSS tSCKP tSCK tSCK tSW tW tWD tSD

TIMING DIAGRAMS (Cont) DOUT Timing Diagram—3-Channel CCD Mode SYMBOL PARAMETER MIN TYP MAX UNITS tCNV Conversion Delay 22 ns tST Start Conversion Time 20 100 ns CCD Output Pixel (n) tCNV tST tCNV tCNV tCNV Pixel (n + 1) (n) (n + 1) R (1) R (1) R (1) RG B R (n) G (n) R (n + 1) G (n +1) B (n) RGB RGB RG B RG B R GB (n + 2) Pixel (n + 2) STRT CK1 CK2 ADCCK CDS Output MUX A/D Input A/D Output NOTE: (1) Depends on the D4 and D5 bits of the Configuration Register and sets to “R” right after the power supply goes ON. Timing for A/D Output SYMBOL PARAMETER MIN TYP MAX UNITS tOES ADC Output Enable Setup Time 20 ns tOEW OE Pulse Width 100 ns tOER Output Enable Time 20 40 ns t3E 3-State Enable Time 2 10 ns tACKD Data Output Delay 12 ns tOEP Parallel Port Setup Time 10 ns tOES tOEP t3EtOER tACKD Valid tOEW P/S OE DOUT ADCCK

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TYPICAL PERFORMANCE CURVES At TA = +25°C, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, fCK1 = 2MHz, and fCK2 = 2MHz, unless otherwise specified. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Gain (V/V) PGA TRANSFER FUNCTION Sample Quantity, N = 100 0 5 10 15 PGA Gain Setting (Setting Code) 20 25 30 35 500 400 300 200 100 Power Dissipation (mW) POWER DISSIPATION vs POWER SUPPLY (1-Channel Mode) Power Supply Voltage (V) 5.00 5.30 650 550 450 350 250 150 Power Dissipation (mW) POWER DISSIPATION vs POWER SUPPLY (3-Channel Mode) 4.70 Power Supply Voltage (V)

The VSP3010 can be operated in one of the following four modes: 3-Channel CCD Mode 3-Channel CIS Mode 1-Channel CCD Mode 1-Channel CIS Mode 3-CHANNEL CCD MODE In this mode, the VSP3010 can simultaneously process three output CCD signals. These signals are AC-coupled to the RINP, GINP, and BINP inputs. RINN, GINN, BINN are not used in this mode and should be grounded. The CLP signal enables internal biasing circuitry to clamp these inputs to a proper voltage, enabling internal CDS circuitry to operate properly. VSP3010 inputs may be applied as DC-coupled inputs, which need to be level-shifted to a proper DC level. The correlated double samplers take two samples of the incoming CCD signals; the CCD reference levels are taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDSs and the result is the CDS’ output. Three channels are used to process three inputs simulta- neously. Each consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset digital-to-analog converter (+50mV to –150mV). A 3-to-1 analog MUX follows the CDS channels and feeds a high performance 12-bit A/D con- verter. The analog MUX can be programmed to cycle between red, green, and blue or blue, green, and red. When the STRT signal is HIGH, the conversion is initiated on the rising edge of ADCCK. The STRT signal indicates the first samples for a scan line. When STRT goes LOW, the analog MUX is switched to the first sample of the sequence. As specified in the “3-Channel CCD Mode” timing diagram, the falling edge of CK2 must be in the LOW period of ADCCK. If the falling edge of CK2 is in the HIGH period of ADCCK (in the timing diagram, ADCCK for sampling B channel), the VSP3010 will not function properly. 3-CHANNEL CIS MODE In this mode, the VSP3010 is operated as 3-channel sam- plers and a digitizer. Unlike the CCD mode, VSP3010 takes only one sample on the falling edge of CK1 for each input. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC-coupled in most cases. For example, for the red channel, RINP is the CIS signal input, and RINN is the CIS reference signal. The same applies to the green channel (GINP and GINN) and blue channel (BINP and BINN). In this mode, three CDSs become CIS signal processing circuits (acting like a track-and-hold) to process three inputs simultaneously. Each CIS signal processing circuit consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX follows the CIS signal processing circuits and feeds a high perfor- mance 12-bit A/D converter. The analog MUX can be programmed to cycle between red, green, and blue or blue, green, and red. When the STRT signal is HIGH, the conversion is initiated on the rising edge of ADCCK. The STRT signal indicates the first sample for a scan line. When STRT goes LOW, the analog MUX is switched to the first sample of the sequence. As specified in the “3-Channel CIS Mode” timing diagram, the falling edge of CK1 must be in the LOW period of ADCCK. If the falling edge of CK1 is in the HIGH period of ADCCK (in the timing diagram, ADCCK for sampling B channel), the VSP3010 will not function properly. 1-CHANNEL CCD MODE In this mode, the VSP3010 processes only one CCD signal. The CCD signal is AC-coupled to RINP, GINP, or BINP (as selected by the data in the Configuration Register). RINN, GINN, BINN are not used in this mode and should be grounded. The CLP signal enables internal biasing circuitry to clamp this input to a proper voltage so that internal CDS circuitry can work properly. The VSP3010 input may be applied as a DC-coupled input, which needs to be level- shifted to a proper DC level. The CDS takes two samples of the incoming CCD signal. The CCD reference value is taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDS and the result is the CDS’ output. In this mode, only one of the three channels is enabled. Each CDS consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX is inserted between the CDSs and a high performance 12-bit A/D converter. The analog MUX is not cycling between channels in this mode. Instead, the analog MUX is con- nected to a specific channel, depending on the data in the Configuration Register. As specified in the “1-Channel CCD Mode” timing diagram, the rising edge of CK1 must be in the HIGH period of ADCCK and the falling edge of the CK2 must be in the LOW period of ADCCK. Otherwise, the VSP3010 will not function properly. 1-CHANNEL CIS MODE In this mode, the VSP3010 is operated as a 1-channel sampler and digitizer. Unlike the CCD mode, VSP3010 takes only one sample on the falling edge of CK1. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC-coupled in most cases. Here, the VSP3010 inputs are differential. For example, for the red channel, RINP is the CIS signal input, and RINN is the CIS reference signal. The same applies to the green channel (GINP and GINN) and blue channel (BINP and BINN).

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on the data in the Configuration Register. VSP3010 will not function properly. register. Figure 1 shows the PGA transfer function plot. DC output of the CCD array from affecting the VSP3010. the DC component of the input signal. FIGURE 2. Equivalent Circuit of VSP3010 Inputs. and N is the number of black pixels, RSW is the total switchFIGURE 1. PGA Transfer Function Plot.

resistance, VD is the droop across CIN and VERROR is the difference between VS and VCLAMP . The nominal value of R SW is 4kW plus the driver’s impedance. 0.1V should be tolerable for VERROR and still keep the VSP3010 working properly. C MIN = ( I/VERROR ) • t where, I is 10nA, the typical leakage current of the VSP3010 input circuitry and t is the time between clamp pulses. PROGRAMMING THE VSP3010 The VSP3010 consists of three CCD or CIS channels and a 12-bit A/D converter. Each channel (red, green, and blue) has its own 8-bit offset and 5-bit gain adjustable registers to be programmed by the user. There is also a 7-bit Configuration Register on-chip to program the different operation modes. These registers are as follows: ADDRESS A2 A1 A0 REGISTER 0 0 0 Configuration Register (7-Bit) 0 0 1 Red Channel Offset Register (8-Bit) 0 1 0 Green Channel Offset Register (8-Bit) 0 1 1 Blue Channel Offset Register (8-Bit) 1 0 0 Red Channel Gain Register (5-Bit) 1 0 1 Green Channel Gain Register (5-Bit) 1 1 0 Blue Channel Gain Reigster (5-Bit) 1 1 1 Reserved For Reading/Writing to the Configuration Register, the ad- dress will be: Example: A 3-channel CCD with internal reference V REF = 1V (2V full-scale input), the mode will be: For this example, VREF will be 1V. Bypass VREF with 10mF and 0.1mF capacitors when internal reference mode is used. Example: A 1-channel CIS mode (red channel) with external 1.2V reference: For this example, VREF will be an input pin, applied with 1.2V. This input will set the full-scale input of the VSP3010 at 2.4V. Offset Registers Offset registers control the analog offset input to the channel prior to the PGA. There is an 8-bit Offset Register on each channel. The offset range varies from –150mV to +50mV. The Offset Register uses a Straight Binary code. All ‘0’s correspond to –150mV and all ‘1’s correspond to +50mV of the offset adjustment. PGA Gain Registers The PGA Gain Registers control the analog gain to the channels prior to the A/D converter. There is a 5-bit PGA Gain Register on each channel. The gain range varies from 1 to 4.44 (0dB to +13dB). The PGA Gain Register is a Straight Binary code. All ‘0’s correspond to analog gain of 0dB and all ‘1’s correspond to the analog gain of 13dB. OFFSET AND GAIN CALIBRATION SEQUENCE DIGITAL OUTPUTS The digital outputs of the VSP3010 are designed to be compatible with both high-speed TTL and CMOS logic families. The driver stage of the digital outputs is supplied through a separate supply pin, VDRV, which is not con- nected to the analog supply pins. By adjusting the voltage on VDRV, the digital output levels will vary respectively. Thus, it is possible to operate the VSP3010 on a +5V analog supply while interfacing the digital outputs to 3V logic. It is recommended to keep the capacitive loading on the data lines as low as possible (typically less than 15pF). Larger capacitive loads demanding higher charging current surges can feed back to the analog portion of the VSP3010 and influence the performance. If necessary, external buffers or latches may be used which provide the added benefit of isolating the VSP3010 from any digital noise activities on OE P/S MODE 0 0 A/D Data Output Enabled, Serial Mode Enabled 0 1 Prohibit Mode 1 0 A/D Data Output Disabled, Serial Mode Enabled 1 1 A/D Data Output Disabled, Parallel Mode Enabled BIT LOGIC ‘0’ LOGIC ‘1’ D0 CCD Mode CIS Mode D1 V REF = 1V V REF = 1.5V D2 Internal Reference External Reference 3-Channel, D4 and D5 Disabled 1-Channel, D4 and D5 Enabled D4 D5 0 0 Red Channel 0 1 Green Channel 1 0 Blue Channel 1 1 Reserved D6 R > G > B MUX Sequence B > G > R MUX Sequence D7 Reserved Reserved These Registers can be accessed by either the parallel or serial port. In the parallel mode, the address and data port are combined with the ADC data output pins. The data bus is assigned as D0 to D7 (pin 25 to pin 32) and the address bus is A0 to A2 (pin 33 to pin 35). In the serial mode, serial data (SD), serial clock (SCLK), and write signal (WRT pin for both parallel and serial writing) are assigned. The following table shows how to access these modes. Configuration Register The Configuration Register is designed as follows:

13 VSP3010

the bus coupling back high frequency noise. In addition, resistors in series with each data line may help minimize the surge current. Their use depends on the capacitive loading seen by the converter. As the output levels change from low to high and high to low, values in the range of 100W to 200W will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances. GROUNDING, BYPASSING, AND POWER SUPPLY RECOMMENDATIONS Proper grounding, bypassing, short lead length and the use of ground planes are particularly important for high fre- quency designs. Multi-layer PC boards are recommended for the best performance since they offer distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers, etc. It is recommended that analog and digital ground pins of the VSP3010 be joined together at the IC and connected only to the analog ground of the system. The VSP3010 has analog and digital supply pins, however, the converter should be treated as an analog component and all supply pins should be powered by the analog supply. This will ensure the most consistent results since digital supply lines often carry high levels of noise that would otherwise be coupled into the converter and degrade the achievable per- formance. As the result of the high operation speed, the converter also generates high frequency current transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 3 shows the recommended decoupling schemes for the entire chip. In most cases, 0.1mF ceramic chip capacitors are adequate to keep the impedance low over the wide frequency range. Their effectiveness largely de- pends on the proximity to the individual supply pin. When the VSP3010 is powered on, it will be initialized as a 3-channel CCD, 1V internal (2V full scale) reference mode with analog gain of 1. This mode is commonly used for CCD scanner applications. The calibration procedure is done at the very beginning of the scan. Once calibration is done, regis- ters on VSP3010 will keep this information (offset and gain for each channel) during the operation. To calibrate the VSP3010, use the following procedure: Step 1: Set the VSP3010 to the proper mode. Step 2: Set analog PGA gain to 1 (code: 00 H ) and offset to 0mV (code: C0H ). Step 3: Scan a dark line. Step 4: Calculate the pixel offsets according to the ADC output. Step 5: Readjust input Offset Registers. Step 6: Scan a white line. Step 7: Calculate gain. It will be the ADC full scale divided by the ADC output when the white line is scanned. Step 8: Set the Gain Register. If the ADC output is not close to full scale, go back to Step 3. The calibration is complete if the output is close to full scale.

33 ADCCK

FIGURE 3. VSP3010 Evaluation Board Schematic

15 VSP3010

FIGURE 4. CCD Application Example.

FIGURE 5. CIS Application Example.