TLV4961-1M INFINEON | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 26
Technical content
Sense & Control Data Sheet Revision 1.0, 2012-05-15 TLV4961-1M High Precision Consumer Hall Effect Latch
81726 Munich, Germany
© 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet 3 Revision 1.0, 2012-05-15 Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CI POS™, CIPURSE™, EconoPAC K™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, Econ oDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, OR IGA™, PRIMARION™, Prim ePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFE T™, thinQ!™, TRENCH STOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Te chnologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVC o, LLC (Visa Holdings In c.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corp oration. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrot echnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics of MURATA MANUFACTURING CO., MICROWAVE OFFI CE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Open wave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sate llite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Sy mbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. T EKTRONIX™ of Tektroni x Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-02-24
Revision History
Page or Item Subjects (major changes since previous revision) Revision 1.0, 2012-05-15
Data Sheet 4 Revision 1.0, 2012-05-15 Table of Contents
Data Sheet 6 Revision 1.0, 2012-05-15 List of Tables
Data Sheet 7 Revision 1.0, 2012-05-15
1 Product Description
1.1 Overview
Figure 1-1 Image of TLV4961-1M in the PG-SOT23-3-15 package
1.2 Features
- 3.0 V to 32 V operating supply voltage
- Operation from unregulated power supply
- Reverse polarity protection (-18 V)
- Overvoltage capability up to 42 V without external resistor
- Output overcurrent & overtemperature protection
- Active error compensation
- High stability of magnetic thresholds
- Low jitter (typ. 0.35 μs)
- High ESD performance
- Small SMD package PG-SOT23-3-15 (TLV4961-1M)
1.3 Target Applications
Target applications for the TLE496x Ha ll switch family are all applications which require a high precision Hall switch with an operating temperature range from -40°C to 85°C. Its superior supply voltage range from 3.0 V to 32 V with overvoltage capa bility (e.g. load-dump) up to 42 V without external resist or makes it ideally suited for automotive and industrial applications. The magnetic behavior as a latch and switching thresholds of typical ±2 mT make the device especially suited for the use with a pole wheel for index counting applications as e.g. power closing and window lifter. Characteristic Supply Voltage Supply Current Sensitivity Interface Temperature Bipolar Hall Effect Latch 3.0~32 V 1.6 mA High BOP:2 mT BRP:-2 mT Open Drain Output -40°C to 85°C Table 1-1 Ordering Information Product Name Product Type Ordering Code Package TLV4961-1M Hall Latch SP000965272 PG-SOT23-3-15
Data Sheet 8 Revision 1.0, 2012-05-15
2 Functional Description
2.1 General
The TLV4961-1M is an integrated Hall effect latch desi gned specifically for highly accurate applications with superior supply voltage c apability, operating temper ature range and temperatur e stability of the magnetic thresholds.
2.2 Pin Configuration (top view)
Figure 2-1 Pin Configuration and Center of Sensitive Area
2.3 Pin Description
Table 2-1 Pin Description PG-SOT23-3-15 Pin No. Symbol Function
1 VDD Supply voltage
2 Q Output
3 GND Ground
1.45± 0.1 0.65± 0.1 SOT23 Center of Sensitive Area
Data Sheet 9 Revision 1.0, 2012-05-15
2.4 Block Diagram
Figure 2-2 Functional Block Diagram TLV4961-1M
2.5 Functional Block Description
The chopped Hall IC switch comprises a Hall probe, bias generator, compensation circuits, oscillator and output transistor. The bias generator provides currents for the Hall probe and the active circuits. Compensation circuits stabilize the temperature behavior and reduce influence of technology variations. The active error compensation (chopping technique) reje cts offsets in the signal path and the influence of mechanical stress to the Hall probe caused by molding and soldering processes and other thermal stress in the package. The chopped measurement principle together with the threshold generator and the comparator ensures highly accurate and temperature stable magnetic thresholds. The output transistor has an integrated overcurrent and overtemperature protection. Voltage Regulator Bias and Compensation Circuits Oscillator and Sequencer To All Subcircuits Spinning Hall Probe Chopper Multiplexer Amplifier Demodulator Low Pass Filter Comparator with Hysteresis Control Overtemperature & overcurrent protection GND Q VDD Reference
Data Sheet 11 Revision 1.0, 2012-05-15
2.6 Start-up behavior
The magnetic threshold exhibit a hysteresis BHYS = BOP-BRP. In case of a power-on with a magnetic field B within hysteresis (BRP < B < BOP) the output of the sensor is set to “HIGH” per default. After the first crossing of B OP or BRP of the magnetic field the output is set to the correct value. Figure 2-5 Illustration of the start-up behavior of the TLV4961-1M t t t VQ t B > BOP B < BRP BOP > B > BRP Magnetic field above threshold Magnetic field below threshold Magnetic field in hysteresis Power on ramp The device always applies VQ level at start -up independent from the applied magnetic field ! VQ VQ VS tPon
Data Sheet 12 Revision 1.0, 2012-05-15
3 Specification
3.1 Application Circuit
The following Figure 3-1 shows one option of an application circuit. As explained above the resistor RS can be left out (see Figure 3-2). The resistor R Q has to be in a dimension to match the applied V S to keep IQ limited to the operating rage of maximum 25 mA. e.g.: V S = 12 V IQ = 12 V/1200 Ω = 10 mA Figure 3-1 Application Circuit 1: with external resistor Figure 3-2 Application Circuit 2: without external resistor TLE496x GND Vs RQ = 1.2kΩ CDD = 47nF VDD Q TVS diode e.g. ESD24VS2U RS = 100Ω TLE496x GND Vs RQ = 1.2kΩ CDD = 47nF VDD Q TVS diode e.g. ESD24VS2U
Data Sheet 13 Revision 1.0, 2012-05-15
3.2 Absolute Maximum Ratings
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Calculation of the dissipated power PDIS and junction temperature TJ of the chip (SOT23 example): e.g for: VDD = 12 V, IS = 2.5 mA, VQSAT = 0.5 V, IQ = 20 mA Power dissipation: PDIS = 12 V x 2.5 mA + 0.5 V x 20 mA = 30 mW + 10 mW = 40 mW Temperature ∆T = RthJA x PDIS = 300 K/W x 40 mW = 12 K For TA = 50 °C: TJ = TA + ∆T = 50 °C + 12 K = 62 °C Table 3-1 Absolute Maxi mum Rating Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply voltage V DD -18 32 V 10h, no external resistor required Output voltage V Q -0.5 32 V Reverse output current I Q -70 mA Junction temperature1) 1) This lifetime statem ent is an anticipation based on an extrapolation of Infineon’s qualification test results. The actual lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime statement shall in no event extend the agreed warranty period. TJ -40 125 °C Ambient temperature T A -40 150 °C Storage temperature T S -40 150 °C Thermal resistance Junction ambient RthJA 300 K/W for PG-SOT23-3-15 (2s2p) Thermal resistance Junction lead RthJL 100 K/W for PG-SOT23-3-15 Table 3-2 ESD Protection 1) (TA = 25°C) 1) Characterization of ESD is carried out on a sample basis, not subject to production test. Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ESD voltage (HBM)2) 2) Human Body Model (HBM) tests according to EIA/JESD22-A114. VESD -7 7 kV R = 1.5 k Ω, C = 100 pF ESD voltage (SDM)3) 3) Socket device model (SDM) tests according to EOS/ESD-DS5.3-1993. -1 1 ESD voltage (system level)4) 4) Gun test (2k Ω / 330pF or 330Ω / 150pF) according to ISO 10605-2008. -15 15 with circuit shown in Figure 3-1 & Figure 3-2
Data Sheet 14 Revision 1.0, 2012-05-15
3.3 Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLV4961-1K. All parameters specified in the following sections refer to these operating conditions unless otherwise mentioned.
3.4 Electrical and Magnetic Characteristics
Product characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are th e median of the production and correspond to V DD = 12 V and TA = 25°C. The below listed specification is valid in combination with the application circuit shown in Figure 3-1 and Figure 3-2 Table 3-3 Operating Conditions Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply voltage V DD 3.0 32 1) 1) Latch-up test with factor 1.5 is not covered. Please see max ratings also. V Output voltage V Q -0.3 32 V Junction temperature T j -40 85 °C Output current I Q 02 5 m A Magnetic signal input frequency2) 2) For operation at the maximum switching fr equency the magnetic input signal must be 1.4 times higher than for static fields. This is due to the -3dB corner frequency of the internal low-pass filter in the signal path. fSW 01 0 k H z Table 3-4 General Electrical Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply current I S 1 . 11 . 62 . 5m A Reverse current I SR 0.05 1 mA for V DD = -18 V Output saturation voltage VQSAT 0.2 0.5 V I Q = 20 mA 0.24 0.6 V I Q = 25 mA Output leakage current IQLEAK 10 μA Output current limitation IQLIMIT 30 56 70 mA internally limited & thermal shutdown Output fall time1) 1) Not subject to production test, ve rified by design/characterization. tf 0.17 0.4 1 μs1 . 2 k Ω / 50 pF, see Figure 2-3 Output rise time1) tr 0.4 0.5 1 μs1 . 2 k Ω / 50 pF, see Figure 2-3 Output jitter1)2) 2) Output jitter is the 1 σ value of the output switching distribution. tQJ 0.35 1 μs For square wave signal with 1 kHz Delay time1)3) 3) Systematic delay between magnetic threshold reached and output switching. td 12 15 30 μss e e Figure 2-3 Power-on time1)4) 4) Time from applying V DD = 3.0 V to the sensor until the output is valid. tPON 80 150 μsV DD =3V ,B ≤ BRP -0 . 5m To r B ≥ BOP +0 . 5m T Chopper frequency1) fOSC 350 kHz
Data Sheet 15 Revision 1.0, 2012-05-15 Field Direction Definition Positive magnetic fields are defined with the south pole of the magnet to the branded side of package. Figure 3-3 Definition of magnetic field direction PG-SOT23-3-15 Table 3-5 Magnetic Characteristics Parameter Symbol T (°C) Values Unit Note / Test Condition Min. Typ. Max. Operating point B OP -40 0.6 2.1 3.6 mT 25 0.5 2.0 3.5 85 0.4 1.9 3.3 Release point B 25 -3.5 -2.0 -0.5 85 -3.3 -1.9 -0.4 Hysteresis B HYS -40 2.7 4.2 5.7 mT 25 2.6 4.0 5.4 85 2.3 3.7 4.9 Effective noise value of the magnetic switching points 1) The magnetic noise is normal distributed and can be assu med as nearly independent to frequency without sampling noise or digital noise effects. The typical value represents the rms-value and corresponds therefore to a 1 σ probability of normal distribution. Consequently a 3 σ value corresponds to 99.7% probability of appearance. BNeff 25 62 μT Temperature compensation of magnetic thresholds2) 2) Not subject to production test, ve rified by design/characterization. TC -1200 ppm/K Branded Side N S
Data Sheet 16 Revision 1.0, 2012-05-15
3.5 Electro Magnetic Compatibility
Characterization of Electro Magnetic Compatibility is carried out on a sample basis from one qualification lot. Not all specification parameters have been monitored during EMC exposure. Figure 3-4 EMC test circuit Ref: ISO 7637-2 (Version 2004), test circuit Figure 3.4 (with external resistor, RS = 100 Ω) Ref: ISO 7637-2 (Version 2004), test circuit Figure 3.4 (without external resistor, RS = 0Ω) Table 3-6 Magnetic Compatibility Parameter Symbol Level / Type Status Testpulse 1 Testpulse 2a1) Testpulse 2b Testpulse 3a Testpulse 3b Testpulse 4 Testpulse 5b3) 1) ISO 7637-2 (2004) describes internal resistance = 2 Ω (former 10 Ω). 2) According to 7637-2 for test pulse 4 the test voltage shall be 12 V +/- 0.2 V. 3) A central load dump protection of 42 V is used. Us* = 42 V-13.5 V. VEMC -100 V
60 V/110 V
-150 V 100 V -7 V / -5.5 V U S = 86.5 V / US* = 28.5 V C A/C C A A A A Table 3-7 Electro Magnetic Compatibility Parameter Symbol Level / Type Status Testpulse 1 Testpulse 2a Testpulse 2b Testpulse 3a Testpulse 3b Testpulse 4 Testpulse 5b3) 1) ISO 7637-2 (2004) describes internal resistance = 2 Ω (former 10 Ω). 2) According to 7637-2 for test pulse 4 the test voltage shall be 12 V +/- 0.2 V. 3) A central load dump protection of 42 V is used. Us* = 42 V-13.5 V. VEMC -50 V 50 V 10 V -150 V 100 V -7 V / 5.5 V U S = 86.5 V / US* = 28.5 V C A C A A A A TLE496x GND Vs RQ = 1.2kΩ CDD = 10nF Rs VDD Q CQ = 10nF +5V
Package Information
Data Sheet 17 Revision 1.0, 2012-05-15
4 Package Information
The TLV4961-1M is available in the small halogen free SMD package PG-SOT23-3-15.
4.1 Package Outline PG-SOT23-3-15
Figure 4-1 PG-SOT23-3-15 Package Outline (All dimensions in mm)
4.2 Packing Information PG-SOT23-3-15
Figure 4-2 Packing of the PG-SOT23-3-15 in a tape
0.25 M BC
1.9 -0.05 +0.10.4 ±0.12.9 0.95 C B 0...8° 0.2 A 0.1 MAX. 10° MAX. 1.3 ±0.1 10° MAX. M 2.4 ±0.15 ±0.11 A 0.15 MIN. 1) Lead width can be 0.6 max. in dambar area SOT23-TP V02 3.15 2.65 2.13 0.9 0.2 1.15Pin 1
Data Sheet 18 Revision 1.0, 2012-05-15
4.3 Footprint PG-SC59- 3-5 and PG-SOT23-3-15
Figure 4-3 Footprint PG-SC59-3-5 and PG-SOT23-3-15
4.4 PG-SOT23-3-15 Distance between Chip and Package
Figure 4-4 Distance between chip and package
4.5 Package Marking
Figure 4-5 Marking of TLV4961-1M Reflow Soldering Wave Soldering 0.8 0.8 1.2 0.9 1.3 0.9 0.8 0.8 1.2 1.6 1.4 min1.4 min Year (y) = 0...9 Month (m) = 1...9, o-O c t o b e r n-N o v e m b e r d-D e c e m b e r y mV11
Graphs of the Magnetic Parameters Data Sheet 19 Revision 1.0, 2012-05-15
5 Graphs of the Magnetic Parameters
Figure 5-1 Operating Point (B OP) of the TLV4961-1M over Temperature Figure 5-2 Release Point (B RP) of the TLV4961-1M over Temperature Figure 5-3 Hysteresis (B Hys) of the TLV4961-1M over Temperature 1,50 2,00 2,50 3,00 3,50 4,00BOP[mT] Typ Min 0,00 0,50 1,00 /g88250,00 0,00 50,00 100,00 150,00 T A[°C] Max /g8822,50 /g8822,00 /g8821,50 /g8821,00 /g8820,50 0,00 BRP[mT] Typ Min /g8824,00 /g8823,50 /g8823,00 /g88250,00 0,00 50,00 100,00 150,00 TA[°C] Max 2,00 3,00 4,00 5,00 6,00BHys[mT] Typ Min 0,00 1,00 -50,00 0,00 50,00 100,00 150,00 TA[°C] Max
Graphs of the Electrical Parameters Data Sheet 20 Revision 1.0, 2012-05-15
6 Graphs of the Electrical Parameters
Figure 6-1 Power On Time t PON of the TLV4961-1M over Temperature Figure 6-2 Signal Delay Time of the TLV4961-1M over Temperature tPON_max[μs] /g88250 /g88230 /g88210 10 30 50 70 90 110 130 150 T/g3[°C] 14,5 15,5tD [µs] 3V 12V 12,5 13,5 -50 -30 -10 10 30 50 70 90 110 130 150 T [°C]
Published by Infineon Technologies AG www.infineon.com