SN0804050PAGR

TAS5508B_17 TI1 | Alldatasheet

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date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES162C December 2005 Revised July 2009

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 3.2.2 Power Down PDN 3.2.3 Back-End Error BKND_ERR 3.2.3.1 BKND_ERR and VALID 3.2.4 Speaker/Headphone Selector HP_SEL 3.2.5 Mute MUTE 3.3 Device Configuration Controls 3.3.1 Channel Configuration Registers 3.3.2 Headphone Configuration Registers 3.3.3 Audio System Configurations 3.3.3.1 Using Line Outputs in 6-Channel Configurations 3.3.4 Recovery from Clock Error 3.3.5 Power-Supply Volume-Control Enable 3.3.6 Volume and Mute Update Rate 3.3.7 Modulation Index Limit 3.4 Master Clock and Serial Data Rate Controls 3.4.1 PLL Operation 3.5 Bank Controls 3.5.1 Manual Bank Selection 3.5.2 Automatic Bank Selection 3.5.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled 3.5.3 Bank Set 3.5.4 Bank-Switch Timeline 3.5.5 Bank-Switching Example 3.5.6 Bank-Switching Example Electrical Specifications 4.1 Absolute Maximum Ratings 4.2 Dissipation Rating Table (High-k Board, 105 C Junction) 4.3 Dynamic Performance at Recommended Operating Conditions at C 4.4 Recommended Operating Conditions 4.5 Electrical Characteristics 4.6 PWM Operation 4.7 Switching Characteristics 4.7.1 Clock Signals 4.7.2 Serial Audio Port 4.7.3 TAS5508B Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I C-Bus Devices 4.7.4 TAS5508B Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I C-Bus Devices 4.7.4.1 Recommended I C Pullup Resistors 4.7.5 Reset Timing RESET 4.7.6 Power-Down PDN Timing 4.7.7 Back-End Error BKND_ERR 4.7.8 Mute Timing MUTE 4.7.9 Headphone Select HP_SEL 4.7.10 Volume Control 4.8 Serial Audio Interface Control and Timing 4.8.1 I S Timing 4.8.2 Left-Justified Timing 4.8.3 Right-Justified Timing I C Serial-Control Interface (Slave Addresses 0x36 and 0x37) 5.1 General I C Operation 5.2 Single- and Multiple-Byte Transfers 5.3 Single-Byte Write

Contents

www.ti.com 5.4 Multiple-Byte Write 5.5 Incremental Multiple-Byte Write 5.6 Single-Byte Read 5.7 Multiple-Byte Read Serial-Control I C Register Summary Serial-Control Interface Register Definitions 7.1 Clock Control Register (0x00) 7.2 General Status Register (0x01) 7.3 System Control Register (0x03) 7.4 System Control Register (0x04) 7.5 Channel Configuration Control Registers (0x05 0x0C) 7.6 Headphone Configuration Control Register (0x0D) 7.7 Serial Data Interface Control Register (0x0E) 7.8 Soft Mute Register (0x0F) 7.9 Automute Control Register (0x14) 7.10 Output Automute PWM Threshold and Back-End Reset Period Register (0x15) 7.11 Modulation Index Limit Register (0x16) 7.12 Bank-Switching Command Register (0x40) 7.13 Input Mixer Registers, Channels (0x41 0x48) 7.14 Bass Management Registers (0x49 0x50) 7.15 Biquad Filter Register (0x51 0x88) 7.16 Bass and Treble Bypass Register, Channels (0x89 0x90) 7.17 Loudness Registers (0x91 0x95) 7.18 DRC1 Control Registers, Channels (0x96) 7.19 DRC2 Control Register, Channel (0x97) 7.20 DRC1 Data Registers (0x98 0x9C) 7.21 DRC2 Data Registers (0x9D 0xA1) 7.22 DRC Bypass Registers (0xA2 0xA9) 7.23 Output Mixer Registers (0xAA 0xAF) 7.24 Output Mixer Registers (0xB0 0xB1) 7.25 PSVC Volume Biquad Register (0xCF) 7.26 Volume, Treble, and Bass Slew Rates Register (0xD0) 7.27 Volume Registers (0xD1 0xD9) 7.28 Bass Filter Set Register (0xDA) 7.29 Bass Filter Index Register (0xDB) 7.30 Treble Filter Set Register (0xDC) 7.31 Treble Filter Index (0xDD) 7.32 AM Mode Register (0xDE) 7.33 PSVC Range Register (0xDF) 7.34 General Control Register (0xE0) 7.35 Incremental Multiple-Byte Write Append Register (0xFE) TAS5508B Example Application Schematic

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 List of Figures 1-1 TAS5508B Functional Structure 1-2 Typical TAS5508B Application (DVD Receiver) 1-3 Pass-Through Output Mixer TAS5508B Channel Configuration 2-1 TAS5508B DAP Architecture With I C Registers S kHz) 2-2 TAS5508B Architecture With I C Registers S 176.4 kHz or f S 192 kHz) 2-3 TAS5508B Detailed Channel Processing 2-4 5.23 Format 2-5 Conversion Weighting Factors 5.23 Format to Floating Point 2-6 Alignment of 5.23 Coefficient in 32-Bit I C Word 2-7 25.23 Format 2-8 Conversion Weighting Factors 25.23 Format to Floating Point 2-9 Alignment of 25.23 Coefficient in Two 32-Bit I C Words 2-10 TAS5508B Digital Audio Processing 2-11 Input Crossbar Mixer 2-12 Biquad Filter Structure 2-13 Automute Threshold 2-14 Loudness Compensation Functional Block Diagram 2-15 Loudness Example Plots 2-16 DRC Positioning in TAS5508B Processing Flow 2-17 Dynamic Range Compression (DRC) Transfer Function Structure 2-18 Output Mixers 2-19 De-Emphasis Filter Characteristics 2-20 Power-Supply and Digital Gains (Linear Space) 2-21 Power-Supply and Digital Gains (Log Space) 2-22 Block Diagrams of Typical Systems Requiring TAS5508B Automatic AM Interference-Avoidance Circuit 4-1 Slave Mode Serial Data Interface Timing 4-2 Start and Stop Conditions Timing Waveforms 4-3 I C Pullup Circuit (With No Series Resistor) 4-4 I C Pullup Circuit (With Series Resistor) 4-5 Reset Timing 4-6 Power-Down Timing 4-7 Error-Recovery Timing 4-8 Mute Timing 4-9 HP_SEL Timing 4-10 I S 64-f S Format 4-11 Left-Justified 64-f S Format 4-12 Right-Justified 64-f S Format 5-1 Typical I C Sequence 5-2 Single-Byte Write Transfer List of Figures

www.ti.com 5-3 Multiple-Byte Write Transfer 5-4 Single-Byte Read Transfer 5-5 Multiple-Byte Read Transfer List of Figures Submit Documentation Feedback

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 List of Tables 1-1 I C Register 0xD0 Bit Usage 2-1 Serial Data Formats 2-2 TAS5508B Audio-Processing Feature Sets 2-3 (Default All-Pass) 2-4 Bass and Treble Filter Selections 2-5 Linear Gain Step Size 2-6 Default Loudness Compensation Parameters 2-7 Example Loudness Function Parameters 2-8 DRC Recommended Changes From TAS5508B Defaults 3-1 Device Outputs During Reset 3-2 Values Set During Reset 3-3 Device Outputs During Power Down 3-4 Device Outputs During Back-End Error 3-5

Description

(0x05 to 0x0C) 3-6 Recommended TAS5508B Configurations for Texas Instruments Power Stages 3-7 Audio System Configuration (General Control Register 0xE0) 3-8 Volume Ramp Periods in ms 7-1 Clock Control Register Format 7-2 General Status Register Format 7-3 System Control Register-1 Format 7-4 System Control Register-2 Format 7-5 Channel Configuration Control Register Format 7-6 Headphone Configuration Control Register Format 7-7 Serial Data Interface Control Register Format 7-8 Soft Mute Register Format 7-9 Automute Control Register Format 7-10 Automute PWM Threshold and Back-End Reset Period Register Format 7-11 Modulation Index Limit Register Format 7-12 Bank-Switching Command Register Format 7-13 Channel Input Mixer Register Format 7-14 Bass Management Register Format 7-15 Biquad Filter Register Format 7-16 (Default All-Pass) 7-17 Channel Bass and Treble Bypass Register Format 7-18 Loudness Register Format 7-19 Channel DCR1 Control Register Format 7-20 Channel-8 DRC2 Control Register Format 7-21 DRC1 Data Register Format 7-22 DRC2 Data Register Format List of Tables

www.ti.com 7-23 DRC Bypass Register Format 7-24 Output Mixer Register Format (Upper Bytes) 7-25 Output Mixer Register Format (Lower Bytes) 7-26 Output Mixer Register Format (Upper Bytes) 7-27 Output Mixer Register Format (Middle Bytes) 7-28 Output Mixer Register Format (Lower Bytes) 7-29 Volume Biquad Register Format (Default All-Pass) 7-30 Volume Gain Update Rate (Slew Rate) 7-31 Treble and Bass Gain Step Size (Slew Rate) 7-32 Volume Register Format 7-33 Master and Individual Volume Controls 7-34 Channel (Subwoofer) 7-35 Channels and (Right and Left Lineout in 6-Channel Configuration; Right and Left Surround in 8-Channel Configuration) 7-36 Channels and (Right and Left Rear) 7-37 Channels and (Center, Right Front, and Left Front) 7-38 Bass Filter Index Register Format 7-39 Bass Filter Indexes 7-40 Channel (Subwoofer) 7-41 Channels and (Right and Left Lineout in 6-Channel Configuration; Right and Left Surround in 8-Channel Configuration) 7-42 Channels and (Right and Left Rear) 7-43 Channels and (Center, Right Front, and Left Front) 7-44 Treble Filter Index Register Format 7-45 Treble Filter Indexes 7-46 AM Mode Register Format 7-47 AM Tuned Frequency Register in BCD Mode (Lower Bytes of 0xDE) 7-48 AM Tuned Frequency Register in Binary Mode (Lower Bytes of 0xDE) 7-49 PSVC Range Register Format 7-50 General Control Register Format List of Tables Submit Documentation Feedback

1.1

Features

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 and C General LS, RS Automated Operation With an Easy-to-Use LR, RR Control Interface Sub I C Serial-Control Slave Interface Configurable Loudness Compensation Integrated AM Interference-Avoidance Circuitry Two Dynamic Range Compressors With Two Thresholds, Two Offsets, and Three Single, 3.3-V Power Supply Slopes 64-Pin TQFP Package Seven Biquads Per Channel 5-V Tolerant Inputs Full Input Crossbar Mixer. Each Audio Input/Output Signal-Processing Channel Input Can Be Automatic Master-Clock-Rate and Any Ratio of the Eight Input Channels. Data-Sample-Rate Detection Output Mixer, Channels Each Eight Serial Audio Input Channels Output Is a Mix of Any Two Eight PWM Audio Output Channels Signal-Processed Channels. It Is Configurable as Six Channels With Stereo Recommended to Use the Pass-Through Lineout or Eight Channels output Mixer Configuration. Line Output Is a PWM Output to Drive an Output Mixer, Channels and Each External Differential-Input Operational Output Is a Mix of Any Three Amplifier Signal-Processed Channels. It Is Headphone PWM Output to Drive an Recommended to Use the Pass-Through External Differential Amplifier Like the Output Mixer Configuration. TPA112 Three Coefficient Sets Stored on the Device PWM Outputs Support Single-Ended and Can Be Selected Manually or Automatically Bridge-Tied Loads (Based on Specific Data Rates). 32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and DC Blocking Filters 192-kHz Sampling Rates Able to Support a Variety of Bass Data Formats: 16-, 20-, or 24-Bit Management Algorithms Left-Justified, I or Right-Justified Input PWM Processing Data 32-Bit Processing PWM Architecture With 64-f S Bit-Clock Rate Bits of Precision 128-, 192-, 256-, 384-, 512-, and 768-f S Oversampling With Fifth-Order Noise Master Clock Rates (Up to a Maximum of Shaping at kHz kHz, MHz) Oversampling at 88.2 kHz and kHz, and Audio Processing Oversampling at 176.4 kHz and 192 kHz 48-Bit Processing Architecture With Bits >102-dB Dynamic Range of Precision for Most Audio-Processing THD+N 0.1% 20-kHz, Flat Noise Floor for 44.1-, Volume Control Range dB to 109 dB 48-, 88.2-, 96-, 176.4-, and 192-kHz Data Master Volume Control Range of dB Rates to 109 dB Digital De-Emphasis for 32-, 44.1-, and Eight Individual Channel Volume Control 48-kHz Data Rates Ranges of dB to 109 dB Flexible Automute Logic With Programmable Soft Volume and Mute Programmable Threshold and Duration for Update Rates Noise-Free Operation Four Bass and Treble Tone Controls With Intelligent AM Interference-Avoidance 18-dB Range, Selectable Corner System Provides Clear AM Reception Frequencies, and Second-Order Slopes Power-Supply Volume Control (PSVC) Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

document. Matlab is a trademark of Math Works, Inc. PRODUCTION DATA information is current as of publication date. Copyright 2005 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

1.2 Overview TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Support for Enhanced Dynamic Range in Adjustable Modulation Limit High-Performance (PWM) that provides both advanced performance and a high level of system integration. The TAS5508B is designed to interface seamlessly with most audio digital signal processors. The TAS5508B automatically adjusts control configurations in response to clock and data rate changes and idle conditions. This enables the TAS5508B to provide an easy-to-use control interface with relaxed timing requirements. The TAS5508B can drive eight channels of H-bridge power stages. Texas Instruments power stage parts TAS5111, TAS5112, or TAS5182 with FETs are designed to work seamlessly with the TAS5508B. The TAS5508B supports either the single-ended or bridge-tied-load configuration. The TAS5508B also provides a high-performance, differential output to drive an external, differential-input, analog headphone amplifier (such as the TPA112). The TAS5508B uses AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data. The oversampling combined with the fifth-order noise shaper provides a broad, flat noise floor and excellent dynamic range from Hz to kHz. The TAS5508B is a clocked slave-only device. The TAS5508B receives MCLK, SCLK, and LRCLK from other system components. The TAS5508B accepts master clock rates of 128, 192, 256, 384, 512, and 768 f S The TAS5508B accepts a 64-f S bit clock. The TAS5508B allows for extending the dynamic range by providing a power-supply, volume-control (PSVC) output signal. Introduction Submit Documentation Feedback

PWM_HPP and MR PWM_HPP and ML MCLK XTL_OUT XTL_IN PLL_FLTM PLL_FLTP OSC CAP SCLK LRCLK SDIN1 SDIN2 SDIN3 SDIN4 SDA SCL RESET PDN MUTE HP_SEL BKND_ERR PWM Section PWM AP and AM7 Center PWM AP and AM4 R Rear PWM AP and AM3 L Rear PWM AP and AM8 Subwoofer PWM AP and AM1 L Front PWM AP and AM2 R Front Power Supply PWM AP and AM5 L Surround PWM L Lineout PWM AP and AM6 R Surround PWM R Lineout Digital Audio Processor VALID Device Control 88 4 2 Det PSVC9 PSVC Volume Control Clock, PLL, and Serial Data I/F I2C Serial Control I/F VR_PLL AVDD_PLL AVSS_PLL AVDD_REF VBGAP VRA_PLL VRD_PLL DVDD DVSS AVDD System Control DAP Control PWM Control 8 × 8 Crossbar Mixer Biquads DC Block De Emph SRC NS PWM Det Biquads DRCLoud Comp Soft Tone DC Block De Emph SRC NS PWM 8 × 2 Crossbar Mixer Det Biquads DRCLoud Comp Soft Tone DC Block De Emph SRC NS PWM Det Biquads DRCLoud Comp Soft Tone DC Block De Emph SRC NS PWM Det Biquads DRCLoud Comp Soft Tone DC Block De Emph SRC NS PWM Det Biquads DRCLoud Comp Soft Tone DC Block De Emph SRC NS PWM Det Biquads DRCLoud Comp Soft Tone DC Block De Emph SRC NS PWM Det Biquads DRCLoud Comp Soft Tone DC Block De Emph Interpolate SRC NS PWM Soft Tone DRCLoud Comp Output Control Interpolate Interpolate Interpolate Interpolate Interpolate Interpolate Interpolate B0011-01 AVSS Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Figure 1-1. TAS5508B Functional Structure Submit Documentation Feedback Introduction

1.3 Changes From the TAS5508A to the TAS5508B 1.4 TAS5508B System Diagrams TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com High-pass filter is enabled by default (0x03 bit I C register 0xD0 bit is added in TAS5508B to support remapped output mixer configuration. It has a default value of Table 1-1. I C Register 0xD0 Bit Usage 0xD0 Bit Output Mixer Configuration Mode PWM (Speaker) Operation Headphone operation 8-channel mode or Pass-through 6-channel mode Normal operation Normal operation channels become lineouts) Constraints are placed in setting the combined volume 8-channel mode Normal Operation below 109 dB and in using individual channel mute. (default) Remapped Following the assertion or Constraints are placed in de-assertion of headphone, 6-channel mode setting the combined volume mute must be asserted and channels become lineouts) below 109 dB and in using de-asserted using the individual channel mute. MUTE pin. The pass-through output mixer configuration means that each DAP channel is mapped to the same output PWM channel. For example, DAP channel is routed to PWM channel etc. The remapped output mixer configuration means that the PWM channel could be a mix or rerouting of the DAP channels. For example, DAP channel is routed to PWM channel This remapping causes some complications in operation (see Table 1-1 The TAS55508 recommended initialization sequence to use the pass-through ouput mixer configuration follows. After TAS5508B reset, the default master volume is muted. It must be updated with a nonmute value for the system to start. I C register 0xD0 bit must be set to a value of Note that for best results, the pass-through ouput mixer configuration is recommended (0xD0 Bit 1). When remapping or mixing DAP channels to different PWM output channels (remapped output mixer configuration) consider the following limitations: Individual channel mute should not be used. The sum of the minimum channel volume and master volume should not be below 109 dB. 0xD0 bit Typical receivers. Figure 1-2 shows the basic system diagram of the DVD receiver. Introduction Submit Documentation Feedback

PWM_M_1 PWM_P_1 PWM_M_2 PWM_P_2 PWM_M_3 PWM_P_3 PWM_M_4 PWM_P_4 PWM_M_7 PWM_P_7 PWM_M_8 PWM_P_8 PWM_M_5 PWM_P_5 PWM_M_6 PWM_P_6 LEFTRIGHT LEFT SURROUNDCENTERSUBWOOFER RIGHT SURROUND LEFT BACK SURROUND RIGHT BACK SURROUND PWM to Analog (Line Level) PWM to Analog (Headphone Level) Headphone Out Right Headphone Out Left PWM_HPML PWM_HPPL PWM_HPMR PWM_HPPR PWM_M_5 PWM_P_5 PWM_M_6 PWM_P_6 B0013-03 I2C Control and Status SDIN 1, 2, 3, 4 (8-Channel PCM) Clocks HW Control and Status Lineout Left Lineout Right TAS5121 + − TAS5121 + − TAS5121 + − TAS5121 + − TAS5121 + − TAS5121 + − TAS5121 + − TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Figure 1-2. Typical TAS5508B Application (DVD Receiver) Figure 1-3 shows the pass-through output mixer channel configuration when using the TAS5508B. Figure 1-3. Pass-Through Output Mixer TAS5508B Channel Configuration Submit Documentation Feedback Introduction

2.1 Physical Characteristics 2.1.1 Terminal Assignments VR_PWM PWM_P_4 PWM_M_4 PWM_P_3 PWM_M_3 PWM_P_2 PWM_M_2 PWM_P_1 PWM_M_1 VALID DVSS BKND_ERR DVDD DVSS DVSS VR_DIG VRA_PLL PLL_FLT_RET PLL_FLTM PLL_FLTP AVSS AVSS VRD_PLL AVSS_PLL AVDD_PLL VBGAP RESET HP_SEL PDN MUTE DVDD DVSS 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PAG P ACKAGE (TOP VIEW) VR_DPLL OSC_CAP XTL_OUT XTL_IN RESERVED RESERVED RESERVED SDA SCL LRCLK SCLK SDIN4 SDIN3 SDIN2 SDIN1 PSVC RESEVED MCLK PWM_HPPR PWM_HPMR PWM_HPPL PWM_HPML PWM_P_6 PWM_M_6 PWM_P_5 PWM_M_5 DVDD_PWM DVSS_PWM PWM_P_8 PWM_M_8 PWM_P_7 PWM_M_7 P0010-01 2.1.2 Ordering Information TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com T A PLASTIC 64-PIN PQFP (P/N) C to C TAS5508BPAG

2.1.3 Terminal Descriptions TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 TERMINAL 5-V TYPE (1) TERMINATION (2) NO. AVDD_PLL P 3.3-V analog power supply for PLL. This terminal can be connected to the same power source used to drive power terminal DVDD; but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PLL with a 0.1- µ F low-ESR capacitor. AVSS P Analog ground AVSS_PLL P Analog ground for PLL. This terminal should reference the same ground as terminal DVSS; but to achieve low PLL jitter, ground noise at this terminal must be minimized. The availability of the AVSS terminal allows a designer to use optimizing techniques such as star ground connections, separate ground planes, or other quiet ground-distribution techniques to achieve a quiet ground reference at this terminal. BKND_ERR DI Pullup Active-low. A back-end error sequence is generated by applying logic low to this terminal. The BKND_ERR results in no change to any system parameters, with all H-bridge drive signals going to a hard-mute state (M-state). DVDD 15, P 3.3-V digital power supply. It is recommended that decoupling capacitors of 0.1 µ F and µ F be mounted close to this pin (see application schematics). DVDD_PWM P 3.3-V digital power supply for PWM DVSS 16, 34, P Digital ground 35, DVSS_PWM P Digital ground for PWM HP_SEL DI V Pullup Headphone in/out selector. When a logic low is applied, the headphone is selected (speakers are off). When a logic high is applied, speakers are selected (headphone is off). LRCLK DI V Serial-audio data left/right clock (sampling-rate clock) MCLK DI V Pulldown MCLK is a 3.3-V master clock input. The input frequency of this clock can range from MHz to MHz. MUTE DI V Pullup Soft mute of outputs, active-low (muted signal a logic low, normal operation a logic high). The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. OSC_CAP AO Oscillator capacitor PDN DI V Pullup Power down, active-low. PDN powers down all logic and stops all clocks whenever a logic low is applied. The internal parameters are preserved through a power-down cycle, as long as RESET is not active. The duration for system recovery from power down is 100 ms. PLL_FLT_RET AO PLL external filter return PLL_FLTM AO PLL negative input. Connected to PLL_FLT_RET via an RC network PLL_FLTP AI PLL positive input. Connected to PLL_FLT_RET via an RC network PSVC O Power-supply volume control PWM output PWM_HPML DO PWM left-channel headphone (differential PWM_HPMR DO PWM right-channel headphone (differential PWM_HPPL DO PWM left-channel headphone (differential PWM_HPPR DO PWM right-channel headphone (differential PWM_M_1 DO PWM output (differential PWM_M_2 DO PWM output (differential PWM_M_3 DO PWM output (differential PWM_M_4 DO PWM output (differential PWM_M_5 DO PWM output (lineout (differential PWM_M_6 DO PWM output (lineout (differential PWM_M_7 DO PWM output (differential PWM_M_8 DO PWM output (differential PWM_P_1 DO PWM output (differential PWM_P_2 DO PWM output (differential PWM_P_3 DO PWM output (differential (1) Type: A analog; D 3.3-V digital; P power/ground/decoupling; I input; O output (2) All pullups are 20- µ A weak pullups and all pulldowns are 20- µ A weak pulldowns. The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups logic-1 input; pulldowns logic-0 input). Devices that drive inputs with pullups must be able to sink µ A while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source µ A while maintaining a logic-1 drive level. Submit Documentation Feedback

www.ti.com TERMINAL 5-V TYPE (1) TERMINATION (2) NO. PWM_P_4 DO PWM output (differential PWM_P_5 DO PWM output (lineout (differential PWM_P_6 DO PWM output (lineout (differential PWM_P_7 DO PWM output (differential PWM_P_8 DO PWM output (differential RESERVED 21, 22, Connect to digital ground 23, RESET DI V Pullup System reset input, active-low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5508B to its default conditions, sets the valid output low, and places the PWM in the hard-mute state (M-state). Master volume is immediately set to full attenuation. On the release of RESET if PDN is high, the system performs a to 5-ms device initialization and sets the volume at mute. SCL DI V I C serial-control clock input/output SCLK DI V Serial-audio data clock (shift clock) input SDA DIO V I C serial-control data-interface input/output SDIN1 DI V Pulldown Serial-audio data input is one of the serial-data input ports. SDIN1 supports four discrete (stereo) data formats and is capable of inputting data at f S SDIN2 DI V Pulldown Serial-audio data input is one of the serial-data input ports. SDIN2 supports four discrete (stereo) data formats and is capable of inputting data at f S SDIN3 DI V Pulldown Serial-audio data input is one of the serial-data input ports. SDIN3 supports four discrete (stereo) data formats and is capable of inputting data at f S SDIN4 DI V Pulldown Serial-audio data input is one of the serial-data input ports. SDIN4 supports four discrete (stereo) data formats and is capable of inputting data at f S VALID DO Output indicating validity of PWM outputs, active-high VBGAP P Band-gap voltage reference. A pinout of the internally regulated 1.2-V reference. Typically has a 1-nF low-ESR capacitor between VBGAP and AVSS_PLL. This terminal must not be used to power external devices. VR_DIG P Voltage reference for 1.8-V digital core supply. A pinout of the internally regulated 1.8-V power used by digital core logic. A 4.7- µ F low-ESR capacitor (3) should be connected between this terminal and DVSS. This terminal must not be used to power external devices. VR_DPLL P Voltage reference for 1.8-V digital PLL supply. A pinout of the internally regulated 1.8-V power used by digital PLL logic. A 0.1- µ F low-ESR capacitor (3) should be connected between this terminal and DVSS_CORE. This terminal must not be used to power external devices. VR_PWM P Voltage reference for 1.8-V digital PWM core supply. A pinout of the internally regulated 1.8-V power used by digital PWM core logic. A 0.1- µ F low-ESR capacitor (3) should be connected between this terminal and DVSS_PWM. This terminal must not be used to power external devices. VRA_PLL P Voltage reference for 1.8-V PLL analog supply. A pinout of the internally regulated 1.8-V power used by PLL logic. A 0.1- µ F low-ESR capacitor (3) should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices. VRD_PLL P Voltage reference for 1.8-V PLL digital supply. A pinout of the internally regulated 1.8-V power used by PLL logic. A 0.1- µ F low-ESR capacitor (3) should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices. XTL_IN AI XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5508B via use of an external fundamental-mode crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. A 13.5-MHz crystal (HCM49) is recommended. XTL_OUT AO XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5508B via use of an external fundamental-mode crystal. XTL_OUT is the 1.8-V output drive to the crystal. A 13.5-MHz crystal (HCM49) is recommended. (3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing parallel resonance circuits that have been observed when paralleling capacitors of different values.

2.2 TAS5508B Functional 2.2.1 Power Supply 2.2.2 Clock, PLL, and Serial Data Interface 2.2.2.1 Serial Audio Interface TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Figure 1-1 shows the TAS5508B functional structure. The following sections describe the TAS5508B functional blocks: Power supply Clock, PLL, and serial data interface I C serial-control interface Device control Digital audio processor (DAP) The power-supply section contains supply regulators that provide analog and digital regulated power for various sections of the TAS5508B. The analog supply supports the analog PLL, whereas digital supplies support the digital PLL, the digital audio processor (DAP), the pulse-width modulator (PWM), and the output control. The TAS5508B is a clocked slave-only device that requires the use of an external 13.5-MHz crystal. It accepts MCLK, SCLK, and LRCLK as inputs only. The TAS5508B uses the external crystal to provide a time base for: Continuous data and clock error detection and management Automatic data-rate detection and configuration Automatic MCLK-rate detection and configuration (automatic bank switching) Supporting I C operation/communication while MCLK is absent The TAS5508B automatically handles clock errors, data-rate changes, and master-clock frequency changes without requiring intervention from an external system controller. This feature significantly reduces system complexity and design. The TAS5508B operates as a slave-only/receive-only serial data interface in all modes. The TAS5508B has four PCM serial data interfaces to permit eight channels of digital data to be received through the SDIN1, SDIN2, SDIN3, and SDIN4 inputs. The serial audio data is in MSB-first, 2s-complement format. The serial data input interface of the TAS5508B can be configured in right-justified, I or left-justified modes. The serial data interface format is specified using the I C data-interface control register. The supported formats and word lengths are shown in Table 2-1 Submit Documentation Feedback

2.2.3 I C Serial-Control Interface 2.2.4 Device Control 2.2.5 Digital Audio Processor (DAP) 2.2.5.1 TAS5508B Audio-Processing Configurations TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Table 2-1. Serial Data Formats RECEIVE SERIAL DATA FORMAT WORD LENGTH Right-justified Right-justified Right-justified I S I S I S Left-justified Left-justified Left-justified Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508B accepts 16-, 20-, or 24-bit serial data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I or right-justified format. Data is input using a 64-f S SCLK clock and an MCLK rate of 128, 192, 256, 384, 512, or 768 f S up to a maximum of MHz. The clock speed and serial data format are I C configurable. The TAS5508B has an I C serial-control slave interface (write address 0x36 and read address 0x37) to receive commands from a system controller. The serial-control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait states. Because the TAS5508B has a crystal time base, this interface operates even when MCLK is absent. The serial control interface supports both single-byte and multiple-byte read/write operations for status registers and the general control registers associated with the PWM. However, for the DAP data-processing registers, the serial control interface also supports multiple-byte (4-byte) write operations. The I C supports a special mode which permits I C write operations to be broken up into multiple data-write operations that are multiples of data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc., write operations that are composed of a device address, read/write bit, subaddress, and any multiple of bytes of data. This permits the system to incrementally write large register values without blocking other I C transactions. In order to use this feature, the first block of data is written to the target I C address, and each subsequent block of data is written to a special append register (0xFE) until all the data is written and a stop bit is sent. An incremental read operation is not supported. The TAS5508B control section provides the control and sequencing for the TAS5508B. The device control provides both high- and low-level control for the serial control interface, clock and serial data interfaces, digital audio processor, and pulse-width modulator sections. The DAP arithmetic unit is used to implement all audio-processing functions: soft volume, loudness compensation, bass and treble processing, dynamic range control, channel filtering, and input and output mixing. Figure 2-1 shows the TAS5508B DAP architecture. The DAP accepts 24-bit data from the serial data interface and outputs 32-bit data to the PWM section. The DAP supports two configurations, one for 32-kHz to 96-kHz data and one for 176.4-kHz to 192-kHz data. The 32-kHz to 96-kHz configuration supports eight channels of data processing that can be configured either as eight channels, or as six channels with two channels for separate stereo line outputs. The 176.4-kHz to 192-kHz configuration supports three channels of signal processing with five channels passed through (or derived from the three processed channels).

2.2.5.2 TAS5508B Audio Signal-Processing Functions TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the 2-channel 176.4-kHz and 192-kHz data, the TAS5508B has separate audio-processing 176.4 kHz and 192 kHz. See Table 2-2 for a summary of TAS5508B processing feature sets. The DAP provides primary signal-processing functions: The data-processing input has a full input crossbar mixer. This enables each input to be any mix of the eight input channels. Two I C programmable threshold detectors in each channel support automute. Seven biquads per channel Four soft bass and treble tone controls with 18-dB range, programmable corner frequencies, and second-order slopes. In 8-channel mode, bass and treble controls are normally configured as follows: Bass and treble Channel (left), channel (right), and channel (center) Bass and treble Channel (left surround) and channel (right surround) Bass and treble Channel (left back surround) and channel (right back surround) Bass and treble Channel (subwoofer) Individual channel and master volume controls. Each control provides an adjustment range of dB to 109 dB plus mute. This permits a total volume device control range of dB to 109 dB plus mute. The master volume control can be configured to control six or eight channels. The DAP soft volume and mute update interval is I C programmable. The update is performed at a fixed rate regardless of the sample rate. Programmable loudness compensation that is controlled via the combination of the master and individual volume settings. Two dual-threshold, dual-rate, dynamic range compressors (DRCs). The volume gain values provided are used as input parameters using the maximum RMS (master volume individual channel volume). output mixer (channels 6). Each output is a mix of any two signal-processed channels. It is recommended to use the pass-through output mixer configuration. output mixer (channels and 8). Each output is a mix of any three signal-processed channels. It is recommended to use the pass-through output mixer configuration. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample-rate-dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These can be set to be automatically selected for one or more data sample rates or can be manually selected under I C program control. This feature enables coefficients for different sample rates to be stored in the TAS5508B and then selected when needed. Submit Documentation Feedback

2.3 TAS5508B DAP Architecture 2.3.1 TAS5508B DAP Architecture Diagrams TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Table 2-2. TAS5508B Audio-Processing Feature Sets kHz kHz kHz kHz 176.4- and 192-kHz FEATURE 8-CHANNEL FEATURE SET LINEOUT FEATURE SET FEATURE SET Signal-processing channels Pass-through channels N/A Master volume for channels for channels for channels Individual channel volume controls Four bass and treble tone controls Four bass and treble tone controls Two bass and treble tone with 18-dB range, programmable with 18-dB range, programmable controls with 18-dB range, corner frequencies, and second- corner frequencies, and second- programmable corner Bass and treble tone order slopes order slopes frequencies, and second-order controls and C (Ch1, and and C (Ch1, and slopes LS, RS (Ch3 and LS, RS (Ch3 and L and R (Ch1 and LBS, RBS (Ch5 and Sub (Ch8) Sub (Ch8) Sub (Ch8) Line L and R (Ch5 and Biquads Dynamic range DRC1 for seven satellites and DRC1 for five satellites and DRC2 DRC1 for two satellites and compressors DRC2 for sub for sub (Ch5 and uncompressed) DRC2 for sub Each of the three signal- processing channels or the five pass-though channel inputs can Each of the eight signal-processing channel inputs can be any mix of the be any mix of the eight input Input/output mapping/ eight input channels. channels. mixing Each of the eight outputs can be any mix of any two processed channels. Each of the eight outputs can be any mix of any of the three processed channels or five bypass channels. DC-blocking filters (implemented in PWM Eight channels section) Digital de-emphasis Eight channels for kHz, Six channels for kHz, 44.1 kHz, (implemented in PWM N/A 44.1 kHz, and kHz and kHz section) Loudness Eight channels Six channels Three channels Number of coefficient sets Three additional coefficient sets can be stored in memory. stored Figure 2-1 shows the TAS5508B DAP architecture for f S kHz. Note the TAS5508B bass management architecture shown in channels and Note that the I C registers are shown to help the designer configure the TAS5508B. Figure 2-2 shows the TAS5508B architecture for f S 176.4 kHz or f S 192 kHz. Note that only channels and contain all the features. Channels are pass-through except for volume controls. Figure 2-3 shows TAS5508B detailed channel processing. The output mixer is for channels and for channels and

Coeff = 0 (lin), (I2C 0x4C) Coeff = 1 (lin) (I2C 0x4D)

7 DAP 1

(0x51− 0x57) SDIN1-L (L) (1) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 1 2C 0x41) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 1 Volume (0xD1) Max Vol Bass and Treble 1 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 1 (I2C 0xAA) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer L to PWM1 DRC1 (0x96− 0x9C)7 DAP 2 BQ (0x58− 0x5E) SDIN1-L (L) SDIN1-R (R) (1) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 2 2C 0x42) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 2 Volume (0xD2) Max Vol Bass and Treble 1 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 2 (I2C 0xAB) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer R to PWM2 DRC1 (0x96− 0x9C)7 DAP 3 BQ (0x5F− 0x65) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) (1) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 3 2C 0x43) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 3 Volume (0xD3) Max Vol Bass and Treble 2 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 3 (I2C 0xAC) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer LS to PWM3 DRC1 (0x96− 0x9C)7 DAP 4 BQ (0x66− 0x6C) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) (1) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 4 2C 0x44) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 4 Volume (0xD4) Max Vol Bass and Treble 2 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 4 (I2C 0xAD) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer RS to PWM4 DRC1 (0x96− 0x9C)7 DAP 5 BQ (0x6D− 0x73) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) (1) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 5 2C 0x45) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 5 Volume (0xD5) Max Vol Bass and Treble 3 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 5 (I2C 0xAE) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer LBS to PWM5 DRC1 (0x96− 0x9C)7 DAP 6 BQ (0x74− 0x7A) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) (1) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 6 2C 0x46) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 6 Volume (0xD6) Max Vol Bass and Treble 3 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 6 (I2C 0xAF) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer RBS to PWM6 DRC1 (0x96− 0x9C)5 DAP 7 BQ (0x7D− 0x81) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) (1) SDIN4-R (LFE) A B C D E F G H IP Mixer 7 2C 0x47) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 7 Volume (0xD7) Max Vol Bass and Treble 1 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 7 (I2C 0xB0) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr3 Output Mixer C to PWM7 DRC1 (0x96− 0x9C)

5 DAP 8

(0x84− 0x88) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) (1) A B C D E F G H IP Mixer 8 2C 0x48) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 8 Volume (0xD8) Max Vol Bass and Treble 4 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 8 (I2C 0xB1) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr3 Output Mixer Sub to PWM8 DRC2 (0x9D− 0xA1)

2 DAP 8

(0x82− 0x83) B0014-01Coeff = 0 (lin), (I2C 0x4F) Coeff = 1 (lin) (I2C 0x50) Coeff = 0 (lin), (I2C 0x49) Coeff = 0 (lin) 2C 0x4A)

2 DAP 7

(0x7B− 0x7C) Coeff = 0 (lin), (I2C 0x4B) Coeff = 0 (lin), (I2C 0x4E) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 (1) Default inputs Figure 2-1. TAS5508B DAP Architecture With I C Registers S kHz) Submit Documentation Feedback

(0x51− 0x57) SDIN1-L (L) (1) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 1 2C 0x41) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 1 Volume (0xD1) Max Vol Bass and Treble 1 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 1 (I2C 0xAA) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer L to PWM1 DRC1 (0x96− 0x9C)7 DAP 2 BQ (0x58− 0x5E) SDIN1-L (L) SDIN1-R (R) (1) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 2 2C 0x42) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 2 Volume (0xD2) Max Vol Bass and Treble 1 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 2 (I2C 0xAB) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer R to PWM2 DRC1 (0x96− 0x9C) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) (1) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 3 2C 0x43) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) OP Mixer 3 (I2C 0xAC) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer LS to PWM3 SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) (1) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 4 2C 0x44) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) OP Mixer 4 (I2C 0xAD) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer RS to PWM4 SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) (1) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 5 2C 0x45) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) OP Mixer 5 (I2C 0xAE) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer LBS to PWM5 SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) (1) SDIN4-L (C) SDIN4-R (LFE) A B C D E F G H IP Mixer 6 2C 0x46) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) OP Mixer 6 (I2C 0xAF) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 Output Mixer RBS to PWM6 SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) (1) SDIN4-R (LFE) A B C D E F G H IP Mixer 7 2C 0x47) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) OP Mixer 7 (I2C 0xB0) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr3 Output Mixer C to PWM75 DAP 8 BQ (0x84− 0x88) SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) (1) A B C D E F G H IP Mixer 8 2C 0x48) 8 × 8 Crossbar Input Mixer Master Vol (0xD9) DAP 8 Volume (0xD8) Max Vol Bass and Treble 4 (0xDA− 0xDD) Loud- ness (0x91− 0x95) OP Mixer 8 (I2C 0xB1) 8 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr3 Output Mixer Sub to PWM8 DRC2 (0x9D− 0xA1) (0x82− 0x83) B0015-01 DAP 3 Volume (0xD3) DAP 4 Volume (0xD4) DAP 5 Volume (0xD5) DAP 6 Volume (0xD6) DAP 7 Volume (0xD7) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com (1) Default inputs Figure 2-2. TAS5508B Architecture With I C Registers S 176.4 kHz or f S 192 kHz)

1 Other

A_to_ipmix B_to_ipmix ASDIN1 B C_to_ipmix D_to_ipmix SDIN2 Left Right Channel Volume Bass and Treble Bypass Bass and Treble Inline Pre- Volume Post- Volume Output Gain Output Mixer Sums Any Two Channels PWM Output C D Left Right DRC Bypass DRC Inline E_to_ipmix F_to_ipmix ESDIN3 F G_to_ipmix H_to_ipmix SDIN4 Left Right G H Left Right B0016-01 Master Volume Max Volume 2.3.2 I C Coefficient Number Formats 2.3.2.1 28-Bit 5.23 Number Format TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Figure 2-3. TAS5508B Detailed Channel Processing The architecture of the TAS5508B is contained in ROM resources within the TAS5508B and cannot be altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I C bus interface, provide a user with the flexibility to set the TAS5508B to a configuration that achieves system-level goals. The firmware is executed in a 48-bit, signed, fixed-point arithmetic machine. The most significant bit of the 48-bit data path is a sign bit, and the lower bits are data bits. Mixer gain operations are implemented by multiplying a 48-bit, signed data value by a 28-bit, signed gain coefficient. The 76-bit, signed output product is then truncated to a signed, 48-bit number. Level offset operations are implemented by adding a 48-bit, signed offset coefficient to a 48-bit, signed data value. In most cases, if the addition results in overflowing the 48-bit, signed number format, saturation logic is used. This means that if the summation results in a positive number that is greater than 0x7FFF FFFF FFFF (the spaces are used to ease the reading of the hexadecimal number), the number is set to 0x7FFF FFFF FFFF. If the summation results in a negative number that is less than 0x8000 0000 0000, the number is set to 0x8000 0000 0000. All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23 numbers have bits to the left of the binary point and bits to the right of the binary point. This is shown in Figure 2-4 Submit Documentation Feedback

2−23 Bit S_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx 2−4 Bit 2−1 Bit

20 Bit

23 Bit

(1 or 0) /C0121 23 + (1 or 0) /C0121 22 + … + (1 or 0) /C0121 20 + (1 or 0) /C0121 2−1 + … + (1 or 0) /C0121 2−4 + … + (1 or 0) /C0121 2−23

23 Bit 22 Bit 20 Bit 2−1 Bit 2−4 Bit 2−23 Bit

u Coefficient Digit 8 u u u S x x x Coefficient Digit 7 x. x x x Coefficient Digit 6 x x x x Coefficient Digit 5 x x x x Coefficient Digit 4 x x x x Coefficient Digit 3 x x x x Coefficient Digit 2 x x x x Coefficient Digit 1 Fraction Digit 5 Sign Bit Fraction Digit 6 Fraction Digit 4 Fraction Digit 3 Fraction Digit 2 Fraction Digit 1 Integer Digit 1 u = unused or don't care bits Digit = hexadecimal digit M0009-01 TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Figure 2-4. 5.23 Format The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 2-5 If the most significant bit is logic the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic then the number is a negative number. In this case, every bit must be inverted, a added to the result, and then the weighting shown in Figure 2-5 applied to obtain the magnitude of the negative number. Figure 2-5. Conversion Weighting Factors 5.23 Format to Floating Point Gain coefficients, entered via the I C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 2-6 Figure 2-6. Alignment of 5.23 Coefficient in 32-Bit I C Word As Figure 2-6 shows, the hexadecimal (hex) value of the integer part of the gain coefficient cannot be

2.3.2.2 48-Bit 25.23 Number Format 2−23 Bit S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx

216 Bit

222 Bit

223 Bit

2−1 Bit 2−10 Bit M0007-02 (1 or 0) /C0121 223 + (1 or 0) /C0121 222 + … + (1 or 0) /C0121 20 + (1 or 0) /C0121 2−1 + … + (1 or 0) /C0121 2−23

223 Bit 222 Bit 20 Bit 2−1 Bit 2−23 Bit

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I C coefficient. The reason is that the 28-bit coefficient contains bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower three bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the zero-valued most significant hex digit). All level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format. Numbers formatted as 25.23 numbers have bits to the left of the decimal point and bits to the right of the decimal point. This is shown in Figure 2-7 Figure 2-7. 25.23 Format Figure 2-8 shows the derivation of the decimal value of a 48-bit 25.23 format number. Figure 2-8. Conversion Weighting Factors 25.23 Format to Floating Point Two 32-bit words must be sent over the I C bus to download a level or threshold coefficient into the TAS5508B. The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I C word is shown in Figure 2-9 Submit Documentation Feedback

u Coefficient Digit 16 u u u u u u u Coefficient Digit 15 u u u u Coefficient Digit 14 u u u u Coefficient Digit 13 S x x x Coefficient Digit 12 x x x x Coefficient Digit 11 x x x x Coefficient Digit 10 x x x x Coefficient Digit 9 W ord 1 (Most- Significant Word) Integer Digit 3 Integer Digit 4 (Bits 211 − 29) Integer Digit 2 Integer Digit 1 Sign Bit x Coefficient Digit 8 x x x x x x x Coefficient Digit 7 x. x x x Coefficient Digit 6 x x x x Coefficient Digit 5 x x x x Coefficient Digit 4 x x x x Coefficient Digit 3 x x x x Coefficient Digit 2 x x x x Coefficient Digit 1 W ord 2 (Least- Significant Word) Fraction Digit 5 Integer Digit 4 (Bit 28) Fraction Digit 6 Fraction Digit 4 Fraction Digit 3 Fraction Digit 2 Fraction Digit 1 Integer Digit 6 Integer Digit 5 u = unused or don’t care bits Digit = hexadecimal digit M0009-02 2.3.2.3 TAS5508B Audio Processing TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Figure 2-9. Alignment of 25.23 Coefficient in Two 32-Bit I C Words The TAS5508B digital audio processing is designed so that noise produced by filter operations is maintained below the smallest signal amplitude of interest, as shown in Figure 2-10 The TAS5508B achieves this low noise level by increasing the precision of the signal representation substantially above the number of bits that are absolutely necessary to represent the input signal. Similarly, the TAS5508B carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. The TAS5508B advanced digital audio processor achieves both of these important performance capabilities by using a high-performance digital audio-processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit accumulator.

Ideal Input Possible Outputs Desired Output Filter Operation Signal Bits Input Overflow Reduced SNR Signal Output Noise Floor as a Result of Additional Precision Signal Bits Output Values Retained by Overflow Bits M0010-01 2.4 Input Crossbar Mixer Gain Coefficient SDIN1-L 48Gain Coefficient SUM /C0119 /C0119 /C0119 Gain Coefficient M0011-01 SDIN1-R SDIN4-R 2.5 Biquad Filters TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Figure 2-10. TAS5508B Digital Audio Processing The TAS5508B has a full input crossbar mixer. This mixer permits each signal-processing channel input to be any mix of any of the eight input channels, as shown in Figure 2-11 The control parameters for the input crossbar mixer are programmable via the I C interface. See the Input Mixer Registers, Channels (0x41 0x48) Section 7.13 for more information. Figure 2-11. Input Crossbar Mixer For 32-kHz to 96-kHz data, the TAS5508B provides biquads across the eight channels (seven per channel). For 176.4-kHz and 192-kHz data, the TAS5508B has biquads across the three channels (seven per channel). All of the biquad filters are second-order direct form I structure. Submit Documentation Feedback

/c83 48 76 76 48 76 48 M0012-01 z z Magnitude Truncation z z 2.6 Bass and Treble Controls TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format number) and a signed 28-bit coefficient (5.23 format number), as shown in Figure 2-12 The 76-bit ALU in the TAS5508B allows the 76-bit resolution to be retained when summing the mixer outputs (filter products). The five 28-bit coefficients for the each of the biquads are programmable via the I C interface. See Table 2-3 Figure 2-12. Biquad Filter Structure All five coefficients for one biquad filter structure are written to one I C register containing bytes (or five 32-bit words). The structure is the same for all biquads in the TAS5508B. Registers 0x51 0x88 show all the biquads in the TAS5508B. Note that u[31:28] bits are unused and default to 0x0. Table 2-3. (Default All-Pass) INITIALIZATION GAIN COEFFICIENT VALUE b coefficient u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] 1.0 0x00, 0x80, 0x00, 0x00 b coefficient u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 b coefficient u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a coefficient u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a coefficient u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0] 0.0 0x00, 0x00, 0x00, 0x00 From 32-kHz to 96-kHz data, the TAS5508B has four bass and treble tone controls. Each control has a 18-dB control range with selectable corner frequencies and second-order slopes. These controls operate four channel groups: and C (channels and LS, RS (channels and LBS, RBS (alternatively called L and R lineout) (channels and Sub (channel For 176.4-kHz and 192-kHz data, the TAS5508B has two bass and treble tone controls. Each control has a 18-dB I C control range with selectable corner frequencies and second-order slopes. These controls operate two channel groups:

2.7 Volume, Automute, and Mute TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 L and R Sub The bass and treble filters use a soft update rate that does not produce artifacts during adjustment. Table 2-4. Bass and Treble Filter Selections 3-dB CORNER FREQUENCIES, Hz f S FILTER SET FILTER SET FILTER SET FILTER SET FILTER SET (kHz) BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE 917 1833 125 3000 146 3667 167 4333 1088 2177 148 3562 173 4354 198 5146 44.1 1263 115 2527 172 4134 201 5053 230 5972 1375 125 2750 188 4500 219 5500 250 6500 88.2 115 2527 230 5053 345 8269 402 10106 459 11944 125 2750 250 5500 375 9000 438 11000 500 13000 176.4 230 5053 459 10106 689 16538 804 20213 919 23888 192 250 5500 500 11000 750 18000 875 22000 1000 26000 The I C registers that control bass and treble are: Bass and treble bypass register (0x89 0x90, channels Bass and treble slew rates (0xD0) Bass filter sets (0xDA) Bass filter index (0xDB) Treble filter sets (0xDC) Treble filter index (0xDD) Note that the bass and treble bypass registers (0x89 0x90) are defaulted to the bypass mode. In order to use the bass and treble, these registers must be in the inline (or enabled) mode for each channel using bass and treble. The TAS5508B provides individual channel and master volume controls. Each control provides an adjustment range of dB to 109 dB in 0.25-dB increments. This permits a total volume device control range of dB to 109 dB plus mute. The master volume control can be configured to control six or eight channels. The TAS5508B has a master soft mute control that can be enabled by a terminal or I C command. The device also has individual channel soft mute controls that are enabled via I The soft volume and mute update rates are programmable. The soft adjustments are performed using a soft-gain linear update with an I C-programmable linear step size at a fixed temporal rate. The linear soft-gain step size can be varied from 0.5 to 0.003906. Table 2-5 lists the linear gain step sizes. Table 2-5. Linear Gain Step Size STEP SIZE (GAIN) 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 0.003906 Time to go from db to 109 dB in ms 10.67 21.33 42.67 85.34 170.67 340.35 682.70 1365.4 Time to go from db to 109 dB in ms 1.33 2.67 5.33 10.67 21.33 42.67 85.33 170.67 Time to go from db to 109 dB in ms 0.17 0.33 0.67 1.33 2.67 5.33 10.67 21.33 Submit Documentation Feedback

2.8 Automute and Mute Channel Controls 24-Bit Input

32 Bits in DSPE

Representation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Threshold Range CD Data Range DVD Data Range M0013-01 2.9 Loudness Compensation TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com The TAS5508B has individual channel automute controls that are enabled via I C register 0x04 bits and (the default setting is enabled Two separate detectors can trigger the automute: Input automute C register 0x14): All channels are muted when all inputs to the TAS5508B are less in magnitude than the input threshold value for a programmable amount of time. Output automute C register 0x15): A single channel is muted when the output of the DAP section is less in magnitude than the input threshold value for a programmable amount of time. The detection period and thresholds for these two detectors are the same. This time interval is selectable via I C to be from ms to 110 ms. The increments of time are 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The default value is mask programmable. The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is adjustable via I The range of the input threshold adjustment is from below the LSB (bit position to below bit position in a 24-bit input-data word. This range provides an input threshold that can be adjusted for to bits of data. The default value is mask programmable. Figure 2-13. Automute Threshold The automute state is exited when the TAS5508B receives one sample that is greater than the output threshold. The output threshold can be one of two values: Equal to the input threshold dB (one bit position) greater than the input threshold The value for the output threshold is selectable via I The default value is mask programmable. The system latency enables the data value that is above the threshold to be preserved and output. A mute command initiated by automute, master mute, individual I C mute, the AM interference mute sequence, or the bank-switch mute sequence overrides an unmute command or a volume command. While a mute command is activated, the commanded channels transition to the mute state. When a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel. The loudness compensation function compensates for the Fletcher-Munson loudness curves. The

H(z) Audio OutAudio In V VLoudness Function = f(V) 2.9.1 Loudness Example TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 TAS5508B loudness implementation tracks the volume control setting to provide spectral compensation for weak low- or high-frequency response at low volume levels. For the volume tracking function, both linear and logarithmic control laws can be implemented. Any biquad filter response can be used to provide the desired loudness curve. The control parameters for the loudness control are programmable via the I C interface. The TAS5508B has a single set of loudness controls for the eight channels. In 6-channel mode, loudness is available to the six speaker outputs and also to the line outputs. The loudness control input uses the maximum individual master volume (V) to control the loudness that is applied to all channels. In the 192-kHz and 176.4-kHz modes, the loudness function is active only for channels and Figure 2-14. Loudness Compensation Functional Block Diagram Loudness function f(V) G (Log LG LO O or alternatively, Loudness function f(V) G LG LO O For example, for the default values LG 0.5, LO G and O then: Loudness function 1/SQRT(V), which is the recommended transfer function for loudness. So, Audio out (audio in) V H(Z) SQRT(V). Other transfer functions are possible. Table 2-6. Default Loudness Compensation Parameters LOUDNESS I C DEFAULT TERM FORMAT SUB- HEX FLOAT ADDRESS V Max volume Gains audio 5.23 NA NA NA Log V Log (max volume) Loudness function 5.23 NA 0000 0000 0.0 H(Z) Loudness biquad Controls shape of 5.23 0x95 b 0000 D513 b 0.006503 loudness curves b 0000 0000 b b 0FFF 2AED b 0.006503 a 00FE 5045 a 1.986825 a 0F81 AA27 a 0.986995 LG Gain (log space) Loudness function 5.23 0x91 FFC0 0000 0.5 LO Offset (log space) Loudness function 25.23 0x92 0000 0000 G Gain Switch to enable 5.23 0x93 0000 0000 loudness (ON OFF O Offset Provides offset 25.23 0x94 0000 0000 Problem: Due to the Fletcher-Munson phenomena, compensation for low-frequency attenuation near Hz is desirable. The TAS5508B provides a loudness transfer function with EQ gain EQ center frequency Hz, and EQ bandwidth Hz. Submit Documentation Feedback

f − Frequency − Hz Gain − dB 10 20k100 1k G001 −10 −20 −40 −30 10k 2.10 Dynamic Range Control (DRC) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Solution: Using Texas Instruments ALE TAS5508B DSP tool, Matlab or other signal-processing tool, develop a loudness function with the parameters listed in Table 2-7 Table 2-7. Example Loudness Function Parameters LOUDNESS I C EXAMPLE TERM FORMAT SUB- HEX FLOAT ADDRESS H(Z) Loudness biquad Controls shape of 5.23 0x95 b 0000 8ACE b 0.004236 loudness curves b 0000 0000 b b FFFF 7532 b 0.004236 a FF01 1951 a 1.991415 a 007E E914 a 0.991488 LG Loudness gain Loudness function 5.23 0x91 FFC0 0000 0.5 LO Loudness offset Loudness function 25.23 0x92 0000 0000 G Gain Switch to enable 5.23 0x93 0080 0000 loudness (ON OFF O Offset Offset 25.23 0x94 0000 0000 See Figure 2-15 for the resulting loudness function at different gains. Figure 2-15. Loudness Example Plots DRC provides both compression and expansion capabilities over three separate and definable regions of audio signal levels. Programmable threshold levels set the boundaries of the three regions. Within each of the three regions, a distinct compression or expansion transfer function can be established and the slope of each transfer function is determined by programmable parameters. The offset (boost or cut) at the two boundaries defining the three regions can also be set by programmable offset coefficients. The DRC implements the composite transfer function by computing a 5.23-format gain coefficient from each sample output from the rms estimator. This gain coefficient is then applied to a mixer element, whose other input is the audio data stream. The mixer output is the DRC-adjusted audio data. The TAS5508B has two distinct DRC blocks. DRC1 services channels in the 8-channel mode and channels and in the 6-channel mode. This DRC computes rms estimates of the audio data streams on all channels that it controls. The estimates are then compared on a sample-by-sample basis and the larger of the estimates is used to compute the compression/expansion gain coefficient. The gain coefficient is then applied to the appropriate channel audio streams. DRC2 services only channel This DRC also computes an rms estimate of the signal level on channel and this estimate is used to compute the compression/expansion gain coefficient applied to the channel-8 audio stream.

From Input Mixer To Output Mixer Loudness Channel Volume Master Volume Max Volume TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 All of the TAS5508B default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 2-8 shows the recommended time constants and their hex values. If the user wants to implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically. It then outputs the TAS5508B hex coefficients for download to the TAS5508B. Table 2-8. DRC Recommended Changes From TAS5508B Defaults I C RECOMMENDED TIME RECOMMENDED REGISTER FIELDS DEFAULT HEX SUBADDRESS CONSTANT (ms) HEX VALUE 0x98 DRC1 energy 0000 883F 0000 883F DRC1 energy) 007F 77C0 007F 77C0 0x9C DRC1 attack 0000 883F 0000 883F DRC1 attack) 007F 77C0 007F 77C0 DRC1 decay 0001 538F 0000 00AE DRC1 decay) 007E AC70 007F FF51 0x9D DRC2 energy 0000 883F 0000 883F DRC2 energy) 007F 77C0 007F 77C0 0xA1 DRC2 attack 0000 883F 0000 883F DRC2 attack) 007F 77C0 007F 77C0 DRC2 decay 0001 538F 0000 0056 DRC2 decay) 007E AC70 003F FFA8 Recommended DRC setup flow if the defaults are used: After power up, load the recommended hex value for DRC1 and DRC2 decay and decay). See Table 2-8 Enable either the pre-volume or post-volume DRC using I C registers 0x96 and 0x97. Note that to avoid a potential timing problem, there should be a 10-ms delay between a write to 0x96 and a write to 0x97. Recommended DRC setup flow if the DRC design uses values different from the defaults: After power up, load all DRC coefficients per the DRC design. Enable either the pre-volume or post-volume DRC. Note that to avoid a potential timing problem, there should be a 10-ms delay between a write to 0x96 and a write to 0x97. Figure 2-16 shows the positioning of the DRC block in the TAS5508B processing flow. As seen, the DRC input can come either before or after soft volume control and loudness processing. Figure 2-16. DRC Positioning in TAS5508B Processing Flow Submit Documentation Feedback

DRC − Compensated Output 1:1 Transfer Function Implemented Transfer Function Region Region Region M0014-01 TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Figure 2-17 illustrates a typical DRC transfer function. Figure 2-17. Dynamic Range Compression (DRC) Transfer Function Structure The three regions shown in Figure 2-17 are defined by three sets of programmable coefficients: Thresholds and define region boundaries. Offsets and define the DRC gain coefficient settings at thresholds and T2, respectively. Slopes k0, k1, and define whether compression or expansion is to be performed within a given region. The magnitudes of the slopes define the degree of compression or expansion to be performed. The three sets of parameters are all defined in logarithmic space and adhere to the following rules: The maximum input sample into the DRC is referenced at dB. All values below this maximum value then have negative values in logarithmic (dB) space. The samples input into the DRC are 32-bit words and consist of the upper bits of the 48-bit word format used by the digital audio processor (DAP). The 48-bit DAP word is derived from the 32-bit serial data received at the serial-audio receive port by adding bits of headroom above the 32-bit word and bits of computational precision below the 32-bit word. If the audio-processing steps between the SAP input and the DRC input result in no accumulative boost or cut, the DRC operates on the bits of headroom and the MSBs of the audio sample. Under these conditions, a 0-dB (maximum value) audio sample (0x7FFF FFFF) is seen at the DRC input as a 48-dB sample bits dB/bit dB). Thresholds and define, in dB, the boundaries of the three regions of the DRC, as referenced to the rms value of the data into the DRC. Zero-valued threshold settings reference the maximum-valued rms input into the DRC and negative-valued thresholds reference all other rms input levels. Positive-valued thresholds have no physical meaning and are not allowed. In addition, zero-valued threshold settings are not allowed. Although the DRC input is limited to 32-bit words, the DRC itself operates using the 48-bit word format of the DAP. The 32-bit samples input into the DRC are placed in the upper bits of this 48-bit word space. This means that the threshold settings must be programmed as 48-bit (25.23 format) numbers. CAUTION Zero-valued and positive-valued threshold settings are not allowed and cause unpredictable behavior if used. Offsets and define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain coefficient at the threshold points and T2, respectively. Positive offsets are defined as cuts, and thus boost or gain selections are negative numbers. Offsets must be programmed as 48-bit (25.23 format) numbers.

2.10.1 DRC Implementation twindow /C0043/C00421 fS /C0527n(1/C0042ae) ta /C0043/C00421 fS /C0527n(1/C0042aa) td /C0043/C00421 fS /C0527n(1/C0042ad) 2.10.2 Compression/Expansion Coefficient Computation Engine Parameters TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Slopes k0, k1, and define whether compression or expansion is to be performed within a given region, and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit (5.23 format) numbers. The three elements comprising the DRC include: (1) an rms estimator, (2) a compression/expansion coefficient computation engine, and (3) an attack/decay controller. RMS estimator This DRC element derives an estimate of the rms value of the audio data stream into the DRC. For the DRC block shared by Ch1 and Ch2, two estimates are computed an estimate of the Ch1 audio data stream into the DRC, and an estimate of the Ch2 audio data stream into the DRC. The outputs of the two estimators are then compared, sample-by-sample, and the larger-valued sample is forwarded to the compression/expansion coefficient computation engine. Two programmable parameters, ae and ae), set the effective time window over which the rms estimate is made. For the DRC block shared by Ch1 and Ch2, the programmable parameters apply to both rms estimators. The time window over which the rms estimation is computed can be determined by: Compression/expansion coefficient computation This DRC element converts the output of the rms estimator to a logarithmic number, determines the region where the input resides, and then computes and outputs the appropriate coefficient to the attack/decay element. Seven programmable parameters, T1, T2, O1, O2, k0, k1, and k2, define the three compression/expansion regions implemented by this element. Attack/decay control This DRC element controls the transition time of changes in the coefficient computed in the compression/expansion coefficient computation element. Four programmable parameters define the operation of this element. Parameters ad and ad) set the decay or release time constant to be used for volume boost (expansion). Parameters aa and aa) set the attack time constant to be used for volume cuts. The transition time constants can be determined by: Seven programmable parameters are assigned to each DRC block: two threshold parameters and T2, two offset parameters and O2, and three slope parameters k0, k1, and k2. The threshold parameters establish the three regions of the DRC transfer curve, the offsets anchor the transfer curve by establishing known gain settings at the threshold levels, and the slope parameters define whether a given region is a compression or an expansion region. The audio input stream into the DRC must pass through DRC-dedicated programmable input mixers. These mixers are provided to scale the 32-bit input into the DRC to account for the positioning of the audio data in the 48-bit DAP word and the net gain or attenuation in signal level between the SAP input and the DRC. The selection of threshold values must take the gain (attenuation) of these mixers into account. The DRC implementation examples that follow illustrate the effect these mixers have on establishing the threshold settings. establishes the boundary between the high-volume region and the mid-volume region. establishes the boundary between the mid-volume region and the low-volume region. Both thresholds are set in logarithmic space, and which region is active for any given rms estimator output sample is determined by the logarithmic value of the sample. Submit Documentation Feedback

O1 No Discontinuity/C0043|T1 /C0042T2|/C0032k1 /C0041O2 For ( |T1|/C0119|T2|) 2.10.2.1 Threshold Parameter Computation T1SUB_ADDRESS_ENTRY /C0043/C004264 /C00426.0206/C004310.63 2.10.2.2 Offset Parameter Computation O INPUT /C0043 O DESIRED /C004124.0824 dB 6.0206 O1 INPUT /C0043±21 dB/C004124.0824 dB 6.0206 /C00430.51197555 /C00430.1000_0011_0001_1101_0100 /C00430x00000041886A in 25.23 format TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Threshold serves as the fulcrum or pivot point in the DRC transfer function. defines the boost dB) or cut dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If dB, the value of the derived gain coefficient is (0x0080 0000 in 5.23 format). is the slope of the DRC transfer function for rms input levels above T2, and is the slope of the DRC transfer function for rms input levels below (and above T1). The labeling of as the fulcrum stems from the fact that there cannot be a discontinuity in the transfer function at T2. The user can, however, set the DRC parameters to realize a discontinuity in the transfer function at the boundary defined by T1. If no discontinuity is desired at T1, the value for the offset term must obey the following equation. and are the threshold settings in dB, is the slope for region and is the offset in dB at T2. If the user chooses to select a value of that does not obey the above equation, a discontinuity at is realized. Decreasing in volume from T2, the slope remains in effect until the input level is reached. If, at this input level, the offset of the transfer function curve from the transfer curve does not equal O1, there is a discontinuity at this input level as the transfer function is snapped to the offset called for by O1. If no discontinuity is wanted, and/or must be adjusted so that the value of the transfer curve at input level is offset from the transfer curve by the value O1. The examples that follow illustrate both continuous and discontinuous transfer curves at T1. Decreasing in volume from T1, starting at offset level O1, slope defines the compression/expansion activity in the lower region of the DRC transfer curve. For thresholds, T dB 6.0206T INPUT 6.0206T SUB_ADDRESS_ENTRY If, for example, it is desired to set dB, then the subaddress entry required to set to dB is: is entered as a 48-bit number in 25.23 format. Therefore: 10.63 1010.1010 0001 0100 0111 1010 111 0x0000 0550 A3D7 in 25.23 format The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An equivalent statement is that offsets represent the departure of the actual transfer function from a transfer at the threshold point. Offsets are 25.23-formatted, 48-bit logarithmic numbers. They are computed by the following equation. Gains or boosts are represented as negative numbers; cuts or attenuations are represented as positive numbers. For example, to achieve a boost of dB at threshold T1, the I C coefficient value entered for must be:

2.10.2.3 Slope Parameter Computation For n compression, the slope k can be found by: k /C00431 n /C00421 k n means k for n Likewise, for compression, k /C00431 n /C00421 means k for n Thus, it 0.5 : 1 compression/C0229k /C00431 0.5 /C00421 /C00431 1 : 2 expansion/C0229k /C00432 /C00421 /C00431 Compression equation: k/C0043 /C00424 /C00431 n /C00421 /C0229n /C0043 /C00421 /C0229 /C00420.3333 : 1 compression Expansion equation: k/C0043 /C00424 /C0043n /C00421 /C0229n /C0043 /C00423 /C02291 :/C00423 expansion 2.11 Output Mixer TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 In developing the equations used to determine the subaddress of the input value required to realize a given compression or expansion within a given region of the DRC, the following convention is adopted. DRC transfer Input increase Output increase If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the DRC, a n expansion is being performed. If the DRC realizes a 1-dB increase in output level for every n-dB increase in the rms value of the audio into the DRC, an n compression is being performed. k n In both expansion and compression 1), n is implied to be greater than Thus, for expansion: appears that k must always lie in the range k The DRC imposes no such restriction and k can be programmed to values as negative as 15.999. To determine what results when such values of k are entered, it is first helpful to note that the compression and expansion equations for k are actually the same equation. For example, a expansion is also a 0.5 compression. As can be seen, the same value for k is obtained either way. The ability to choose values of k less than allows the DRC to implement negative-slope transfer curves within a given region. Negative-slope transfer curves are usually not associated with compression and expansion operations, but the definition of these operations can be expanded to include negative-slope transfer functions. For example, if k With k the output decreases dB for every dB increase in the rms value of the audio into the DRC. As the input increases in volume, the output decreases in volume. The TAS5508B provides an output mixer for channels and For channels and the TAS5508B provides an output mixer. These mixers allow each output to be any mix of any two (or three) signal-processed channels. The control parameters for the output crossbar mixer are programmable via the I C interface. All of the TAS5508B configuration, where the audio data from each DAP channel maps directly to the corresponding PWM channel (i.e., DAP channel to PWM channel etc). When mixing or remapping DAP channels to different PWM output channels there are limitations to consider: Individual channel mute should not be used. The sum of the minimum channel volume and master volume should not be below 109 dB. Submit Documentation Feedback

N 48Gain Coefficient Output Select Output N Gain Coefficient 48Select Output N 48Gain Coefficient Output Select Output N 7 or 8 48Gain Coefficient 48Select Output N M0011-02 2.12 PWM TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Figure 2-18. Output Mixers The TAS5508B has eight channels of high-performance digital PWM modulators that are designed to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge-tied-load) configurations. The TAS5508B device uses noise-shaping and sophisticated, error-correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5508B uses an AD1 PWM modulation scheme combined with a fifth-order noise shaper to provide a 102-dB SNR from Hz to kHz. The PWM section accepts 32-bit PCM data from the DAP and outputs eight PWM audio output channels configurable as either: Six channels to drive power stages and two channels to drive a differential-input active filter to provide a separately controllable stereo lineout Eight channels to drive power stages The TAS5508B PWM section output supports both single-ended and bridge-tied loads. The PWM section provides a headphone PWM output to drive an external differential amplifier like the TPA112. The headphone circuit uses the PWM modulator for channels and The headphone does not operate while the six or eight back-end drive channels are operating. The headphone is enabled via a headphone-select terminal. The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff frequency is less than Hz. The PWM section has individual-channel de-emphasis filters for 32, 44.1, and kHz that can be enabled and disabled.

2.12.1 DC Blocking (High-Pass Filter Enable/Disable) 2.12.2 De-Emphasis Filter f – Frequency – kHz 3.18 (50 µs) −10 10.6 (15 µs) De-emphasis Response – dB M0015-01 2.12.3 Power-Supply Volume Control (PSVC) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 The PWM section also contains the power-supply volume control (PSVC) PWM. The interpolator, noise shaper, and PWM sections provide a PWM output with the following features: Up to oversampling at f S 44.1 kHz, kHz, kHz, kHz at f S 88.2 kHz, kHz at f S 176.4 kHz, 192 kHz Fifth-order noise shaping 100-dB dynamic range kHz (TAS5508B TAS5111 system measured at speaker terminals) THD 0.01% Adjustable maximum modulation limit of 93.8% to 99.2% 3.3-V digital signal Each input channel incorporates a first-order, digital, high-pass filter to block potential dc components. The filter 3-dB point is approximately 0.89-Hz at the 44.1-kHz sampling rate. The high-pass filter can be enabled and disabled via the I C system control register (0x03 bit D7). The default setting is (high-pass filter enabled). For audio sources that have been pre-emphasized, a precision 50- µ s/15- µ s de-emphasis filter is provided to support the sampling rates of kHz, 44.1 kHz, and kHz. Figure 2-19 shows a graph of the de-emphasis filtering characteristics. De-emphasis is set using two bits in the system control register. Figure 2-19. De-Emphasis Filter Characteristics The TAS5508B supports volume control both by conventional digital gain/attenuation and by a combination of digital and analog gain/attenuation. Varying the H-bridge power-supply voltage performs the analog volume control function. The benefits of using power-supply volume control (PSVC) are reduced idle channel noise, improved signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions at reduced power levels. The PSVC is enabled via I When enabled, the PSVC provides a PWM output that is filtered to provide a reference voltage for the power supply. The power-supply adjustment range can be set for 12, 18, or dB, to accommodate a range of variable power-supply designs. Figure 2-20 and Figure 2-21 show how power-supply and digital gains can be used together. The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to match the PSVC volume transfer function. Note that if the PVSC function is not used, the volume biquad should be all-pass (default). Submit Documentation Feedback

−60 −50 −40 −30 −20 −10 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 Desired Gain − dB Power-Supply and Digital Gains − dB Digital Gain Power-Supply Gain G002 G003 Desired Gain − Linear Power-Supply and Digital Gains − dB Digital Gain Power-Supply Gain 0.00001 0.1 100 0.0001 0.01 100 0.001 0.1 100.0001 0.001 0.01 2.12.4 AM Interference Avoidance TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Figure 2-20. Power-Supply and Digital Gains (Linear Space) Figure 2-21. Power-Supply and Digital Gains (Log Space) Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments' patented AM interference-avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5508B adjusts the radiated emissions to provide an emission-clear zone for the tuned AM frequency. The inputs to the TAS5508B for this operation are the tuned AM frequency, the IF frequency, and the sample rate. The sample rate is automatically detected.

The Digital Receiver or the Audio DSP Provides the Master and Bit Clocks TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Figure 2-22. Block Diagrams of Typical Systems Requiring TAS5508B Automatic AM Interference-Avoidance Circuit Submit Documentation Feedback

3.1 I C Status Registers 3.1.1 General Status Register (0x01) 3.1.2 Error Status Register (0x02) 3.2 TAS5508B Pin Controls 3.2.1 Reset RESET TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com The TAS5508B provides control and status information from both the I C registers and device pins. This section describes some of these controls and status functions. The I C summary and detailed register descriptions are contained in Section and Section The TAS5508B has two status registers that provide general device information. These are the general status register (0x01) and the error status register (0x02). Device identification code Clip indicator The TAS5508B has a clipping indicator. Writing to the register clears the indicator. No internal errors (the valid signal is high) A clock error has occurred These are sticky bits that are cleared by writing to the register. LRCLK error when the number of MCLKs per LRCLK is incorrect SCLK error when the number of SCLKS per LRCLK is incorrect Frame slip when the number of MCLKs per LRCLK changes by more than MCLK cycles PLL phase-lock error This error status register is normally used for system development only. The TAS5508B provide a number of terminal controls to manage the device operation. These controls are: RESET PDN BKND_ERR HP_SEL MUTE The TAS5508B is placed in the reset mode either by the power-up reset circuitry when power is applied, or by setting the RESET terminal low. RESET is an asynchronous control signal that restores the TAS5508B to the hard-mute state (M-state). Master volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all I C and serial data bus operations are ignored. Table 3-1 shows the device output signals while RESET is active. Table 3-1. Device Outputs During Reset SIGNAL SIGNAL STATE Valid Low PWM P-outputs Low (M-state) PWM M-outputs Low (M-state) SDA Signal input (not driven) TAS5508B Controls and Status Submit Documentation Feedback

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the hard-mute state (M-state) to the operational state is performed using a quiet start-up sequence to minimize noise. This control uses the PWM reset and unmute sequence to shut down and start up the PWM. A detailed section. If a completely quiet reset or power-down sequence is desired, MUTE should be applied before applying RESET The rising edge of the reset pulse begins device initialization before the transition to the operational mode. During device initialization, all controls are reset to their initial states. Table 3-2 shows the default control settings following a reset. Table 3-2. Values Set During Reset CONTROL SETTING Output mixer configuration 0xD0 bit (remapped output mixer configuration) High pass Enabled Unmute from clock error Hard unmute Input automute Enabled Output automute Enabled De-emphasis Disabled Serial data interface format I 24-bit Individual channel mute No channels are muted Automute delay ms Automute threshold bits Automute threshold Same as automute threshold Modulation limit 97.7% (Note: Some power stages require a lower modulation index) Six- or eight-channel configuration Eight channels Volume and mute update rate Volume ramp 88.2 ms Treble and bass slew rate Update every 1.31 ms Bank switching Manual bank selection is enabled Biquad coefficients Set to all pass Input mixer coefficients Input N Channel no attenuation Output mixer coefficients Channel N Output no attenuation Subwoofer sum into Ch1 and Ch2 Gain of Ch1 and Ch2 sum in subwoofer Gain of Bass and treble bypass/inline Bypass DRC bypass/inline Bypass DRC Default values Master volume Mute Individual channel volumes dB All bass and treble indexes 0x12 neutral Treble filter sets Filter set Bass filter sets Filter set Loudness Loudness disabled, default values AM interference mode enable Disabled AM interference mode IF 455 kHz AM interference mode select sequence AM interference mode tuned frequency and 0000, BCD input mode Submit Documentation Feedback TAS5508B Controls and Status

3.2.2 Power Down PDN 3.2.3 Back-End Error BKND_ERR TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com After the initialization time, the TAS5508B starts the transition to the operational state with the master volume set at mute. Because the TAS5508B has an external crystal time base, following the release of reset, the TAS5508B sets the MCLK and data rates and performs the initialization sequences. The PWM outputs are held at a mute state until the master volume is set to a value other than mute via I The TAS5508B can be placed into the power-down mode by holding the PDN terminal low. When the power-down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation (there is no ramp down). This control uses the PWM mute sequence that provides a low click and pop transition to the hard-mute state (M-state). Power down is an asynchronous operation that does not require MCLK to go into the power-down state. To initiate the power-up sequence requires MCLK to be operational and the TAS5508B to receive five MCLKs prior to the release of PDN As long as the PDN terminal is held low, the device is in the power-down state with the PWM outputs in a hard-mute state (M-state). During power down, all I C and serial data bus operations are ignored. Table 3-3 shows the device output signals while PDN is active. Table 3-3. Device Outputs During Power Down SIGNAL SIGNAL STATE VALID Low PWM P-outputs M-state low PWM M-outputs M-state low SDA Signal input PSVC M-state low Following the application of PDN the TAS5508B does not perform a quiet shutdown to prevent clicks and pops produced during the application (the leading edge) of this command. The application of PDN immediately performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE before PDN When PDN is released, the system goes to the end state specified by the MUTE and BKND_ERR pins and the I C register settings. The crystal time base allows the TAS5508B to determine the CLK rates. Once these rates are determined, the TAS5508B unmutes the audio. Back-end error is used to provide error management for back-end error conditions. Back-end error is a level-sensitive signal. Back-end error can be initiated by bringing the BKND_ERR terminal low for a minimum of five MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels into the PWM back-end error state. This state is described in Section 2.12 Once the back-end error sequence is initiated, a delay of ms is performed before the system starts the output re-initialization sequence. After the initialization time, the TAS5508B begins normal operation. Back-end error does not affect other PWM modulator operations. TAS5508B Controls and Status Submit Documentation Feedback

3.2.3.1 BKND_ERR and VALID 3.2.4 Speaker/Headphone Selector HP_SEL 3.2.5 Mute MUTE TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Table 3-4. Device Outputs During Back-End Error SIGNAL SIGNAL STATE Valid Low PWM P-outputs M-state low PWM M-outputs M-state low PWM_HP P-outputs M-state low PWM_HP M-outputs M-state low SDA Signal input (not driven) The number of channels that are affected by the BKND_ERR signal depends on the setting of bit of I C register 0xE0. If the I C setting is (8-channel mode), the TAS5508B places all eight PWM outputs in the PWM back-end error state. If the I C setting is the TAS5508B is in 6-channel mode. For proper operation in 6-channel mode, the lineout configuration registers (0x09 and 0x0A) must be 0x00 instead of the default of 0xE0. In this case, VALID is pulled LOW, and the TAS5508B brings PWM outputs and to a back-end error state, while not affecting lineout channels and Table 3-4 shows the device output signal states during back-end error. The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output receives the processed data output from DAP and PWM channels and In 6-channel configuration, this feature does not affect the two lineout channels. When low, the headphone output is enabled. In this mode, the speaker outputs are disabled. When high, the speaker outputs are enabled and the headphone is disabled. Changes in the pin logic level result in a state change sequence using soft mute to the hard-mute state (M-state) for both speaker and headphone followed by a soft unmute. When HP_SEL is low, the configuration of channels and is defined by the headphone configuration register. When HP_SEL is high, the channel-1 and configuration registers define the configuration of channels and If using the remapped-output mixer configuration (0xD0 bit in the 6-channel mode, the headphone operation is modified. That is, following the assertion or de-assertion of headphone, mute must be asserted and de-asserted using the MUTE pin. The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. The TAS5508B has both master and individual channel mute commands. A terminal is also provided for the master mute. The active-low master mute I C register and the MUTE terminal are logically ORed together. If either is set to low, a mute on all channels is performed. The master mute command operates on all channels regardless of whether the system is in the or 8-channel configuration. When mute is invoked, the PWM output stops switching and then goes to an idle state. The master mute terminal is used to support a variety of other operations in the TAS5508B, such as setting the the biquad coefficients, the serial interface format, and the clock rates. A mute command by the master mute terminal, individual I C mute, the AM interference mute sequence, the bank-switch mute sequence, or automute overrides an unmute command or a volume command. While a mute is active, the commanded channels are placed in a mute state. When a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel. Submit Documentation Feedback TAS5508B Controls and Status

3.3 Device Configuration Controls 3.3.1 Channel Configuration Registers TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com The TAS5508B provides a number of system configuration controls that are set at initialization and following a reset. Channel configuration Headphone configuration Audio system configurations Recovery from clock error Power-supply volume-control enable Volume and mute update rate Modulation index limit Master-clock and data-rate controls Bank controls For the TAS5508B to have full control of the power stages, registers 0x05 to 0x0C must be programmed to reflect the proper power stage and how each one should be controlled. There are eight channel configuration registers, one for each channel. For information on using BKND_ERR and VALID, see Section 3.2.3.1 The primary reason for using these registers is that different power stages require different handling during start-up, mute/unmute, shutdown, and error recovery. The TAS5508B must select the sequence that gives the best click and pop performance and ensures that the bootstrap capacitor is charged correctly during start-up. This sequence depends on which power stage is present at the TAS5508B output. Table 3-5. (0x05 to 0x0C) BIT sequence. In case the BKND_ERR pin is pulled low, this register determines if this channel is to follow the error recovery sequence or to continue with no interruption. Determines if the power stage needs the TAS5508B VALID pin to go low to reset the power stage. Some power stages can be reset by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is shared for power stages. This provides better control of each power stage. Determines if the power stage needs the TAS5508B VALID pin to go low to mute the power stage. Some power stages can be muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is shared for power stages. This provides better control of each power stage. Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin is opposite the TAS5508B PWM pinout. This makes routing on the PCB easier. To keep the phase of the output, the speaker terminals must also be inverted. When using the TAS5182 power stage this bit must be set. Can be used to handle click and pop for some applications. This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of both speaker outputs to be low. This bit sets the PWM outputs high-high during mute. Not used Table 3-6 lists the optimal setting for each output-stage configuration. Note that the default value is applicable in all configurations except the TAS5182 SE/BTL configuration. TAS5508B Controls and Status Submit Documentation Feedback

3.3.2 Headphone Configuration Registers 3.3.3 Audio System Configurations TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Table 3-6. Recommended TAS5508B Configurations for Texas Instruments Power Stages DEVICE ERROR RECOVERY CONFIGURATION BTL RES SE TAS5111 (default) BTL AUT SE BTL RES SE TAS5112 BTL AUT SE BTL TAS5182 RES SE RES: To recover from a shutdown, the output stage requires VALID to go low. AUT: The power stage can auto-recover from a shutdown. BTL: Bridge-tied load configuration SE: Single-ended configuration The headphone configuration controls are identical to the speaker configuration controls. The headphone configuration control settings are used in place of the speaker configuration control settings for channels and when the headphones are selected. However, only one configuration setting for headphones is used, and that is the default setting. The TAS5508B can be configured to comply with various audio systems: 5.1-channel system, 6-channel system, 7.1-channel system, and 8-channel system. The audio system configuration is set in the general control register (0xE0). Bits D31 must be zero and is don't care Must always be (default). Note that subwoofer cannot be used as lineout when PSVC is enabled. (D3 is a write-only bit) Enables/disables power-supply volume control Sets number of speakers in the system, including possible line outputs must be configured for the audio system in the application, as shown in Table 3-7 Table 3-7. Audio System Configuration (General Control Register 0xE0) Audio System D31 channels or 5.1 not using PSVC X channels using PSVC X 5.1 system using PSVC X channels or 7.1 not using PSVC (default) X channels using PSVC X 7.1 system using PSVC X Submit Documentation Feedback TAS5508B Controls and Status

3.3.3.1 Using Line Outputs in 6-Channel Configurations 3.3.4 Recovery from Clock Error 3.3.5 Power-Supply Volume-Control Enable 3.3.6 Volume and Mute Update Rate 3.3.7 Modulation Index Limit TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com The audio system can be configured for a 6-channel configuration (with lineouts) by writing a to bit of register 0xE0 (general control register). In this configuration, channel-5 and processing are exactly the same as the other channels, except that the master volume and the loudness function have no effect on the signal. Note that in 6-channel configuration, channels and are unaffected by back-end error BKND_ERR goes low). To use channels and as unprocessed lineouts, the following setup is recommended: Channel-5 volume and channel-6 volume should be set for a constant output, such as dB. Bass and treble for channels and can be used if desired. DRC1 should be bypassed for channels and If a down mix is desired on channels and as lineout, the down mixing can be performed using the channel-5 and channel-6 input mixers. The operation of the channel-5 and biquads is unaffected by the 6-/8-channel configuration setting. The TAS5508B can be set either to perform a volume ramp up during the recovery sequence of a clock error or simply to come up in the last state (or desired state if a volume or tone update was in progress). This feature is enabled via I C system control register 0x03. The power-supply volume control (PSVC) can be enabled and disabled via I C register 0xE0. The subwoofer PWM output is always controlled by the PSVC. When using PSVC the subwoofer cannot be used as lineout. The TAS5508B has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute ramp rates are adjustable by programming the I C register 0xD0 for the appropriate number of steps to be 512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate. In normal speed, the update rate is step every 4/f S seconds. In double speed, the update is step every 8/f S seconds. In quad speed, the update is step every 16/f S seconds. Because of processor loading, the update rate can increase for some increments by one step every 1/f S to 3/f S However, the variance of the total time to go from dB to mute is less than 25%. Table 3-8. Volume Ramp Periods in ms SAMPLE RATE (kHz) NUMBER OF STEPS 44.1, 88.2, 176.4 32, 48, 96, 192 512 46.44 42.67 1024 92.88 85.33 2048 185.76 170.67 PWM modulation is a linear function of the audio signal. When the audio signal is the PWM modulation is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%. For negative signals, the PWM modulations fall below 50% toward 0%. However, the maximum possible modulation does have a limit. During the offtime period, the power stage TAS5508B Controls and Status Submit Documentation Feedback

3.4 Master Clock and Serial Data Rate Controls 3.4.1 PLL Operation 3.5 Bank Controls TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 connected to the TAS5508B output needs to get ready for the next on-time period. The maximum possible modulation is then set by the power stage requirements. The default modulation index limit setting is 97.7%; however, some power stages may require a lower modulation limit. See the applicable power stage data sheet for details on setting the modulation index limit. The default setting of 97.7% can be changed in the modulation index register (0x16). The TAS5508B functions only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right clock) signals that control the flow of data on the four serial data interfaces. The 13.5-MHz external crystal allows the TAS5508B to detect MCLK and the data rate automatically. The MCLK frequency can be f S 128 f S 196 f S 256 f S 384 f S 512 f S or 768 f S The TAS5508B operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK. However, the phase relationship of these signals has no constraint. The TAS5508B accepts a f S SCLK rate and a f S LRCLK. If the phase of SCLK or LRCLK drifts more than MCLK cycles since the last reset, the TAS5508B senses a clock error and resynchronizes the clock timing. The clock and serial data interface have several control parameters: MCLK ratio (64 f S 128 f S 196 f S 256 f S 384 f S 512 f S or 768 f S I C parameter Data rate (32, 38, 44.1, 48, 88.2, 96, 176.4, 192 kHz) I C parameter AM mode enable/disable I C parameter During AM interference avoidance, the clock control circuitry uses three other configuration inputs: Tuned AM frequency (for AM interference avoidance) (550 kHz to 1750 kHz) I C parameter Frequency set select I C parameter Sample rate I C parameter or auto-detected The TAS5508B uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL (DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL provides the reference clock for the digital audio processor and the control logic. The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal provides the input reference clock for the DPLL. The crystal provides a time base to support a number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal time base provides a constant rate for all controls and signal timing. Even if MCLK is not present, the TAS5508B can receive and store I C commands and provide status. The TAS5508B permits the user to specify and assign sample-rate-dependent parameters for biquad, loudness, DRC, and tone in one of three banks that can be manually selected or selected automatically based on the data sampling rate. Each bank can be enabled for one or more specific sample rates via I C bank control register 0x40. Each bank set holds the following values: Coefficients for seven biquads coefficients) for each of the eight channels (registers 0x51 0x88) Coefficients for one loudness biquad (register 0x95) DRC1 energy and energy) values (register 0x98) DRC1 attack, attack), decay, decay) values (register 0x9C) DRC2 energy and energy) values (register 0x9D) DRC2 attack, attack), decay, decay) values (register 0xA1) Submit Documentation Feedback TAS5508B Controls and Status

3.5.1 Manual Bank Selection 3.5.2 Automatic Bank Selection 3.5.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled 3.5.3 Bank Set TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Five bass filter-set selections (register 0xDA) Five treble filter-set selections (register 0xDC) The default selection for bank control is manual bank with bank selected. Note that if bank switching is used, bank and bank must be programmed on power up, because the default values are all zeroes. If bank switching is used and bank and bank are not programmed correctly, then the output of the TAS5508B could be muted when switching to those banks. The three bank-selection bits of the bank control register allow the appropriate bank to be manually selected (000 bank 001 bank 010 bank 3). In the manual mode, when a write occurs to the biquad, DRC, or loudness coefficients, the currently selected bank is updated. If audio data is streaming to the TAS5508B during a manual bank selection, the TAS5508B first performs a mute sequence, then performs the bank switch, and finally restores the volume using an unmute sequence. A mute command initiated by the bank-switch mute sequence overrides an unmute command or a volume command. While a mute is active, the commanded channels are muted. When a channel is unmuted, the volume level goes to the last commanded volume setting that has been received for that channel. If MCLK or SCLK is stopped, the TAS5508B performs a bank-switch operation. If the clocks start up once the manual bank-switch command has been received, the bank-switch operation is performed during the 5-ms, silent-start sequence. To enable automatic bank selection, a value of is written into the bank-selection bits of the bank control register. Banks are associated with one or more sample rates by writing values into the bank or bank data-rate selection registers. The automatic bank selection is performed when a frequency change is detected according to the following scheme: The system scans bank-1 data-rate associations to see if bank is assigned for that data rate. If bank is assigned, then the bank-1 coefficients are loaded. If bank is not assigned, the system scans bank to see if bank is assigned for that data rate. If bank is assigned, the bank-2 coefficients are loaded. If bank is not assigned, the system loads the bank-3 coefficients. The default is that all frequencies are enabled for bank This default is expressed as a value of all in the bank-1 auto-selection byte and all in the bank-2 auto-selection byte. In automatic mode, if a write occurs to the tone, EQ, DRC, or loudness coefficients, the bank that is written to is the current bank. Bank set is used to provide a secure way to update the bank coefficients in both the manual and automatic switching modes without causing a bank switch to occur. Bank-set mode does not alter the current bank register mapping. It simply enables any bank coefficients to be updated while inhibiting any bank switches from taking place. In manual mode, this enables the coefficients to be set without switching banks. In automatic mode, this prevents a clock error or data-rate change from corrupting a bank coefficient write. To update the coefficients of a bank, a value of or is written into in the bank-selection bits of the bank control register. This enables the tone, EQ, DRC, and loudness coefficient values of bank or respectively, to be updated. Once the coefficients of the bank have been updated, the bank-selection bits are then returned to the desired manual or automatic bank-selection mode. TAS5508B Controls and Status Submit Documentation Feedback

3.5.4 Bank-Switch Timeline 3.5.5 Bank-Switching Example 3.5.6 Bank-Switching Example TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 After a bank switch is initiated (manual or automatic), no I C writes to the TAS5508B should occur before a minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate. Problem: The audio unit containing a TAS5508B needs to handle different audio formats with different sample rates. Format requires f S kHz, format requires f S 44.1 kHz, and format requires f S kHz. The sample-rate-dependent parameters in the TAS5508B require different coefficients and data depending on the sample rate. Strategy: Use the TAS5508B bank-switching feature to allow for managing and switching three banks associated with the three sample rates, kHz (bank 1), 44.1 kHz (bank 2), and kHz (bank 3). One possible algorithm is to generate, load, and automatically manage bank switching for this problem: Generate bank-related coefficients for sample rates of kHz, 44.1 kHz, and kHz, and include the same in the microprocessor-based TAS5508B I C firmware. On TAS5508B power up or reset, the microprocessor runs the following TAS5508B initialization code: a Update bank (write 0x0004 8040 to register 0x40). b Write bank-related I C registers with appropriate values for bank c Write bank (write 0x0005 8040 to register 0x40). d Load bank-related I C registers with appropriate values for bank e Write bank (write 0x0006 8040 to register 0x40). f Load bank-related I C registers with appropriate values for bank g Select automatic bank switching (write 0x0003 8040 to register 0x40). When the audio media changes, the TAS5508B automatically detects the incoming sample rate and automatically switches to the appropriate bank. In this example, any sample rates other than kHz and 44.1 kHz use bank If other sample rates are used, then the banks must be set up differently. Problem: The audio system uses all of the sample rates supported by the TAS5508B. How can the automatic bank switching be set up to handle this situation? Strategy: Use the TAS5508B bank-switching feature to allow for managing and switching three banks associated with sample rates as follows: Bank Coefficients for kHz, kHz, 44.1 kHz, and kHz Bank Coefficients for 88.2 kHz and kHz Bank Coefficients for 176.4 kHz and 192 kHz One possible algorithm is to generate, load, and automatically manage bank switching for this problem: Generate bank-related coefficients for sample rates kHz (bank 1), kHz (bank 2), and 192 kHz (bank and include the same in the microprocessor-based TAS5508B I C firmware. On TAS5508B power up or reset, the microprocessor runs the following TAS5508B initialization code: a Update bank (write 0x0004 F00C to register 0x40). b Write bank-related I C registers with appropriate values for bank c Write bank (write 0x0005 F00C to register 0x40). d Load bank-related I C registers with appropriate values for bank e Write bank (write 0x0006 F00C to register 0x40). f Load bank-related I C registers with appropriate values for bank g Select automatic bank switching (write 0x0003 F00C to register 0x40). When the audio media changes, the TAS5508B automatically detects the incoming sample rate and automatically switches to the appropriate bank. Submit Documentation Feedback TAS5508B Controls and Status

4.1 Absolute Maximum Ratings (1) 4.2 Dissipation Rating Table (High-k Board, 105 C Junction) 4.3 Dynamic Performance at Recommended Operating Conditions at C 4.4 Recommended Operating Conditions TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Supply voltage, DVDD and DVD_PWM 0.3 V to 3.6 V Supply voltage, AVDD_PLL 0.3 V to 3.6 V 3.3-V digital input 0.5 V to DVDD 0.5 V Input voltage 5-V tolerant (2) digital input 0.5 V to V 1.8-V LVCMOS (3) 0.5 V to VREF (4) 0.5 V I IK Input clamp current I or V I 1.8 V µ A I OK Output clamp current O or V O 1.8 µ A T A Operating free-air temperature C to C T stg Storage temperature range C to 150 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) 5-V tolerant inputs are RESET PDN MUTE HP_SE SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. (3) VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM (4) VREF is a 1.8-V supply derived from regulators internal to the TAS5508B chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source power to external devices. T A C DERATING FACTOR T A C PACKAGE POWER RATING ABOVE T A C POWER RATING PAG 1869 mW 23.36 mW/ C 818 mW PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Dynamic range TAS5508B TAS5111 A-weighted S kHz) 102 dB TAS5111 at W 0.1% Total harmonic distortion TAS5508B output 0.01% 32-kHz to 96-kHz sample rates 0.1 Frequency response dB 176.4, 192-kHz sample rates 0.2 MIN NOM MAX UNIT Digital supply voltage, DVDD and DVDD_PWM 3.3 3.6 V Analog supply voltage, AVDD_PLL 3.3 3.6 V 3.3 V V IH High-level input voltage 5-V tolerant (1) V 1.8-V LVCMOS (XTL_IN) 1.26 3.3 V 0.8 V IL Low-level input voltage 5-V tolerant (1) 0.8 V 1.8-V (XTL_IN) 0.54 T A Operating ambient-air temperature range C T J Operating junction temperature range 105 C (1) 5-V tolerant inputs are RESET PDN MUTE HP_SE SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. Electrical Specifications Submit Documentation Feedback

4.5 Electrical Characteristics 4.6 PWM Operation 4.7 Switching Characteristics 4.7.1 Clock Signals TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3-V TTL and 5-V (1) tolerant I OH mA 2.4 V OH High-level output voltage V 1.8-V LVCMOS (XTL_OUT) I OH 0.55 mA 1.44 3.3-V TTL and 5-V (1) tolerant I OL mA 0.5 V OL Low-level output voltage V 1.8-V LVCMOS (XTL_OUT) I OL 0.75 mA 0.5 I OZ High-impedance output current 3.3-V TTL µ A 3.3-V TTL V I V IL I IL Low-level input current 1.8-V LVCMOS (XTL_IN) V I V IL µ A 5-V tolerant (2) V I DVDD V 3.3-V TTL V I V IH I IH High-level input current 1.8-V LVCMOS (XTL_IN) V I V IH µ A 5-V tolerant (2) V I 5.5 DVDD V f S kHz 140 f S kHz 150 Digital supply voltage, DVDD f S 192 kHz 155 I DD Input supply current mA Power down Normal Analog supply voltage, AVDD Power down (1) 5-V tolerant outputs are SCL and SDA. (2) 5-V tolerant inputs are RESET PDN MUTE HP_SE SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. Over recommended operating conditions PARAMETER TEST CONDITIONS MODE VALUE UNIT 32-kHz data rate sample rate 384 kHz Output sample rate oversampled 44.1-, 88.2-, 176.4-kHz data rate or sample rate 352.8 kHz 48-, 96-, 192-kHz data rate or sample rate 384 kHz PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f XTALI Frequency, XTAL IN Only use 13.5-MHz crystal 1000 ppm 13.5 MHz f MCLKI Frequency, MCLK (1/t cyc2 MHz MCLK duty cycle 40% 50% 60% 2-V MCLK 49.152 MHz, within the min MCLK minimum high time ns and max duty cycle constraints 0.8-V MCLK 49.152 MHz, within the min MCLK minimum low time ns and max duty cycle constraints LRCLK allowable drift before LRCLK reset MCLKs External PLL filter capacitors C11 and C12 SMD 0603 Y5V 100 nF External PLL filter capacitors C10 and C13 SMD 0603 Y5V nF External PLL filter resistors R10 and R11 SMD 0603, metal film 200 Ω External VRA_PLL decoupling C14 SMD, Y5V 100 nF (1) See the TAS5508B Example Application Schematic Section Submit Documentation Feedback Electrical Specifications

4.7.2 Serial Audio Port th1 tsu1 tsu2 th2 SCLK (Input) LRCLK (Input) SDIN1 SDIN2 SDIN3 T0026-01 4.7.3 TAS5508B Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Serial audio port slave mode over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f SCLKIN SCLK input frequency C L pF, SCLK f S 2.048 12.288 MHz t su1 Setup time, LRCLK to SCLK rising edge ns t Hold time, LRCLK from SCLK rising edge ns t su2 Setup time, SDIN to SCLK rising edge ns t Hold time, SDIN from SCLK rising edge ns LRCLK frequency 192 kHz SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60% SCLK SCLK rising edges between LRCLK rising edges edges LRCLK clock edge with respect to the falling edge of SCLK SCLK period Figure 4-1. Slave Mode Serial Data Interface Timing I C-Bus Devices STANDARD MODE FAST MODE PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX V IL LOW-level input voltage 0.5 0.3 V DD 0.5 0.3 V DD V V IH HIGH-level input voltage 0.7 V DD 0.7 V DD V V hys Hysteresis of Schmitt-trigger inputs N/A N/A 0.05 V DD V V OL1 LOW-level output voltage (open drain or 3-mA sink current 0.4 V open collector) t of Output fall time from V IHmin to VILmax Bus capacitance from pF 250 0.1 C b 250 ns to 400 pF (1) t SP Pulse duration of spikes suppressed (2) N/A N/A ns I i Input current, each I/O pin (3) (3) µ A C i Capacitance, each I/O pin pF (1) C b capacitance of one bus line in pF. The output fall time is faster than the standard I C specification. (2) SCL and SDA have a 30-ns glitch filter. (3) The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if V DD is switched off. Electrical Specifications Submit Documentation Feedback

4.7.4 TAS5508B Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode SDA SCL tf tSU-DAT tHD-STA tr tBUF tSU-STO P S tSP tSU-STA Sr tHIGH tHD-DAT tLOW tr tHD-STA S tf T0114-01 TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 I C-Bus Devices All values are referred to V IHmin and V ILmax (see Section 4.7.3 A STANDARD MODE FAST MODE PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX f SCL SCL clock frequency 100 400 kHz Hold time (repeated) START condition. t HD-STA After this period, the first clock pulse is 0.6 µ s generated. t LOW LOW period of the SCL clock 4.7 1.3 µ s t HIGH HIGH period of the SCL clock 0.6 µ s t SU-STA Setup time for repeated START 4.7 0.6 µ s t SU-DAT Data setup time 250 100 µ s t HD-DAT Data hold time (1) (2) 3.45 0.9 µ s t r Rise time of both SDA and SCL 1000 0.1 C b (3) 500 (4) ns t f Fall time of both SDA and SCL 300 0.1 C b (3) 300 ns t SU-STO Setup time for STOP condition 0.6 µ s t BUF Bus free time between a STOP and 4.7 1.3 µ s START condition C b Capacitive loads for each bus line 400 400 pF V nL Noise margin at the LOW level for each 0.1 V DD 0.1 V DD V connected device (including hysteresis) V nH Noise margin at the HIGH level for each 0.2 V DD 0.2 V DD V connected device (including hysteresis) (1) Note that SDA does not have the standard I C specification 300-ns hold time and that SDA must be valid by the rising and falling edges of SCL. TI recommends that a 3.3-k Ω pullup resistor be used to avoid potential timing issues. (2) A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement t SU-DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r-max t SU-DAT 1000 250 1250 ns (according to the standard-mode I C bus specification) before the SCL line is released. (3) C b total capacitance of one bus line in pF. (4) Rise time varies with pullup resistor. Figure 4-2. Start and Stop Conditions Timing Waveforms Submit Documentation Feedback Electrical Specifications

4.7.4.1 Recommended I C Pullup Resistors B0099-01 TAS5508B External Microcontroller VI(SDA) 5□V IP IP VI(SCL) SDA RP RP SCL B0100-01 TAS5508B External Microcontroller VI 5□V IP SDA or SCL RS (2) VS (1) RS (2) RP TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com It is recommended that the I C pullup resistors R P be 3.3 k Ω (see Figure 4-3 If a series resistor is in the circuit (see Figure 4-4 then the series resistor R S should be less than or equal to 300 Ω Figure 4-3. I C Pullup Circuit (With No Series Resistor) (1) V S R S /(R S R P When driven low, V S V IL requirements. (2) R S 300 Ω Figure 4-4. I C Pullup Circuit (With Series Resistor) Electrical Specifications Submit Documentation Feedback

4.7.5 Reset Timing RESET tw(RESET) Earliest time that PWM outputs could be enabled RESET VALID td(PWM_off) /C0051 370 ns td(I2C_ready) Start system td(run) Determine SCLK rate and MCLK ratio. Enable via I2C. T0029-04 4.7.6 Power-Down PDN Timing PDN VALID tsutd(PWM_off) < 300 µs T0030-03 TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT t d(PWM_off) Time from reset to PWM_EN low (PWM outputs disabled) 370 ns t w(RESET) Pulse duration, RESET active 400 ns t d(I2C_ready) Time to enable I C ms t d(run) Device start-up time ms NOTE: Because a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock ratio is determined, the system outputs audio if a master volume command is issued at the beginning of t d(run) Figure 4-5. Reset Timing Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT t d(PWM_off) Time from reset to PWM_EN low (PWM outputs disabled) 300 µ s Number of MCLKs preceding the release of PDN t su Device start-up time 120 ms Figure 4-6. Power-Down Timing Submit Documentation Feedback Electrical Specifications

4.7.7 Back-End Error BKND_ERR BKND_ERR td(valid_low) VALID tw(ER) td(valid_high) Normal Operation Normal Operation T0031-03 4.7.8 Mute Timing MUTE td(VOL) VOLUME MUTE Normal Operation Normal Operation td(VOL) T0032-02 TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT t w(ER) Pulse duration, BKND_ERR active 350 None ns t d(valid_low) Time from back-end error to PWM_EN low (PWM outputs disabled) 100 µ s t d(valid_high) I C programmable to be between to ms of interval Figure 4-7. Error-Recovery Timing Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT t d(VOL) Volume ramp time Defined by rate setting (1) ms (1) See the Volume, Treble, and Base Slew Rates Register (0xD0) Section 7.26 Figure 4-8. Mute Timing Electrical Specifications Submit Documentation Feedback

4.7.9 Headphone Select HP_SEL td(VOL) HP Volume HP_SEL Spkr Volume t(SW) T0033-02 td(VOL) td(VOL) td(VOL) t(SW) tw(HP_SEL) 4.7.10 Volume Control TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT t w(HP_SEL) Pulse duration, HP_SEL active 350 ns t d(VOL) Soft volume update time Defined by rate setting (1) ms t (SW) Switchover time 0.2 ms (1) See the Volume, Treble, and Base Slew Rates Register (0xD0) Section 7.26 Figure 4-9. HP_SEL Timing Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT Individual volume, master volume, or a Maximum attenuation before mute 109 dB combination of both Maximum gain Individual volume, master volume dB Maximum volume before the onset of clipping 0-dB input, any modulation limit dB PSVC range PSVC enabled 12, 18, or dB PSVC rate f S PSVC modulation Single sided PSVC quantization 2048 Steps 95% PSVC PWM modulation limits PSVC range dB dB (120 2048) (1944 2048) Submit Documentation Feedback Electrical Specifications

4.8 Serial Audio Interface Control and Timing 4.8.1 I S Timing 23 22 SCLK 32□Clks LRCLK□(Note□Reversed□Phase) Left□Channel 24-Bit□Mode 19 18 20-Bit□Mode 16-Bit□Mode 15 14 MSB LSB 32□Clks Right□Channel 2-Channel□I S□(Philips□Format)□Stereo□Input T0034-01 5 49 8 1 0 1 0 23 22 1 19 18 15 14 MSB LSB 5 49 8 1 0 1 0 SCLK TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com I S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at f S is used to clock in the data. From the time the LRCLK signal changes state to the first bit of data on the data lines is a delay of one bit clock. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508B masks unused trailing data bit positions. Figure 4-10. I S 64-f S Format Electrical Specifications Submit Documentation Feedback

4.8.2 Left-Justified Timing 23 22 SCLK 32□Clks LRCLK Left□Channel 24-Bit□Mode 19 18 20-Bit□Mode 16-Bit□Mode 15 14 MSB LSB 32□Clks Right□Channel 2-Channel□Left-Justified□Stereo□Input T0034-02 459 8 145 23 22 1 19 18 15 14 MSB LSB 459 8 145 SCLK TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at f S is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508B masks unused trailing data bit positions. Figure 4-11. Left-Justified 64-f S Format Submit Documentation Feedback Electrical Specifications

4.8.3 Right-Justified Timing 23 22 SCLK 32□Clks LRCLK Left□Channel 24-Bit□Mode 20-Bit□Mode 16-Bit□Mode 15 14 MSB LSB SCLK 32□Clks Right□Channel 2-Channel□Right-Justified□(Sony□Format)□Stereo□Input T0034-03 19 18 119 18 15 14 15 14 23 22 1 15 14 MSB LSB 19 18 119 18 15 14 15 14 TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at f S is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508B masks unused leading data bit positions. Figure 4-12. Right-Justified 64-f S Format Electrical Specifications Submit Documentation Feedback

I C Serial-Control Interface (Slave Addresses 0x36 and 0x37) 5.1 General I C Operation 7-Bit□Slave Address R/ W 8-Bit□Register Address□(N)A 8-Bit□Register□Data□For Address□(N) Start Stop SDA SCL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 A 8-Bit□Register□Data□For Address□(N)A A T0035-01 TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 The TAS5508B has a bidirectional I C interface that is compatible with the Inter-IC bus protocol and supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status. The TAS5508B supports the standard-mode I C bus operation (100 kHz maximum) and the fast I C bus operation (400 kHz maximum). The TAS5508B performs all I C operations without I C wait cycles. The I C write address is 0x36 and the I C read address is 0x37. The I C bus employs two signals SDA (data) and SCL (clock) to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on SDA while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 5-1 The master generates the 7-bit slave address and the read/write (R/ W bit to open communication with another device and then waits for an acknowledge condition. The TAS5508B holds SDA low during the acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus W bit byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus. Figure 5-1. Typical I C Sequence The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 5-1 The 7-bit address for the TAS5508B is 0011011. When the W bit is added as the LSB, the I C write address is 0x36 and the I C read address is 0x37. Submit Documentation Feedback I C Serial-Control Interface (Slave Addresses 0x36 and 0x37)

5.2 Single- and Multiple-Byte Transfers 5.3 Single-Byte Write A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I C□Device Address□and Read/Write□Bit Subaddress Data□□Byte T0036-01 TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com The serial-control interface supports both single-byte and multiple-byte read/write operations for status registers and the general control registers associated with the PWM. However, for the DAP data processing registers, the serial-control interface supports only multiple-byte (four-byte) read/write operations. During multiple-byte read operations, the TAS5508B responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain bits, the unused bits are read as logic During multiple-byte write operations, the TAS5508B compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. If a write command is received for a biquad subaddress, the TAS5508B expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5508B expects to receive one 32-bit word. Supplying a subaddress for each subaddress transaction is referred to as random I C addressing. The TAS5508B also supports sequential I C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the subaddresses that follow, a sequential I C write transaction has taken place, and the data for all subaddresses is successfully received by the TAS5508B. For I C sequential write transactions, the subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As is true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data is discarded. As shown in Figure 5-2 a single-byte, data-write transfer begins with the master device transmitting a start condition followed by the I C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit is a After receiving the correct I C device address and the read/write bit, the TAS5508B device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5508B internal memory address being accessed. After receiving the address byte, the TAS5508B again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5508B again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte, data-write transfer. Figure 5-2. Single-Byte Write Transfer Submit Documentation Feedback I C Serial-Control Interface (Slave Addresses 0x36 and 0x37)

5.4 Multiple-Byte Write D7 D0 ACK Stop Condition Acknowledge I C□Device Address□and Read/Write□Bit Subaddress Last□Data□Byte A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK Start Condition Acknowledge Acknowledge Acknowledge First□Data□Byte A4 A3A6 Other□Data□Bytes ACK Acknowledge D0 D7 D0 T0036-02 5.5 Incremental Multiple-Byte Write TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data bytes are transmitted by the master device to TAS5508B, as shown in Figure 5-3 After receiving each data byte, the TAS5508B responds with an acknowledge bit. Figure 5-3. Multiple-Byte Write Transfer The I C supports a special mode which permits I C write operations to be broken up into multiple data write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc., write operations that are composed of a device address, read/write bit, subaddress, and any multiple of four bytes of data. This permits the system to write large register values incrementally without blocking other I C transactions. This feature is enabled by the append subaddress function in the TAS5508B. This function enables the TAS5508B to append four bytes of data to a register that was opened by a previous I C register write operation but has not received its complete number of data bytes. Because the length of the long registers is a multiple of four bytes, using four-byte transfers has only an integral number of append operations. When the correct number of bytes has been received, the TAS5508B starts processing the data. The procedure to perform an incremental multibyte-write operation is as follows: Start a normal I C write operation by sending the device address, write bit, register subaddress, and the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point, the register has been opened and accepts the remaining data that is sent by writing four-byte blocks of data to the append subaddress (0xFE). At a later time, one or more append data transfers are performed to incrementally transfer the remaining number of bytes in sequential order to complete the register write operation. Each of these append operations is composed of the device address, write bit, append subaddress (0xFE), and four bytes of data followed by a stop condition. The operation is terminated due to an error condition, and the data is flushed: a If a new subaddress is written to the TAS5508B before the correct number of bytes are written. b If more or fewer than four bytes are data written at the beginning or during any of the append operations. c If a read bit is sent. Submit Documentation Feedback I C Serial-Control Interface (Slave Addresses 0x36 and 0x37)

5.6 Single-Byte Read A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I C□Device Address□and Read/Write□Bit Subaddress Data□Byte D7 D6 D1 D0 ACK I C□Device Address□and Read/Write□Bit Not Acknowledge R/WA1 A1 Repeat□Start Condition T0036-03 5.7 Multiple-Byte Read A6 A0 ACK Acknowledge I C□Device Address□and Read/Write□Bit R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge Last□Data□Byte ACK First□Data□Byte Repeat□Start Condition Not Acknowledge I C□Device Address□and Read/Write□Bit Subaddress Other□Data□Bytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 T0036-04 TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com As shown in Figure 5-4 a single-byte, data-read transfer begins with the master device transmitting a start condition followed by the I C device address and the read/write bit. For the data-read transfer, both a write and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit is a After receiving the TAS5508B address and the read/write bit, the TAS5508B responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5508B address and the read/write bit again. This time the read/write bit is a indicating a read transfer. After receiving the TAS5508B address and the read/write bit, the TAS5508B again responds with an acknowledge bit. Next, the TAS5508B transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte, data-read transfer. Figure 5-4. Single-Byte Read Transfer A multiple-byte, data-read transfer is identical to a single-byte, data-read transfer except that multiple data bytes are transmitted by the TAS5508B to the master device, as shown in Figure 5-5 Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Figure 5-5. Multiple-Byte Read Transfer Submit Documentation Feedback I C Serial-Control Interface (Slave Addresses 0x36 and 0x37)

I C Register Summary TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 The TAS5508B slave write address is 0x36 and the read address is 0x37. See Serial-Control Interface Register Definitions Section for complete bit definitions. Note that u indicates unused bits. TOTAL I C REGISTER FIELDS f S kHz MCLK 256 f S 12.288 MHz 0x01 General status register Clip indicator and ID code for the 0x03 TAS5508B 0x02 Reserved PWM (dc blocking) high-pass filter enabled PWM high pass, clock set, unmute Auto clock set 0x03 System control register select, PSVC select Hard unmute on clock error recovery PSVC Hi-Z disabled Automute time-out disabled Post-DAP detection automute enabled 0x04 System control register Automute and de-emphasis control 8-Ch device input detection automute enabled Unmute threshold dB over input No de-emphasis Enable back-end reset. VALID low for reset VALID low for mute Channel configuration Configure channels 0x05 0x0C 1/reg. Normal BEPolarity control registers and Do not remap the output for the TAS5182. Do not go low-low in mute. Do not remap Hi-Z state to low-low state. Disable back-end reset sequence. VALID does not have to be low for reset. VALID does not have to be low for mute. Headphone configuration 0x0D Configure headphone output Normal BEPolarity control register Do not remap output to comply with TAS5182. Do not go low-low in mute. Do not remap Hi-Z state to low-low state. 0x0E Serial data interface control Set serial data interface to 24-bit I S register right-justified, I or left-justified. 0x0F Soft mute register Soft mute for channels Unmute all channels. and 0x10 0x13 Reserved 0x14 Automute control register Set automute delay and threshold. Set automute delay ms. Set automute threshold less than bit 0x15 Automute PWM threshold Set PWM automute threshold; set Set the PWM threshold the same as the and back-end reset period back-end reset period. TAS5508B input threshold. register Set back-end reset period ms. 0x16 Modulation index limit Set modulation index. 97.7% register 0x17 0x3F Reserved 0x40 Bank-switching command Set up DAP coefficients bank Manual selection bank register switching for banks and SDIN1 left to input mixer SDIN1 right to input mixer SDIN2 left to input mixer Input mixer registers, SDIN2 right to input mixer 0x41 0x48 32/reg. input crossbar mixer setup Ch1 Ch8 SDIN3 left to input mixer SDIN3 right to input mixer SDIN4 left to input mixer SDIN4 right to input mixer 0x49 ipmix_1_to_ch8 Input mixer to Ch8 mixer coefficient 0.0 0x4A ipmix_2_to_ch8 Input mixer to Ch8 mixer coefficient 0.0 0x4B ipmix_7_to_ch2 Input mixer to Ch2 mixer coefficient 0.0 0x4C Ch7_bp_bq2 Bypass Ch7 biquad coefficient 0.0 0x4D Ch7_bq2 Ch7 biquad coefficient 1.0 0x4E ipmix_8_to_ch12 Ch8 biquad output to Ch1 mixer and 0.0 Ch2 mixer coefficient Submit Documentation Feedback Serial-Control I C Register Summary

www.ti.com TOTAL I C REGISTER FIELDS Ch8_bp_bq2 Bypass Ch8 biquad coefficient 0.0 0x50 Ch8_bq2 Ch8 biquad coefficient 1.0 0x51 0x88 20/reg. Biquad filter register Ch1 Ch8 biquad filter coefficients All biquads All pass for all channels 0x89 0x90 Bass and treble bypass Bypass bass and treble for Ch1 Ch8 Bass and treble bypassed for all channels register, Ch1 Ch8 0x91 Loudness Log2 LG Loudness Log2 LG 0.5 0x92 Loudness Log2 LO Loudness Log2 LO 0.0 0x93 Loudness G Loudness G 0.0 0x94 Loudness O Loudness O 0.0 Loudness biquad coefficient 0x00, 0x00, 0xD5, 0x13 Loudness biquad coefficient 0x00, 0x00, 0x00, 0x00 0x95 Loudness biquad Loudness biquad coefficient 0x0F, 0xFF, 0x2A, 0xED Loudness biquad coefficient 0x00, 0xFE, 0x50, 0x45 Loudness biquad coefficient 0x0F, 0x81, 0xAA, 0x27 0x96 DRC1 control Ch1 Ch7 DRC1 control Ch1 Ch7 DRC1 disabled in Ch1 Ch7 0x97 DRC2 control register, Ch8 DRC2 control Ch8 DRC2 disabled in Ch8 Ch1 Ch7, DRC1 energy DRC1 energy 0.0041579 0x98 Ch1 Ch7, DRC1 energy) 0.9958421 DRC1 energy) Ch1 Ch7 DRC1 threshold DRC1 threshold (T1) upper bytes 0x00, 0x00, 0x00, 0x00 DRC1 threshold (T1) lower bytes 0x0B, 0x20, 0xE2, 0xB2 0x99 Ch1 Ch7 DRC1 threshold DRC1 threshold (T2) upper bytes 0x00, 0x00, 0x00, 0x00 DRC1 threshold (T2) lower bytes 0x06, 0xF9, 0xDE, 0x58 Ch1 Ch7 DRC1 slope DRC1 slope (k0) 0x0F, 0xC0, 0x00, 0x00 0x9A Ch1 Ch7, DRC1 slope DRC1 slope (k1) 0x0F, 0xC0, 0x00, 0x00 Ch1 Ch7 DRC1 slope DRC1 slope (k2) 0x0F, 0x90, 0x00, 0x00 Ch1 Ch7 DRC1 offset DRC1 offset (O1) upper bytes 0x00, 0x00, 0xFF, 0xFF DRC1 offset (O1) lower bytes 0xFF, 0x82, 0x30, 0x98 0x9B Ch1 Ch7 DRC1 offset DRC1 offset (O2) upper bytes 0x00, 0x00, 0x00, 0x00 DRC1 offset (O2) lower bytes 0x01, 0x95, 0xB2, 0xC0 Ch1 Ch7 DRC1 attack DRC1 attack 0x00, 0x00, 0x88, 0x3F Ch1 Ch7 DRC1 attack) DRC1 attack) 0x00, 0x7F, 0x77, 0xC0 0x9C Ch1 Ch7 DRC1 decay DRC1 decay 0x00, 0x00, 0x00, 0xAE Ch1 Ch7 DRC1 decay) DRC1 decay) 0x00, 0x7F, 0xFF, 0x51 Ch8 DRC2 energy DRC2 energy 0x00, 0x00, 0x88, 0x3F 0x9D Ch8 DRC2 energy) DRC2 energy) 0x00, 0x7F, 0x77, 0xC0 DRC2 threshold (T1) upper bytes 0x00, 0x00, 0x00, 0x00 Ch8 DRC2 threshold DRC2 threshold (T1) lower bytes 0x0B, 0x20, 0xE2, 0xB2 0x9E DRC2 threshold (T2) upper bytes 0x00, 0x00, 0x00, 0x00 Ch8 DRC2 threshold DRC2 threshold (T2) lower bytes 0x06, 0xF9, 0xDE, 0x58 Ch8 DRC2 slope DRC2 slope (k0) 0x00, 0x40, 0x00, 0x00 0x9F Ch8 DRC2 slope DRC2 slope (k1) 0x0F, 0xC0, 0x00, 0x00 Ch8 DRC2 slope DRC2 slope (k2) 0x0F, 0x90, 0x00, 0x00 DRC2 offset (O1) upper bytes 0x00, 0x00, 0xFF, 0xFF Ch8 DRC2 offset DRC2 offset (O1) lower bytes 0xFF, 0x82, 0x30, 0x98 0xA0 DRC2 offset (O2) upper bytes 0x00, 0x00, 0x00, 0x00 Ch8 DRC2 offset DRC2 offset (O2) lower bytes 0x01, 0x95, 0xB2, 0xC0 Ch8 DRC2 attack DRC attack 0x00, 0x00, 0x88, 0x3F Ch8 DRC2 attack) DRC2 attack) 0x00, 0x7F, 0x77, 0xC0 0xA1 Ch8 DRC2 decay DRC2 decay 0x00, 0x00, 0x00, 0xAE Ch8 DRC2 decay) DRC2 decay) 0x00, 0x7F, 0xFF, 0x51 Submit Documentation Feedback Serial-Control I C Register Summary

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 TOTAL I C REGISTER FIELDS 1.0 0xA2 DRC inline Ch1 DRC1 inline coefficient 0.0 DRC bypass Ch2 DRC1 bypass coefficient 1.0 0xA3 DRC inline Ch2 DRC1 inline coefficient 0.0 DRC bypass Ch3 DRC1 bypass coefficient 1.0 0xA4 DRC inline Ch3 DRC1 inline coefficient 0.0 DRC bypass Ch4 DRC1 bypass coefficient 1.0 0xA5 DRC inline Ch4 DRC1 inline coefficient 0.0 DRC bypass Ch5 DRC1 bypass coefficient 1.0 0xA6 DRC inline Ch5 DRC1 inline coefficient 0.0 DRC bypass Ch6 DRC1 bypass coefficient 1.0 0xA7 DRC inline Ch6 DRC1 inline coefficient 0.0 DRC bypass Ch7 DRC1 bypass coefficient 1.0 0xA8 DRC inline Ch7 DRC1 inline coefficient 0.0 DRC bypass Ch8 DRC2 bypass coefficient 1.0 0xA9 DRC inline Ch8 DRC2 inline coefficient 0.0 0xAA sel op1 and mix to PWM1 Select to of eight channels to Mix channels to PWM1. output mixer 0xAB sel op1 and mix to PWM2 Select to of eight channels to Mix channels to PWM2. output mixer 0xAC sel op1 and mix to PWM3 Select to of eight channels to Mix channels to PWM3. output mixer 0xAD sel op1 and mix to PWM4 Select to of eight channels to Mix channels to PWM4. output mixer 0xAE sel op1 and mix to PWM5 Select to of eight channels to Mix channels to PWM5. output mixer 0xAF sel op1 and mix to PWM6 Select to of eight channels to Mix channels to PWM6. output mixer 0xB0 sel op1 and mix to PWM7 Select to of eight channels to Mix channels to PWM7. output mixer 0xB1 sel op1 and mix to PWM8 Select to of eight channels to Mix channels to PWM8. output mixer 0xB2 0xCE Reserved 0xCF Volume biquad Volume biquad All pass 0xD0 Volume, treble, and bass u [31:24], u [23:16], u [15:12] 0x00, 0x00, 0x01, 0x3F slew rates register VSR[11:8], TBSR[7:0] 0xD1 Ch1 volume Ch1 volume dB 0xD2 Ch2 volume Ch2 volume dB 0xD3 Ch3 volume Ch3 volume dB 0xD4 Ch4 volume Ch4 volume dB 0xD5 Ch5 volume Ch5 volume dB 0xD6 Ch6 volume Ch6 volume dB 0xD7 Ch7 volume Ch7 volume dB 0xD8 Ch8 volume Ch8 volume dB 0xD9 Master volume Master volume Mute 0xDA Bass filter set register Bass filter set (all channels) Filter set 0xDB Bass filter index register Bass filter level (all channels) dB 0xDC Treble filter set register Treble filter set (all channels) Filter set 0xDD Treble filter index register Treble filter level (all channels) dB 0xDE AM mode register Set up AM mode for AM-interference AM mode disabled reduction Select sequence IF frequency 455 kHz Use BCD-tuned frequency 0xDF PSVC range register Set PSVC control range 12-dB control range 0xE0 General control register or 8-channel configuration, PSVC 8-channel configuration enable Power-supply volume control disabled Submit Documentation Feedback Serial-Control I C Register Summary

www.ti.com TOTAL I C REGISTER FIELDS (min) Multiple-byte write-append Special register N/A register 0xFF Reserved Submit Documentation Feedback Serial-Control I C Register Summary

7.1 Clock Control Register (0x00) 7.2 General Status Register (0x01) 7.3 System Control Register (0x03) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Unless otherwise noted, the I C register default values are in bold font. Note that u indicates unused bits. Bit is don't care Table 7-1. Clock Control Register Format FUNCTION 32-kHz data rate 38-kHz data rate 44.1-kHz data rate 48-kHz data rate 88.2-kHz data rate 96-kHz data rate 176.4-kHz data rate 192-kHz data rate MCLK frequency MCLK frequency 128 MCLK frequency 192 MCLK frequency 256 MCLK frequency 384 MCLK frequency 512 MCLK frequency 768 Reserved Clock register is valid (read-only) Clock register is not valid (read-only) Table 7-2. General Status Register Format FUNCTION Clip indicator Identification code for TAS5508B Bits D6, D5, D2, D1, and are don't care Table 7-3. System Control Register-1 Format Function PWM high pass disabled PWM high pass enabled Soft unmute on recovery from clock error Hard unmute on recovery from clock error PSVC Hi-Z enabled PSVC Hi-Z disabled Submit Documentation Feedback Serial-Control Interface Register Definitions

7.4 System Control Register (0x04) 7.5 Channel Configuration Control Registers (0x05 0x0C) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Bits and are don't care Table 7-4. System Control Register-2 Format Function Reserved Output automute detection enabled Output automute detection disabled Input detection automute enabled Input detection automute disabled Unmute threshold dB over input threshold Unmute threshold equal to input threshold No de-emphasis De-emphasis for f S kHz De-emphasis for f S 44.1 kHz De-emphasis for f S kHz Channels and are mapped into 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, and 0x0C, respectively. Note that in 6-channel mode, the channel configuration control registers for lineouts (Ch 0x09 and Ch 0x0A) must be 0x00. Table 7-5. Channel Configuration Control Register Format FUNCTION Disable back-end reset sequence for a channel. Enable back-end reset sequence for a channel. Valid does not have to be low for this channel to be reset. Valid must be low for this channel to be reset. Valid does not have to be low for this channel to be muted. Valid must be low for this channel to be muted. Normal BEPolarity Switches PWM+ and PWM and inverts audio signal Do not remap output to comply with 5182 interface. Remap output to comply with 5182 interface. Do not go to low-low in mute. Go to low-low in mute. Do not remap Hi-Z state to low-low state. Remap Hi-Z state to low-low state. Serial-Control Interface Register Definitions Submit Documentation Feedback

7.6 Headphone Configuration Control Register (0x0D) 7.7 Serial Data Interface Control Register (0x0E) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Bit is don't care Table 7-6. Headphone Configuration Control Register Format FUNCTION Disable back-end reset sequence for a channel. Enable back-end reset sequence for a channel. Valid does not have to be low for this channel to be reset. Valid must be low for this channel to be reset. Valid does not have to be low for this channel to be muted. Valid must be low for this channel to be muted. Normal BEPolarity Switches PWM+ and PWM and inverts audio signal Do not remap output to comply with 5182 interface. Remap output to comply with 5182 interface. Do not go to low-low in mute. Go to low-low in mute. Do not remap Hi-Z state to low-low state. Remap Hi-Z state to low-low state. Nine serial modes can be programmed via the I C interface. Table 7-7. Serial Data Interface Control Register Format RECEIVE SERIAL DATA WORD LENGTHS INTERFACE FORMAT Right-justified 0000 Right-justified 0000 Right-justified 0000 I S 0000 I S 0000 I S 0000 Left-justified 0000 Left-justified 0000 Left-justified 0000 Reserved 0000 Reserved 0000 Reserved 0000 Reserved 0000 Reserved 0000 Reserved 0000 Reserved 0000 Submit Documentation Feedback Serial-Control Interface Register Definitions

7.8 Soft Mute Register (0x0F) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Do not use this register if using the remapped output mixer configuration. Table 7-8. Soft Mute Register Format FUNCTION Soft mute channel Soft mute channel Soft mute channel Soft mute channel Soft mute channel Soft mute channel Soft mute channel Soft mute channel Unmute all channels Serial-Control Interface Register Definitions Submit Documentation Feedback

7.9 Automute Control Register (0x14) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 For more information on how to use this register, see Automute and Mute Channel Controls Section 2.8 Table 7-9. Automute Control Register Format FUNCTION Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to 70ms Set input automute and output automute delay to ms Set input automute and output automute delay to ms Set input automute and output automute delay to 100 ms Set input automute and output automute delay to 110 ms Set input automute threshold less than bit (zero input signal), lowest automute threshold. Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Set input automute threshold less than bit Submit Documentation Feedback Serial-Control Interface Register Definitions

7.10 Output Automute PWM Threshold and Back-End Reset Period Register (0x15) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com For more information on how to use this register, see Automute and Mute Channel Controls Section 2.8 Table 7-10. Automute PWM Threshold and Back-End Reset Period Register Format FUNCTION Set output automute threshold equal to input automute threshold Set output automute threshold bit more than input automute threshold Set output automute threshold bits more than input automute threshold Set output automute threshold bits more than input automute threshold Set output automute threshold bits more than input automute threshold Set output automute threshold bits more than input automute threshold Set output automute threshold bits more than input automute threshold Set output automute threshold bits more than input automute threshold Set output automute threshold equal to input automute threshold Set output automute threshold bit less than input automute threshold Set output automute threshold bits less than input automute threshold Set output automute threshold bits less than input automute threshold Set output automute threshold bits less than input automute threshold Set output automute threshold bits less than input automute threshold Set output automute threshold bits less than input automute threshold Set output automute threshold bits less than input automute threshold Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms Set back-end reset period ms X X Set back-end reset period ms Serial-Control Interface Register Definitions Submit Documentation Feedback

7.11 Modulation Index Limit Register (0x16) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Bits are don't care Note that some power stages require a lower modulation limit than the default of 97.7%. Contact Texas Instruments for more details about the requirements for a particular power stage. Table 7-11. Modulation Index Limit Register Format LIMIT MIN WIDTH MODULATION [DCLKs] [DCLKs] INDEX 99.2% 98.4% 97.7% 96.9% 96.1% 95.3% 94.5% 93.8% Submit Documentation Feedback Serial-Control Interface Register Definitions

7.12 Bank-Switching Command Register (0x40) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Bits D31 D24, D22 D19 are don't care Table 7-12. Bank-Switching Command Register Format D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Unused bits D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION Manual selection bank Manual selection bank Manual selection bank Automatic bank selection Update the values in bank Update the values in bank Update the values in bank Update only the bank map Update the bank map using values in D15 Do not update the bank map using values in D15 D15 D14 D13 D12 D11 D10 FUNCTION 32-kHz data rate use bank 38-kHz data rate use bank 44.1-kHz data rate use bank 48-kHz data rate use bank 88.2-kHz data rate use bank 96-kHz data rate use bank 176.4-kHz data rate use bank 192-kHz data rate use bank Default FUNCTION 32-kHz data rate use bank 38-kHz data rate use bank 44.1-kHz data rate use bank 48-kHz data rate use bank 88.2-kHz data rate use bank 96-kHz data rate use bank 176.4-kHz data rate use bank 192-kHz data rate use bank Default Serial-Control Interface Register Definitions Submit Documentation Feedback

7.13 Input Mixer Registers, Channels (0x41 0x48) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Input mixers and are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and 0x48, respectively. Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of Each gain coefficient is written as a 32-bit word with the upper four bits not used. For eight gain coefficients, the total is bytes. Bold indicates the one channel that is passed through the mixer. Table 7-13. Channel Input Mixer Register Format I C TOTAL REGISTER (Ch1) A to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 A_to_ipmix[1] u[31:28], A_1[27:24], A_1[23:16], A_1[15:8], A_1[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 B_to_ipmix[1] u[31:28], B_1[27:24], B_1[23:16], B_1[15:8], B_1[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 C_to_ipmix[1] u[31:28], C_1[27:24], C_1[23:16], C_1[15:8], C_1[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 D_to_ipmix[1] u[31:28], D_1[27:24], D_1[23:16], D_1[15:8], D_1[7:0] 0x41 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 E_to_ipmix[1] u[31:28], E_1[27:24], E_1[23:16], E_1[15:8], E_1[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 F_to_ipmix[1] u[31:28], F_1[27:24], F_1[23:16], F_1[15:8], F_1[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 G_to_ipmix[1] u[31:28], G_1[27:24], G_1[23:16], G_1[15:8], G_1[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 H_to_ipmix[1] u[31:28], H_1[27:24], H_1[23:16], H_1[15:8], H_1[7:0] SDIN1-left (Ch1) A to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 A_to_ipmix[2] u[31:28], A_2[27:24], A_2[23:16], A_2[15:8], A_2[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 B_to_ipmix[2] u[31:28], B_2[27:24], B_2[23:16], B_2[15:8], B_2[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 C_to_ipmix[2] u[31:28], C_2[27:24], C_2[23:16], C_2[15:8], C_2[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 D_to_ipmix[2] u[31:28], D_2[27:24], D_2[23:16], D_2[15:8], D_2[7:0] 0x42 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 E_to_ipmix[2] u[31:28], E_2[27:24], E_2[23:16], E_2[15:8], E_2[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 F_to_ipmix[2] u[31:28], F_2[27:24], F_2[23:16], F_2[15:8], F_2[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 G_to_ipmix[2] u[31:28], G_2[27:24], G_2[23:16], G_2[15:8], G_2[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 H_to_ipmix[2] u[31:28], H_2[27:24], H_2[23:16], H_2[15:8], H_2[7:0] Submit Documentation Feedback Serial-Control Interface Register Definitions

www.ti.com Table 7-13. Channel Input Mixer Register Format (continued) I C TOTAL REGISTER (Ch1) A to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 A_to_ipmix[3] u[31:28], A_3[27:24], A_3[23:16], A_3[15:8], A_3[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 B_to_ipmix[3] u[31:28], B_3[27:24], B_3[23:16], B_3[15:8], B_3[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 C_to_ipmix[3] u[31:28], C_3[27:24], C_3[23:16], C_3[15:8], C_3[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 D_to_ipmix[3] u[31:28], D_3[27:24], D_3[23:16], D_3[15:8], D_3[7:0] 0x43 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 E_to_ipmix[3] u[31:28], E_3[27:24], E_3[23:16], E_3[15:8], E_3[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 F_to_ipmix[3] u[31:28], F_3[27:24], F_3[23:16], F_3[15:8], F_3[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 G_to_ipmix[3] u[31:28], G_3[27:24], G_3[23:16], G_3[15:8], G_3[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 H_to_ipmix[3] u[31:28], H_3[27:24], H_3[23:16], H_3[15:8], H_3[7:0] SDIN1-left (Ch1) A to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 A_to_ipmix[4] u[31:28], A_4[27:24], A_4[23:16], A_4[15:8], A_4[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 B_to_ipmix[4] u[31:28], B_4[27:24], B_4[23:16], B_4[15:8], B_4[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 C_to_ipmix[4] u[31:28], C_4[27:24], C_4[23:16], C_4[15:8], C_4[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 D_to_ipmix[4] u[31:28], D_4[27:24], D_4[23:16], D_4[15:8], D_4[7:0] 0x44 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 E_to_ipmix[4] u[31:28], E_4[27:24], E_4[23:16], E_4[15:8], E_4[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 F_to_ipmix[4] u[31:28], F_4[27:24], F_4[23:16], F_4[15:8], F_4[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 G_to_ipmix[4] u[31:28], G_4[27:24], G_4[23:16], G_4[15:8], G_4[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 H_to_ipmix[4] u[31:28], H_4[27:24], H_4[23:16], H_4[15:8], H_4[7:0] SDIN1-left (Ch1) A to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 A_to_ipmix[5] u[31:28], A_5[27:24], A_5[23:16], A_5[15:8], A_5[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 B_to_ipmix[5] u[31:28], B_5[27:24], B_5[23:16], B_5[15:8], B_5[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 C_to_ipmix[5] u[31:28], C_5[27:24], C_5[23:16], C_5[15:8], C_5[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 D_to_ipmix[5] u[31:28], D_5[27:24], D_5[23:16], D_5[15:8], D_5[7:0] 0x45 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 E_to_ipmix[5] u[31:28], E_5[27:24], E_5[23:16], E_5[15:8], E_5[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 F_to_ipmix[5] u[31:28], F_5[27:24], F_5[23:16], F_5[15:8], F_5[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 G_to_ipmix[5] u[31:28], G_5[27:24], G_5[23:16], G_5[15:8], G_5[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 H_to_ipmix[5] u[31:28], H_5[27:24], H_5[23:16], H_5[15:8], H_5[7:0] Serial-Control Interface Register Definitions Submit Documentation Feedback

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Table 7-13. Channel Input Mixer Register Format (continued) I C TOTAL REGISTER (Ch1) A to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 A_to_ipmix[6] u[31:28], A_6[27:24], A_6[23:16], A_6[15:8], A_6[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 B_to_ipmix[6] u[31:28], B_6[27:24], B_6[23:16], B_6[15:8], B_6[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 C_to_ipmix[6] u[31:28], C_6[27:24], C_6[23:16], C_6[15:8], C_6[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 D_to_ipmix[6] u[31:28], D_6[27:24], D_6[23:16], D_6[15:8], D_6[7:0] 0x46 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 E_to_ipmix[6] u[31:28], E_6[27:24], E_6[23:16], E_6[15:8], E_6[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 F_to_ipmix[6] u[31:28], F_6[27:24], F_6[23:16], F_6[15:8], F_6[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 G_to_ipmix[6] u[31:28], G_6[27:24], G_6[23:16], G_6[15:8], G_6[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 H_to_ipmix[6] u[31:28], H_6[27:24], H_6[23:16], H_6[15:8], H_6[7:0] SDIN1-left (Ch1) A to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 A_to_ipmix[7] u[31:28], A_7[27:24], A_7[23:16], A_7[15:8], A_7[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 B_to_ipmix[7] u[31:28], B_7[27:24], B_7[23:16], B_7[15:8], B_7[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 C_to_ipmix[7] u[31:28], C_7[27:24], C_7[23:16], C_7[15:8], C_7[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 D_to_ipmix[7] u[31:28], D_7[27:24], D_7[23:16], D_7[15:8], D_7[7:0] 0x47 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 E_to_ipmix[7] u[31:28], E_7[27:24], E_7[23:16], E_7[15:8], E_7[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 F_to_ipmix[7] u[31:28], F_7[27:24], F_7[23:16], F_7[15:8], F_7[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 G_to_ipmix[7] u[31:28], G_7[27:24], G_7[23:16], G_7[15:8], G_7[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 H_to_ipmix[7] u[31:28], H_7[27:24], H_7[23:16], H_7[15:8], H_7[7:0] SDIN1-left (Ch1) A to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 A_to_ipmix[8] u[31:28], A_8[27:24], A_8[23:16], A_8[15:8], A_8[7:0] SDIN1-right (Ch2) B to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 B_to_ipmix[8] u[31:28], B_8[27:24], B_8[23:16], B_8[15:8], B_8[7:0] SDIN2-left (Ch3) C to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 C_to_ipmix[8] u[31:28], C_8[27:24], C_8[23:16], C_8[15:8], C_8[7:0] SDIN2-right (Ch4) D to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 D_to_ipmix[8] u[31:28], D_8[27:24], D_8[23:16], D_8[15:8], D_8[7:0] 0x48 SDIN3-left (Ch5) E to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 E_to_ipmix[8] u[31:28], E_8[27:24], E_8[23:16], E_8[15:8], E_8[7:0] SDIN3-right (Ch6) F to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 F_to_ipmix[8] u[31:28], F_8[27:24], F_8[23:16], F_8[15:8], F_8[7:0] SDIN4-left (Ch7) G to input mixer coefficient (default 0x00, 0x00, 0x00, 0x00 G_to_ipmix[8] u[31:28], G_8[27:24], G_8[23:16], G_8[15:8], G_8[7:0] SDIN4-right (Ch8) H to input mixer coefficient (default 0x00, 0x80, 0x00, 0x00 H_to_ipmix[8] u[31:28], H_8[27:24], H_8[23:16], H_8[15:8], H_8[7:0] Submit Documentation Feedback Serial-Control Interface Register Definitions

7.14 Bass Management Registers (0x49 0x50) 7.15 Biquad Filter Register (0x51 0x88) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Registers 0x49 0x50 provide configuration control for bass mangement. Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 7-14. Bass Management Register Format SUB- TOTAL REGISTER ipmix_1_to_ch8 Input mixer to Ch8 mixer coefficient (default 0x00, 0x00, 0x00, 0x00 u[31:28], ipmix18[27:24], ipmix18[23:16], ipmix18[15:8], ipmix18[7:0] 0x4A ipmix_2_to_ch8 Input mixer to Ch8 mixer coefficient (default 0x00, 0x00, 0x00, 0x00 u[31:28], ipmix28[27:24], ipmix28[23:16], ipmix28[15:8], ipmix28[7:0] 0x4B ipmix_7_to_ch12 Input mixer to Ch1 and Ch2 mixer coefficient (default 0x00, 0x00, 0x00, 0x00 u[31:28], ipmix72[27:24], ipmix72[23:16], ipmix72[15:8], ipmix72[7:0] 0x4C Ch7_bp_bq2 Ch7 biquad-2 bypass coefficient (default 0x00, 0x00, 0x00, 0x00 u[31:28], ch7_bp_bq2[27:24], ch7_bp_bq2[23:16], ch7_bp_bq2[15:8], ch7_bp_bq2[7:0] 0x4D Ch7_bq2 Ch7 biquad-2 inline coefficient (default 0x00, 0x80, 0x00, 0x00 u[31:28], ch6_bq2[27:24], ch6_bq2[23:16], ch6_bq2[15:8], ch6_bq2[7:0] 0x4E ipmix_8_to_ch12 Ch8 biquad-2 output to Ch1 mixer and Ch2 mixer coefficient 0x00, 0x00, 0x00, 0x00 (default u[31:28], ipmix8_12[27:24], ipmix8_12[23:16], ipmix8_12[15:8], ipmix8_12[7:0] 0x4F Ch8_bp_bq2 Ch8 biquad-2 bypass coefficient (default 0x00, 0x00, 0x00, 0x00 u[31:28], ch8_bp_bq2[27:24], ch8_bp_bq2[23:16], ch8_bp_bq2[15:8], ch8_bp_bq2[7:0] 0x50 Ch8_bq2 Ch8 biquad-2 inline coefficient (default 0x00, 0x80, 0x00, 0x00 u[31:28], ch7_bq2[27:24], ch7_bq2[23:16], ch7_bq2[15:8], ch7_bq2[7:0] Table 7-15. Biquad Filter Register Format I C TOTAL REGISTER DEFAULT 20/reg. Ch1_bq[1:7] Ch1 biquads See Table 7-16 for bit definition. See Table 7-16 0x58 0x5E 20/reg. Ch2_bq[1:7] Ch2 biquads See Table 7-16 for bit definition. See Table 7-16 0x5F 0x65 20/reg. Ch3_bq[1:7] Ch3 biquads See Table 7-16 for bit definition. See Table 7-16 0x66 0x6C 20/reg. Ch4_bq[1:7] Ch4 biquads See Table 7-16 for bit definition. See Table 7-16 0x6D 0x73 20/reg. Ch5_bq[1:7] Ch5 biquads See Table 7-16 for bit definition. See Table 7-16 0x74 0x7A 20/reg. Ch6_bq[1:7] Ch6 biquads See Table 7-16 for bit definition. See Table 7-16 0x7B 0x81 20/reg. Ch7_bq[1:7] Ch7 biquads See Table 7-16 for bit definition. See Table 7-16 0x82 0x88 20/reg. Ch8_bq[1:7] Ch8 biquads See Table 7-16 for bit definition. See Table 7-16 Serial-Control Interface Register Definitions Submit Documentation Feedback

7.16 Bass and Treble Bypass Register, Channels (0x89 0x90) 7.17 Loudness Registers (0x91 0x95) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 7-16. (Default All-Pass) DEFAULT GAIN COEFFICIENT VALUES b coefficient u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] 1.0 0x00, 0x80, 0x00, 0x00 b coefficient u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 b coefficient u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a coefficient u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a coefficient u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0] 0.0 0x00, 0x00, 0x00, 0x00 Channels and are mapped into registers 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, and 0x90, respectively. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 7-17. Channel Bass and Treble Bypass Register Format REGISTER TOTAL u[31:28], bypass[27:24], bypass[23:16], bypass[15:8], bypass[7:0] 0x00, 0x80, 0x00, 0x00 treble bypass Channel bass and u[31:28], inline[27:24], inline[23:16], inline[15:8], inline[7:0] 0x00, 0x00, 0x00, 0x00 treble inline Table 7-18. Loudness Register Format I C SUB- TOTAL REGISTER NAME (LG) u[31:28], LG[27:24], LG[23:16], LG[15:8], LG[7:0] 0xFF, 0xC0, 0x00, 0x00 Loudness Log2 offset (LO) u[31:24], u[23:16], LO[15:8], LO[7:0] 0x00, 0x00, 0x00, 0x00 0x92 Loudness Log2 offset (LO) LO[31:24], LO[23:16], LO[15:8], LO[7:0] 0x00, 0x00, 0x00, 0x00 0x93 Loudness gain (G) u[31:28], G[27:24], G[23:16], G[15:8], G[7:0] 0x00, 0x00, 0x00, 0x00 Loudness offset upper u[31:24], u[23:16], O[15:8], O[7:0] 0x00, 0x00, 0x00, 0x00 bits (O) 0x94 Loudness offset lower O[31:24], O[23:16], O[15:8], O[7:0] 0x00, 0x00, 0x00, 0x00 bits (O) Loudness biquad u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] 0x00, 0x00, 0xD5, 0x13 Loudness biquad u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0] 0x00, 0x00, 0x00, 0x00 0x95 Loudness biquad u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0] 0x0F, 0xFF, 0x2A, 0xED Loudness biquad u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0] 0x00, 0xFE, 0x50, 0x45 Loudness biquad u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0] 0x0F, 0x81, 0xAA, 0x27 Submit Documentation Feedback Serial-Control Interface Register Definitions

7.18 DRC1 Control Registers, Channels (0x96) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Bits D31 D14 are don't care Note that there must be a 10-ms delay between a write to register 0x96 and a write to register 0x97. Table 7-19. Channel DCR1 Control Register Format D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Unused bits D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION Unused bits D15 D14 D13 D12 D11 D10 FUNCTION Channel (node j): No DRC Channel Pre-volume DRC Channel Post-volume DRC Channel No DRC Channel No DRC Channel Pre-volume DRC Channel Post-volume DRC Channel No DRC Channel No DRC Channel Pre-volume DRC Channel Post-volume DRC Channel No DRC FUNCTION Channel No DRC Channel Pre-volume DRC Channel Post-volume DRC Channel No DRC Channel No DRC Channel Pre-volume DRC Channel Post-volume DRC Channel No DRC Channel No DRC Channel Pre-volume DRC Channel Post-volume DRC Channel No DRC Channel No DRC Channel Pre-volume DRC Channel Post-volume DRC Channel No DRC Serial-Control Interface Register Definitions Submit Documentation Feedback

7.19 DRC2 Control Register, Channel (0x97) 7.20 DRC1 Data Registers (0x98 0x9C) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Note that there must be a 10-ms delay between a write to register 0x96 and a write to register 0x97. Table 7-20. Channel-8 DRC2 Control Register Format D31 FUNCTION Channel (node r): no DRC Channel (node r): pre-volume DRC Channel (node r): post-volume DRC Channel (node r): no DRC DRC1 applies to channels and Table 7-21. DRC1 Data Register Format I C TOTAL REGISTER NAME u[31:28], E[27:24], E[23:16], E[15:8], E[7:0] 0x00, 0x00, 0x88, 0x3F energy 0x98 Channel and DRC1 u[31:28], E[27:24], E[23:16], E[15:8], E[7:0] 0x00, 0x7F, 0x77, 0xC0 energy) Channel and DRC1 u[31:24], u[23:16], T1[15:8], T1[7:0] 0x00, 0x00, 0x00, 0x00 threshold upper bits (T1) Channel and DRC1 T1[31:24], T1[23:16], T1[15:8], T1[7:0] 0x0B, 0x20, 0xE2, 0xB2 threshold lower bits (T1) 0x99 Channel and DRC1 u[31:24], u[23:16], T2[15:8], T2[7:0] 0x00, 0x00, 0x00, 0x00 threshold upper bits (T2) Channel and DRC1 T2[31:24], T2[23:16], T2[15:8], T2[7:0] 0x06, 0xF9, 0xDE, 0x58 threshold lower bits (T2) Channel and DRC1 u[31:28], k0[27:24], k0[23:16], k0[15:8], k0[7:0] 0x00, 0x40, 0x00, 0x00 slope (k0) Channel and DRC1 u[31:28], k1[27:24], k1[23:16], k1[15:8], k1[7:0] 0x0F, 0xC0, 0x00, 0x00 0x9A slope (k1) Channel and DRC1 u[31:28], k2[27:24], k2[23:16], k2[15:8], k2[7:0] 0x0F, 0x90, 0x00, 0x00 slope (k2) Channel and DRC1 u[31:24], u[23:16], O1[15:8], O1[7:0] 0x00, 0x00, 0xFF, 0xFF offset-1 upper bits (O1) Channel and DRC1 O1[31:24], O1[23:16], O1[15:8], O1[7:0] 0xFF, 0x82, 0x30, 0x98 offset-1 lower bits (O1) 0x9B Channel and DRC1 u[31:24], u[23:16], O2[15:8], O2[7:0] 0x00, 0x00, 0x00, 0x00 offset-2 upper bits (O2) Channel and DRC1 O2[31:24], O2[23:16], O2[15:8], O2[7:0] 0x01, 0x95, 0xB2, 0xC0 offset-2 lower bits (O2) Channel and DRC1 u[31:28], A[27:24], A[23:16], A[15:8], A[7:0] 0x00, 0x00, 0x88, 0x3F attack Channel and DRC1 u[31:28], A[27:24], A[23:16], A[15:8], A[7:0] 0x00, 0x7F, 0x77, 0xC0 attack) 0x9C Channel and DRC1 u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] 0x00, 0x00, 0x00, 0x56 decay Channel and DRC1 u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] 0x00, 0x3F, 0xFF, 0xA8 decay) Submit Documentation Feedback Serial-Control Interface Register Definitions

7.21 DRC2 Data Registers (0x9D 0xA1) 7.22 DRC Bypass Registers (0xA2 0xA9) 7.23 Output Mixer Registers (0xAA 0xAF) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com DRC2 applies to channel Table 7-22. DRC2 Data Register Format TOTAL I C REGISTER NAME u[31:28], E[27:24], E[23:16], E[15:8], E[7:0] 0x00, 0x00, 0x88, 0x3F 0x9D Channel DRC2 energy) u[31:28], E[27:24], E[23:16], E[15:8], E[7:0] 0x00, 0x7F, 0x77, 0xC0 Channel DRC2 threshold u[31:24], u[23:16], T1[15:8], T1[7:0] 0x00, 0x00, 0x00, 0x00 upper bits (T1) Channel DRC2 threshold T1[31:24], T1[23:16], T1[15:8], T1[7:0] 0x0B, 0x20, 0xE2, 0xB2 lower bits (T1) 0x9E Channel DRC2 threshold u[31:24], u[23:16], T2[15:8], T2[7:0] 0x00, 0x00, 0x00, 0x00 upper bits (T2) Channel DRC2 threshold T2[31:24], T2[23:16], T2[15:8], T2[7:0] 0x06, 0xF9, 0xDE, 0x58 lower bits (T2) Channel DRC2 slope (k0) u[31:28], k0[27:24], k0[23:16], k0[15:8], k0[7:0] 0x00, 0x40, 0x00, 0x00 0x9F Channel DRC2 slope (k1) u[31:28], k1[27:24], k1[23:16], k1[15:8], k1[7:0] 0x0F, 0xC0, 0x00, 0x00 Channel DRC2 slope (k2) u[31:28], k2[27:24], k2[23:16], k2[15:8], k2[7:0] 0x0F, 0x90, 0x00, 0x00 Channel DRC2 offset upper u[31:24], u[23:16], O1[15:8], O1[7:0] 0x00, 0x00, 0xFF, 0xFF bits (O1) Channel DRC2 offset lower O1[31:24], O1[23:16], O1[15:8], O1[7:0] 0xFF, 0x82, 0x30, 0x98 bits (O1) 0xA0 Channel DRC2 offset upper u[31:24], u[23:16], O2[15:8], O2[7:0] 0x00, 0x00, 0x00, 0x00 bits (O2) Channel DRC2 offset lower O2[31:24], O2[23:16], O2[15:8], O2[7:0] 0x01, 0x95, 0xB2, 0xC0 bits (O2) Channel DRC2 attack u[31:28], A[27:24], A[23:16], A[15:8], A[7:0] 0x00, 0x00, 0x88, 0x3F Channel DRC2 attack) u[31:28], A[27:24], A[23:16], A[15:8], A[7:0] 0x00, 0x7F, 0x77, 0xC0 0xA1 Channel DRC2 decay u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] 0x00, 0x00, 0x00, 0x56 Channel DRC2 decay) u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] 0x00, 0x3F, 0xFF, 0xA8 DRC bypass/inline for channels and are mapped into registers 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, and 0xA9, respectively. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format, so 0x0080 0000 is a gain of Each gain coefficient is written as a 32-bit word with the upper bits not used. To enable DRC for a given channel (with unity gain), bypass 0x0000 0000 and inline 0x0080 0000. To disable DRC for a given channel, bypass 0x0080 0000 and inline 0x0000 0000. Table 7-23. DRC Bypass Register Format TOTAL REGISTER NAME u[31:28], bypass[27:24], bypass[23:16], bypass[15:8], bypass[7:0] 0x00, 0x80, 0x00, 0x00 Channel DRC inline u[31:28], inline[27:24], inline[23:16], inline[15:8], inline[7:0] 0x00, 0x00, 0x00, 0x00 The pass-through output mixer setting is: DAP channel is mapped though the crossbar mixer (0xAA) to PWM channel DAP channel is mapped though the crossbar mixer (0xAB) to PWM channel DAP channel is mapped though the crossbar mixer (0xAC) to PWM channel DAP channel is mapped though the crossbar mixer (0xAD) to PWM channel DAP channel is mapped though the crossbar mixer (0xAE) to PWM channel Serial-Control Interface Register Definitions Submit Documentation Feedback

7.24 Output Mixer Registers (0xB0 0xB1) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 DAP channel is mapped though the crossbar mixer (0xAF) to PWM channel Note that the pass-through output mixer configuration (0xD0 bit is recommended. Using the remapped output mixer configuration (0xD0 bit increases the complexity of using some mute. See TAS5508B Errata SLEZ006 Total data per register is bytes. The default gain for each selected channel is (0x0 00). Table 7-24. Output Mixer Register Format (Upper Bytes) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer G27 G26 G25 G24 Selected channel gain (upper bits) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued) D15 D14 D13 D12 D11 D10 FUNCTION G15 G14 G13 G12 G11 G10 Selected channel gain (continued) FUNCTION Selected channel gain (lower bits) Table 7-25. Output Mixer Register Format (Lower Bytes) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer G27 G26 G25 G24 Selected channel gain (upper bits) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued) D15 D14 D13 D12 D11 D10 FUNCTION G15 G14 G13 G12 G11 G10 Selected channel gain (continued) FUNCTION Selected channel gain (lower bits) The pass-through output mixer setting is: DAP channel is mapped though the crossbar mixer (0xB0) to PWM channel DAP channel is mapped though the crossbar mixer (0xB1) to PWM channel Submit Documentation Feedback Serial-Control Interface Register Definitions

www.ti.com Note that the default setting is recommended for most systems. Any variation from this setting increases the complexity of using some mute. See TAS5508B Errata SLEZ006 Total data per register is bytes. The default gain for each selected channel is (0x0080 0000). Table 7-26. Output Mixer Register Format (Upper Bytes) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer G27 G26 G25 G24 Selected channel gain (upper bits) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued) D15 D14 D13 D12 D11 D10 FUNCTION G15 G14 G13 G12 G11 G10 Selected channel gain (continued) FUNCTION Selected channel gain (lower bits) Table 7-27. Output Mixer Register Format (Middle Bytes) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer G27 G26 G25 G24 Selected channel gain (upper bits) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued) D15 D14 D13 D12 D11 D10 FUNCTION G15 G14 G13 G12 G11 G10 Selected channel gain (continued) FUNCTION Selected channel gain (lower bits) Table 7-28. Output Mixer Register Format (Lower Bytes) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer Serial-Control Interface Register Definitions Submit Documentation Feedback

7.25 PSVC Volume Biquad Register (0xCF) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Table 7-28. Output Mixer Register Format (Lower Bytes) (continued) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Select channel to output mixer Select channel to output mixer Select channel to output mixer Select channel to output mixer G27 G26 G25 G24 Selected channel gain (upper bits) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued) D15 D14 D13 D12 D11 D10 FUNCTION G15 G14 G13 G12 G11 G10 Selected channel gain (continued) FUNCTION Selected channel gain (lower bits) Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of Each gain coefficient is written as a 32-bit word with the upper four bits not used. Note that this register should be used only with the PSVC feature its use is not required. For systems not using this feature, it is recommended that this biquad be set to all-pass (default). Table 7-29. Volume Biquad Register Format (Default All-Pass) DEFAULT GAIN COEFFICIENT VALUES b o coefficient u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] 1.0 0x00, 0x80, 0x00, 0x00 b coefficient u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 b coefficient u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a coefficient u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a coefficient u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0] 0.0 0x00, 0x00, 0x00, 0x00 Submit Documentation Feedback Serial-Control Interface Register Definitions

7.26 Volume, Treble, and Bass Slew Rates Register (0xD0) 7.27 Volume Registers (0xD1 0xD9) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com If using pass-through output mixer configuration, bit D30 must to be set to after reset. For remapped output mixer configuration, this bit must be left in the default state (0). Table 7-30. Volume Gain Update Rate (Slew Rate) D31 D30 D29-D10 FUNCTION x x Remapped output mixer configuration (not recommended) x x Pass-through output mixer configuration (recommended) 512-step update at f S 42.6 ms at kHz 1024-step update at f S 85.3 ms at kHz 2048-step update at f S 170 ms at kHz 2048-step update at f S 170 ms at kHz Table 7-31. Treble and Bass Gain Step Size (Slew Rate) FUNCTION No operation Minimum rate Updates every 0.083 ms (every LRCLK at kHz) Updates every 0.67 ms (32 LRCLKs at kHz) Default rate Updates every 1.31 ms (63 LRCLKs at kHz). This is the maximum constant time that can be set for all sample rates. Maximum rate Updates every 5.08 ms (every 255 LRCLKs at kHz) Channels and are mapped into registers 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, and 0xD8, respectively. The default volume for all channels is dB. Master volume is mapped into register 0xD9. The default for the master volume is mute. Bits D31 D12 are don't care Table 7-32. Volume Register Format D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Unused bits D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION Unused bits D15 D14 D13 D12 D11 D10 FUNCTION V11 V10 Volume FUNCTION Volume Serial-Control Interface Register Definitions Submit Documentation Feedback

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Table 7-33. Master and Individual Volume Controls VOLUME INDEX (H) GAIN (dB) 001 17.75 002 17.5 003 17.25 004 005 16.75 006 16.5 007 16.25 008 009 15.75 00A 15.5 00B 15.25 00C 00D 14.75 00E 14.5 00F 14.25 010 TO 044 045 0.75 046 0.5 047 0.25 048 049 0.25 04A 0.5 04B 0.75 04C TO 1F8 108 1F9 108.25 1FA 108.5 1FB 108.75 1FC -109 1FD Mute TO 245 Mute Submit Documentation Feedback Serial-Control Interface Register Definitions

7.28 Bass Filter Set Register (0xDA) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com To use the bass and treble function, the bass and treble bypass registers (0x89 0x90) must be configured as inline (default is bypass). Table 7-34. Channel (Subwoofer) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION No change Bass filter set Bass filter set Bass filter set Bass filter set Bass filter set Reserved Reserved Table 7-35. Channels and (Right and Left Lineout in 6-Channel Configuration; Right and Left Surround in 8-Channel Configuration) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION No change Bass filter set Bass filter set Bass filter set Bass filter set Bass filter set Reserved Reserved Table 7-36. Channels and (Right and Left Rear) D15 D14 D13 D12 D11 D10 FUNCTION No change Bass filter set Bass filter set Bass filter set Bass filter set Bass filter set Reserved Reserved Serial-Control Interface Register Definitions Submit Documentation Feedback

7.29 Bass Filter Index Register (0xDB) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Table 7-37. Channels and (Center, Right Front, and Left Front) FUNCTION No change Bass filter set Bass filter set Bass filter set Bass filter set Bass filter set Reserved Reserved Index values above 0x24 are invalid. To use the bass and treble function, the bass and treble bypass registers (0x89 0x90) must be configured as inline (default is bypass). Table 7-38. Bass Filter Index Register Format I C TOTAL REGISTER Ch8_BFI[31:24], Ch65_BFI[23:16], Ch43_BFI[15:8], 0x12, 0x12, 0x12, 0x12 (BFI) Ch721_BFI[7:0] Table 7-39. Bass Filter Indexes BASS INDEX VALUE ADJUSTMENT (dB) BASS INDEX VALUE ADJUSTMENT (dB) 0x00 0x13 0x01 0x14 0x02 0x15 0x03 0x16 0x04 0x17 0x05 0x18 0x06 0x19 0x07 0x1A 0x08 0x1B 0x09 0x1C 0x0A 0x1D 0x0B 0x1E 0x0C 0x1F 0x0D 0x20 0x0E 0x21 0x0F 0x22 0x10 0x23 0x11 0x24 0x12 Submit Documentation Feedback Serial-Control Interface Register Definitions

7.30 Treble Filter Set Register (0xDC) TAS5508B 8-Channel Digital Audio PWM Processor SLES162C DECEMBER 2005 REVISED JULY 2009 www.ti.com Bits D31 D27 are don't care To use the bass and treble function, the bass and treble bypass registers (0x89 0x90) must be configured as inline (enabled). Table 7-40. Channel (Subwoofer) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION No change Treble filter set Treble filter set Treble filter set Treble filter set Treble filter set Reserved Reserved Bits D23 D19 are don't care Table 7-41. Channels and (Right and Left Lineout in 6-Channel Configuration; Right and Left Surround in 8-Channel Configuration) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION No change Treble filter set Treble filter set Treble filter set Treble filter set Treble filter set Reserved Reserved Bits D15 D11 are don't care Table 7-42. Channels and (Right and Left Rear) D15 D14 D13 D12 D11 D10 FUNCTION No change Treble filter set Treble filter set Treble filter set Treble filter set Treble filter set Reserved Reserved Serial-Control Interface Register Definitions Submit Documentation Feedback

7.31 Treble Filter Index (0xDD) 7.32 AM Mode Register (0xDE) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Bits are don't care Table 7-43. Channels and (Center, Right Front, and Left Front) FUNCTION No change Treble filter set Treble filter set Treble filter set Treble filter set Treble filter set Reserved Reserved Index values above 0x24 are invalid. To use the bass and treble function, the bass and treble bypass registers (0x89 0x90) must be configured as inline (enabled). Table 7-44. Treble Filter Index Register Format I C REGISTER TOTAL BYTES (TFI) Ch8_TFI[31:24], Ch65_TFI[23:16], 0x12, 0x12, 0x12, 0x12 Ch43_TFI[15:8], Ch721_TFI[7:0] Table 7-45. Treble Filter Indexes TREBLE INDEX VALUE ADJUSTMENT (dB) TREBLE INDEX VALUE ADJUSTMENT (dB) 0x00 0x13 0x01 0x14 0x02 0x15 0x03 0x16 0x04 0x17 0x05 0x18 \\06 0x19 0x07 0x1A 0x08 0x1B 0x09 0x1C 0x0A 0x1D 0x0B 0x1E 0x0C 0x1F 0x0D 0x20 0x0E 0x21 0x0F 0x22 0x10 0x23 0x11 0x24 0x12 Bits D31 D21 are don't care Submit Documentation Feedback Serial-Control Interface Register Definitions

www.ti.com Table 7-46. AM Mode Register Format D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Unused bits D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION AM mode disabled AM mode enabled Select sequence Select sequence Select sequence Select sequence IF frequency 455 kHz IF frequency 262.5 kHz Use BCD-tuned frequency Use binary-tuned frequency Table 7-47. AM Tuned Frequency Register in BCD Mode (Lower Bytes of 0xDE) D15 D14 D13 D12 D11 D10 FUNCTION BCD frequency (1000s kHz) BCD frequency (100s kHz) Default value FUNCTION BCD frequency (10s kHz) BCD frequency (1s kHz) Default value Table 7-48. AM Tuned Frequency Register in Binary Mode (Lower Bytes of 0xDE) D15 D14 D13 D12 D11 D10 FUNCTION B10 Binary frequency (upper bits) Default value FUNCTION Binary frequency (lower bits) Default value Serial-Control Interface Register Definitions Submit Documentation Feedback

7.33 PSVC Range Register (0xDF) 7.34 General Control Register (0xE0) 7.35 Incremental Multiple-Byte Write Append Register (0xFE) TAS5508B 8-Channel Digital Audio PWM Processor www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 Bits D31 are zero. Table 7-49. PSVC Range Register Format D31 FUNCTION 12.04-dB control range for PSVC 18.06-dB control range for PSVC 24.08-dB control range for PSVC Ignore retain last value Bits D31 are zero. Bit is don't care Table 7-50. General Control Register Format D31 FUNCTION 8-channel configuration 6-channel configuration Power-supply volume control disabled Power-supply volume control enabled Subwoofer part of PSVC. This bit must always be (D3 is a write-only bit) This is a special register used to append data to a previously opened register. See Multiple-Byte Write Section 5.4 for programming details. Submit Documentation Feedback Serial-Control Interface Register Definitions

www.ti.com Serial-Control Interface Register Definitions Submit Documentation Feedback

www.ti.com SLES162C DECEMBER 2005 REVISED JULY 2009 The following page contains an example application schematic for the TAS5508B. Submit Documentation Feedback TAS5508B Example Application Schematic

TAS5508B Example Application Schematic RIGHT SPEAKER OUTPUT (Circuit is Subject To Change Without Notice) CH1 TAS5121 H-Bridge Output Stage /SHUTDOWN_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING CH4 TAS5121 H-Bridge Output Stage /SHUTDOWN_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING CH7 TAS5121 H-Bridge Output Stage /SHUTDOWN_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING Left + Right Line Out

2 Channel Line Out (TLV272)

+3.3V +5.0V PWM_P_L PWM_M_L PWM_P_R PWM_M_R OUT_L OUT_R /OE CH5 TAS5121 H-Bridge Output Stage /SHUTDOWN_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING CH8 TAS5121 H-Bridge Output Stage /SHUTDOWN_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING PSU and Interface Logic +3.3V +5.0V GVDD V-HBRIDGE /RESET PSVC_MCPU /RESET_TAS5508 /OTW_TAS5121 /OTW /BKND_ERR /BKND_ERR_TAS5508 /SD1_TAS5121 /SD1 CONF_SEL /VALID /VALID_CH5+CH6 /LINE_OUT_ENABLE /SD2 /SD2_TAS5121 PSVC_TAS5508 CH3 TAS5121 H-Bridge Output Stage /SHUTDOWN_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING CH2 TAS5121 H-Bridge Output Stage /SHUTDOWN_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING CH6 TAS5121 H-Bridge Output Stage /SD1_TAS5121 PWM_P PWM_M /VALID OUT_1 OUT_2 GVDD V-HBRIDGE /TEMP_WARNING Left + Right Headphone

2 Channel Headphone Design (TPA112)

PWM_HPP_R PWM_HPM_R OUT_L OUT_R +5.0V PWM_HPP_L PWM_HPM_L OUT_GND +3.3V GND GND +3.3V GVDD V-HBRIDGE GVDD V-HBRIDGE GVDD V-HBRIDGE GVDD V-HBRIDGE V-HBRIDGE GVDD V-HBRIDGE GVDD V-HBRIDGE GVDD V-HBRIDGE GVDD +3.3V GND +3.3V GND +5.0V+3.3V +5.0V GVDDV-HBRIDGE +5.0V +3.3V GND GND C25 220nF J600 R21 C13 10nF C14 100nF C17 100nF C20 100nF J951 Phono socket R13 3.30R J100 X10 13.5MHz J400 J700 J800 C15 100nF R12 1 2 C11 100nF C10 10nF C29 100nF R18 1 2 R20 22.0R 1 2 J500 R10 200R 1 2 R11 200R 1 2 C28 15pF 2 1 C27 15pF 2 1 J300 C23 10uF 1 2 C21 100nF C18 1nF 1 2 C26 10uF 1 2 J950 Phono socket C16 10uF 1 2 J200 C12 100nF C24 100nF U10 TAS5508B VRA_PLL PLL_FLT_RET PLL_FLTM PLL_FLTP AVSS AVSS VRD_PLL AVSS_PLL AVDD_PLL VBGAP RESET HP_SEL PDN MUTE DVDD DVSS VR_DPLL OSC_CAP XTL_OUT XTL_IN RESERVED RESERVED SDA SCL LRCLK SCLK SDIN4 SDIN3 SDIN2 SDIN1 PSVC VR_PWM PWM_P_4 PWM_M_4 PWM_P_3 PWM_M_3 PWM_P_2 PWM_M_2 PWM_P_1 PWM_M_1 VAILD DVSS BKND_ERR DVDD DVSS DVSS VR_DIG RESERVED MCLK PWM_HPPR PWM_HPMR PWM_HPPL PWM_HPML PWM_P_6 PWM_M_6 PWM_P_5 PWM_M_5 DVDD_PWM DVSS_PWM PWM_P_8 PWM_M_8 PWM_P_7 PWM_M_7 RESERVEDR14 J900 Mini-Jack (3.5mm) C22 100nF C19 10uF 1 2 /VALID_CH5+CH6 /VALID /VALID /VALID /VALID /VALID /VALID /RESET_TAS5508 /RESET /BKND_ERR /BKND_ERR_TAS5508 /OTW_TAS5121 /OTW /SD1_TAS5121 /SD1 /SD2_TAS5121 /SD2 /VALID_CH5+CH6 /VALID CONF_SEL /VALID_CH5+CH6 /SD1_TAS5121 /OTW_TAS5121 /SD1_TAS5121 /OTW_TAS5121 /SD2_TAS5121 /OTW_TAS5121 /SD2_TAS5121 /OTW_TAS5121 /SD1_TAS5121 /OTW_TAS5121 /SD2_TAS5121 /OTW_TAS5121 /SD2_TAS5121 /OTW_TAS5121 /SD2_TAS5121 /OTW_TAS5121/LINE_OUT_ENABLE PSVC_TAS5508 PSVC_MCPU /LINE_OUT_ENABLE /BKND_ERR_TAS5508/HP_SEL /PDN_TAS5508 /VALID /MUTE_TAS5508 MCLK /RESET_TAS5508 SCL PSVC_TAS5508 SDA LRCLK SDIN4 SCLK SDIN3 SDIN2 SDIN1

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN0804050PAGR NRND TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5508B TAS5508BPAG NRND TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5508B TAS5508BPAGG4 NRND TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5508B TAS5508BPAGR NRND TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5508B TAS5508BPAGRG4 NRND TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5508B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 15-Apr-2017 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 4040282/C 11/96 Gage Plane 0,17 0,27 7,50 TYP SQ 9,80 1,05 0,95 11,80 12,20 1,20 MAX 10,20 SQ 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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