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AFE7950-SP TI | Alldatasheet

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AFE7950-x 4T6R RF Sampling AFE with 12GSPS DACs and 3GSPS ADCs

1 Features

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Radiation hardness assured AFE7950-SP: – Single-event latch up (SEL): 70MeV-cm2/mg – RLAT Total ionizing dose (TID): 100krad (Si)
Radiation tolerant AFE7950-SEP: – Single-event latch up (SEL): 43MeV-cm2/mg – RLAT Total ionizing dose (TID): 30krad (Si)
Four RF sampling 12GSPS TX DACs
Six RF sampling 3GSPS RX ADCs
Maximum RF signal bandwidth: 1200MHz (or 2400MHz for 2TX)
RF frequency range: – TX: 600MHz to 12GHz – RX: 5MHz to 12GHz
Digital Step Attenuators (DSA): – TX: 40dB range, 0.125dB steps – RX or FB: 25dB range, 0.5dB steps
Single or dual-band DUC or DDCs for TX and RX
SerDes data interface: – 8 SerDes transceivers up to 24.75Gbps – JESD204B/C subclass 1 compatible
Package: 17mm × 17mm FCBGA, 0.8mm pitch
Screening: – One fabrication, assembly, and test site – Product traceability – Extended product life cycle – Extended product change notification – Vendor item drawing – Radiation lot acceptance Test (RLAT) (AFE7950-Sx only) – Meets ASTM E595 out gassing specification (AFE7950-Sx only) – Production burn-in (AFE7950-SP only)

2 Applications

Satellite communications payload downlink
Satellite telemetry payload downlink

3 Description

The AFE7950-x is a high performance, wide bandwidth multi-channel transceiver, integrating four RF sampling transmitter chains, four RF sampling receiver chains and two RF sampling feedback chains (six RF sampling ADCs total). With operation up to 12GHz, this device enables direct RF sampling in the L, S, C and X-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems. The TX signal paths support interpolation and digital up conversion options that deliver up to 1200MHz of signal bandwidth for four TX or 2400MHz for two TX. The output of the DUCs drives a 12GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2 nd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40dB range and 1dB analog and 0.125dB digital steps. Each receiver chain includes a 25dB range Digital Step Attenuator (DSA), followed by a 3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths (1200MHz BW each). Device Information PART NUMBER GRADE PACKAGE SIZE(1) (2) AFE7950-SP Radiation-hardness- assured space (RHA) 17mm x 17mm plastic substrate FC-BGA

400 SnPb balls

0.8mm pitch AFE7950-SEP (3) Radiation-tolerant Space Enhanced Product AFE7950-EP (3) Enhanced Product (1) For more information, see Section 7. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Product preview AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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5.1 Receiving Notification of Documentation Updates.. 119

7 Mechanical, Packaging, and Orderable Information 119

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply Voltage Range DVDD0P9, VDDT0P9 –0.3 1.2 V VDD1P2RX, VDD1P2TXCLK, VDD1P2TXENC, VDD1P2PLL, VDD1P2PLLCLKREF, VDD1P2FB, VDD1P2FBCML, VDD1P2RXCML –0.3 1.4 V VDD1P8RX, VDD1P8RXCLK, VDD1P8TX, VDD1P8TXDAC, VDD1P8TXENC, VDD1P8PLL, VDD1P8PLLVCO, VDD1P8FB, VDD1P8FBCLK, VDD1P8GPIO, VDDA1P8 –0.5 2.1 V Pin Volatge Range {1/2/3/4}RXIN+/- –0.5 VDDRX1P8+0.3 V 1FBIN+/-, 2FB+/- –0.5 VDDFB1P8+0.3 V {1/2/3/4}TXOUT+/- –0.5 VDDTX1P8+0.3 V REFCLK+/-, SYSREF+/- –0.3 1.4 V GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, BISTB0, BISTB1 –0.5 VDD1P8GPIO + 0.3 V IFORCE, VSENSE –0.3 VDDCLK1P8 + 0.3 V SRDAMUX1, SRDAMUX2 –0.3 VDDA1P8+0.3 V Peak Input Current any input 20 mA TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) 1000 V Charged device model (CDM), per ANSI/ESDA/ JEDEC JS-002, all pins 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT DVDD0P9, VDDT0P9 Supply voltage 0.9V 0.9 0.925 0.95 V VDD1P2{RX/TXCLK/TXENC/FB/PLL/ PLLCLKREF/FBCML/RXCML} Supply voltage 1.2V 1.15 1.2 1.25 V VDD1P8{RX/RXCLK/TX/TXDAC/ TXENC/PLL/PLLVCO/FB/FBCLK/ GPIO}, VDDA1P8 Supply voltage 1.8V 1.75 1.8 1.85 V TA Ambient temperature –45 85 °C TJ Operating Junction Temperature 105 °C

4.4 Thermal Information

THERMAL METRIC(1) FC-BGA UNIT

400 PINS

RθJA Junction-to-ambient thermal resistance 15.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.44 °C/W RθJB Junction-to-board thermal resistance 4.8 °C/W ΨJB Junction-to-board characterization parameter 4.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: AFE7950-SP

4.5 Transmitter Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist, nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DACRES DAC resolution 14 bits FDAC DAC Sample Rate 9 12 GSPS fRFout_MIN RF output frequency range Requires PCB matching based on frequency range 600 MHz fRFout_MAX RF output frequency range Requires PCB matching based on frequency range 12000 MHz Pmax_FS Max Full Scale Output Power, max gain 1 tone, at device pins fout = 850 MHz, fDAC = 5898.24 MSPS, -0.5dBFS 4.2 dBm fout = 1800 MHz, fDAC = 5898.24 MSPS, -0.5dBFS 4.6 dBm fout = 2600 MHz, fDAC = 8847.36 MSPS, -0.5dBFS 4.0 dBm fout = 3500 MHz, -0.5dBFS 3.9 dBm fout = 4900 MHz, -0.5dBFS 3.1 dBm fout = 3500 MHz, fDAC = 5898.24 MSPS, -0.5dBFS, straight mode 1.0 dBm fout = 4900 MHz, fDAC = 5898.24 MSPS, -0.5dBFS, straight mode 0.1 dBm fout = 4900 MHz, fDAC = 8847.36 MSPS, -0.5dBFS, straight mode -0.7 dBm fout = 8100 MHz, -0.1dBFS, mixed mode -2.8 dBm fout = 9600 MHz, -0.1dBFS, mixed mode -4.3 dBm RTERM Output termination resistor Default setting 50 Ω ATTrange DSA Attenuation range 40 dB ATTstep DSA Analog Attenuation step 1.0 dB DSA Attenuation step accuracy (DNL) 0 < Atten < 40dB, before calibration ±0.2 dB DSA Attenuation step accuracy (DNL) 0 < Atten < 40dB, after calibration ±0.1 dB ATTphase-err DSA Gain Steps Phase accuracy, any 8dB range fout = 850MHz(2) ±1 deg fout = 1800MHz(2) ±1 deg fout =2600MHz(2) ±1 deg fout = 3500MHz(2) ±1 fout = 4900MHz(2) ±1 deg fout = 8100MHz(2) ±2 deg fout = 9600MHz(2) ±2 deg Gflat Gain flatness any 20MHz 0.1 dB 600MHz BW, Fout < 4.9G 1.2 AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist, nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IMD3 3rd Order Intermodulation distortion, 2 tones at fIF±10 MHz fout = 850MHz, -7dBFS each tone -66 dBc fout = 1800MHz, -7dBFS each tone -63 dBc fout = 2600MHz, -7dBFS each tone -62 dBc fout = 3500MHz, -7dBFS each tone -61 dBc fout = 4900MHz, -7dBFS each tone -57 dBc fout = 8100MHz, -7dBFS each tone -55 dBc fout = 9600MHz, -7dBFS each tone -52 dBc fout = 850MHz, -13dBFS each tone -74 dBc fout = 1800MHz, -13dBFS each tone -71 dBc fout = 2501MHz, -12dBFS each tone -67 -60 dBc fout = 2600MHz, -13dBFS each tone -73 dBc fout = 3500MHz, -13dBFS each tone -72 dBc fout = 4900MHz, -13dBFS each tone -68 dBc fout = 8100MHz, -13dBFS each tone -64 dBc fout = 9600MHz, -13dBFS each tone -68 dBc SFDR Spurious Free Dynamic Range (within Nyquist zone) fout = 850 MHz 51 dBc fout = 1800 MHz 52 dBc fout = 2600 MHz 42 dBc fout = 3500 MHz 44 dBc fout= 4900 MHz 46 dBc fS/2 - fOUT Interleaving Image fDAC = 5898.24MSPS, interleave mode -52 dBc fDAC = 8847.36 MSPS, interleave mode -46 dBc fDAC = 11796.48MSPS, interleave mode -42 dBc HD2 2nd Harmonic Distortion (within Nyquist zone) fout = 850 MHz -49 dBc fout = 1800 MHz -53 dBc fout = 2600 MHz -50 dBc fout = 3500 MHz -48 dBc fout= 4900 MHz -47 dBc fout= 8100 MHz -50 dBc fout= 9600 MHz -53 dBc fout = 850 MHz, AOUT=-12dBFS -60 dBc fout = 1800 MHz, AOUT=-12dBFS -64 dBc fout = 2600 MHz, AOUT=-12dBFS -45 dBc fout = 3500 MHz, AOUT=-12dBFS -57 dBc fout= 4900 MHz, AOUT=-12dBFS -58 dBc fout= 8100 MHz, AOUT=-12dBFS -60 dBc fout= 9600 MHz, AOUT=-12dBFS -62 dBc www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist, nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HD3 3rd Harmonic Distortion (within Nyquist zone) fout = 850 MHz -62 dBc fout = 1800 MHz -55 dBc fout = 2600 MHz -57 dBc fout = 3500 MHz -60 dBc fout= 4900 MHz -54 dBc fout= 8100 MHz -54 dBc fout= 9600 MHz -56 dBc fout = 850 MHz, AOUT=-12dBFS -80 dBc fout = 1800 MHz, AOUT=-12dBFS -79 dBc fout = 2600 MHz, AOUT=-12dBFS -77 dBc fout = 3500 MHz, AOUT=-12dBFS -77 dBc fout= 4900 MHz, AOUT=-12dBFS -78 dBc fout= 8100 MHz, AOUT=-12dBFS -82 dBc fout= 9600 MHz, AOUT=-12dBFS -80 dBc HDn, n >= 4 Harmonic Distortion n >= 4 (within Nyquist zone) fout = 850 MHz -81 dBc fout = 1800 MHz -88 dBc fout = 2600 MHz -86 dBc fout = 3500 MHz -79 dBc fout= 4900 MHz -86 dBc fout= 8100 MHz -87 dBc fout= 9600 MHz -85 dBc fout = 850 MHz, AOUT=-12dBFS -93 dBc fout = 1800 MHz, AOUT=-12dBFS -98 dBc fout = 2600 MHz, AOUT=-12dBFS -84 dBc fout = 3500 MHz, AOUT=-12dBFS -87 dBc fout= 4900 MHz, AOUT=-12dBFS -87 dBc fout= 8100 MHz, AOUT=-12dBFS -87 dBc fout= 9600 MHz, AOUT=-12dBFS -87 dBc SFDR +/- 250 MHz Spurious Free Dynamic Range within +/- 250 MHz fout = 850 MHz 69 dBc fout = 1800 MHz 79 dBc fout = 2600 MHz 77 dBc fout = 3500 MHz 75 dBc fout= 4900 MHz 76 dBc fout= 8100 MHz 61 dBc fout= 9600 MHz 64 dBc fS/4 Fixed Spur fDAC = 5898.24MSPS -64 dBFS fDAC = 8847.36MSPS -75 dBFS fDAC = 11796.48MSPS -67 dBFS fS/2 Fixed Spur fDAC = 5898.24MSPS -49 dBFS fDAC = 8847.36MSPS -48 dBFS fDAC = 11796.48 MSPS -48 dBFS AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist, nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3*fS/4 Fixed Spur 2nd Nyquist, fDAC = 5898.24MSPS -76 dBFS 2nd Nyquist, fDAC = 8847.36MSPS -89 dBFS 2nd Nyquist, fDAC = 11796.48MSPS -63 dBFS ACPR1xcarr ACPR - 1 carrier, LTE 20MHz E-TM1.1 carrier fout = 0.85 GHz Atten=0dB, Pout=-13dBFs -68.5 dBc Atten=20dB,Pout=-13dBFs -67.2 dBc Atten=28dB,Pout=-13dBFs -64.5 dBc Atten=39dB, Pout=-13dBFs -53.9 dBc ACPR1xcarr ACPR - 1 carrier, LTE 20MHz E-TM1.1 carrier fout = 1.8425 GHz Atten=0dB,Pout=-13dBFs -70.7 dBc Atten=20dB, Pout=-13dBFs -68.3 dBc Atten=28dB, Pout=-13dBFs -62.9 dBc Atten=39dB, Pout=-13dBFs -52.0 dBc ACPR1xcarr ACPR - 1 carrier, LTE 20MHz E-TM1.1 carrier fout = 2.6 GHz Atten=0dB, Pout=-13dBFs -71 dBc Atten=20dB, Pout=-13dBFs -68 dBc Atten=28dB, Pout=-13dBFs -62 dBc Atten=39dB, Pout=-13dBFs -51.3 dBc ACPR1xcarr ACPR - 1 carrier, LTE 20MHz E-TM1.1 carrier fout = 3.5 GHz Atten=0dB, Pout=-13dBFs -70 dBc Atten=20dB, Pout=-13dBFs -67 dBc Atten=28dB, Pout=-13dBFs -60 dBc Atten=39dB, Pout=-13dBFs -49.8 dBc ACPR1xcarr ACPR - 1 carrier, LTE 20MHz E-TM1.1 carrier fout = 4.9 GHz Atten=0dB, Pout=-13dBFs -68.8 dBc Atten=20dB, Pout=-13dBFs -65.9 dBc Atten=28dB, Pout=-13dBFs -60.6 dBc Atten=39dB, Pout=-13dBFs -49.5 dBc ACPR1xcarr ACPR - 1 carrier, NR 100MHz E- TM1.1 carrier fout = 2.6 GHz Atten=0dB, Pout=-13dBFs -65 dBc Atten=20dB, Pout=-13dBFs -62 dBc Atten=20dB, Pout=-13dBFs -55 dBc Atten=39dB,Pout=-13dBFs -44.3 dBc ACPR1xcarr ACPR - 1 carrier, NR 100MHz E- TM1.1 carrier fout = 3.5 GHz Atten=0dB, Pout=-13dBFs -64 dBc Atten=20dB, Pout=-13dBFs -59 dBc Atten=28dB, Pout=-13dBFs -52 dBc Atten=39dB, Pout=-13dBFs -41.1 dBc ACPR1xcarr ACPR - 1 carrier, NR 100MHz E- TM1.1 carrier fout = 4.9 GHz Atten=0dB, Pout=-13dBFs -64.1 dBc Atten=20dB, Pout=-13dBFs -60.4 dBc Atten=28dB, Pout=-13dBFs -53.5 dBc Atten=39dB, Pout=-13dBFs -42.5 dBc ACPR1xcarr ACPR - 1 carrier, NR 100MHz E- TM1.1 carrier fout = 8.1 GHz Atten=0dB, Pout=-13dBFs -58 dBc Atten=20dB, Pout=-13dBFs -53 dBc Atten=28dB, Pout=-13dBFs -46 dBc Atten=39dB, Pout=-13dBFs -36 dBc ACPR1xcarr ACPR - 1 carrier, NR 100MHz E- TM1.1 carrier fout = 9.6 GHz Atten=0dB, Pout=-13dBFs -57 dBc Atten=20dB, Pout=-13dBFs -50 dBc Atten=28dB, Pout=-13dBFs -42 dBc Atten=39dB, Pout=-13dBFs -31 dBc www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist, nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EVM Error Vector Magnitude, 1x 20MHz E- TM3.1/3.1a, no ref. clock noise Fout =0.85 GHz, POUT=-13dBFs 0.16 % Fout =1.8425 GHz, POUT=-13dBFs 0.29 % Fout =2.6 GHz, POUT=-13dBFs 0.28 % Fout =3.5 GHz, POUT=-13dBFs 0.38 % Fout =4.9 GHz, POUT=-13dBFs 0.43 % NSDdBFS Noise Spectral Density 20MHz offset fOUT = 0.85 GHz Atten=0dB, fDAC = 5898.24MSPS, Pout=-13dBFs -156 dBFS/ Hz Atten=20dB, fDAC = 5898.24MSPS, Pout=-13dBFs -151 dBFS/ Hz Atten=28dB, fDAC = 5898.24MSPS, Pout=-13dBFs -145 dBFS/ Hz Atten=39dB, fDAC = 5898.24MSPS, Pout=-13dBFs -134 dBFS/ Hz NSDdBFS Noise Spectral Density 20MHz offset fOUT = 1.8 GHz Atten=0dB, fDAC = 5898.24MSPS, Pout=-13dBFs -158 dBFS/ Hz Atten=20dB, fDAC = 5898.24MSPS, Pout=-13dBFs -152 dBFS/ Hz Atten=28dB, fDAC = 5898.24MSPS, Pout=-13dBFs -146 dBFS/ Hz Atten=39dB, fDAC = 5898.24MSPS, Pout=-13dBFs -135 dBFS/ Hz NSDdBFS Noise Spectral Density 20MHz offset fOUT = 2.6 GHz Atten=0dB, fDAC = 8847.36MSPS, Pout=-13dBFs -157 dBFS/ Hz Atten=20dB, fDAC = 8847.36MSPS, Pout=-13dBFs -151 dBFS/ Hz Atten=28dB, fDAC = 8847.36MSPS, Pout=-13dBFs -144 dBFS/ Hz Atten=39dB, fDAC = 8847.36MSPS, Pout=-13dBFs -133 dBFS/ Hz NSDdBFS Noise Spectral Density 20MHz offset Fout =3.5 GHz Atten=0dB, Pout=-13dBFs -158 dBFS/ Hz Atten=20dB, Pout=-13dBFs -150 dBFS/ Hz Atten=28dB, Pout=-13dBFs -143 dBFS/ Hz Atten=39dB, Pout=-13dBFs -132 dBFS/ Hz NSDdBFS Noise Spectral Density 20MHz offset Fout =4.9 GHz Atten=0dB, Pout=-13dBFs -155 dBFS/ Hz Atten=20dB, Pout=-13dBFs -148 dBFS/ Hz Atten=28dB, Pout=-13dBFs -141 dBFS/ Hz Atten=39dB, Pout=-13dBFs -130 dBFS/ Hz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist, nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSDdBFS Noise Spectral Density 50MHz offset Fout =8.1 GHz Atten=0dB, Pout=-13dBFs -149 dBFS/ Hz Atten=20dB, Pout=-13dBFs -147 dBFS/ Hz Atten=28dB, Pout=-13dBFs -141 dBFS/ Hz Atten=39dB, Pout=-13dBFs -130 dBFS/ Hz NSDdBFS Noise Spectral Density 50MHz offset Fout =9.6 GHz Atten=0dB, Pout=-13dBFs -148 dBFS/ Hz Atten=20dB, Pout=-13dBFs -144 dBFS/ Hz Atten=28dB, Pout=-13dBFs -137 dBFS/ Hz Atten=39dB, Pout=-13dBFs -126 dBFS/ Hz S22 Output Return Loss, <6GHz, +/- fc * 10% with matching -17 dB Output Return Loss, >8GHz, +/- fc * 10% with matching -13 dB Isolation Near Channel: 1TXOUT to 2TXOUT or 3TXOUT to 4TXOUT(1) fout = 900 MHz, fDAC = 8847.36MSPS, straight mode -49 dB fout = 1850 MHz, fDAC = 8847.36MSPS, straight mode -59 dB fout = 2600 MHz, fDAC = 8847.36MSPS, straight mode -64 dB fout = 3500 MHz, fDAC = 8847.36MSPS, straight mode -66 dB fout= 4900 MHz, fDAC = 8847.36MSPS, straight mode -60 dB fout = 900 MHz, fDAC = 8847.36MSPS, straight mode -90 dB fout = 1850 MHz, fDAC = 8847.36MSPS, straight mode -91 dB fout = 2600 MHz, fDAC = 8847.36MSPS, straight mode -93 dB fout = 3500 MHz, fDAC = 8847.36MSPS, straight mode -94 dB fout= 4900 MHz, fDAC = 8847.36MSPS, straight mode -83 dB fout= 8100 MHz -47 dB fout= 9600 MHz -60 dB Far Channel: 1/2TXOUT to 3/4TXOUT fout= 8100 MHz -80 dB www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist, nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PNTXADD Additive Phase Noise External Clock Mode(3) fout = 9.6GHz, fOFFSET = 100Hz -88 dBc/Hz fout = 9.6GHz, fOFFSET = 1kHz -102 dBc/Hz fout = 9.6GHz, fOFFSET = 10kHz -110 dBc/Hz fout = 9.6GHz, fOFFSET = 100kHz -123 dBc/Hz fout = 9.6GHz, fOFFSET = 1MHz -136 dBc/Hz fout = 9.6GHz, fOFFSET = 10MHz -143 dBc/Hz fout = 9.6GHz, fOFFSET = 100MHz -146 dBc/Hz (1) Measured with differential 50 ohm across TxP/M. The DC bias to 1.8V to each TxP/M at each pin remains and is not removed. Other external components on the TX paths are disconnected. (2) After DSA calibration procedure (3) Single side band, input clock phase noise subtracted. AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.6 RF ADC Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADCRES ADC resolution 14 bits FADC ADC Sample Rate 1.5 3 GSPS FRFin_MAX RF input frequency range Requires PCB matching based on frequency range 12000 MHz FRFin_MIN RF input frequency range Requires PCB matching based on frequency range 5 MHz PFS_CW,min Min Full scale input power, at device pins (1) fIN = 830 MHz, DSA=0dB -2.9 dBm fIN = 1760 MHz, DSA=0dB -2.8 dBm fIN = 2610 MHz, DSA=0dB -1.8 dBm fIN = 3610 MHz, DSA=0dB -0.4 dBm fIN = 4910 MHz, DSA=0dB 0.1 dBm fIN = 8150 MHz, DSA=0dB 2.1 dBm fIN = 9610 MHz, DSA=0dB 4.3 dBm PFS_CW,MAX MAX Full scale input power - reliability limited, at device pins fIN = 830 MHz, DSA = 20dB 16.7 dBm fIN = 1760 MHz, DSA = 20dB 17.0 dBm fIN = 2610 MHz, DSA = 20dB 18 dBm fIN = 3610 MHz, DSA = 20dB 18.5 dBm fIN = 4910 MHz, DSA = 20dB 19.3 dBm fIN = 8150 MHz, DSA = 20dB 21.3 dBm fIN = 9610 MHz, DSA = 20dB 23.5 dBm S11 Input Return Loss with matching network -12 dB ATTrange DSA Attenuation range 25 dB ATTstep DSA Attenuation step 0.5 dB DSA Attenuation step accuracy Delta=Gatt(X)-Gatt(X-1), Fin=3610MHz, after calibration ±0.1 dB DSA Gain Steps Phase accuracy any 8dB range Fin=3610MHz, after calibration ±0.9 deg DSA Gain Steps Phase accuracy any 8dB range Fin=4910MHz, after calibration ±1.8 deg www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSD Noise Density (small signal) fIN = 830 MHz, DSA = 3dB(3) -155.2 dBFS/Hz fIN = 1760 MHz, DSA = 3dB(3) -155.0 dBFS/Hz fIN = 2610 MHz, DSA = 3dB(3) -154.4 dBFS/Hz fIN = 3610 MHz, DSA = 3dB(3) -154.1 dBFS/Hz fIN = 4910 MHz, DSA = 3dB(3) -155.1 dBFS/Hz fIN = 8150 MHz, DSA = 3dB(3) -150 dBFS/Hz fIN = 9610 MHz, DSA = 3dB(3) -151 dBFS/Hz fIN = 830 MHz, 3<=Atten<=22 -156.0 dBFS/Hz fIN = 1760 MHz, 3<=Atten<=25 -155.8 dBFS/Hz fIN = 2610 MHz, 3<=Atten<=25 -155.7 dBFS/Hz fIN = 3610 MHz, 3<=Atten<=25 -155.4 dBFS/Hz fIN = 4910 MHz, 3<=Atten<=25 -155.8 dBFS/Hz fIN = 8150 MHz, 3<=Atten<=25 -152.5 dBFS/Hz fIN = 9610 MHz, 3<=Atten<=25 -152.5 dBFS/Hz NFmin Noise Figure min DSA Atten=0 - 3dB fIN = 830 MHz 19.1 dB fIN = 1760 MHz 19.0 dB fIN = 2610 MHz 20.9 dB fIN = 3610 MHz 22.8 dB fIN = 4910 MHz 22.4 dB fIN = 8150 MHz 27.3 dB fIN = 9610 MHz 30 dB NF Noise Figure DSA Atten=4dB fIN = 830 MHz(4) 20.0 dB fIN = 1760 MHz(4) 20.6 dB fIN = 2610 MHz(4) 21.9 dB fIN = 3610 MHz(4) 23.5 dB fIN = 4910 MHz(4) 22.3 dB fIN = 8150 MHz(4) 27.9 dB fIN = 9610 MHz(4) 30.7 dB NFmax Noise Figure DSA Atten=20dB fIN = 830 MHz 34.7 dB fIN = 1760 MHz 35.2 dB fIN = 2610 MHz 36.0 dB fIN = 3610 MHz 37.3 dB fIN = 4910 MHz 37.6 dB fIN = 8150 MHz 42.8 dB fIN = 9610 MHz 45 dB AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IMD3 3rd order intermodulation 2 tones at at fIN ± 10MHz -7dBFS each tone fIN = 840 MHz, 3<=Atten<=12 -82 dBc fIN = 1770 MHz, 3<=Atten<=12 -84 dBc fIN = 2610 MHz, 3<=Atten<=12 -74 dBc fIN = 3610 MHz, 3<=Atten<=12 -77 dBc fIN = 4920 MHz, 3<=Atten<=12 -76 dBc fIN = 8150 MHz, 3<=Atten<=12, 25MHz tone spacing -55 dBc fIN = 9610 MHz, 3<=Atten<=12, 25MHz tone spacing -60 dBc SFDR Spurious Free Dynamic Range within output bandwidth, AIN = -3 dBFS fIN = 830 MHz 88 dBFS fIN = 1760 MHz 81 dBFS fIN = 2610 MHz 88 dBFS fIN = 3610 MHz 84 dBFS fIN = 4910 MHz 79 dBFS fIN = 8150 MHz 78 dBFS fIN = 9610 MHz 71 dBFS HD2 2nd Harmonic Distortion AIN = -3 dBFS(2) fIN = 830 MHz -86 dBFS fIN = 1760 MHz -91 dBFS fIN = 2610 MHz -88 dBFS fIN = 3610 MHz -87 dBFS fIN = 4910 MHz -84 dBFS fIN = 8150 MHz -70 dBFS fIN = 9610 MHz -70 dBFS HD3 3rd Harmonic Distortion AIN = -3 dBFS fIN = 830 MHz -80 dBFS fIN = 1760 MHz -85 dBFS fIN = 2501 MHz -80 -58 dBFS fIN = 2610 MHz -85 dBFS fIN = 3610 MHz -78 dBFS fIN = 4910 MHz -75 dBFS fIN = 8150 MHz -70 dBFS fIN = 9610 MHz -70 dBFS HDn, n>3 SFDR excl. HD2 and HD3 AIN = -3 dBFS fIN = 830 MHz -88 dBFS fIN = 1760 MHz -81 dBFS fIN = 2610 MHz -88 dBFS fIN = 3610 MHz -84 dBFS fIN = 4910 MHz -82 dBFS fIN = 8150 MHz -78 dBFS fIN = 9610 MHz -78 dBFS www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SFDR Spurious Free Dynamic Range AIN = -13 dBFS 0<=Atten<=16 fIN = 830 MHz 89 dBFS fIN = 1760 MHz 89 dBFS fIN = 2610 MHz 95 dBFS fIN = 3610 MHz 90 dBFS fIN = 4910 MHz 90 dBFS fIN = 8150 MHz 83 dBFS fIN = 9610 MHz 80 dBFS HD2 2nd Harmonic Distortion AIN = -13 dBFS 0<=Atten<=16 fIN = 830 MHz, with board trim -79 dBFS fIN = 1760 MHz, with board trim -102 dBFS fIN = 2610 MHz, with board trim -100 dBFS fIN = 3610 MHz, with board trim -101 dBFS fIN = 4910 MHz, with board trim -99 dBFS fIN = 8150 MHz, with board trim -107 dBFS fIN = 9610 MHz, with board trim -107 dBFS HD3 3rd Harmonic Distortion AIN = -13 dBFS 0<=Atten<=16 fIN = 830 MHz -95 dBFS fIN = 1760 MHz -95 dBFS fIN = 2610 MHz -98 dBFS fIN = 3610 MHz -97 dBFS fIN = 4910 MHz -94 dBFS fIN = 8150 MHz -100 dBFS fIN = 9610 MHz -102 dBFS HDn, n>3 SFDR excl. HD2 and HD3 AIN = -13 dBFS 0<=Atten<=16 fIN = 830 MHz -89 dBFS fIN = 1760 MHz -89 dBFS fIN = 2610 MHz -95 dBFS fIN = 3610 MHz -90 dBFS fIN = 4910 MHz -90 dBFS fIN = 8150 MHz -83 dBFS fIN = 9610 MHz -80 dBFS RX-RX Isolation Near Channel: 1RXIN to 2RXIN 3RXIN to 4RXIN fIN = 830 MHz -77 dBc fIN = 1760 MHz -71 dBc fIN = 2610 MHz -74 dBc fIN = 3610 MHz -77 dBc fIN = 4910 MHz -65 dBc fIN = 8150 MHz -64 dBc fIN = 9610 MHz -60 dBc TX-FB Isolation Near Channel: 2TXOUT to 1FBIN 4TXOUT to 2FBIN fIN = 830 MHz -84 dBc fIN = 1760 MHz -88 dBc fIN = 2610 MHz -85 dBc fIN = 3610 MHz -75 dBc fIN = 4910 MHz -82 dBc fIN = 8150 MHz -71 dBc fIN = 9610 MHz -69 dBc AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX-RX Isolation Far Channel: 2TXOUT to 1RXIN 4TXOUT to 3RXIN fIN = 830 MHz -86 dBc fIN = 1760 MHz -87 dBc fIN = 2610 MHz -91 dBc fIN = 3610 MHz -83 dBc fIN = 4910 MHz -82 dBc fIN = 8150 MHz -68 dBc fIN = 9610 MHz -68 dBc (1) The input fullscale at minimum attenuation can be reduce by adding a digital gain range to the DSA, extending the useful range of the DSA. The noise figure remains constant over the digital gain range. (2) NLE correction of HD2 (3) From DSA = 3dB down to 0dB, NSD increases 1dB per DSA dB (4) NF increase 1dB per DSA 1dB above DSA = 3dB www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: AFE7950-SP

4.7 PLL/VCO/Clock Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency 491.52MHz (unless otherwise noted), fDAC = fVCO, fOUT = fDAC/4, normalized to fVCO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fVCO1 VCO1 min frequency 7.2 GHz VCO1 max frequency 7.68 GHz fVCO2 VCO2 min frequency 8.8 GHz VCO2 max frequency 9.1 GHz fVCO3 VCO3 min frequency 9.7 GHz VCO3 max frequency 10.24 GHz fVCO4 VCO4 min frequency 11.6 GHz VCO4 max frequency 12.08 GHz DIVDAC DAC sample rate divider 1, 2 or 3 DIVFBAD C ADC sample rate divider from DAC sample rate 1, 2, 3, 4, 6 or 8 DIVRXAD C ADC sample rate divider 1, 2, 3, 4, 6 or 8 PNVCO Closed Loop Phase Noise FPLL = 11.79848 GHz FREF=491.52MHz 600kHz -113 dBc/Hz 800kHz -116 dBc/Hz 1MHz -119 dBc/Hz 1.8MHz -125 dBc/Hz 5MHz -133 dBc/Hz 50MHz –141 dBc/Hz Closed Loop Phase Noise FPLL=8.84736 GHz FREF=491.52MHz 600kHz -114 dBc/Hz 800kHz –118 dBc/Hz 1MHz –120 dBc/Hz 1.8MHz –127 dBc/Hz 5MHz –135 dBc/Hz 50MHz –142 dBc/Hz Closed Loop Phase Noise FPLL= 9.8403 GHz FREF=491.52MHz 600kHz –113 dBc/Hz 800kHz –116 dBc/Hz 1MHz –119 dBc/Hz 1.8MHz –125 dBc/Hz 5MHz –134 dBc/Hz 50MHz –140 dBc/Hz Closed Loop Phase Noise FPLL= 7.86432GHz FREF=491.52MHz 600kHz –116 dBc/Hz 800kHz –119 dBc/Hz 1MHz –122 dBc/Hz 1.8MHz –127 dBc/Hz 5MHz –136 dBc/Hz 50MHz –143 dBc/Hz Frms Clock PLL integrated phase error(1) fPLL=11.79848 GHz, [1KHz, 100MHz] -43.4 dBc/Hz fPLL=8.8536 GHz, [1KHz, 100MHz] -47.6 dBc/Hz fPLL=9.8304 GHz, [1KHz, 100MHz] -46.2 dBc/Hz fPFD PFD frequency 100 500 MHz FREF Input clock minimum frequency 0.1 GHz FREF Input Clock maximum frequency 12 GHz VCLKMIN Input clock minimum level 0.6 Vppdiff AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency 491.52MHz (unless otherwise noted), fDAC = fVCO, fOUT = fDAC/4, normalized to fVCO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCLKMAX Input Clock maximum level 1.8 Vppdiff PNpll_flat Normalized PLL flat Noise fVCO = 11796.48MHz –226.5 dBc/Hz Coupling AC Coupling Only REFCLK input impedance(2) Parallel resistance 100 Ω Parallel capacitance 0.5 pF (1) Single Sideband, not including the reference clock contribution (2) Refer to S11 data available from TI for impedance vs frequency www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: AFE7950-SP

4.8 Digital Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CML SerDes Inputs [8:1]SRX+/- VSRDIFF SerDes Receiver Minimum Input Amplitude 100 mVpp VSRDIFF SerDes Receiver Maximum Input Amplitude 1200 mVpp VSRCOM SerDes Minimum Input Common Mode 0.5 V VSRCOM SerDes Maximum Input Common Mode 0.6 V ZSRdiff SerDes Internal Differential Termination(1) 115 Ω FSerDes SerDes Bit Rate Minimum full rate mode 19 Gbps FSerDes SerDes Bit Rate Maximum full rate mode 24.75 Gbps FSerDes SerDes Bit Rate Minimum half rate mode 9.5 Gbps FSerDes SerDes Bit Rate Maximum half rate mode 16.25 Gbps FSerDes SerDes Bit Rate Minimum quarter rate mode 4.75 Gbps FSerDes SerDes Bit Rate Maximum quarter rate mode 8.125 Gbps Insertion Loss Tolerance(2) Serdes supply = 1.8V 25 dB TJ Total Jitter Tolerance 0.42 UI CML SerDes Outputs [8:1]STX+/- VSTDIFF SerDes Transmitter Minimum Output Amplitude differential 500 mVpp VSTDIFF SerDes Transmitter Maximum Output Amplitude differential 1000 mVpp VSTCOM SerDes Output Minimum Common Mode 0.5 V VSTCOM SerDes Output Common Mode 0.6 V ZSTdiff SerDes Output Impedance 115 Ω TRF Output rise and fall time 20-80% 8 ps TEQS Equalization range 7 dB TTJ Output total jitter 0.21 UI CMOS I/O: GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, BISTB0, BISTB1 VIH High-Level Input Voltage 0.6×VDD1 P8GPIO V VIL Low-Level Input Voltage 0.4×VDD1 P8GPIO V VOH High-Level Ouput Voltage VDD1P8G PIO–0.2 V VOL Low-Level Output Voltage 0.2 V Differential Inputs: SYSREF+/- Mode A FSYSREFMAX SYSREF Input Frequency Maximum 40 MHz VSWINGSRMAX SYSREF Input Swing Maximum 1.8 Vppdiff(3) VSWINGSRMIN SYSREF Input Swing Minimum fREF < 500MHz 0.3 Vppdiff(3) VSWINGSRMIN SYSREF Input Swing Minimum fREF > 500MHz 0.6 Vppdiff(3) VCOMSRMAX SYSREF Input Common Mode Voltage Maximum 0.8 V VCOMSRMIN SYSREF Input Common Mode Voltage Minimum 0.6 V ZT Input termination differential 108 (1) Ω AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CL Input capacitance Each pin to GND 0.5 pF LVDS Inputs: 0SYNCIN+/- and 1SYNCIN+/- VICOM Input Common Voltage 1.2 V VID Differential Input Voltage swing 450 mVppdiff(3) ZT Input termination differential 100 Ω LVDS Outputs: 0SYNCOUT+/- and 1SYNCOUT+/- VOCOM Output Common Voltage 1.2 V VOD Differential Output Voltage swing 355 mVppdiff(3) (1) Default setting. SYSREF termination is programmable between nominally 100Ω, 150Ω and 300Ω (2) Loss tolerance is bump to bump from STX to SRX (3) Vppdiff is the difference between the maximum differential voltage (positive value) and minimum differential voltage (negative value).

4.9 Power Supply Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 1: 4T2F - FDD FB 100% on, no RX TX/FB Rate: 491.52 Msps Single Band: 12x Int, FB 6x Dec fDAC = 5898.24 SPS fADC = 2949.12MSPS fTX = 1.85 GHz 64/66 coding, 16.22Gbps TX: 4-8-4-1, FB: 2-4-4-1 948.2 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 533.7 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 77.3 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 299.4 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 804.5 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 49.1 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2041.3 mA Pdiss Power Dissipation 6027.1 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 2: 4T4R - TDD 1F shared with RX TX 75%, RX 25%, FB 75% Dual Band: 12x Int, FB 6x Dec, RX 24x Dec TX/FB Rate 491.52 Msps RX Rate 122.88 Msps fDAC = 8847.36MSPS fADC = 2949.12MSPS fOUT=fIN= 1.9, 2.6 GHz 64/66 coding, 16.22Gbps TX: 8-16-4-1, 820.4 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 735.2 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 74.4 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 289.0 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 822.0 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 45.6 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2263.8 mA Pdiss Power Dissipation 6359.2 mW www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 3: 4T4R2F - FDD FB 100% on TX Dual Band: 12x Int, FB 6x Dec RX Dual Band: RX 24x TX/FB Rate 491.52 Msps RX Rate 122.88 Msps fDAC = 11796.48 MSPS fADC = 2949.12 MSPS fTX = 1.85 + 2.15 GHz fRX = 1.75 + 1.88 GHz 64/66 coding, 16.22Gbps TX: 8-16-4-1, 1668.6 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 965.1 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 77.6 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 893.4 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 879.5 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 50.7 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3826.9 mA Pdiss Power Dissipation 10513.0 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 4: 4T4R2F - FDD FB 100% on 7.5 GSPS DAC, 2.5 GSPS ADC Single Band: 15x Int, FB 5x Dec Dual Band: RX 20x TX/FB Rate 491.52 Msps RX Rate 122.88 Msps fDAC = 7372.8 MSPS fADC = 2457.6 MSPS fTX = 1.85 + 2.15 GHz fRX = 1.75 + 1.88 GHz 64/66 coding, 16.22Gbps TX: 1611.5 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 694.5 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 72.8 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 768.5 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 940.5 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 45.5 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3000.5 mA Pdiss Power Dissipation 9087.4 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 5: 4T4R - TDD 1F shared with RX TX 75%, RX 25%, FB 75% Single Band: 12x Int, FB 3x Dec, RX 6x Dec TX/FB Rate = 983.04 Msps RX Rate 491.52 Msps fDAC = 11796.48 MSPS fADC = 2949.12 MSPS fTX = 3.5 GHz fRX =3.5 GHz 64/66 coding, 16.22Gbps TX: 821.8 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 808.5 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 77.4 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 289.5 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 682.0 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 49.0 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2123.3 mA Pdiss Power Dissipation 6209.3 mW AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 7a: TDD 4T1FB (RX iin Standby) TX 9G and FB 3G -16bit: 368.64M; DSA = 6dB, non-interleave mode RX 3G : 368.64M. 16 bit, Standby Serdes: 25gbps) -> 2 lanes for Rx/FB (lane shared) and 2lanes for Tx 658.1 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 431.1 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 75.3 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 189.2 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 1041.1 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 39.0 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2208.7 mA Pdiss Power Dissipation 5607.0 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 7b: TDD 4R (TX in Standby) TX 9G and FB 3G -16bit: 368.64M; DSA = 6dB, , non-interleave mode, Standby RX 3G : 368.64M. 16 bit Serdes: 25gbps) -> 2 lanes for Rx/FB (lane shared) and 2lanes for Tx 789.5 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 471.3 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 73.4 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 599.3 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 169.6 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 39.1 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 1645.3 mA Pdiss Power Dissipation 4851.9 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 7c: TDD 4T4R1FB TX 9G and FB 3G -16bit: 368.64M; DSA = 6dB, , non-interleave mode, 75% on RX 3G : 368.64M. 16 bit 25% on Serdes: 25gbps) -> 2 lanes for Rx/FB (lane shared) and 2lanes for Tx 691.0 mA IVDD1P8 Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 441.2 mA IVDD1P8 Group 3C: VDD1P8PLL + VDD1P8PLLVCO 74.8 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 291.7 mA IVDD1P2 Group 2B: VDD1P2TXCLK + VDD1P2TXENC 823.2 mA IVDD1P2 Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 39.0 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2067.9 mA Pdiss Power Dissipation 5418.2 mW www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 7d: FDD 4T4R1FB TX 9G and FB 3G -16bit: 368.64M; DSA = 6dB, , non-interleave mode, RX 3G : 368.64M. 16 bit Serdes: 25gbps) -> 2 lanes for Rx/FB (lane shared) and 2lanes for Tx 1283.8 mA IVDD1P8 Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 752.0 mA IVDD1P8 Group 3C: VDD1P8PLL + VDD1P8PLLVCO 74.6 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 750.5 mA IVDD1P2 Group 2B: VDD1P2TXCLK + VDD1P2TXENC 1077.6 mA IVDD1P2 Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 47.7 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2695.5 mA Pdiss Power Dissipation 8475.5 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 8: same configuration as mode 7, Sleep Mode. SLEEP pin is pull high. 20.3 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 292.8 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 12.6 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 4.6 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 54.3 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 15.3 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 313.1 mA Pdiss Power Dissipation 956.8 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 9: 4T4R2F - FDD FB 100% on TX Single Band: 24x Int, FB 12x Dec RX Single Band: RX 24x TX/FB Rate 245.76 Msps RX Rate 122.88 Msps fDAC = 5898.24 MSPS fADC = 2949.12 MSPS fTX = 0.85 GHz fRX = 0.8 GHz 8/10 coding, 9.8304Gbps TX: 4-8-4-1, FB: 2-4-4-1, RX: 2-8-8-1 1593.2 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 840.6 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 77.3 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 905.0 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 817.7 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 52.1 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2405.2 mA Pdiss Power Dissipation 8814.3 mW AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 10: 4T4R2F - FDD FB 100% on TX Single Band: 18x Int, FB 6x Dec RX Single Band: RX 12x TX/FB Rate 491.52 Msps RX Rate 245.76 Msps fDAC = 8847.36 MSPS fADC = 2949.12 MSPS fTX = 1.85 GHz fRX = 1.75 GHz 8/10 coding, 9.8304Gbps TX: 8-8-2-1, FB: 4-4-2-1, RX: 4-8-4-1 1626.2 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 976.4 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 74.6 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 902.7 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 1111.9 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 48.0 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3578.9 mA Pdiss Power Dissipation 10515.0 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 11a: TDD 4T1FB (RX in Standby) Single Band: 8x Int, FB 2x Dec, RX uses FB TX/FB/RX Rate = 1474.56 Msps fDAC = 11796.48 MSPS fADC = 2949.12 MSPS fTX = fRX = 8 GHz 64/66 coding, 24.33 Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2 800 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 840 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 73 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 190 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 1440 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 75 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3070 mA Pdiss Power Dissipation 8010 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 11b: TDD 4R (TX in Standby) Single Band: 8x Int, FB 2x Dec, RX uses FB TX/FB/RX Rate = 1474.56 Msps fDAC = 11796.48 MSPS fADC = 2949.12 MSPS fTX = fRX = 8 GHz 64/66 coding, 24.33 Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2 750 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 890 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 72 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 610 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 280 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 72 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2360 mA Pdiss Power Dissipation 6460 mW www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 11c: TDD 4T4R1FB average TX/FB: 75%, RX 25% Single Band: 8x Int, FB 2x Dec, RX uses FB TX/FB/RX Rate = 1474.56 Msps fDAC = 11796.48 MSPS fADC = 2949.12 MSPS fTX = fRX = 8 GHz 64/66 coding, 24.33 Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2 790 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 850 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 73 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 300 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 1150 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 75 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2890 mA Pdiss Power Dissipation 7620 mW IVDD1P8 Group 3A: VDD1P8FB + VDD1P8RX + VDD1P8TX Mode 11d: FDD 4T4R Single Band: 8x Int, RX uses FB TX/FB/RX Rate = 1474.56 Msps fDAC = 11796.48 MSPS fADC = 2949.12 MSPS fTX = fRX = 8 GHz 64/66 coding, 24.33 Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2 1260 mA Group 3B: VDD1P8FBCLK + VDD1P8RXCLK + VDD1P8TXDAC+ VDD1P8GPIO + VDDA1P8 940 mA Group 3C: VDD1P8PLL + VDD1P8PLLVCO 73 mA IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX 630 mA Group 2B: VDD1P2TXCLK + VDD1P2TXENC 1480 mA Group 2C: VDD1P2FBCML + VDD1P2RXCML + VDD1P2PLLCLKREF 78 mA IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 4200 mA Pdiss Power Dissipation 10640 mW AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.10 Timing Requirements

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. MIN NOM MAX UNIT Timing: SYSREF+/- ts(SYSREF) Setup Time, SYSREF+/- Valid to Rising Edge of CLK+/- 50 ps th(SYSREF) Hold Time, SYSREF+/- Valid after Rising Edge of CLK+/- 50 ps Timing: Serial ports ts(SENB) Setup Time, SENB to Rising Edge of SCLK 15 ns th(SENB) Hold Time, SENB after last Rising Edge of SCLK (1) 5 + tSCLK ns ts(SDIO) Setup Time, SDIO valid to Rising Edge of SCLK 15 ns th(SDIO) Hold Time, SDIO valid after Rising Edge of SCLK 5 ns t(SCLK)_W Minimum SCLK period: registers write 25 ns t(SCLK)_R Minimum SCLK period: registers read 50 ns t(SCLK)_R SCLK period: temp sensor (2) 1000 ns td(data_out) Minimum Data Output delay after Falling Edge of SCLK 0 ns Maximum Data Output delay after Falling Edge of SCLK 15 ns tRESET Minimum RESETZ Pulse Width 1 ms (1) SDEN\\\\ need to be held one more extra clock cycle with the last SCLK edge (2) Temp sensor requires a maximum of 1MHz SCLK cycle. www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: AFE7950-SP

4.11 Switching Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX Channel Latency tJESDTX JESD to TX output Latency LMFSHd=2-8-8-1, 368.64 MSPS input rate, 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 152 interface clock cycles(1) LMFSHd=8-16-4-1, 491.52 MSPS 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 176 LMFSHd=4-16-8-1, 245.76 MSPS 48x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 124 LMFSHd=2-16-16-1, 122.88 MSPS 96x Interpolation, Serdes rate = 16.22Gbps (JESD204C) RX Channel Latency SerDes Transmitter Analog Delay 3.6 ns tJESDRX RX input to JESD output Latency LMFS=2-16-16-1, 122.88 MSPS, 24x Decimation, Serdes rate = 16.22Gbps (JESD204C) interface clock cycles(1) LMFS=4-16-8-1, 245.76 MSPS, 12x Decimation, Serdes rate = 16.22Gbps (JESD204C) 108 LMFS=4-8-4-1, 491.52 MSPS, 6x Decimation, Serdes rate = 16.22Gbps (JESD204C) 153 FB Channel Latency SerDes Transmitter Analog Delay 3.6 ns tJESDFB FB input to JESD output Latency LMFS=1-2-8-1, 368.64 MSPS, 8x Decimation 151 interface clock cycles(1)LMFS=2-4-4-1, 491.52 MSPS, 6x Decimation 177 (1) Interface clock cycles is the period of the digital interface sample rate, e.g. 1GSPS = 1ns. AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12 Typical Characteristics

4.12.1 TX Typical Characteristics 800MHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Output Frequency (MHz) Output Full Scale (dBm) 600 750 900 1050 1200 1350 1500 fDAC=5898.24MSPS, straight mode fDAC=5898.24MSPS, interleave mode fDAC=8847.36MSPS, straight mode fDAC=8847.36MSPS, interleave mode fDAC=11796.48MSPS, straight mode fDAC=11796.48MSPS, interleave mode including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, 0.8GHz matching Figure 4-1. TX Output Fullscale vs Output Frequency Temperature (Cq) Output Full Scale (dBm) -40 -15 10 35 60 85 105 2.5 3.5 4.5 5.5 6.5 fdac=5898.24MSPS, straight mode fdac=5898.24MSPS, interleaved mode fdac=8847.36MSPS, straight mode fdac=8847.36MSPS, interleaved mode fdac=11796.48MSPS, interleaved mode including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, 0.8GHz matching Figure 4-2. TX Output Fullscale vs Temperature DSA (dB) Output Power (dBm) 0 5 10 15 20 25 30 35 40 -35 -30 -25 -20 -15 -10 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleave mode, Aout = -0.5dFBS, matching 0.8GHz Figure 4-3. TX Output Power vs DSA Setting and Channel at 0.85GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-4. TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 0.85GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-5. TX Calibrated Differential Gain Error vs DSA Setting and Channel at 0.85GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 0.05 0.1 0.15 0.2 0.25 0.3 0.35 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Settings Figure 4-6. TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 0.85GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: AFE7950-SP

4.12.1 TX Typical Characteristics 800MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Calibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.02 0.02 0.04 0.06 0.08 0.1 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting Figure 4-7. TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 0.85GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-8. TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 0.85GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-9. TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 0.85GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting Figure 4-10. TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85GHz DSA (dB) Calibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.04 -0.02 0.02 0.04 0.06 0.08 0.1 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting Figure 4-11. TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85GHz DSA (dB) Uncalibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.02 -0.01 0.01 0.02 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-12. TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 0.85GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Calibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Phase DNL spike may occur at any DSA setting. Figure 4-13. TX Calibrated Differential Phase Error vs DSA Setting and Channel at 0.85GHz DSA (dB) Uncalibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 0.05 0.1 0.15 0.2 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0) Figure 4-14. TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 0.85GHz DSA (dB) Calibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0) Figure 4-15. TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 0.85GHz DSA (dB) Uncalibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.02 -0.01 0.01 0.02 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) + 1 Figure 4-16. TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 0.85GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Calibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.02 -0.01 0.01 0.02 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz, channel with the median variation over DSA setting at 25°C Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) + 1 Figure 4-17. TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 0.85GHz DSA (dB) Uncalibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.02 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0) Figure 4-18. TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 0.85GHz DSA (dB) Calibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0) Figure 4-19. TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 0.85GHz DSA (dB) Noise (dBFS/Hz) 0 4 8 12 16 20 24 28 32 36 40 -159 -154 -149 -144 -139 -134 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz, POUT = –13 dBFS Figure 4-20. TX Output Noise vs Channel and Attenuation at 0.85GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) IMD3 (dBc) 0 4 8 12 16 20 24 28 32 36 40 -100 -95 -90 -85 -80 -75 -70 -65 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85GHz, matching at 0.8 GHz, –13 dBFS each tone Figure 4-21. TX IMD3 vs DSA Setting at 0.85GHz Tone Spacing (MHz) IMD3 (dBc) 0 40 80 120 160 200 240 280 320 360 400 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone Figure 4-22. TX IMD3 vs Tone Spacing and Channel at 0.85GHz Tone Spacing (MHz) IMD3 (dBc) 0 40 80 120 160 200 240 280 320 360 400 -83 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone Figure 4-23. TX IMD3 vs Tone Spacing and Channel at 0.85GHz Tone Spacing (MHz) IMD3 (dBc) 0 40 80 120 160 200 240 280 320 360 400 -85 -84 -83 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone Figure 4-24. TX IMD3 vs Tone Spacing and Channel at 0.85GHz Tone Spacing (MHz) IMD3 (dBc) 0 40 80 120 160 200 240 280 320 360 400 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 -40qC 25qC 105qC fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone, worst channel Figure 4-25. TX IMD3 vs Tone Spacing and Temperature at 0.85GHz Tone Spacing (MHz) IMD3 (dBc) 0 40 80 120 160 200 240 280 320 360 400 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -40qC 25qC 105qC DAC = 8847.3 MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8 GHz, –13dBFS each tone, worst channel Figure 4-26. TX IMD3 vs Tone Spacing and Temperature at 0.85GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Tone Spacing (MHz) IMD3 (dBc) 0 40 80 120 160 200 240 280 320 360 400 -83 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -40qC 25qC 105qC fDAC = 11796.48MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone, worst channel Figure 4-27. TX IMD3 vs Tone Spacing and Temperature at 0.85GHz Pout/tone (dBFS) IMD3 (dBc) -100 -95 -90 -85 -80 -75 -70 -65 -60 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85GHz, fSPACING = 20MHz, matching at 0.8GHz Figure 4-28. TX IMD3 vs Digital Level at 0.85GHz Pout/tone (dBFS) IMD3 (dBc) -100 -95 -90 -85 -80 -75 -70 -65 -60 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85GHz, fSPACING = 20MHz, matching at 0.8GHz Figure 4-29. TX IMD3 vs Digital Level at 0.85GHz Pout/tone (dBFS) IMD3 (dBc) -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85GHz, fSPACING = 20MHz, matching at 0.8GHz Figure 4-30. TX IMD3 vs Digital Level at 0.85GHz Output Frequency (MHz) Noise (dBFS/Hz) 600 750 900 1050 1200 1350 1500 -159 -158 -157 -156 -155 -154 -153 -152 -151 -150 Aout=-30dBFS Aout=-20dBFS Aout=-12dBFS Aout=-6dBFS Aout=-1dBFS Matching at 2.6GHz, Single tone, fDAC = 11.79648GSPS, interleave mode, 40MHz offset, DSA = 0dB Figure 4-31. TX Single Tone Output Noise vs Frequency and Amplitude at 0.85GHz TM1.1, POUT_RMS = –13dBFS Figure 4-32. TX 20-MHz LTE Output Spectrum at 0.85 GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Pout (dBFS) Ajacent channel ACPR (dBc) -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 1TX 2TX 3TX 4TX Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-33. TX 20-MHz LTE ACPR vs Digital Level at 0.85GHz Pout(dBFS) Alternate channel ACPR (dBc) -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 1TX 2TX 3TX 4TX Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-34. TX 20MHz LTE alt-ACPR vs Digital Level at 0.85GHz DSA (dB) Ajacent channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -70 -67 -64 -61 -58 -55 -52 1TX 2TX 3TX 4TX Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-35. TX 20MHz LTE ACPR vs DSA at 0.85GHz DSA (dB) Alternate channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -72 -69 -66 -63 -60 -57 -54 -51 1TX 2TX 3TX 4TX Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-36. TX 20-MHz LTE alt-ACPR vs DSA at 0.85GHz Output Frequency (MHz) HD2 (dBFS/Hz) 600 750 900 1050 1200 1350 1500 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 0.8GHz, fDAC = 5898.2 GSPS, straight mode Figure 4-37. TX HD2 vs Digital Amplitude and Output Frequency at 0.85GHz Output Frequency (MHz) HD2 (dBFS/Hz) 600 750 900 1050 1200 1350 1500 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 0.8GHz, fDAC = 8847.36GSPS, straight mode Figure 4-38. TX HD2 vs Digital Amplitude and Output Frequency at 0.85GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Output Frequency (MHz) HD3 (dBFS/Hz) 600 750 900 1050 1200 1350 1500 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 0.8GHz, fDAC = 5898.24MSPS, straight mode, normalized to output power at harmonic frequency Figure 4-39. TX HD3 vs Digital Amplitude and Output Frequency at 0.85GHz Output Frequency (MHz) HD3 (dBFS/Hz) 600 750 900 1050 1200 1350 1500 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 0.8GHz, fDAC = 8847.36MSPS, straight mode, normalized to output power at harmonic frequency Figure 4-40. TX HD3 vs Digital Amplitude and Output Frequency at 0.85GHz Output Frequency (MHz) Amplitude (dBm) 0 1000 2000 3000 4000 5000 6000 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Tone = -6.0dBm HD2 = -68.7dBm HD3 = -88.6dBm IL2 = -75.0dBm fDAC = 5898.24MSPS, interleave mode, 0.8GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT. Figure 4-41. TX Single Tone (–12 dBFS) Output Spectrum at 0.85GHz (0-fDAC) Output Frequency (MHz) Amplitude (dBm) 0 1000 2000 3000 4000 5000 6000 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Tone = 0dBm HD2 = -56.4dBm HD3 = -73.1dBm IL2 = -70.9dBm fDAC = 5898.2 MSPS, interleave mode, 0.8GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT. Figure 4-42. TX Single Tone (–6dBFS) Output Spectrum at 0.85GHz (0-fDAC) Output Frequency (MHz) Amplitude (dBm) 0 1000 2000 3000 4000 5000 6000 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Tone = 5.0dBm HD2 = -47.7dBm HD3 = -67.7dBm IL2 = -65.2dBm fDAC = 5898.24MSPS, interleave mode, 0.8GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT. Figure 4-43. TX Single Tone (–1dBFS) Output Spectrum at 0.85GHz (0-fDAC) AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.2 TX Typical Characteristics at 1.8GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Uncalibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-50. TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 1.8GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-51. TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 1.8GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-52. TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 1.8GHz DSA (dB) Calibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.04 -0.02 0.02 0.04 0.06 -40 qC 25 qC 105 qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-53. TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 1.8GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.2 TX Typical Characteristics at 1.8GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Uncalibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.02 -0.01 0.01 0.02 0.03 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-58. TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 1.8GHz DSA (dB) Calibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.02 -0.01 0.01 0.02 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz, channel with the median variation over DSA setting at 25°C Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-59. TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 1.8GHz DSA (dB) Uncalibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.02 0.02 0.06 0.1 0.14 0.18 0.22 0.26 0.3 0.34 0.38 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz, channel with the median variation over DSA setting at 25°C Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-60. TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 1.8GHz DSA (dB) Calibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 -40qC 25qC 105qC fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz, channel with the median variation over DSA setting at 25°C Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-61. TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 1.8GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.2 TX Typical Characteristics at 1.8GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated TM1.1, POUT_RMS = –13dBFS Figure 4-68. TX 20-MHz LTE Output Spectrum at 1.8425GHz Pout (dBFS) Ajacent channel ACPR (dBc) -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 1TX 2TX 3TX 4TX Matching at 1.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-69. TX 20MHz LTE ACPR vs Digital Level at 1.8425GHz Pout(dBFS) Alternate channel ACPR (dBc) -73 -71 -69 -67 -65 -63 -61 -59 -57 -55 1TX 2TX 3TX 4TX Matching at 1.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-70. TX 20MHz LTE alt-ACPR vs Digital Level at 1.8425GHz DSA (dB) Ajacent channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -72 -69 -66 -63 -60 -57 -54 -51 1TX 2TX 3TX 4TX Matching at 1.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-71. TX 20MHz LTE ACPR vs DSA at 1.8GHz DSA (dB) Alternate channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -73 -70 -67 -64 -61 -58 -55 -52 -49 1TX 2TX 3TX 4TX Matching at 1.8GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-72. TX 20MHz LTE alt-ACPR vs DSA at 1.8GHz Output Frequency (MHz) HD2 (dBFS/Hz) 1200 1500 1800 2100 2400 2700 -115 -105 -95 -85 -75 -65 -55 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 1.8GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency Figure 4-73. TX HD2 vs Digital Amplitude and Output Frequency at 1.8GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.3 TX Typical Characteristics at 2.6GHz Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Frequency (MHz) Fullscale POUT (dBm) 2000 2200 2400 2600 2800 3000 3200 straight mode interleave mode Including PCB and cable losses, Aout = -0.5dBFS, DSA = 0, 2.6GHz matching Figure 4-78. TX Full Scale vs RF Frequency at 11796.48MSPS DSA (dB) Output Power (dBm) 0 5 10 15 20 25 30 35 40 -40 -35 -30 -25 -20 -15 -10 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, Aout = -0.5dBFS, matching 2.6GHz Figure 4-79. TX Output Power vs DSA Setting and Channel at 2.6GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-80. TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 2.6GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-81. TX Calibrated Differential Gain Error vs DSA Setting and Channel at 2.6GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-82. TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 2.6GHz DSA (dB) Calibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.04 -0.02 0.02 0.04 0.06 0.08 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-83. TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 2.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.3 TX Typical Characteristics at 2.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Uncalibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.08 -0.06 -0.04 -0.02 0.02 0.04 0.06 0.08 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-88. TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 2.6GHz DSA (dB) Calibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Phase DNL spike may occur at any DSA setting. Figure 4-89. TX Calibrated Differential Phase Error vs DSA Setting and Channel at 2.6GHz DSA (dB) Uncalibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-90. TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 2.6GHz DSA (dB) Calibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-91. TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 2.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.3 TX Typical Characteristics at 2.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Noise (dBFS/Hz) 0 4 8 12 16 20 24 28 32 36 40 -159 -156 -153 -150 -147 -144 -141 -138 -135 -132 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz, POUT = –13 dBFS Figure 4-96. TX Output Noise vs Channel and Attenuation at 2.6GHz DSA (dB) IMD3 (dBc) 0 4 8 12 16 20 24 28 32 36 40 -95 -90 -85 -80 -75 -70 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6GHz, matching at 2.6GHz, –13 dBFS each tone Figure 4-97. TX IMD3 vs DSA Setting at 2.6GHz Tone Spacing (MHz) IMD3 (dBc) 0 50 100 150 200 250 300 350 400 -80 -75 -70 -65 -60 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6GHz, matching at 2.6GHz, –13 dBFS each tone Figure 4-98. TX IMD3 vs Tone Spacing and Channel at 2.6GHz Tone Spacing (MHz) IMD3 (dBc) 0 50 100 150 200 250 300 350 400 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 TA = -40qC TA = 25qC TA = 105qC fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6GHz, matching at 2.6GHz, –13 dBFS each tone, worst channel. Figure 4-99. TX IMD3 vs Tone Spacing and Temperature at 2.6GHz POUT/tone (dBFS) IMD3 (dBc) -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6GHz, fSPACING = 20 MHz, matching at 2.6GHz Figure 4-100. TX IMD3 vs Digital Level at 2.6GHz Tone Spacing (MHz) IMD3 (dBc) 0 50 100 150 200 250 300 350 400 -90 -85 -80 -75 -70 -65 -40qC, straight mode -40qC, interleaved mode 25qC, straight mode 25qC, interleaved mode 105qC, straight mode 105qC, interleaved mode fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6GHz, matching at 2.6GHz, –13 dBFS each tone Figure 4-101. TX IMD3 vs Tone Spacing and Temperature AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.3 TX Typical Characteristics at 2.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Ajacent channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -72 -69 -66 -63 -60 -57 -54 -51 1TX 2TX 3TX 4TX Matching at 2.6GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-108. TX 20-MHz LTE ACPR vs DSA at 2.6GHz DSA (dB) Alternate channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -72 -69 -66 -63 -60 -57 -54 -51 1TX 2TX 3TX 4TX Matching at 2.6GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-109. TX 20-MHz LTE alt-ACPR vs DSA at 2.6GHz DSA (dB) Ajacent channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -66 -63 -60 -57 -54 -51 -48 -45 -42 1TX 2TX 3TX 4TX Matching at 2.6GHz, single carrier 100MHz BW TM1.1 NR Figure 4-110. TX 100-MHz NR ACPR vs DSA at 2.6GHz DSA (dB) Alternate channel ACPR (dBc) 0 4 8 12 16 20 24 28 32 36 40 -67 -64 -61 -58 -55 -52 -49 -46 -43 1TX 2TX 3TX 4TX Matching at 2.6GHz, single carrier 100MHz BW TM1.1 NR Figure 4-111. TX 100-MHz NR alt-ACPR vs DSA at 2.6GHz FOUT (MHz) HD2 (dBFS) 1800 2000 2200 2400 2600 2800 3000 3200 -100 -90 -80 -70 -60 -50 -40 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 2.6GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency Figure 4-112. TX HD2 vs Digital Amplitude and Output Frequency at 2.6GHz FOUT (MHz) HD3 (dBFS) 1800 2000 2200 2400 2600 2800 3000 3200 -120 -110 -100 -90 -80 -70 -60 -50 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 2.6GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency Figure 4-113. TX HD3 vs Digital Amplitude and Output Frequency at 2.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.4 TX Typical Characteristics at 3.5GHz Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Fundamental Frequency (MHz) Output Power (dBm) 2800 3000 3200 3400 3600 3800 4000 4200 fDAC=8847.36, straight mode fDAC=11796.48, straight mode fDAC=8847.36, interleave mode fDAC=11796.48, interleave mode Aout = -0.5dFBS, 3.5GHz Matching, included PCB and cable losses Figure 4-118. TX Output Power vs Frequency DSA (dB) Output Power (dBm) 0 5 10 15 20 25 30 35 40 -40 -35 -30 -25 -20 -15 -10 1TX 2TX 3TX 4TX Aout = -0.5dFBS, 3.5GHz Matching, included PCB and cable losses Figure 4-119. TX Output Power vs DSA Setting at 3.5GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.06 -0.04 -0.02 0.02 0.04 0.06 1TX 2TX 3TX 4TX 3.5GHz Matching, included PCB and cable losses Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-120. TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX 3.5GHz Matching, included PCB and cable losses Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-121. TX Calibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1TX 2TX 3TX 4TX 3.5GHz Matching, included PCB and cable losses Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-122. TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz DSA (dB) Calibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.06 -0.04 -0.02 0.02 0.04 1TX 2TX 3TX 4TX 3.5GHz Matching, included PCB and cable losses Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-123. TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.4 TX Typical Characteristics at 3.5GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40 qC 25 qC 105 qC 3.5GHz Matching, 1TX Figure 4-130. TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz DSA (dB) Calibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.06 -0.04 -0.02 0.02 -40 qC 25 qC 105 qC 3.5GHz Matching, 1TX, Calibrated at 25°C Figure 4-131. TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz DSA (dB) Uncalibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.06 -0.04 -0.02 0.02 0.04 0.06 0.08 -40qC 25qC 105qC 3.5GHz Matching, 1TX Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-132. TX Uncalibrated Differential Phase Error vs DSA setting and Temperature at 3.5GHz DSA (dB) Calibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.18 -0.15 -0.12 -0.09 -0.06 -0.03 0.03 0.06 -40qC 25qC 105qC 3.5GHz Matching, 1TX, Calibrated at 25°C Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-133. TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 3.5GHz DSA (dB) Uncalibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -40qC 25qC 105qC 3.5GHz Matching, 1TX Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting=0) Figure 4-134. TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz DSA (dB) Calibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 -40qC 25qC 105qC 3.5GHz Matching, 1TX, Calibrated at 25°C Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-135. TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.4 TX Typical Characteristics at 3.5GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated POUT (dBFS) ACPR (dBc) -75 -70 -65 -60 -55 1TX 2TX 3TX 4TX 3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE Figure 4-142. TX 20MHz LTE ACPR vs Digital Level at 3.5GHz POUT (dBFS) Alternate Channel ACPR (dBc) -75 -70 -65 -60 -55 1TX 2TX 3TX 4TX 3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE Figure 4-143. TX 20MHz LTE alt-ACPR vs Digital Level at 3.5GHz FOUT (MHz) HD2 (dBFS) 2800 3000 3200 3400 3600 3800 4000 4200 -100 -90 -80 -70 -60 -50 -40 -30 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency Figure 4-144. TX Single Tone HD2 vs Frequency and Digital Level at 3.5GHz FOUT (MHz) HD3 (dBFS) 2800 3000 3200 3400 3600 3800 4000 4200 -120 -110 -100 -90 -80 -70 -60 1TX, -12dBFS 1TX, -6dBFS 2TX, -12dBFS 2TX, -6dBFS 3TX, -12dBFS 3TX, -6dBFS 4TX, -12dBFS 4TX, -6dBFS Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency. Dip is due to HD3 falling near DC. Figure 4-145. TX Single Tone HD3 vs Frequency and Digital Level at 3.5GHz Frequency (MHz) Amplitude (dBm) 0 2000 4000 6000 8000 10000 12000 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Tone=0dBm HD2=-52dBm HD3=-53dBm IL2=-44dBm IL3=-85dBm Fs/2=-44dBm D095 Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode. Figure 4-146. TX Single Tone (–1dBFS) Output Spectrum at 3.5GHz (0 - fDAC) Frequency (MHz) Amplitude (dBm) 0 2000 4000 6000 8000 10000 12000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Tone=-4.9dBm HD2=-63dBm HD3=-71dBm IL2=-49dBm fs/2=-43.6dBm D096 Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode. Figure 4-147. TX Single Tone (–6dBFS) Output Spectrum at 3.5GHz (0-fDAC) AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.4 TX Typical Characteristics at 3.5GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Frequency (MHz) Amplitude (dBm) 0 2000 4000 6000 8000 10000 12000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Tone=-10.9dBm HD2=-76dBm HD3=-83dBm IL2=-54dBm fs/2=-44dBm D098 Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode. Figure 4-148. TX Single Tone (–12dBFS) Output Spectrum at 3.5GHz (0-fDAC) www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: AFE7950-SP

4.12.5 TX Typical Characteristics at 4.9GHz Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Output Frequency (MHz) Output Full Scale (dBm) 4300 4500 4700 4900 5100 5300 5500 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 1TX 2TX 3TX 4TX Excluding PCB and cable losses, Aout = -0.5 dFBS, DSA = 0, 4.9GHz matching Figure 4-149. TX Full Scale vs RF Frequency and Channel at 11796.48MSPS Output Frequency (MHz) Output Full Scale (dBm) 4300 4500 4700 4900 5100 5300 5500 -1.8 -1.6 -1.4 -1.2 -0.8 -0.6 -0.4 -0.2 1TX 2TX 3TX 4TX Excluding PCB and cable losses, Aout = -0.5 dFBS, DSA = 0, 4.9GHz matching Figure 4-150. TX Full Scale vs RF Frequency and Channel at

5898.24 MSPS, Straight Mode, 2nd Nyquist Zone

Temperature (Cq) Output Full Scale (dBm) -45 -20 5 30 55 80 105 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, Aout = -0.5dFBS, matching 4.9GHz Figure 4-151. TX Output Power vs DSA Setting and Channel at 4.9GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX fDAC =11796.48MSPS, interleave mode, matching at 4.9GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-152. TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 4.9GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX fDAC =11796.48MSPS, interleave mode, matching at 4.9GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-153. TX Calibrated Differential Gain Error vs DSA Setting and Channel at 4.9GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 4 8 12 16 20 24 28 32 36 40 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1TX 2TX 3TX 4TX fDAC =11796.48MSPS, interleave mode, matching at 4.9GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-154. TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 4.9GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.5 TX Typical Characteristics at 4.9GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) Calibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Phase DNL spike may occur at any DSA setting. Figure 4-161. TX Calibrated Differential Phase Error vs DSA Setting and Channel at 4.9GHz DSA (dB) Uncalibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-162. TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 4.9GHz DSA (dB) Calibrated Integrated Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-163. TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 4.9GHz DSA (dB) Uncalibrated Differential Phase Error (deg) 0 4 8 12 16 20 24 28 32 36 40 -0.1 -0.08 -0.06 -0.04 -0.02 0.02 0.04 0.06 0.08 -40qC 25qC 105qC fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-164. TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 4.9GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.5 TX Typical Characteristics at 4.9GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Tone Spacing (MHz) IMD3 (dBc) 0 40 80 120 160 200 240 280 320 360 400 -70 -69 -68 -67 -66 -65 -64 -40 qC 25 qC 105 qC fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, fCENTER = 4.9GHz, –13 dBFS each tone, worst channel Figure 4-171. TX IMD3 vs Tone Spacing and Temperature at 4.9GHz Pout/tone (dBFS) IMD3 (dBc) -95 -90 -85 -80 -75 -70 -65 -60 -55 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, fCENTER = 4.9GHz, fSPACING = 20MHz Figure 4-172. TX IMD3 vs Digital Level at 4.9GHz Output Frequency (MHz) Noise (dBFS/Hz) 4300 4500 4700 4900 5100 5300 5500 -159 -157 -155 -153 -151 -149 -147 -145 -143 -141 -139 Ain=-30dBFS Ain=-20dBFS Ain=-12dBFS Ain=-6dBFS Ain=-1dBFS Matching at 4.9GHz, Single tone, fDAC = 11.79648GSPS, interleave mode, 40MHz offset, DSA = 0dB Figure 4-173. TX Single Tone Output Noise vs Frequency and Amplitude at 4.9GHz TM1.1, POUT_RMS = –13dBFS Figure 4-174. TX 20MHz LTE Output Spectrum at 4.9GHz Pout(dBFS) Ajacent channel ACPR (dBc) -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 1TX 2TX 3TX 4TX Matching at 4.9GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-175. TX 20MHz LTE ACPR vs Digital Level at 4.9GHz Pout (dBFS) Alternate channel ACPR (dBc) -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 1TX 2TX 3TX 4TX Matching at 4.9GHz, single carrier 20MHz BW TM1.1 LTE Figure 4-176. TX 20MHz LTE alt-ACPR vs Digital Level at 4.9GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.5 TX Typical Characteristics at 4.9GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated Output Frequency (MHz) Amplitude (dBm) 0 2000 4000 6000 8000 10000 12000 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Tone = -0.5dBm HD2 = -48.1dBm HD3 = -52.2dBm IL2 = -69.9dBm Fs/2 = -54.7dBm fDAC = 11796.48MSPS, interleave mode, 4.9GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT. Figure 4-183. TX Single Tone (–1 dBFS) Output Spectrum at 4.9GHz (0-fDAC) AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.6 TX Typical Characteristics at 8.1GHz Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching O u t p u t F r e q u e n c y ( M H z ) Output Power (dBm) 7 2 0 0 7 4 0 0 7 6 0 0 7 8 0 0 8 0 0 0 8 2 0 0 8 4 0 0 8 6 0 0 8 8 0 0 9 0 0 0 - 1 0 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1

1 T X

2 T X

3 T X

4 T X

includes PCB and cable losses. Figure 4-184. TX Output Power vs Frequency at 8.11GHz D S A S e t t i n g ( d B ) Output Power (dBm) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 includes PCB and cable losses. Figure 4-185. TX Output Power vs DSA Setting at 8.11GHz T e m p e r a t u r e (  C ) Output Power (dBm) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 1 0 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 includes PCB and cable losses. Figure 4-186. TX Output Power vs Temperature at 8.11GHz D S A S e t t i n g ( d B ) Uncalibrated Amplitude Differential Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 1 - 0 . 0 8 - 0 . 0 6 - 0 . 0 4 - 0 . 0 2 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 Figure 4-187. TX DSA Uncalibrated Amplitude Differential Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Calibrated Amplitude Differential Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 1 - 0 . 0 8 - 0 . 0 6 - 0 . 0 4 - 0 . 0 2 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 Figure 4-188. TX DSA Calibrated Amplitude Differential Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Uncalibrated Amplitude Differential Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 1 - 0 . 0 8 - 0 . 0 6 - 0 . 0 4 - 0 . 0 2 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 - 4 0  C 2 5  C 1 1 0  C Figure 4-189. TX DSA Uncalibrated Amplitude Differential Nonlinearity at 8.11GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: AFE7950-SP

4.12.6 TX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching D S A S e t t i n g ( d B ) Calibrated Amplitude Differential Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 1 - 0 . 0 8 - 0 . 0 6 - 0 . 0 4 - 0 . 0 2 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 - 4 0  C 2 5  C 1 1 0  C Figure 4-190. TX DSA Calibrated Amplitude Differential Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) UnCalibrated Amplitude Integrated Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 Figure 4-191. TX DSA Uncalibrated Amplitude Integrated Nonlinearity at 8.11GHz Figure 4-192. TX DSA Calibrated Amplitude Integrated Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Uncalibrated Amplitude Integrated Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 - 4 0  C 2 5  C 1 1 0  C Figure 4-193. TX DSA Uncalibrated Amplitude Integrated Nonlinearity at 8.11GHz Figure 4-194. TX DSA Calibrated Amplitude Integrated Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) UnCalibrated Phase Differential Nonlinearity (deg) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 Figure 4-195. TX DSA Uncalibrated Phase Differential Nonlinearity at 8.11GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.6 TX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching D S A S e t t i n g ( d B ) Calibrated Phase Differential Nonlinearity (deg) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 Figure 4-196. TX DSA Calibrated Phase Differential Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Uncalibrated Phase Differential Nonlinearity (deg) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 - 4 0  C 2 5  C 1 1 0  C Figure 4-197. TX DSA Uncalibrated Phase Differential Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Calibrated Phase Differential Nonlinearity (deg) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 - 4 0  C 2 5  C 1 1 0  C Figure 4-198. TX DSA Calibrated Phase Differential Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Uncalibrated Phase Integrated Nonlinearity (deg) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 Figure 4-199. TX DSA Uncalibrated Phase Integrated Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Calibrated Phase Integrated Nonlinearity (deg) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 Figure 4-200. TX DSA Calibrated Phase Integrated Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Uncalibrated Phase Integrated Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 - 4 0  C 2 5  C 1 1 0  C Figure 4-201. TX DSA Uncalibrated Phase Integrated Nonlinearity at 8.11GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: AFE7950-SP

4.12.6 TX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching D S A S e t t i n g ( d B ) Calibrated Phase Integrated Nonlinearity (dB) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 - 4 0  C 2 5  C 1 1 0  C Figure 4-202. TX DSA Calibrated Phase Integrated Nonlinearity at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 -1dBFS Figure 4-203. TX Single Tone Output Spectrum at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 7 5 0 0 7 7 5 0 8 0 0 0 8 2 5 0 8 5 0 0 8 7 0 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 -1dBFS Figure 4-204. TX Single Tone Output Spectrum at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 -6dBFS Figure 4-205. TX Single Tone Output Spectrum at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 7 5 0 0 7 7 5 0 8 0 0 0 8 2 5 0 8 5 0 0 8 7 0 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 -6dBFS Figure 4-206. TX Single Tone Output Spectrum at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 -12dBFS Figure 4-207. TX Single Tone Output Spectrum at 8.11GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.6 TX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching F r e q u e n c y ( M H z ) Amplitude (dBm) 7 5 0 0 7 7 5 0 8 0 0 0 8 2 5 0 8 5 0 0 8 7 0 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 50MHz tone spacing, -30dBFS each tone Figure 4-214. TX Dual Tone Output Spectrum at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 50MHz tone spacing, -60dBFS each tone Figure 4-215. TX Dual Tone Output Spectrum at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 7 5 0 0 7 7 5 0 8 0 0 0 8 2 5 0 8 5 0 0 8 7 0 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 50MHz tone spacing, -60dBFS each tone Figure 4-216. TX Dual Tone Output Spectrum at 8.11GHz D i g i t a l A m p l i t u d e p e r T o n e ( d B F S ) IMD3 (dBc) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 -7dBFS each tone, 50MHz tone spacing Figure 4-217. TX IMD3 vs Digital Amplitude at 8.11GHz D i g i t a l A m p l i t u d e p e r T o n e ( d B F S ) IMD3 (dBc) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 4 0  C 2 5  C 1 1 0  C -7dBFS each tone, 50MHz tone spacing Figure 4-218. TX IMD3 vs Digital Amplitude at 8.11GHz D S A S e t t i n g ( d B ) IMD3 (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0

1 T X , - 1 3 d B F S

2 T X , - 1 3 d B F S

3 T X , - 1 3 d B F S

4 T X , - 1 3 d B F S

1 T X , - 7 d B F S

2 T X , - 7 d B F S

3 T X , - 7 d B F S

4 T X , - 7 d B F S

Figure 4-219. TX IMD3 vs DSA Setting at 8.11GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.6 TX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching D S A S e t t i n g ( d B ) IMD3 (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 1 3 d B F S , - 4 0  C - 1 3 d B F S , 2 5  C - 1 3 d B F S , 1 1 0  C - 7 d B F S , - 4 0  C - 7 d B F S , 2 5  C - 7 d B F S , 1 1 0  C

50 MHz tone spacing

Figure 4-220. TX IMD3 vs DSA Setting at 8.11GHz T o n e A m p l i t u d e ( d B F S ) 2-tone SFDR (dBFS) - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 Figure 4-221. TX 2-Tone SFDR vs Digital Amplitude at 8.11GHz D i g i t a l A m p l i t u d e ( d B F S ) NSD at 50MHz Offset (dBFS/Hz) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 - 1 6 0 - 1 5 8 - 1 5 6 - 1 5 4 - 1 5 2 - 1 5 0 - 1 4 8 - 1 4 6 - 1 4 4 - 1 4 2 - 1 4 0

50 MHz offset

Figure 4-222. TX NSD vs Digital Amplitude at 8.11GHz D i g i t a l A m p l i t u d e ( d B F S ) NSD at 50MHz Offset (dBFS/Hz) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 - 1 6 0 - 1 5 8 - 1 5 6 - 1 5 4 - 1 5 2 - 1 5 0 - 1 4 8 - 1 4 6 - 1 4 4 - 1 4 2 - 1 4 0 - 4 0  C 2 5  C 1 1 0  C Figure 4-223. TX NSD vs Digital Amplitude at 8.11GHz D S A S e t t i n g ( d B ) NSD at 50MHz offset (dBFS/Hz) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 2 5 - 1 2 0

1 T X , - 1 2 d B F S

2 T X , - 1 2 d B F S

3 T X , - 1 2 d B F S

4 T X , - 1 2 d B F S

1 T X , - 1 d B F S

2 T X , - 1 d B F S

3 T X , - 1 d B F S

4 T X , - 1 d B F S

Figure 4-224. TX NSD vs DSA Setting at 8.11GHz D S A S e t t i n g ( d B ) NSD at 50MHz offset (dBFS/Hz) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 2 5 - 1 2 0 - 1 2 d B F S , - 4 0  C - 1 2 d B F S , 2 5  C - 1 2 d B F S , 1 1 0  C - 1 d B F S , - 4 0  C - 1 d B F S , 2 5  C - 1 d B F S , 1 1 0  C Figure 4-225. TX NSD vs DSA Setting at 8.11GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: AFE7950-SP

4.12.6 TX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching D S A S e t t i n g ( d B ) ACPR (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 6 0 - 5 7 - 5 4 - 5 1 - 4 8 - 4 5 - 4 2 - 3 9 - 3 6 - 3 3 Figure 4-226. TX NR100MHz ACPR vs DSA Setting 8.11GHz D S A S e t t i n g ( d B ) ACPR (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 6 0 - 5 7 - 5 4 - 5 1 - 4 8 - 4 5 - 4 2 - 3 9 - 3 6 - 3 3 4 T X Figure 4-227. TX NR100MHz alt-ACPR vs DSA Setting 8.11GHz D S A S e t t i n g ( d B ) NR 100MHz Composite EVM (%rms) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 Figure 4-228. TX NR100MHz EVM vs DSA Setting 8.11GHz Figure 4-229. TX 100MHz NR Output Spectrum at 8.11GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.6 TX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48 MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, 8.1GHz matching Figure 4-232. TX 4x100MHz NR Output Spectrum 8.11GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.7 TX Typical Characteristics at 9.6GHz Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 1474.56MSPS, fDAC = 11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated, 9.6GHz matching O u t p u t F r e q u e n c y ( M H z ) Output Power (dBm) 8 8 0 0 9 0 0 0 9 2 0 0 9 4 0 0 9 6 0 0 9 8 0 0 1 0 0 0 0 1 0 2 0 0 1 0 4 0 0 - 1 4 - 1 3 - 1 2 - 1 1 - 1 0 - 9 - 8 - 7 - 6 - 5 - 4 Includes PCB and cable losses. Figure 4-233. TX Output Power vs Frequency at 9.61GHz T e m p e r a t u r e (  C ) Output Power (dBm) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 1 0 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 Includes PCB and cable losses. Figure 4-234. TX Output Power vs Frequency at 9.61GHz D S A S e t t i n g ( d B ) Output Power (dBm) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 Includes PCB and cable losses. Figure 4-235. TX Output Power vs DSA Setting at 9.61GHz D S A S e t t i n g ( d B ) Uncalibrated Amplitude Differential Nonlinearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 0 . 2 - 0 . 1 5 - 0 . 1 - 0 . 0 5 0 . 0 5 0 . 1 0 . 1 5 0 . 2 Figure 4-236. TX DSA Uncalibrated Amplitude Differential Nonlinearity D S A S e t t i n g ( d B ) Calibrated Amplitude Differential Nonlinearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 0 . 2 - 0 . 1 5 - 0 . 1 - 0 . 0 5 0 . 0 5 0 . 1 0 . 1 5 0 . 2 Figure 4-237. TX DSA Calibrated Amplitude Differential Nonlinearity D S A S e t t i n g ( d B ) Uncalibrated Amplitude Differential Nonlinearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 0 . 2 - 0 . 1 5 - 0 . 1 - 0 . 0 5 0 . 0 5 0 . 1 0 . 1 5 0 . 2 - 4 0  C 2 5  C 1 1 0  C Figure 4-238. TX DSA Uncalibrated Amplitude Differential Nonlinearity www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: AFE7950-SP

4.12.7 TX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 1474.56MSPS, fDAC = 11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated, 9.6GHz matching D S A S e t t i n g ( d B ) Calibrated Amplitude Differential Nonlinearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 0 . 2 - 0 . 1 5 - 0 . 1 - 0 . 0 5 0 . 0 5 0 . 1 0 . 1 5 0 . 2 - 4 0  C 2 5  C 1 1 0  C Figure 4-239. TX DSA Calibrated Amplitude Differential Nonlinearity Figure 4-240. TX DSA Uncalibrated Amplitude Integrated Nonlinearity D S A S e t t i n g ( d B ) Calibrated Amplitude Integrated Nonlinearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 Figure 4-241. TX DSA Calibrated Amplitude Integrated Nonlinearity D S A S e t t i n g ( d B ) Uncalibrated Amplitude Integrated Nonlinearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 - 4 0  C 2 5  C 1 1 0  C Figure 4-242. TX DSA Uncalibrated Amplitude Integrated Nonlinearity D S A S e t t i n g ( d B ) Calibrated Amplitude Integrated Nonlinearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 - 4 0  C 2 5  C 1 1 0  C Figure 4-243. TX DSA Calibrated Amplitude Integrated Nonlinearity D S A S e t t i n g ( d B ) Uncalibrated Phase Differential Nonlinearity (deg) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 Figure 4-244. TX DSA Uncalibrated Phase Differential Nonlinearity AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.7 TX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 1474.56MSPS, fDAC = 11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated, 9.6GHz matching D S A S e t t i n g ( d B ) Calibrated Phase Differential Nonlinearity (deg) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 Figure 4-245. TX DSA Calibrated Phase Differential Nonlinearity D S A S e t t i n g ( d B ) Uncalibrated Phase Differential Nonlinearity (deg) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 - 4 0  C 2 5  C 1 1 0  C Figure 4-246. TX DSA Uncalibrated Phase Differential Nonlinearity D S A S e t t i n g ( d B ) Calibrated Phase Differential Nonlinearity (deg) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 - 4 0  C 2 5  C 1 1 0  C Figure 4-247. TX DSA Calibrated Phase Differential Nonlinearity D S A S e t t i n g ( d B ) Uncalibrated Phase IntegratedNonlinearity (deg) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 4 T X Figure 4-248. TX DSA Uncalibrated Phase Integrated Nonlinearity D S A S e t t i n g ( d B ) Calibrated Phase Differential Nonlinearity (deg) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 - 4 0  C 2 5  C 1 1 0  C Figure 4-249. TX DSA Calibrated Phase Integrated Nonlinearity Figure 4-250. TX DSA Uncalibrated Phase Integrated Nonlinearity www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: AFE7950-SP

4.12.7 TX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 1474.56MSPS, fDAC = 11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated, 9.6GHz matching D S A S e t t i n g ( d B ) Calibrated Phase Integrated Nonlinearity (deg) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 - 4 0  C 2 5  C 1 1 0  C Figure 4-251. TX DSA Calibrated Amplitude Integrated Nonlinearity T o n e A m p l i t u d e ( d B F S ) IMD3 (dBc or dBFS) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 - 1 4 0 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0

1 T X ( d B c )

2 T X ( d B c )

3 T X ( d B c )

4 T X ( d B c )

1 T X ( d B F S )

2 T X ( d B F S )

3 T X ( d B F S )

4 T X ( d B F S )

Figure 4-252. TX IMD3 vs Digital Amplitude at 9.61GHz T o n e A m p l i t u d e ( d B F S ) IMD3 (dBc or dBFS) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 - 1 4 0 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 4 0 (  C , d B c ) 2 5 (  C , d B c ) 1 1 0 (  C , d B c ) - 4 0 (  C , d B F S ) 2 5 (  C , d B F S ) 1 1 0 (  C , d B F S ) 50MHz tone spacing Figure 4-253. TX IMD3 vs Digital Amplitude at 9.61GHz D S A S e t t i n g ( d B ) IMD3 (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 1 3 d B F S , 1 T X - 1 3 d B F S , 2 T X - 1 3 d B F S , 3 T X - 1 3 d B F S , 4 T X - 7 d B F S , 1 T X - 7 d B F S , 2 T X - 7 d B F S , 3 T X - 7 d B F S , 4 T X 50MHz tone spacing Figure 4-254. TX IMD3 vs DSA Setting at 9.61GHz D S A S e t t i n g ( d B ) IMD3 (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 1 3 d B F S , 1 T X - 1 3 d B F S , 2 T X - 1 3 d B F S , 3 T X - 1 3 d B F S , 4 T X - 7 d B F S , 1 T X - 7 d B F S , 2 T X - 7 d B F S , 3 T X - 7 d B F S , 4 T X 50MHz tone spacing Figure 4-255. TX IMD3 vs DSA Setting at 9.61GHz D S A S e t t i n g ( d B ) IMD3 (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 1 3 d B F S , - 4 0  C - 1 3 d B F S , - 2 5  C - 1 3 d B F S , 1 1 0  C - 7 d B F S , - 4 0  C - 7 d B F S , 2 5  C - 7 d B F S , 1 0 0  C 50MHz tone spacing Figure 4-256. TX IMD3 vs DSA Setting at 9.61GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.7 TX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 1474.56MSPS, fDAC = 11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated, 9.6GHz matching T o n e S p a c i n g ( M H z ) IMD3 (dBc) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 - 8 0 - 7 8 - 7 6 - 7 4 - 7 2 - 7 0 - 6 8 - 6 6 - 6 4 - 6 2 - 6 0 Figure 4-257. TX IMD3 vs Tone Spacing at 9.61GHz T o n e S p a c i n g ( M H z ) IMD3 (dBc) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 6 0 d B F S p e r t o n e - 3 0 d B F S p e r t o n e - 1 3 d B F S p e r t o n e Figure 4-258. TX IMD3 vs Tone Spacing at 9.61GHz T o n e S p a c i n g ( M H z ) IMD3 (dBc) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 - 7 0 - 6 9 - 6 8 - 6 7 - 6 6 - 6 5 - 6 4 - 6 3 - 6 2 - 6 1 - 6 0 - 4 0  C 2 5  C 1 1 0  C Figure 4-259. TX IMD3 vs Tone Spacing at 9.61GHz D i g i t a l A m p l i t u d e ( d B F S ) NSD (dBFS/Hz) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 - 1 5 4 - 1 5 3 - 1 5 2 - 1 5 1 - 1 5 0 - 1 4 9 - 1 4 8 - 1 4 7 - 1 4 6 - 1 4 5 - 1 4 4 4 T X Figure 4-260. TX NSD vs Digital Amplitude at 9.61GHz D i g i t a l A m p l i t u d e ( d B F S ) NSD (dBFS/Hz) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 - 1 5 4 - 1 5 3 - 1 5 2 - 1 5 1 - 1 5 0 - 1 4 9 - 1 4 8 - 1 4 7 - 1 4 6 - 1 4 5 - 1 4 4 - 4 0  C 2 5  C 1 1 0  C Figure 4-261. TX NSD vs Digital Amplitude at 9.61GHz Figure 4-262. TX NSD vs DSA Setting at 9.61GHz D S A S e t t i n g ( d B ) NSD (dBFS/Hz) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 2 5 - 1 2 0 Figure 4-263. TX NSD vs DSA Setting at 9.61GHz D S A S e t t i n g ( d B ) NSD (dBFS/Hz) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 2 5 - 1 2 0 - 4 0  C 2 5  C 1 1 0  C Figure 4-264. TX NSD vs DSA Setting at 9.61GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: AFE7950-SP

4.12.7 TX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 1474.56MSPS, fDAC = 11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated, 9.6GHz matching T o n e A m p l i t u d e ( d B F S ) 2-tone SFDR (dBFS) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 Figure 4-265. TX 2-tone SFDR vs Digital Amplitude at 9.61GHz F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 Includes PCB and cable losses. Figure 4-266. TX Single Tone Spectrum at 9.61GHz and -1dBFS (wideband) F r e q u e n c y ( M H z ) Amplitude (dBm) 9 0 0 0 9 2 0 0 9 4 0 0 9 6 0 0 9 8 0 0 1 0 0 0 0 1 0 2 0 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 Includes PCB and cable losses. Figure 4-267. TX Single Tone Spectrum at 9.61GHz and -1dBFS (1.2GHz BW) F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 Includes PCB and cable losses. Figure 4-268. TX Single Tone Spectrum at 9.61GHz and -6dBFS (wideband) Includes PCB and cable losses. Figure 4-269. TX Single Tone Spectrum at 9.61GHz and -6dBFS (1.2GHz BW) F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 Includes PCB and cable losses. Figure 4-270. TX Single Tone Spectrum at 9.61GHz and -12dBFS (wideband) AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.7 TX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 1474.56MSPS, fDAC = 11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated, 9.6GHz matching F r e q u e n c y ( M H z ) Amplitude (dBm) 9 0 0 0 9 2 0 0 9 4 0 0 9 6 0 0 9 8 0 0 1 0 0 0 0 1 0 2 0 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 Includes PCB and cable losses, 50MHz tone spacing. Figure 4-277. TX 2-Tone Spectrum at 9.61GHz and -30dBFS Each (1.2GHz BW) F r e q u e n c y ( M H z ) Amplitude (dBm) 0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 Includes PCB and cable losses, 50MHz tone spacing. Figure 4-278. TX 2-Tone Spectrum at 9.61GHz and -60dBFS Each (wideband) F r e q u e n c y ( M H z ) Amplitude (dBm) 9 0 0 0 9 2 0 0 9 4 0 0 9 6 0 0 9 8 0 0 1 0 0 0 0 1 0 2 0 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 Includes PCB and cable losses, 50MHz tone spacing. Figure 4-279. TX 2-Tone Spectrum at 9.61GHz and -60dBFS Each (1.2GHz BW) O f f s e t F r e q u e n c y ( H z ) Additive Phase Noise (dBc/Hz) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 Single sideband, external clock mode, input clock phase noise removed Figure 4-280. TX Additive Phase Noise vs Offset Frequency at 9.61GHz Figure 4-281. TX NR100MHz ACPR vs DSA Setting at 9.61GHzTX NR100MHz alt-ACPR vs DSA Setting at 9.61GHz D S A S e t t i n g ( d B ) NR 100MHz Composite EVM (%rms) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 Figure 4-282. TX NR100MHz EVM vs DSA Setting at 9.61GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.8 RX Typical Characteristics at 800MHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Output Frequency (MHz) Relative Input Power (dB) 700 800 900 1000 1100 -0.8 -0.6 -0.4 -0.2 0.2 0.4 DSA=4dB DSA=6dB DSA=8dB DSA=10dB DSA=12dB DSA=14dB With 0.8GHz matching, normalized to 830MHz Figure 4-285. RX In-Band Gain Flatness for Channel 1RX, fIN = 830MHz Temperature (qC) Input FS (dB) -40 -30 -20 -10 0 10 20 30 40 50 60 70 -0.2 -0.17 -0.14 -0.11 -0.08 -0.05 -0.02 0.01 0.04 0.07 0.1 0.13 1RX 2RX 3RX 4RX With 0.8GHz matching, normalized to fullscale at 25°C for each channel Figure 4-286. RX Input Fullscale vs Temperature and Channel at 800MHz Temperature (qC) Input Phase (degree) -40 -30 -20 -10 0 10 20 30 40 50 60 70 1RX 2RX 3RX 4RX With 0.8GHz matching, normalized to phase at 25°C Figure 4-287. RX Input Phase vs Temperature and DSA at fOUT = 0.8GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 5 10 15 20 25 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 1RX 2RX 3RX 4RX With 0.8GHz matching Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1 Figure 4-288. RX Uncalibrated Differential Amplitude Error vs DSA Setting at 0.8GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 5 10 15 20 25 -0.025 -0.02 -0.015 -0.01 -0.005 0.005 0.01 0.015 0.02 0.025 0.03 1RX 2RX 3RX 4RX With 0.8GHz matching Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1 Figure 4-289. RX Calibrated Differential Amplitude Error vs DSA Setting at 0.8GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 5 10 15 20 25 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 1RX 2RX 3RX 4RX With 0.8GHz matching Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting) Figure 4-290. RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 0.8GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.8 RX Typical Characteristics at 800MHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. DSA (dB) Calibrated Integrated Gain Error (dB) 0 5 10 15 20 25 -0.04 -0.02 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 1RX 2RX 3RX 4RX With 0.8GHz matching Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting) Figure 4-291. RX Calibrated Integrated Amplitude Error vs DSA Setting at 2.6GHz DSA (dB) Uncalibrated Differential Phase Error (deg) 0 5 10 15 20 25 -0.4 -0.2 0.2 0.4 0.6 1RX 2RX 3RX 4RX With 0.8GHz matching Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting) Figure 4-292. RX Uncalibrated Differential Phase Error vs DSA Setting at 0.8GHz DSA (dB) Calibrated Differential Phase Error (deg) 0 5 10 15 20 25 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 1RX 2RX 3RX 4RX With 0.8GHz matching Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting) Figure 4-293. RX Calibrated Differential Phase Error vs DSA Setting at 0.8GHz DSA (dB) Uncalibrated Integrated Phase Error (deg) 0 5 10 15 20 25 -1.2 -0.9 -0.6 -0.3 0.3 0.6 0.9 1.2 1RX 2RX 3RX 4RX With 0.8GHz matching Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-294. RX Uncalibrated Integrated Phase Error vs DSA Setting at 0.8GHz DSA (dB) Calibrated Integrated Phase Error (deg) 0 5 10 15 20 25 -0.6 -0.4 -0.2 0.2 0.4 0.6 1RX 2RX 3RX 4RX With 0.8GHz matching Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-295. RX Calibrated Integrated Phase Error vs DSA Setting at 0.8GHz Output Frequency (MHz) Amplitude (dBFS) -250 -200 -150 -100 -50 0 50 100 150 200 250 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 63.2dBFS With 0.8GHz matching, fIN = 840MHz, AIN= –3dBFS Figure 4-296. RX Output FFT at 0.8GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Temperature (qC) Noise (dBFS/Hz) -40 -25 -10 5 20 35 50 65 80 95 110 -156 -155.8 -155.6 -155.4 -155.2 -155 -154.8 -154.6 -154.4 -154.2 -154 -153.8 DSA = 4dB DSA = 12dB With 0.8GHz matching, 12.5MHz offset from tone Figure 4-297. RX Noise Spectral Density vs Temperature at 0.8GHz Input Amplitude (dBFS) Noise (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 -157 -156 -155 -154 -153 -152 -151 -150 -149 -148 -147 -40 qC, DSA = 4dB -40 qC, DSA = 12dB 25 qC, DSA = 4dB 25 qC, DSA = 12dB 110 qC, DSA = 4dB 110 qC, DSA = 12dB With 0.8GHz matching, DSA Setting = 12dB, 12.5MHz offset from tone Figure 4-298. RX Noise Spectral Density vs Input Amplitude and Temperature at 0.8GHz Input Amplitude (dBFS) Noise (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 -157 -156 -155 -154 -153 -152 -151 -150 -149 -148 -147 1RX, DSA = 4dB 1RX, DSA = 12dB 2RX, DSA = 4dB 2RX, DSA = 12dB 3RX, DSA = 4dB 3RX, DSA = 12dB With 0.8GHz matching, 12.5MHz offset from tone Figure 4-299. RX Noise Spectral Density vs Input Amplitude and Channel at 0.8GHz DSA (dB) IMD3 (dBFS) 0 2 4 6 8 10 12 14 16 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -40 qC 25 qC 110qC A. With 0.8GHz matching, each tone –7dBFS, tone spacing = 20MHz Figure 4-300. RX IMD3 vs DSA Setting and Temperature at 0.8GHz DSA (dB) IMD5 (dBFS) 0 2 4 6 8 10 12 14 16 -110 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -40 qC 25 qC 110qC With 0.8GHz matching, each tone –7dBFS, tone spacing = 20MHz Figure 4-301. RX IMD5 vs DSA Setting and Temperature at 0.8GHz Input Amplitude (dBFS) IMD3 (dBFS) -122 -118 -114 -110 -106 -102 -98 -94 -90 -86 -40 qC 25 qC 110qC With 0.8GHz matching, tone spacing = 20MHz, DSA = 4dB Figure 4-302. RX IMD3 vs Input Level and Temperature at 0.8GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Input Amplitude (dBFS) IMD3 (dBFS) -120 -115 -110 -105 -100 -95 -90 -85 -40 qC 25 qC 110qC With 0.8GHz matching, tone spacing = 20MHz, DSA = 12dB Figure 4-303. RX IMD3 vs Input Level and Temperature at 0.8GHz Input Amplitude (dBFS) IMD5 (dBFS) -120 -115 -110 -105 -100 -95 -90 -85 -40 qC 25 qC 110qC With 0.8GHz matching, tone spacing = 20MHz, DSA = 12dB Figure 4-304. RX IMD5 vs Input Level and Temperature at 0.8GHz DSA (dB) HD2 (dBc) 3 6 9 12 15 18 -95 -90 -85 -80 -75 -70 -65 -60 -55 1RX 2RX 3RX 4RX With 0.8GHz matching, measured after HD2 trim, DDC bypass mode (TI only mode for characterization) Figure 4-305. RX HD2 vs DSA Setting and Channel at 0.8GHz DSA (dB) HD2 (dBc) 3 6 9 12 15 18 -87 -84 -81 -78 -75 -72 -69 -66 -63 -60 -40qC 25qC 110qC With 0.8GHz matching, measured after HD2 trim, DDC bypass mode (TI only mode for characterization) Figure 4-306. RX HD2 vs DSA Setting and Temperature at 0.8GHz Input Amplitude (dBFS) HD2 (dBFS) -96 -91 -86 -81 -76 -71 -66 -61 -40 qC, DSA=4dB -40 qC, DSA=12dB 25 qC, DSA=4dB 25 qC, DSA=12dB 110 qC, DSA=4dB 110 qC, DSA=12dB With 0.8GHz matching, measured after HD2 trim, DDC bypass mode (TI only mode for characterization) Figure 4-307. RX HD2 vs Input Level and Temperature at 0.8GHz DSA (dB) HD3 (dBc) 3 5 7 9 11 13 15 17 18 -94 -89 -84 -79 -74 -69 1RX 2RX 3RX 4RX With 0.8GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-308. RX HD3 vs DSA Setting and Channel at 0.8GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: AFE7950-SP

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. DSA (dB) HD3 (dBc) 3 6 9 12 15 18 -87 -84 -81 -78 -75 -72 -69 -40qC 25qC 110qC With 0.8GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-309. RX HD3 vs DSA Setting and Temperature at 0.8GHz Input Amplitude (dBFS) HD3 (dBFS) -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 1RX 2RX 3RX 4RX With 0.8GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-310. RX HD3 vs Input Level and Channel at 0.8GHz Input Amplitude (dBFS) HD3 (dBFS) -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -40 qC, DSA=4dB -40 qC, DSA=12dB 25 qC, DSA=4dB 25 qC, DSA=12dB 110 qC, DSA=4dB 110 qC, DSA=12dB With 0.8GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-311. RX HD3 vs Input Level and Temperature at 0.8GHz DSA (dB) Non HD2/3 SFDR (dBFS) 0 2 4 6 8 10 12 14 16 100 1RX 2RX 3RX 4RX With 0.8GHz matching Figure 4-312. RX Non-HD2/3 vs DSA Setting at 0.8GHz Supply Voltage IMD3 (dBFS) -94 -92 -90 -88 -86 -84 -82 -80 MIN TYP MAX 1RX 2RX 3RX 4RX With 0.8GHz matching, –7dBFS each tone, 20MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-313. RX IMD3 vs Supply and Channel at 0.8GHz Supply Voltages IMD5 (dBFS) -112 -110 -108 -106 -104 -102 -100 -98 -96 -94 MIN TYP MAX 1RX 2RX 3RX 4RX With 0.8GHz matching, –7dBFS each tone, 20MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-314. RX IMD5 vs Supply and Channel at 0.8GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Supply Voltages NSD (dBFS) -156 -155.8 -155.6 -155.4 -155.2 -155 -154.8 -154.6 -154.4 -154.2 -154 MIN TYP MAX 1RX 2RX 3RX 4RX With 0.8GHz matching, 12.5MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-315. RX Noise Spectral Density vs Supply and Channel at 0.8GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: AFE7950-SP

4.12.9 RX Typical Characteristics at 1.75-1.9GHz Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Output Frequency (MHz) Relative Input Power (dB) 1650 1750 1850 1950 2050 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 DSA=4dB DSA=6dB DSA=8dB DSA=10dB DSA=12dB DSA=14dB With 1.8GHz matching, normalized to 1.75GHz Figure 4-316. RX In-Band Gain Flatness, fIN = 1750MHz Temperature (qC) Input FS (dB) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 1RX 2RX 3RX 4RX With 1.8GHz matching, normalized to fullscale at 25°C for each channel Figure 4-317. RX Input Fullscale vs Temperature and Channel at 1.75GHz Temperature (qC) Input Phase (degree) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -20 -15 -10 1RX 2RX 3RX 4RX With 2.6GHz matching, normalized to phase at 25°C Figure 4-318. RX Input Phase vs Temperature and DSA at fIN = 1.75GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 5 10 15 20 25 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 1RX 2RX 3RX 4RX With 1.8GHz matching Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1 Figure 4-319. RX Uncalibrated Differential Amplitude Error vs DSA Setting at 1.75GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 5 10 15 20 25 -0.025 -0.02 -0.015 -0.01 -0.005 0.005 0.01 0.015 0.02 0.025 0.03 1RX 2RX 3RX 4RX With 1.8GHz matching Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1 Figure 4-320. RX Calibrated Differential Amplitude Error vs DSA Setting at 1.75GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 5 10 15 20 25 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 1RX 2RX 3RX 4RX With 1.8GHz matching Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting) Figure 4-321. RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 1.75GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.9 RX Typical Characteristics at 1.75-1.9GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Temperature (qC) Noise (dBFS/Hz) -40 -25 -10 5 20 35 50 65 80 95 110 -156 -155.8 -155.6 -155.4 -155.2 -155 -154.8 -154.6 DSA = 4dB DSA = 12dB With 1.8GHz matching, 12.5MHz offset from tone Figure 4-328. RX Noise Spectral Density vs Temperature at 1.75GHz Input Amplitude (dBFS) Noise (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 -157 -156 -155 -154 -153 -152 -151 -150 -149 -148 -147 -146 -145 -40 qC, DSA = 4dB -40 qC, DSA = 12dB 25 qC, DSA = 4dB 25 qC, DSA = 12dB 110 qC, DSA = 4dB 110 qC, DSA = 12dB With 1.8GHz matching, DSA Setting = 12dB, 12.5MHz offset from tone Figure 4-329. RX Noise Spectral Density vs Input Amplitude and Temperature at 1.75GHz Input Amplitude (dBFS) Noise (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 -157 -156 -155 -154 -153 -152 -151 -150 -149 -148 -147 -146 -145 1RX, DSA = 4dB 1RX, DSA = 12dB 2RX, DSA = 4dB 2RX, DSA = 12dB 3RX, DSA = 4dB 3RX, DSA = 12dB 4RX, DSA = 4dB 4RX, DSA = 12dB With 1.8GHz matching, 12.5MHz offset from tone Figure 4-330. RX Noise Spectral Density vs Input Amplitude and Channel at 1.75GHz DSA (dB) IMD3 (dBFS) 0 2 4 6 8 10 12 14 16 18 20 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -40 qC 25 qC 110qC With 1.8GHz matching, each tone –7dBFS, tone spacing = 20MHz Figure 4-331. RX IMD3 vs DSA Setting and Temperature at 1.75GHz Input Amplitude (dBFS) IMD3 (dBFS) -124 -120 -116 -112 -108 -104 -100 -96 -92 -88 -40 qC 25 qC 110qC With 1.8GHz matching, tone spacing = 20MHz, DSA = 4dB Figure 4-332. RX IMD3 vs Input Level and Temperature at 1.75GHz Input Amplitude (dBFS) IMD3 (dBFS) -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -40 qC 25 qC 110qC With 1.8GHz matching, tone spacing = 20MHz, DSA = 12dB Figure 4-333. RX IMD3 vs Input Level and Temperature at 1.75GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.9 RX Typical Characteristics at 1.75-1.9GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Input Amplitude (dBFS) HD3 (dBFS) -120 -110 -100 -90 -80 -70 -60 -50 1RX, DSA=4dB 1RX, DSA=12dB 2RX, DSA=4dB 2RX, DSA=12dB 3RX, DSA=4dB 3RX, DSA=12dB 4RX, DSA = 4dB 4RX, DSA = 12dB With 1.8GHz matching, fin = 1900MHz, DDC bypass mode (TI only mode for characterization) Figure 4-340. RX HD3 vs Input Level and Channel at 1.9GHz Input Amplitude (dBFS) HD3 (dBFS) -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -40 qC, DSA=4dB -40 qC, DSA=12dB 25 qC, DSA=4dB 25 qC, DSA=12dB 110 qC, DSA=4dB 110 qC, DSA=12dB With 1.8GHz matching, fin = 1900MHz, DDC bypass mode (TI only mode for characterization) Figure 4-341. RX HD3 vs Input Level and Temperature at 1.9GHz Input Amplitude (dBFS) Inband SFDR (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 1RX, 2RX 3RX 4RX With 1.8GHz matching, decimated by 3 Figure 4-342. RX In-Band SFDR (±400MHz) vs Input Amplitude at 1.75GHz DSA (dB) Non HD2/3 SFDR (dBFS) 0 2 4 6 8 10 12 14 16 79.2 79.4 79.6 79.8 80.2 80.4 80.6 80.8 1RX 2RX 3RX 4RX With 1.8GHz matching Figure 4-343. RX Non-HD2/3 vs DSA Setting at 1.75GHz Supply Voltage IMD3 (dBFS) -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 MIN TYP MAX 1RX 2RX 3RX 4RX With 1.8GHz matching, –7dBFS each tone, 20MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-344. RX IMD3 vs Supply and Channel at 1.75GHz Supply Voltages NSD (dBFS) -156 -155.5 -155 -154.5 -154 -153.5 -153 -152.5 -152 -151.5 -151 MIN TYP MAX 1RX 2RX 3RX 4RX With 1.8GHz matching, 12.5MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-345. RX Noise Spectral Density vs Supply and Channel at 1.75GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.10 RX Typical Characteristics at 2.6GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Input Amplitude (dBFS) NSD (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 -156 -154 -152 -150 -148 -146 1RX, DSA=4 1RX, DSA=12 2RX, DSA=4 2RX, DSA=12 3RX, DSA=4 3RX, DSA=12 4RX, DSA=4 4RX, DSA=12 With 2.6GHz matching, 12.5MHz offset from tone Figure 4-352. RX Noise Spectral Density vs Input Amplitude and Channel at 2.6GHz DSA Setting (dB) IMD3 (dBFS) 0 2 4 6 8 10 12 14 16 -90 -85 -80 -75 -70 -65 -60 Temp=-40qC Temp=25qC Temp=110qC With 2.6GHz matching, each tone –7dBFS, tone spacing = 20MHz Figure 4-353. RX IMD3 vs DSA Setting and Temperature at 2.6GHz Input Level (dBFS) IMD3 (dBFS) -40 -35 -30 -25 -20 -15 -10 -5 0 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 Temp=-40qC Temp=25qC Temp=110qC With 2.6GHz matching, tone spacing = 20MHz, DSA = 4dB Figure 4-354. RX IMD3 vs Input Level and Temperature at 2.6GHz Input Level (dBFS) IMD3 (dBFS) -40 -35 -30 -25 -20 -15 -10 -5 0 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 Temp=-40qC Temp=25qC Temp=110qC With 2.6GHz matching, tone spacing = 20MHz, DSA = 12dB Figure 4-355. RX IMD3 vs Input Level and Temperature at 2.6GHz DSA Setting (dB) HD2 (dBc) 2 4 6 8 10 12 14 16 18 20 -100 -95 -90 -85 -80 -75 -70 -65 -60 1RX 2RX 3RX 4RX With 2.6GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-356. RX HD2 vs DSA Setting and Channel at 2.6GHz Input Level (dBFS) HD2 (dBFS) -30 -25 -20 -15 -10 -5 0 -110 -105 -100 -95 -90 -85 -80 -75 -70 Temp=-40qC Temp=25qC Temp=110qC With 2.6GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-357. RX HD2 vs Input Level and Temperature at 2.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.10 RX Typical Characteristics at 2.6GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. S u p p l y V o l t a g e s IMD3 (dBFS) - 9 0 - 8 8 - 8 6 - 8 4 - 8 2 - 8 0 - 7 8 - 7 6 - 7 4 - 7 2 - 7 0 M I N T Y P M A X

1 R X

2 R X

3 R X

4 R X

With 2.6GHz matching, –7dBFS each tone, 20MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-364. RX IMD3 vs Supply and Channel at 2.6GHz S u p p l y V o l t a g e s NSD (dBFS/Hz) - 1 5 4 - 1 5 3 . 5 - 1 5 3 - 1 5 2 . 5 - 1 5 2 - 1 5 1 . 5 - 1 5 1 - 1 5 0 . 5 - 1 5 0 M I N T Y P M A X With 2.6GHz matching, 12.5MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-365. RX Noise Spectral Density vs Supply and Channel at 2.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.11 RX Typical Characteristics at 3.5GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. DSA Setting (dB) Differential Phase Error (q) 0 5 10 15 20 25 -1.5 -0.5 0.5 1.5 -40qC 25qC 105qC With 3.6GHz matching Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting) Figure 4-372. RX Uncalibrated Phase Error vs DSA Setting at 3.6GHz DSA Setting (dB) Differential Phase Error (q) 0 5 10 15 20 25 -2.5 -1.5 -0.5 0.5 1.5 2.5 -40qC 25qC 105qC With 3.6GHz matching Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting) Figure 4-373. RX Calibrated Differential Phase Error vs DSA Setting at 3.6GHz DSA Setting (dB) Phase Integrated Nonlinearity (q) 0 5 10 15 20 25 -40qC 25qC 105qC With 3.6GHz matching Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-374. RX Uncalibrated Integrated Phase Error vs DSA Setting at 3.6GHz DSA Setting (dB) Integrated Phase Error (q) 0 5 10 15 20 25 -2.5 -1.5 -0.5 0.5 1.5 2.5 -40qC 25qC 105qC With 3.6GHz matching Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-375. RX Calibrated Integrated Phase Error vs DSA Setting at 3.6GHz Frequency (MHz) Amplitude (dBFS) -250 250 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR=62.2dBFS With 3.6GHz matching , fIN = 3610MHz, AIN = –3dBFS Figure 4-376. RX Output FFT at 3.6GHz DSA Setting (dB) IMD3 (dBFS) 0 2 4 6 8 10 12 14 16 -90 -85 -80 -75 -70 -65 -60 Temp=-40qC Temp=25qC Temp=110qC With 3.5 GHz matching, each tone at –7dBFS, 20MHz tone spacing Figure 4-377. RX IMD3 vs DSA Setting and Temperature at 3.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.11 RX Typical Characteristics at 3.5GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. DSA (dB) HD3 (dBc) 3 6 9 12 15 18 -79 -76 -73 -70 -67 -64 -40qC 25qC 110qC With 3.5GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-384. RX HD3 vs DSA Setting and Temperature at 3.6GHz Input Amplitude (dBFS) HD3 (dBFS) -30 -25 -20 -15 -10 -5 0 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 1RX 2RX 3RX 4RX With 3.5GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-385. RX HD3 vs Input Level and Channel at 3.6GHz Input Level (dBFS) HD3 (dBFS) -30 -25 -20 -15 -10 -5 0 -110 -105 -100 -95 -90 -85 -80 -75 -70 Temp=-40qC Temp=25qC Temp=110qC With 3.5GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-386. RX HD3 vs Input Level and Temperature at 3.6GHz Input Level (dBFS) Noise Spectral Density (dBFS) -30 -25 -20 -15 -10 -5 0 -160 -158 -156 -154 -152 -150 -148 -146 -144 -142 -140 1RX, DSA=4dB 1RX, DSA=12dB 2RX, DSA=4dB 2RX, DSA=12dB 3RX, DSA=4dB 3RX, DSA=12dB 4RX, DSA=4dB 4RX, DSA=12dB With 3.5GHz matching, 12.5-MHz offset from tone Figure 4-387. RX Noise Spectral Density vs Input Level and DSA Setting at 3.6GHz Input Amplitude (dBFS) In-band SFDR (dBFS) -30 -25 -20 -15 -10 -5 0 100 105 110 1RX 2RX 3RX 4RX With 3.5GHz matching Figure 4-388. RX In-Band SFDR (±200MHz) vs Input Level and Channel at 3.6GHz DSA Setting (dB) SFDR excl. HD2/3 (dBc) 0 2 4 6 8 10 12 14 16 18 1RX 2RX 3RX 4RX With 3.5GHz matching Figure 4-389. RX SFDR Excluding HD2/3 vs DSA Setting and Channel at 3.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.11 RX Typical Characteristics at 3.5GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. S u p p l y V o l t a g e s IMD3 (dBFS) - 9 0 - 8 8 - 8 6 - 8 4 - 8 2 - 8 0 - 7 8 - 7 6 - 7 4 - 7 2 - 7 0 M I N T Y P M A X With 3.6GHz matching, –7dBFS each tone, 20MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-390. RX IMD3 vs Supply Voltage and Channel at 3.6GHz S u p p l y V o l t a g e s IMD5 (dBFS) - 1 1 0 - 1 0 8 - 1 0 6 - 1 0 4 - 1 0 2 - 1 0 0 - 9 8 - 9 6 - 9 4 - 9 2 - 9 0 M I N T Y P M A X With 3.6GHz matching, –7dBFS each tone, 20-MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-391. RX IMD5 vs Supply Voltage and Channel at 3.6GHz S u p p l y V o l t a g e s NSD (dBFS/Hz) - 1 5 6 - 1 5 5 . 5 - 1 5 5 - 1 5 4 . 5 - 1 5 4 - 1 5 3 . 5 - 1 5 3 - 1 5 2 . 5 - 1 5 2 M I N T Y P M A X With 3.6GHz matching, tone at 20 dBFS, 12.5MHz offset frequency, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-392. RX Noise Spectral Density vs Supply Voltage and Channel at 3.6GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: AFE7950-SP

4.12.12 RX Typical Characteristics at 4.9GHz Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Output Frequency (MHz) Relative Input Power (dB) 4700 4800 4900 5000 5100 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 DSA=4dB DSA=6dB DSA=8dB DSA=10dB DSA=12dB DSA=14dB With matching, normalized to power at 4.9GHz for each DSA setting Figure 4-393. RX Inband Gain Flatness, fIN = 4900MHz Temperature (qC) Input FS (dB) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -2.3 -1.7 -1.4 -1.1 -0.8 -0.5 -0.2 0.1 0.4 0.7 1RX 2RX 3RX 4RX With 4.9GHz matching, normalized to fullscale at 25°C for each channel Figure 4-394. RX Input Fullscale vs Temperature and Channel at 4.9GHz Temperature (qC) Input Phase (degree) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -35 -25 -15 1RX 2RX 3RX 4RX With 4.9GHz matching, normalized to phase at 25°C Figure 4-395. RX Input Phase vs Temperature and DSA at fOUT = 4.9GHz DSA (dB) Uncalibrated Differential Gain Error (dB) 0 5 10 15 20 25 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 1RX 2RX 3RX 4RX With 4.9GHz matching Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1 Figure 4-396. RX Uncalibrated Differential Amplitude Error vs DSA Setting at 4.9GHz DSA (dB) Calibrated Differential Gain Error (dB) 0 5 10 15 20 25 -0.025 -0.02 -0.015 -0.01 -0.005 0.005 0.01 0.015 0.02 0.025 0.03 1RX 2RX 3RX 4RX With 4.9GHz matching Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1 Figure 4-397. RX Calibrated Differential Amplitude Error vs DSA Setting at 4.9GHz DSA (dB) Uncalibrated Integrated Gain Error (dB) 0 5 10 15 20 25 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.2 1RX 2RX 3RX 4RX With 4.9GHz matching Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting) Figure 4-398. RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 4.9GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.12 RX Typical Characteristics at 4.9GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Temperature (qC) Noise (dBFS/Hz) -40 -25 -10 5 20 35 50 65 80 95 110 -156 -155.8 -155.6 -155.4 -155.2 -155 -154.8 DSA = 4dB DSA = 12dB With 4.9GHz matching, 12.5-MHz offset from tone Figure 4-405. RX Noise Spectral Density vs Temperature at 4.9GHz Input Amplitude (dBFS) Noise (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 -157 -156 -155 -154 -153 -152 -151 -150 -149 -148 -147 -146 -145 -40 qC, DSA = 4dB -40 qC, DSA = 12dB 25 qC, DSA = 4dB 25 qC, DSA = 12dB 110 qC, DSA = 4dB 110 qC, DSA = 12dB With 4.9GHz matching, DSA Setting = 12dB, 12.5MHz offset from tone Figure 4-406. RX Noise Spectral Density vs Input Amplitude and Temperature at 4.9GHz Input Amplitude (dBFS) Noise (dBFS/Hz) -30 -25 -20 -15 -10 -5 0 -157 -156 -155 -154 -153 -152 -151 -150 -149 -148 -147 -146 -145 1RX, DSA = 4dB 1RX, DSA = 12dB 2RX, DSA = 4dB 2RX, DSA = 12dB 3RX, DSA = 4dB 3RX, DSA = 12dB 4RX, DSA = 4dB 4RX, DSA = 12dB With 4.9GHz matching, 12.5MHz offset from tone Figure 4-407. RX Noise Spectral Density vs Input Amplitude and Channel at 4.9GHz DSA (dB) IMD3 (dBFS) 0 2 4 6 8 10 12 14 16 18 20 -94 -89 -84 -79 -74 -69 -64 -40 qC 25 qC 110qC With 4.9GHz matching, each tone –7dBFS, tone spacing = 20MHz Figure 4-408. RX IMD3 vs DSA Setting and Temperature at 4.9GHz Input Amplitude (dBFS) IMD3 (dBFS) -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -40 qC 25 qC 110qC With 4.9GHz matching, tone spacing = 20MHz, DSA = 4dB Figure 4-409. RX IMD3 vs Input Level and Temperature at 4.9GHz Input Amplitude (dBFS) IMD3 (dBFS) -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -40 qC 25 qC 110qC With 4.9GHz matching, tone spacing = 20MHz, DSA = 12dB Figure 4-410. RX IMD3 vs Input Level and Temperature at 4.9GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.12 RX Typical Characteristics at 4.9GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB. Input Amplitude (dBFS) HD3 (dBFS) -108 -105 -102 -99 -96 -93 -90 -87 -84 -81 -78 -75 -72 -69 -66 -40 qC 25 qC 110qC With 4.9GHz matching, DDC bypass mode (TI only mode for characterization) Figure 4-417. RX HD3 vs Input Level and Temperature at 4.9GHz Input Amplitude (dBFS) Inband SFDR (dBFS) 102 1RX 2RX 3RX 4RX With 4.9GHz matching, decimate by 3 Figure 4-418. RX In-Band SFDR (±400 MHz) vs Input Amplitude and Channel at 4.9GHz DSA (dB) Non HD2/3 SFDR (dBFS) 0 2 4 6 8 10 12 14 16 79.5 80.5 81.5 82.5 1RX 2RX 3RX 4RX With 4.9GHz matching Figure 4-419. RX Non-HD2/3 vs DSA Setting at 4.9GHz Supply Voltage IMD3 (dBFS) -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 MIN TYP MAX 1RX 2RX 3RX 4RX With 4.9GHz matching, –7dBFS each tone, 20MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-420. RX IMD3 vs Supply and Channel at 4.9GHz Supply Voltages NSD (dBFS) -156 -155.5 -155 -154.5 -154 -153.5 -153 -152.5 -152 -151.5 -151 MIN TYP MAX 1RX 2RX 3RX 4RX With 4.9GHz matching, 12.5MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages Figure 4-421. RX Noise Spectral Density vs Supply and Channel at 4.9GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.13 RX Typical Characteristics at 8.1GHz Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 1474.56MSPS (decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3dBFS, DSA setting = 3 dB, 8.1GHz matching. I n p u t F r e q u e n c y ( M H z ) Amplitude (dB) 7 4 0 0 7 6 0 0 7 8 0 0 8 0 0 0 8 2 0 0 8 4 0 0 8 6 0 0 8 8 0 0 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 Normalized to 8.11GHz Figure 4-422. RX Amplitude vs Frequency and Channel I n p u t F r e q u e n c y ( M H z ) Amplitude (dB) 7 4 0 0 7 6 0 0 7 8 0 0 8 0 0 0 8 2 0 0 8 4 0 0 8 6 0 0 8 8 0 0 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 D S A = 0 d B D S A = 4 d B D S A = 8 d B D S A = 1 2 d B D S A = 1 6 d B D S A = 2 0 d B D S A = 2 4 d B 1RX and 3RX, Normalized to 8.11GHz Figure 4-423. RX Amplitude vs Frequency and DSA Setting I n p u t F r e q u e n c y ( M H z ) Amplitude (dB) 7 4 0 0 7 6 0 0 7 8 0 0 8 0 0 0 8 2 0 0 8 4 0 0 8 6 0 0 8 8 0 0 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 D S A = 0 d B D S A = 4 d B D S A = 8 d B D S A = 1 2 d B D S A = 1 6 d B D S A = 2 0 d B D S A = 2 4 d B 2RX and 4RX, Normalized to 8.11GHz Figure 4-424. RX Amplitude vs Frequency and DSA Setting D S A S e t t i n g ( d B ) Amplitude Differential Non-linearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 5 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 n o c a l , - 4 0  C n o c a l , 2 5  C n o c a l , 1 1 0  C a f t e r c a l , - 4 0  C a f t e r c a l , 2 5  C a f t e r c a l , 1 1 0  C Figure 4-425. RX Amplitude Differential Nonlinearity at 8.11GHz Figure 4-426. RX Amplitude Integrated Nonlinearity at 8.11GHz D S A S e t t i n g ( d B ) Phase Differential Non-linearity (degrees) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 5 - 5 - 4 - 3 - 2 - 1 n o c a l , - 4 0  C n o c a l , 2 5  C n o c a l , 1 1 0  C a f t e r c a l , - 4 0  C a f t e r c a l , 2 5  C a f t e r c a l , 1 1 0  C Figure 4-427. RX Phase Differential Nonlinearity at 8.11GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: AFE7950-SP

4.12.13 RX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 1474.56MSPS (decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3dBFS, DSA setting = 3 dB, 8.1GHz matching. D S A S e t t i n g ( d B ) Phase Differential Non-linearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 5 - 1 0 - 8 - 6 - 4 - 2 1 0 n o c a l , - 4 0  C n o c a l , 2 5  C n o c a l , 1 1 0  C a f t e r c a l , - 4 0  C a f t e r c a l , 2 5  C a f t e r c a l , 1 1 0  C Figure 4-428. RX Phase Differential Nonlinearity at 8.11GHz I n p u t A m p l i t u d e p e r T o n e ( d B F S ) IMD3 (dBFS) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 4 0  C 2 5  C 1 1 0  C 50MHz tone spacing Figure 4-429. RX IMD3 vs Input Amplitude at 8.11GHz D S A S e t t i n g ( d B ) IMD3 (dBFS) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 A I N = - 1 3 d B F S , - 4 0  C A I N = - 1 3 d B F S , 2 5  C A I N = - 1 3 d B F S , 1 1 0  C A I N = - 7 . d B F S , - 4 0  C A I N = - 7 d B F S , 2 5  C A I N = - 7 d B F S , 1 1 0  C 50MHz tone spacing Figure 4-430. RX IMD3 vs DSA Setting at 8.11GHz Figure 4-431. RX IMD3 vs Tone Spacing at 8.11GHz Figure 4-432. RX NSD vs Digital Amplitude at 8.11GHz I n p u t A m p l i t u d e ( d B F S ) NSD (dBFS/Hz) - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 - 1 5 4 - 1 5 3 - 1 5 2 - 1 5 1 - 1 5 0 - 1 4 9 - 1 4 8 - 1 4 7 - 1 4 6 - 1 4 5 - 1 4 4

1 R X , D S A = 3 d B

1 R X , D S A = 1 2 d B

2 R X , D S A = 3 d B

2 R X , D S A = 1 2 d B

3 R X , D S A = 3 d B

3 R X , D S A = 1 2 d B

4 R X , D S A = 3 d B

4 R X , D S A = 1 2 d B Figure 4-433. RX NSD vs Digital Amplitude at 8.11GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: AFE7950-SP

4.12.13 RX Typical Characteristics at 8.1GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 1474.56MSPS (decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3dBFS, DSA setting = 3 dB, 8.1GHz matching. D i g i t a l A m p l i t u d e p e r T o n e ( d B F S ) 2-tone SFDR (dBFS) - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 - 1 0 0 - 9 7 . 5 - 9 5 - 9 2 . 5 - 9 0 - 8 7 . 5 - 8 5 - 8 2 . 5 - 8 0 - 7 7 . 5 - 7 5 - 7 2 . 5 - 4 0  C 2 5  C 1 1 0  C 50MHz Tone Spacing Figure 4-440. RX 2-tone SFDR vs Digital Amplitude at 8.11GHz F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 External clock mode Figure 4-441. RX Single Tone Output FFT at 8.11GHz, -1dBFS F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 External clock mode Figure 4-442. RX Single Tone Output FFT at 8.11GHz, -12dBFS F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 External clock mode Figure 4-443. RX Single Tone Output FFT at 8.11GHz, -30 dBFS F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 External clock mode Figure 4-444. RX Single Tone Output FFT at 8.11GHz, -60 dBFS F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 External clock mode, -7dBFS each tone Figure 4-445. RX Dual Tone Output FFT at 8.11GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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4.12.14 RX Typical Characteristics at 9.6GHz Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 1474.56MSPS (decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3dBFS, DSA setting = 3 dB, 9.6GHz matching. I n p u t F r e q u e n c y ( M H z ) Input Amplitude (dB) 9 0 0 0 9 2 0 0 9 4 0 0 9 6 0 0 9 8 0 0 1 0 0 0 0 1 0 2 0 0 - 2 . 5 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 2 . 5 D S A = 3 d B , 1 R X D S A = 3 d B , 2 R X D S A = 3 d B , 3 R X D S A = 3 d B , 4 R X D S A = 1 2 d B , 1 R X D S A = 1 2 d B , 2 R X D S A = 1 2 d B , 3 R X D S A = 1 2 d B , 4 R X Normalized to 9.6GHz Figure 4-449. RX Input Amplitude vs Frequency I n p u t F r e q u e n c y ( M H z ) Input Amplitude (dB) 9 0 0 0 9 2 0 0 9 4 0 0 9 6 0 0 9 8 0 0 1 0 0 0 0 1 0 2 0 0 - 2 . 5 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 2 . 5 D S A = 0 d B D S A = 4 d B D S A = 8 d B D S A = 1 2 d B D S A = 1 6 d B D S A = 2 0 d B D S A = 2 4 d B Normalized to 9.6GHz Figure 4-450. RX Input Amplitude vs Frequency at 9.6GHz D S A S e t t i n g ( d B ) Amplitude Differential Non-linearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 5 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 n o c a l , - 4 0  C n o c a l , 2 5  C n o c a l , 1 1 0  C a f t e r c a l , - 4 0  C a f t e r c a l , 2 5  C a f t e r c a l , 1 1 0  C Figure 4-451. RX Amplitude Differential Non-linearity at 9.6GHz D S A S e t t i n g ( d B ) Amplitude Integral Non-linearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 5 - 5 - 4 - 3 - 2 - 1 n o c a l , - 4 0  C n o c a l , 2 5  C n o c a l , 1 1 0  C a f t e r c a l , - 4 0  C a f t e r c a l , 2 5  C a f t e r c a l , 1 1 0  C Figure 4-452. RX Amplitude Integrated Non-linearity at 9.6GHz D S A S e t t i n g ( d B ) Phase Differential Non-linearity (degrees) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 5 - 5 - 4 - 3 - 2 - 1 n o c a l , - 4 0  C n o c a l , 2 5  C n o c a l , 1 1 0  C a f t e r c a l , - 4 0  C a f t e r c a l , 2 5  C a f t e r c a l , 1 1 0  C Figure 4-453. RX Phase Differential Non-linearity at 9.6GHz D S A S e t t i n g ( d B ) Phase Differential Non-linearity (dB) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 5 - 1 0 - 8 - 6 - 4 - 2 1 0 n o c a l , - 4 0  C n o c a l , 2 5  C n o c a l , 1 1 0  C a f t e r c a l , - 4 0  C a f t e r c a l , 2 5  C a f t e r c a l , 1 1 0  C Figure 4-454. RX Phase Integrated Non-linearity at 9.6GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: AFE7950-SP

4.12.14 RX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 1474.56MSPS (decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3dBFS, DSA setting = 3 dB, 9.6GHz matching. I n p u t A m p l i t u d e p e r T o n e ( d B F S ) IMD3 (dBFS) - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 4 0  C 2 5  C 1 1 0  C Figure 4-455. RX IMD3 vs Digital Amplitude at 9.6GHz D S A S e t t i n g ( d B ) IMD3 (dBFS) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 A I N = - 1 3 d B F S , - 4 0  C A I N = - 1 3 d B F S , 2 5  C A I N = - 1 3 d B F S , 1 1 0  C A I N = - 7 . d B F S , - 4 0  C A I N = - 7 d B F S , 2 5  C A I N = - 7 d B F S , 1 1 0  C 50MHz tone spacing Figure 4-456. RX IMD3 vs DSA Setting at 9.6GHz D S A S e t t i n g ( d B ) IMD3 (dBFS) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 A I N = - 1 3 d B F S , - 4 0  C A I N = - 1 3 d B F S , 2 5  C A I N = - 1 3 d B F S , 1 1 0  C A I N = - 7 . d B F S , - 4 0  C A I N = - 7 d B F S , 2 5  C A I N = - 7 d B F S , 1 1 0  C 50MHz tone spacing Figure 4-457. RX IMD3 vs DSA Setting at 9.6GHz T o n e S p a c i n g ( M H z ) IMD3 (dBFS) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 A I N = - 3 0 d B F S , - 4 0  C A I N = - 3 0 d B F S , 2 5  C A I N = - 3 0 d B F S , 1 1 0  C A I N = - 1 3 d B F S , - 4 0  C A I N = - 1 3 d B F S , 2 5  C A I N = - 1 3 d B F S , 1 1 0  C 50MHz tone spacing Figure 4-458. RX IMD3 vs Tone Spacing at 9.6GHz I n p u t A m p l i t u d e ( d B F S ) NSD (dBFS/Hz) - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 - 1 5 4 - 1 5 3 - 1 5 2 - 1 5 1 - 1 5 0 - 1 4 9 - 1 4 8 - 1 4 7 - 1 4 6 - 1 4 5 - 1 4 4

1 R X , - 4 0  C

1 R X , 2 5  C

1 R X , 1 1 0  C

2 R X , - 4 0  C

2 R X , 2 5  C

2 R X , 1 1 0  C

3 R X , - 4 0  C

3 R X , 2 5  C

3 R X , 1 1 0  C

4 R X , - 4 0  C

4 R X , 2 5  C

4 R X , 1 1 0  C

Figure 4-459. RX NSD vs Digital Amplitude at 9.6GHz Figure 4-460. RX NSD vs Digital Amplitude at 9.6GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: AFE7950-SP

4.12.14 RX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 1474.56MSPS (decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3dBFS, DSA setting = 3 dB, 9.6GHz matching. D S A S e t t i n g ( d B ) Noise Spectral Density (dBFS/Hz) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 - 1 6 0 - 1 5 8 - 1 5 6 - 1 5 4 - 1 5 2 - 1 5 0 - 1 4 8 - 1 4 6 - 1 4 4 - 1 4 2 - 1 4 0 A I N = - 1 2 d B F S , - 4 0  C A I N = - 1 2 d B F S , 2 5  C A I N = - 1 2 d B F S , 1 1 0  C A I N = - 6 d B F S , - 4 0  C A I N = - 6 d B F S , 2 5  C A I N = - 6 d B F S , 1 1 0  C A I N = - 1 d B F S , - 4 0  C A I N = - 1 d B F S , 2 5  C A I N = - 1 d B F S , 1 1 0  C Figure 4-461. RX NSD vs DSA Setting at 9.6GHz I n p u t A m p l i t u d e ( d B F S ) HD2 (dBFS) - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 - 1 2 0 - 1 1 5 - 1 1 0 - 1 0 5 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 4 0  C 2 5  C 1 1 0  C Figure 4-462. RX HD2 vs Digital Level at 9.6GHz D S A S e t t i n g ( d B ) HD2 (dBFS) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 A I N = - 1 2 d B F S , - 4 0  C A I N = - 1 2 d B F S , 2 5  C A I N = - 1 2 d B F S , 1 1 0  C A I N = - 6 d B F S , - 4 0  C A I N = - 6 d B F S , 2 5  C A I N = - 6 d B F S , 1 1 0  C A I N = - 1 d B F S , - 4 0  C A I N = - 1 d B F S , 2 5  C A I N = - 1 d B F S , 1 1 0  C Figure 4-463. RX HD2 vs DSA Setting at 9.6GHz I n p u t A m p l i t u d e ( d B F S ) HD3 (dBFS) - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0  C 2 5  C 1 1 0  C Figure 4-464. RX HD3 vs Digital Level at 9.6GHz D S A S e t t i n g ( d B ) HD3 (dBFS) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 A I N = - 1 2 d B F S , - 4 0  C A I N = - 1 2 d B F S , 2 5  C A I N = - 1 2 d B F S , 1 1 0  C A I N = - 6 d B F S , - 4 0  C A I N = - 6 d B F S , 2 5  C A I N = - 6 d B F S , 1 1 0  C A I N = - 1 d B F S , - 4 0  C A I N = - 1 d B F S , 2 5  C A I N = - 1 d B F S , 1 1 0  C Figure 4-465. RX HD3 vs DSA Setting at 9.6GHz F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 0 -1dBFS Figure 4-466. RX Single Tone Output FFT at 9.61 GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: AFE7950-SP

4.12.14 RX Typical Characteristics at 9.6GHz (continued) Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 1474.56MSPS (decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3dBFS, DSA setting = 3 dB, 9.6GHz matching. F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 9.61 and 9.635GHz , -30dBFS each tone Figure 4-473. RX Two Tone Output FFT at 9.61GHz F r e q u e n c y ( M H z ) Amplitude (dBFS) - 7 5 0 - 5 0 0 - 2 5 0 0 2 5 0 5 0 0 7 5 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 9.61 and 9.635GHz , -60dBFS each tone Figure 4-474. RX Two Tone Output FFT at 9.61GHz AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com

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5 Device and Documentation Support

5.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

5.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

5.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

5.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

5.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

6 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from March 6, 2024 to August 1, 2024 (from Revision * (March 2024) to Revision A (August 2024)) Page

7 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: AFE7950-SP

www.ti.com 26-Feb-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AFE7950ALKSHP Active Production FCBGA (ALK) | 400 90 | JEDEC TRAY (5+1) No Call TI Call TI -40 to 85 AFE7950SHP SNPB SN0400ALK-DC Active Production FCBGA (ALK) | 400 90 | JEDEC TRAY (5+1) - Call TI Call TI -45 to 105 AFE7950ALKDC SNPB (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF AFE7950-SP : Addendum-Page 1

www.ti.com 26-Feb-2026

Catalog : AFE7950 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) AFE7950ALKSHP ALK FCBGA 400 90 6 x 15 150 315 135.9 7620 19.5 21 19.2 Pack Materials-Page 1

www.ti.com PACKAGE OUTLINE C 2.65 2.29 0.5

0.3 TYP

15.2 TYP

0.8 TYP

400X 0.55 0.45 0.76 0.56 (1.4) A17.2 16.8 B 17.2 16.8 (0.9) TYP ( 16) FCBGA - 2.65 mm max heightALK0400A BALL GRID ARRAY 4225930/C 03/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C. 4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls. 5. Pb-Free die bump and SnPb solder ball. 6. The lids are electrically floating (e.g. not tied to GND). BALL A1 CORNER SEATING PLANE BALL TYP 0.12 C NOTE 4 0.2 C W U R N L J G E C A

0.15 C A B

0.08 C SYMM SYMM NOTE 3 15 17 19 16 18 20 Y V T P M K H F D B SCALE 0.750

www.ti.com EXAMPLE BOARD LAYOUT 400X ( 0.4) (0.8) TYP (0.8) TYP ( 0.4) METAL

0.025 MAX

( 0.4) SOLDER MASK OPENING

0.025 MIN

FCBGA - 2.65 mm max heightALK0400A BALL GRID ARRAY 4225930/C 03/2023 NOTES: (continued) 7. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X 1 20A Y B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.8) TYP (0.8) TYP ( 0.4) TYP FCBGA - 2.65 mm max heightALK0400A BALL GRID ARRAY 4225930/C 03/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:6X 1 20A Y B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

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Product Information

SN0400ALK-DC specifications and overview.

Summary

AFE7950-x 4T6R RF Sampling AFE with 12GSPS DACs and 3GSPS ADCs REVISED AUGUST 2024

Description

AFE7950-x 4T6R RF Sampling AFE with 12GSPS DACs and 3GSPS ADCs REVISED AUGUST 2024

Source title SN0400ALK-DC Datasheet(PDF) - Texas Instruments

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