SMX320CC6713BGJCM20EP

SM320C6713-EP TI | Alldatasheet

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date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SGUS049H August 2003 Revised September 2008

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 10.3.2 Power-Supply Design Considerations 10.4 Power-Supply Decoupling 10.5 IEEE Std 1149.1 JTAG Compatibility Statement 10.6 EMIF Device Speed 10.7 EMIF Big Endian Mode Correctness (C6713B Only) 10.8 Bootmode PARAMETRIC INFORMATION 11.1 Absolute Maximum Ratings 11.2 Recommended Operating Conditions 11.3 Electrical Characteristics 11.4 Parameter Measurement Information 11.4.1 Timing Information 11.4.2 Signal Transition Levels 11.4.3 Timing Parameters and Board Routing Analysis 11.5 Input and Output Clocks 11.6 Asynchronous Memory Timing 11.7 Synchronous-Burst Memory Timing 11.8 Synchronous DRAM Timing 11.9 HOLD HOLDA Timing 11.10 BUSREQ Timing 11.11 Reset Timing 100 11.12 External Interrupt Timing 102 11.13 Multichannel Audio Serial Port (McASP) Timing 103 11.14 Inter-Integrated Circuits Timing 106 11.15 Host-Port Interface Timing 108 11.16 Multichannel Buffered Serial Port (McBSP) Timing 112 11.17 Timer Timing 119 11.18 General-Purpose Input/Output (GPIO) Port Timing 120 11.19 JTAG Test Port Timing 121 MECHANICAL DATA 122 12.1 Mechanical Information 122 12.2 Packaging Information 122

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FEATURES

DEFENSE, AEROSPACE, AND MEDICAL

APPLICATIONS

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Bit External Memory Interface (EMIF) Highest Performance Floating Point Digital Signal Processors (DSPs): C6713/C6713B Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM Eight Bit Instructions/Cycle 512M Byte Total Addressable External Bit Data Word Memory Space 200 and 300 MHz Clock Rate Enhanced Direct Memory Access (EDMA) Instruction Cycle Times Controller (16 Independent Channels) and MIPS/MFLOPS Bit Host Port Interface (HPI) Rich Peripheral Set, Optimized for Audio Highly Optimized C/C++ Compiler Two Multichannel Audio Serial Ports (McASPs) Two Independent Clock Zones Each Advanced Very Long Instruction Word (VLIW) (One TX and One RX) 320C67x DSP Core Eight Serial Data Pins Per Port: Individually Eight Independent Functional Units: Assignable to any of the Clock Zones Two ALUs (Fixed Point) Wide Variety of I S and Similar Bit Stream Four ALUs (Floating Point and Fixed Formats Point) Integrated Digital Audio Interface Two Multipliers (Floating Point and Transmitter (DIT) Fixed Point) Extensive Error Checking and Recovery Load Store Architecture With 32-Bit Two Inter-Integrated Circuit Bus C Bus) General Purpose Registers Multi-Master and Slave Interfaces Instruction Packing Reduces Code Size All Instructions Conditional Two Multichannel Buffered Serial Ports: Serial Peripheral Interface (SPI) Instruction Set (8/16/32 Bit Data) Bit Overflow Protection Two Bit General Purpose Timers Saturation; Bit-Field Extract, Set, Clear; Dedicated GPIO Module With Pins (External Bit-Counting; Normalization Interrupt Capable) L1/L2 Memory Architecture Flexible Phase Locked Loop (PLL) Based Byte L1P Program Cache Clock Generator Module (Direct-Mapped) IEEE-1149.1 (JTAG) (1) Boundary-Scan Byte L1D Data Cache (2-Way) Compatible 256K Byte Memory Total: 64K-Byte 272 Ball, Ball Grid Array Package (GDP) Unified Cache/Mapped RAM, and 192K Byte 0.13 µ m/6 Level Copper Metal Process Additional Mapped RAM CMOS Technology Device Configuration 3.3 V I/Os, 1.26 V Internal Boot Mode: HPI, 8/16/32 Bit ROM Boot (1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Endianness: Little Endian, Big Endian Boundary Scan Architecture. break Controlled Baseline Extended Product Life Cycle One Assembly/Test Site Extended Product-Change Notification One Fabrication Site Product Traceability Available in Military C/125 Temperature Range (2) (2) Custom temperature ranges available Please be aware that an important notice concerning availability, standard warranty, and use in critical document. PRODUCTION DATA information is current as of publication date. Copyright 2003 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Y W V U T R P N M L K J H G F E D C B A EA20DV DDEA18EA16EA14VSS CLKOUT2/ GP[2]ECLKINECLKOUTEA9EA7DVDDEA2ARDYBE2ED18VSSVSS VSS CVDD DVDD ED17 VSS CE2 EA4 EA6 DVDD AOE SDRAS SSOE AWE SDWE SSWE ARE SDCAS SSADS VSS DVDD EA11 EA13 EA15 VSS EA19 CE1 CVDD VSS BE0DVDDCVDDCE0EA17DVDDEA12DVDDEA10EA8EA5EA3CE3BE3ED16CVDDED19ED20 ED22 ED28 SCL0 FSX1 CLKR1/ AXR0[6] DR1/ SDA1 DR0/ AXR0[0] DX0/ AXR0[1] FSR1/ AXR0[7] DVDD ED24 ED21 ED29 SDA0 DX1 AXR0[5] CLKX1/ AMUTE0 CLKS1/ SCL1 GP[5] (EXT_INT5) AMUTEIN0 GP[4] (EXT_INT4) AMUTEIN1 GP[7] (EXT_INT7) GP[6] (EXT_INT6) CLKS0 AHCLKR0 ED27 ED25 ED23 ED30 ED31 ED26 DVDD EA21 BE1 VSSVSS VSS VSS CVDD VSS CVDD VSS DVDD CVDD DVDD VSS VSS VSS VSSCVDD CVDDCVDD CVDDDVDD DVDD VSS VSS VSS CVDD CVDD CVDD VSS ED13 ED6 ED9 DVDD ED2 ED0 DVDD ED15 ED7 VSS ED11 ED3 ED1 ED4 ED14 ED8 ED10 ED12 CVDD VSS ED5 HOLD HINT/ GP[1] HRDY/ ACLKR[1] HCS/ AXR1[1] HAS/ ACLKX1 HDS/ AXR1[6] HDS2/ AXR1[5] HCNTL1/ AXR1[1] HCNTL0/ AXR1[3] HD6/ AHCLKR1 HD9/ GP[9] HD5/ AHCLKX1 HD12/ GP[12] HD14/ GP[14] HD15/ GP[15] HD13/ GP[13] HD11/ GP[11] HD10/ GP[10] HD8/ GP[8] HD7/ GP[3] HD4/ GP[0] HD2/ AFSX1 HD3/ AMUTE1 HD1/ AXR1[7] HHWIL/ AFSR[1] HD0/ AXR1[4] HR/ / AXR1[0] W HOLDA BUS REQ V SS VSS VSS VSS VSS DVDD CVDD CVDD VSS CVDD DVDD FSR0/ AFSR0 CLKR0/ ACLKR0 CLKX0/ ACLKX0 TOUT0/ AXR0[2] TOUT1/ AXR0[4] TINP0/ AXR0[3] TINP1/ AHCLKX0 FSX0/ AFSX0 VSS VSS VSS DVDD DVDD CVDD CVDD CVDD CVDD CVDD DVDD VSS VSS VSS VSS VSS VSSVSS EMU2 CLKIN CLK MODE0 PLLHV RSV RSV CV DD VSS TRST TCK TDI TMS CVDD CVDD CVDD CVDD CVDD CVDD DVDD DVDD DVDDDVDD RSV RSV RSV RSV V SS VSS VSS TD0 CVDD EMU1 EMU0 CLKOUT3 DVDD EMU3 CVDD VSS VSS VSS VSS VSS VSS VSS RSV EMU4 EMU5 NMI RESET DVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Shading□denotes□the□GDP□package□pin□functions□that□drop□out□on□the□PYP□package. SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com GDP 272-BALL BGA PACKAGE (BOTTOM VIEW) DEVICE INFORMATION Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME V SS GP5/AMUTEIN0 V SS GP4/AMUTEIN1 CLKIN CV DD CV DD CLKMODE0 RSV PLLHV TCK V SS TDI CV DD TDO V SS CV DD V SS A10 CV DD C10 DV DD A11 V SS C11 EMU4 A12 RSV C12 RSV A13 RESET C13 NMI A14 V SS C14 HD14/GP[14] A15 HD13/GP[13] C15 HD12/GP[12] A16 HD11/GP[11] C16 HD9/GP[9] A17 DV DD C17 HD6/AHCLKR1 A18 HD7/GP[3] C18 CV DD A19 V SS C19 HD4/GP[0] A20 V SS C20 HD3/AMUTE1 V SS DV DD CV DD GP6 DV DD EMU2 V SS V SS RSV CV DD TRST CV DD TMS RSV DV DD V SS EMU1 EMU0 B10 EMU3 D10 CLKOUT3 B11 RSV D11 CV DD B12 EMU5 D12 RSV B13 DV DD D13 V SS B14 HD15/GP[15] D14 CV DD B15 V SS D15 CV DD B16 HD10/GP[10] D16 DV DD B17 HD8/GP[8] D17 V SS B18 HD5/AHCLKX1 D18 HD2/AFSX1 B19 CV DD D19 DV DD B20 V SS D20 HD1/AXR1[7] CLKS1/SCL1 J17 HOLD V SS J18 HOLDA GP[7]/(EXP_INT7) J19 BUSREQ V SS J20 HINT /GP[1] E17 V SS CV DD E18 HAS /ACLKX1 V SS E19 HDS1 /AXR1[6] CLKS0/AHCLKR0 E20 HD0/AXR1[4] CV DD TOUT1/AXR0[4] V SS TINP1/AHCLKX0 K10 V SS DV DD K11 V SS Submit Documentation Feedback DEVICE INFORMATION

www.ti.com Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) (continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME CV DD K12 V SS F17 CV DD K17 CV DD F18 HDS2 /AXR1[5] K18 ED0 F19 V SS K19 ED1 F20 HCS /AXR1[2] K20 V SS TOUT0/AXR0[2] FSX1 TINP0/AXR0[3] DX1/AXR0[5] CLKX0/ACLKX0 CLKX1/AMUTE0 V SS CV DD G17 V SS V SS G18 HCNTL0/AXR1[3] L10 V SS G19 HCNTL1/AXR1[1] L11 V SS G20 HR/ W /AXR1[0] L12 V SS FSX0/AFSX0 L17 CV DD DX0/AXR0[1] L18 ED2 CLKR0/ACLKR0 L19 ED3 V SS L20 CV DD H17 V SS CLKR1/AXR0[6] H18 DV DD DR1/SDA1 H19 HRDY /ACLKR1 FSR1/AXR0[7] H20 HHWIL/AFSR1 V SS DR0/AXR0[0] V SS DV DD M10 V SS FSR0/AFSR0 M11 V SS V SS M12 V SS V SS M17 V SS J10 V SS M18 DV DD J11 V SS M19 ED4 J12 V SS M20 ED5 SCL0 V SS SDA0 U10 CV DD ED31 U11 CV DD V SS U12 DV DD N17 V SS U13 V SS N18 ED6 U14 CV DD N19 ED7 U15 CV DD N20 ED8 U16 DV DD ED28 U17 V SS ED29 U18 EA21 ED30 U19 BE1 V SS U20 V SS P17 V SS ED20 P18 ED9 ED19 P19 V SS CV DD P20 ED10 ED16 DV DD BE3 ED27 CE3 ED26 EA3 CV DD EA5 R17 CV DD EA8 R18 DV DD V10 EA10 DEVICE INFORMATION Submit Documentation Feedback

3.1

Description

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) (continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME R19 ED11 V11 ARE SDCAS SSADS R20 ED12 V12 AWE SDWE SSWE ED24 V13 DV DD ED25 V14 EA17 DV DD V15 DV DD V SS V16 EA T17 V SS V17 CE0 T18 ED13 V18 CV DD T19 ED15 V19 DV DD T20 ED14 V20 BE0 ED22 V SS ED21 CV DD ED23 DV DD V SS ED17 DV DD V SS CV DD CE2 DV DD EA4 V SS EA6 DV DD ARDY W10 AOE SDRAS SSOE EA2 W11 V SS DV DD W12 DV DD EA7 W13 EA11 EA9 W14 EA13 Y10 ECLKOUT W15 EA15 Y11 ECLKIN W16 V SS Y12 CLKOUT2/GP[2] W17 EA19 Y13 V SS W18 CE1 Y14 EA14 W19 CV DD Y15 EA16 W20 V SS Y16 EA18 V SS Y17 DV DD V SS Y18 EA20 ED18 Y19 V SS BE2 Y20 V SS The TMS320C67x DSPs (including the SM320C6713 and SM320C6713B devices) compose the floating-point DSP generation in the TMS320C6000 DSP platform. The C6713 and C6713B devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Throughout the remainder of this document, the SM320C6713 and SM320C6713B are referred to as 320C67x or C67x or 13/13B where generic, and where specific, their individual full device part numbers are used or abbreviated as C6713, C6713B, 13, or 13B, and so forth. Operating at 225 MHz, the C6713/13B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS). Submit Documentation Feedback DEVICE INFORMATION

www.ti.com The C6713/13B has a rich peripheral set that includes two multichannel audio serial ports (McASPs), two multichannel buffered serial ports (McBSPs), two inter-integrated circuit buses, one dedicated general-purpose input/output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASPs has eight serial data pins that can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from to time slots. The C6713/13B has sufficient bandwidth to support all serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, and CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock, which verifies that the master clock is within a programmed frequency range. The two I C ports on the 320C6713/13B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI mode peripheral devices. The 320C6713/13B device has two boot modes from the HPI or from external asynchronous ROM. For more detailed information, see the Bootmode section of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSP set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS kernel. DEVICE INFORMATION Submit Documentation Feedback

3.2 Device Characteristics SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 3-2 provides an overview of the C6713/C6713B DSPs. The table shows significant device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Table 6-1 and Figure 6-1 Table 3-2. Characteristics of the C6713 and C6713B Processor C6713/C6713B INTERNAL CLOCK (FLOATING-POINT DSPs) HARDWARE (32 bit) EDMA CPU clock frequency (16 channels) Peripherals HPI (16 bit) SYSCLK2 Not all peripheral pins are available at the AUXCLK, same time. (For more details, see the McASPs SYSCLK2 (1) Device Configurations section.) Peripheral performance is dependent on I Cs SYSCLK2 chip-level configuration. McBSPs SYSCLK2 32-bit timers of SYSCLK2 GPIO module SYSCLK2 On-chip memory Size (Bytes) 264K 4K-Byte (KB) program (L1P) cache 4KB data (L1D) cache Organization 64KB unified cache/mapped RAM 192KB mapped RAM CPU ID+CPU Rev ID Control Status Register (CSR[31:16]) 0x0203 BSDL file For the C6713/13B BSDL file, contact your field sales representative. Frequency MHz 200 Time ns ns Core (V) 1.26 V (C6713/C6713B) Voltage I/O (V) 3.3 V Prescaler /1, /2, /3, ..., /32 Clock generator options Multiplier ..., Postscaler /1, /2, /3, ..., /32 Package mm mm 272-ball BGA (GDP) Process technology µ m 0.13 Product status (2) Product preview (PP) PD (13) Advance information (AI) Production data (PD) (1) AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock check (high-frequency) circuit. (2) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Submit Documentation Feedback DEVICE INFORMATION

3.3 Functional Block and CPU (DSP Core) Diagram Test C67x/c228 CPU Data□Path B B□Register□File Instruction□Fetch Instruction□Dispatch Instruction□Decode Data□Path A A□Register□File Power-Down Logic .L1 (A) (A) (A) (A) (A) (A) L1P□Cache Direct□Mapped 4K□Bytes□Total Control Registers Control Logic L1D□Cache 2-Way Set□Associative 4K□Bytes In-Circuit Emulation Interrupt Control C6713/13B Digital□Signal□Processors Enhanced DMA Controller (16 channel) L2□Cache/ Memory 4□Banks 64K□Bytes T otal (up□to 4-Way) Clock□Generator□and□PLL x4□through□x25□Multiplier /1□through□/32□Dividers Memory 192K Bytes EMIF McASP1 McASP0 McBSP1 McBSP0 I2C1 I2C0 Timer□1 Timer□0 GPIO HPI Pin□Multiplexing NOTE□A: In□addition□to□fixed-point□instructions,□these□functional□units□execute□floating-point□instructions. EMIF□interfaces□to: McBSPs□interface□to: McASPs□interface□to: SDRAM/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 SPI□control□port I S□multichannel□ADC,□DAC,□codec,□DIR SBSRAM High-speed□TDM□codecs DIT :□□Multiple□outputs SRAM AC97□codecs ROM/flash□and Serial□EEPROM I/O□devices SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com DEVICE INFORMATION Submit Documentation Feedback

4.1 CPU (DSP Core) www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 The 320C6713/13B floating-point digital signal processor is based on the C67x CPU. The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1. The other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32-bit registers for a total of general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the Functional Block and CPU (DSP Core) Diagram and Figure 4-1 The four functional units on each side of the CPU can freely share the registers belonging to that side. Additionally, each side a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two functional units (.D1 and .D2) also execute the new LDDW instruction, which loads bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with or 15-bit offsets. All instructions are conditional, and most can access any one of the registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically true). The two functional units are dedicated for multiplies. The two and functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are chained together by bits in the least significant bit (LSB) position of the instructions. The instructions that are chained together for simultaneous execution (up to eight in total) compose an execute packet. A in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte, half-word, or word addressable. Submit Documentation Feedback OVERVIEW

long□dst long□dst dst dst dst dst dst dst dst src2 src2 src2 src2 src2 src2 src2 long□src long□src long□dst long□dst long□src .L2 .S2 .M2 .D2 .D1 .M1 .S1 .L1 Control Register□File DA1 DA2 ST1 LD1□32□LSB LD2□32□LSB LD2□32□MSB Data□Path□A Data□Path□B Register File□A (A0−A15) Register File□B (B0−B15) LD1□32□MSB ST2 (A) (A) (A) (A) (A) (A) 4.2 Memory Map Summary SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com In addition to fixed-point instructions, these functional units execute floating-point instructions. Figure 4-1. 320C67x CPU (DSP Core) Data Paths Table 4-1 shows the memory map address ranges of the C6713/13B devices. OVERVIEW Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 4-1. 320C6713/13B Memory Map Summary MEMORY BLOCK (BYTES) HEX ADDRESS RANGE Internal RAM (L2) 192K 0000 0000 0002 FFFF Internal RAM/Cache 64K 0003 0000 0003 FFFF Reserved 24M 256K 0004 0000 017F FFFF External Memory Interface (EMIF) Registers 256K 0180 0000 0183 FFFF Registers 128K 0184 0000 0185 FFFF Reserved 128K 0186 0000 0187 FFFF HPI Registers 256K 0188 0000 018B FFFF McBSP Registers 256K 018C 0000 018F FFFF McBSP Registers 256K 0190 0000 0193 FFFF Timer Registers 256K 0194 0000 0197 FFFF Timer Registers 256K 0198 0000 019B FFFF Interrupt Selector Registers 512 019C 0000 019C 01FF Device Configuration Registers 019C 0200 019C 0203 Reserved 256K 516 019C 0204 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 01A3 FFFF Reserved 768K 01A4 0000 01AF FFFF GPIO Registers 16K 01B0 0000 01B0 3FFF Reserved 240K 01B0 4000 01B3 FFFF I2C0 Registers 16K 01B4 0000 01B4 3FFF I2C1 Registers 16K 01B4 4000 01B4 7FFF Reserved 16K 01B4 8000 01B4 BFFF McASP0 Registers 16K 01B4 C000 01B4 FFFF McASP1 Registers 16K 01B5 0000 01B5 3FFF Reserved 160K 01B5 4000 01B7 BFFF PLL Registers 01B7 C000 01B7 DFFF Reserved 264K 01B7 E000 01BB FFFF Emulation Registers 256K 01BC 0000 01BF FFFF Reserved 01C0 0000 01FF FFFF QDMA Registers 0200 0000 0200 0033 Reserved 16M 0200 0034 02FF FFFF Reserved 720M 0300 0000 2FFF FFFF McBSP0 Data Port 64M 3000 0000 33FF FFFF McBSP1 Data Port 64M 3400 0000 37FF FFFF Reserved 64M 3800 0000 3BFF FFFF McASP0 Data Port 3C00 0000 3C0F FFFF McASP1 Data Port 3C10 0000 3C1F FFFF Reserved 62M 3C20 0000 7FFF FFFF EMIF CE0 (1) 256M 8000 0000 8FFF FFFF EMIF CE1 (1) 256M 9000 0000 9FFF FFFF EMIF CE2 (1) 256M A000 0000 AFFF FFFF EMIF CE3 (1) 256M B000 0000 BFFF FFFF Reserved C000 0000 FFFF FFFF (1) The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. Submit Documentation Feedback OVERVIEW

4.3 Memory Structure Expanded 0x0000□0000 011010001 111 0x0003□0000 000 L2□Mode L2□Memory Block□□Base Address 0x0003□C000 0x0003□8000 0x0003□4000 0x0003□FFFF 16K1-WayCache 32K 2-Way□Cache48K□3-W ay□Cache 64K□4-W ay□Cache 256K□SRAM□(All) 240K□SRAM 224K□SRAM 208K□SRAM 192K□SRAM 192K-Byte□RAM 16K-Byte□RAM 16K-Byte□RAM 16K-Byte□RAM 16K-Byte□RAM SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 4-2 shows the detail of the memory structure. Figure 4-2. Memory Configuration OVERVIEW Submit Documentation Feedback

4.4 Peripheral Register Descriptions SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 4-2 through Table 4-15 identify the peripheral registers for the C6713/C6713B devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide literature number SPRU190 Table 4-2. EMIF Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 GBLCTL EMIF global control 0180 0004 CECTL1 EMIF CE1 space control 0180 0008 CECTL0 EMIF CE0 space control 0180 000C Reserved 0180 0010 CECTL2 EMIF CE2 space control 0180 0014 CECTL3 EMIF CE3 space control 0180 0018 SDCTL EMIF SDRAM control 0180 001C SDTIM EMIF SDRAM refresh control 0180 0020 SDEXT EMIF SDRAM extension 0180 0024 0183 FFFF Reserved Submit Documentation Feedback OVERVIEW

www.ti.com Table 4-3. Cache Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 CCFG Cache configuration 0184 4000 L2WBAR writeback base address register 0184 4004 L2WWC writeback word count 0184 4010 L2WIBAR writeback-invalidate base address register 0184 4014 L2WIWC writeback-invalidate word count 0184 4020 L1PIBAR L1P invalidate base address register 0184 4024 L1PIWC L1P invalidate word count 0184 4030 L1DWIBAR L1D writeback-invalidate base address register 0184 4034 L1DWIWC L1D writeback-invalidate word count 0184 5000 L2WB writeback all 0184 5004 L2WBINV writeback-invalidate all 0184 8200 MAR0 Memory attribute register Controls CE0 range 8000 0000 80FF FFFF 0184 8204 MAR1 Memory attribute register Controls CE0 range 8100 0000 81FF FFFF 0184 8208 MAR2 Memory attribute register Controls CE0 range 8200 0000 82FF FFFF 0184 820C MAR3 Memory attribute register Controls CE0 range 8300 0000 83FF FFFF 0184 8240 MAR4 Memory attribute register Controls CE1 range 9000 0000 90FF FFFF 0184 8244 MAR5 Memory attribute register Controls CE1 range 9100 0000 91FF FFFF 0184 8248 MAR6 Memory attribute register Controls CE1 range 9200 0000 92FF FFFF 0184 824C MAR7 Memory attribute register Controls CE1 range 9300 0000 93FF FFFF 0184 8280 MAR8 Memory attribute register Controls CE2 range A000 0000 A0FF FFFF 0184 8284 MAR9 Memory attribute register Controls CE2 range A100 0000 A1FF FFFF 0184 8288 MAR10 Memory attribute register 10. Controls CE2 range A200 0000 A2FF FFFF 0184 828C MAR11 Memory attribute register 11. Controls CE2 range A300 0000 A3FF FFFF 0184 82C0 MAR12 Memory attribute register 12. Controls CE3 range B000 0000 B0FF FFFF 0184 82C4 MAR13 Memory attribute register 13. Controls CE3 range B100 0000 B1FF FFFF 0184 82C8 MAR14 Memory attribute register 14. Controls CE3 range B200 0000 B2FF FFFF 0184 82CC MAR15 Memory attribute register 15. Controls CE3 range B300 0000 B3FF FFFF 0184 82D0 0185 FFFF Reserved Table 4-4. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Selects which interrupts drive CPU interrupts 019C 0000 MUXH Interrupt multiplexer high (INT10 INT15) Selects which interrupts drive CPU interrupts 019C 0004 MUXL Interrupt multiplexer low (INT04 INT09) Sets the polarity of the external interrupts 019C 0008 EXTPOL External interrupt polarity (EXT_INT4 EXT_INT7) 019C 000C 019F FFFF Reserved OVERVIEW Submit Documentation Feedback

Word□0 EDMA□Channel□Options□Parameter□(OPT) OPT Word□1 EDMA□Channel□Source□Address□(SRC) SRC Word□2 Array/Frame□Count□(FRMCNT) Element□Count□(ELECNT) CNT Word□3 EDMA□Channel□Destination□Address□(DST) DST Word□4 Array/Frame□Index□(FRMIDX) Element□Index□(ELEIDX) IDX Word□5 Element□Count□Reload□(ELERLD) Link□Address□(LINK) RLD SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 4-5. Device Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Allows the user to control peripheral selection. This register also offers the user control of the EMIF input clock source. For 019C 0200 DEVCFG Device configuration more detailed information on the device configuration register, see the Device Configurations section of this data sheet. 019C 0204 019F FFFF Reserved Identifies which CPU and defines the silicon revision of the CPU. This register also offers the user control of device operation. For more N/A CSR CPU control status register detailed information on the CPU Control Status Register, see the CPU CSR Register sheet. Table 4-6. EDMA Parameter RAM (1) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0000 01A0 0017 Parameters for Event words) or Reload/Link parameters for other event 01A0 0018 01A0 002F Parameters for Event words) or Reload/Link parameters for other event 01A0 0030 01A0 0047 Parameters for Event words) or Reload/Link parameters for other event 01A0 0048 01A0 005F Parameters for Event words) or Reload/Link parameters for other event 01A0 0060 01A0 0077 Parameters for Event words) or Reload/Link parameters for other event 01A0 0078 01A0 008F Parameters for Event words) or Reload/Link parameters for other event 01A0 0090 01A0 00A7 Parameters for Event words) or Reload/Link parameters for other event 01A0 00A8 01A0 00BF Parameters for Event words) or Reload/Link parameters for other event 01A0 00C0 01A0 00D7 Parameters for Event words) or Reload/Link parameters for other event 01A0 00D8 01A0 00EF Parameters for Event words) or Reload/Link parameters for other event 01A0 00F0 01A0 00107 Parameters for Event words) or Reload/Link parameters for other event 01A0 0108 01A0 011F Parameters for Event words) or Reload/Link parameters for other event 01A0 0120 01A0 0137 Parameters for Event words) or Reload/Link parameters for other event 01A0 0138 01A0 014F Parameters for Event words) or Reload/Link parameters for other event 01A0 0150 01A0 0167 Parameters for Event words) or Reload/Link parameters for other event 01A0 0168 01A0 017F Parameters for Event words) or Reload/Link parameters for other event 01A0 0180 01A0 0197 Reload/link parameters for Event 01A0 0198 01A0 01AF Reload/link parameters for Event ... ... ... 01A0 07E0 01A0 07F7 Reload/link parameters for Event 01A0 07F8 01A0 07FF Scratch pad area (two words) (1) The C6713/13B device has EDMA parameters total: Event/Reload parameters and Reload-only parameters. For more details on the EDMA parameter RAM six-word parameter entry structure, see Figure 4-3 Figure 4-3. EDMA Channel Parameter Entries (Six Words) for Each EDMA Event Submit Documentation Feedback OVERVIEW

www.ti.com Table 4-7. EDMA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0800 01A0 FEFC Reserved 01A0 FF00 ESEL0 EDMA event selector 01A0 FF04 ESEL1 EDMA event selector 01A0 FF08 01A0 FF0B Reserved 01A0 FF0C ESEL3 EDMA event selector 01A0 FF1F 01A0 FFDC Reserved 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPR Channel interrupt pending register 01A0 FFE8 CIER Channel interrupt enable register 01A0 FFEC CCER Channel chain enable register 01A0 FFF0 ER Event register 01A0 FFF4 EER Event enable register 01A0 FFF8 ECR Event clear register 01A0 FFFC ESR Event set register 01A1 0000 01A3 FFFF Reserved Table 4-8. Quick DMA (QDMA) and Pseudo Registers (1) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0200 0000 QOPT QDMA options parameter 0200 0004 QSRC QDMA source address 0200 0008 QCNT QDMA frame count 0200 000C QDST QDMA destination address 0200 0010 QIDX QDMA index 0200 0014 0200 001C Reserved 0200 0020 QSOPT QDMA pseudo options 0200 0024 QSSRC QDMA pseudo source address 0200 0028 QSCNT QDMA pseudo frame count 0200 002C QSDST QDMA pseudo destination address 0200 0030 QSIDX QDMA pseudo index (1) All the QDMA and Pseudo registers are write accessible only. Table 4-9. PLL Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C000 PLLPID Peripheral identification (C6713/13B value: 0x00010801 for PLL Controller) 01B7 C004 01B7 C0FF Reserved 01B7 C100 PLLCSR PLL control/status register 01B7 C104 01B7 C10F Reserved 01B7 C110 PLLM PLL multiplier control 01B7 C114 PLLDIV0 PLL controller divider 01B7 C118 PLLDIV1 PLL controller divider 01B7 C11C PLLDIV2 PLL controller divider 01B7 C120 PLLDIV3 PLL controller divider 01B7 C124 OSCDIV1 Oscillator divider 01B7 C128 01B7 DFFF Reserved OVERVIEW Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 4-10. McASP0 and McASP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME AND bus. Used when RSEL or XSEL bits (these bits are located in the RFMT or XFMT registers, respectively). Peripheral identification 01B4 C000 01B5 0000 MCASPPIDx [13/13B value: 0x00100101 for McASP0 and for McASP1] 01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management 01B4 C008 01B5 0008 Reserved 01B4 C00C 01B5 000C Reserved 01B4 C010 01B5 0010 PFUNCx Pin function 01B4 C014 01B5 0014 PDIRx Pin direction 01B4 C018 01B5 0018 PDOUTx Pin data out Pin data in/data set 01B4 C01C 01B5 001C PDIN/PDSETx Read returns: PDIN Writes affect: PDSET 01B4 C020 01B5 0020 PDCLRx Pin data clear 01B4 C024 01B4 C040 01B5 0024 01B5 0040 Reserved 01B4 C044 01B5 0044 GBLCTLx Global control 01B4 C048 01B5 0048 AMUTEx Mute control 01B4 C04C 01B5 004C DLBCTLx Digital loopback control 01B4 C050 01B5 0050 DITCTLx DIT mode control 01B4 C054 01B4 C05C 01B5 0054 01B5 005C Reserved Alias of GBLCTL containing only Receiver Reset bits; allows 01B4 C060 01B5 0060 RGBLCTLx transmit to be reset independently from receive 01B4 C064 01B5 0064 RMASKx Receiver format unit bit mask 01B4 C068 01B5 0068 RFMTx Receive bit stream format 01B4 C06C 01B5 006C AFSRCTLx Receive frame sync control 01B4 C070 01B5 0070 ACLKRCTLx Receive clock control 01B4 C074 01B5 0074 AHCLKRCTLx High-frequency receive clock control 01B4 C078 01B5 0078 RTDMx Receive TDM slot 01B4 C07C 01B5 007C RINTCTLx Receiver interrupt control 01B4 C080 01B5 0080 RSTATx Status receiver 01B4 C084 01B5 0084 RSLOTx Current receive TDM slot 01B4 C088 01B5 0088 RCLKCHKx Receiver clock check control 01B4 C08C 01B4 C09C 01B5 008C 01B5 009C Reserved Alias of GBLCTL containing only Transmitter Reset bits; allows 01B4 C0A0 01B5 00A0 XGBLCTLx transmit to be reset independently from receive 01B4 C0A4 01B5 00A4 XMASKx Transmit format unit bit mask 01B4 C0A8 01B5 00A8 XFMTx Transmit bit stream format 01B4 C0AC 01B5 00AC AFSXCTLx Transmit frame sync control 01B4 C0B0 01B5 00B0 ACLKXCTLx Transmit clock control 01B4 C0B4 01B5 00B4 AHCLKXCTLx High-frequency Transmit clock control 01B4 C0B8 01B5 00B8 XTDMx Transmit TDM slot 01B4 C0BC 01B5 00BC XINTCTLx Transmit interrupt control 01B4 C0C0 01B5 00C0 XSTATx Status transmitter 01B4 C0C4 01B5 00C4 XSLOTx Current transmit TDM slot 01B4 C0C8 01B5 00C8 XCLKCHKx Transmit clock check control 01B4 C0D0 01B4 C0FC 01B5 00CC 01B5 00FC Reserved 01B4 C100 01B5 0100 DITCSRA0x Left (even TDM slot) channel status register file 01B4 C104 01B5 0104 DITCSRA1x Left (even TDM slot) channel status register file 01B4 C108 01B5 0108 DITCSRA2x Left (even TDM slot) channel status register file 01B4 C10C 01B5 0108 DITCSRA3x Left (even TDM slot) channel status register file Submit Documentation Feedback OVERVIEW

www.ti.com Table 4-10. McASP0 and McASP1 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME AND (even TDM slot) channel status register file 01B4 C114 01B5 0114 DITCSRA5x Left (even TDM slot) channel status register file 01B4 C118 01B5 0118 DITCSRB0x Right (odd TDM slot) channel status register file 01B4 C11C 01B5 011C DITCSRB1x Right (odd TDM slot) channel status register file 01B4 C120 01B5 0120 DITCSRB2x Right (odd TDM slot) channel status register file 01B4 C124 01B5 0124 DITCSRB3x Right (odd TDM slot) channel status register file 01B4 C128 01B5 0128 DITCSRB4x Right (odd TDM slot) channel status register file 01B4 C12C 01B5 012C DITCSRB5x Right (odd TDM slot) channel status register file 01B4 C130 01B5 0130 DITUDRA0x Left (even TDM slot) user data register file 01B4 C134 01B5 0134 DITUDRA1x Left (even TDM slot) user data register file 01B4 C138 01B5 0138 DITUDRA2x Left (even TDM slot) user data register file 01B4 C13C 01B5 013C DITUDRA3x Left (even TDM slot) user data register file 01B4 C140 01B5 0140 DITUDRA4x Left (even TDM slot) user data register file 01B4 C144 01B5 0144 DITUDRA5x Left (even TDM slot) user data register file 01B4 C148 01B5 0148 DITUDRB0x Right (odd TDM slot) user data register file 01B4 C14C 01B5 014C DITUDRB1x Right (odd TDM slot) user data register file 01B4 C150 01B5 0150 DITUDRB2x Right (odd TDM slot) user data register file 01B4 C154 01B5 0154 DITUDRB3x Right (odd TDM slot) user data register file 01B4 C158 01B5 0158 DITUDRB4x Right (odd TDM slot) user data register file 01B4 C15C 01B5 015C DITUDRB5x Right (odd TDM slot) user data register file 01B4 C160 01B4 C17C 01B5 0160 01B5 017C Reserved 01B4 C180 01B5 0180 SRCTL0x Serializer control 01B4 C184 01B5 0184 SRCTL1x Serializer control 01B4 C188 01B5 0188 SRCTL2x Serializer control 01B4 C18C 01B5 018C SRCTL3x Serializer control 01B4 C190 01B5 0190 SRCTL4x Serializer control 01B4 C194 01B5 0194 SRCTL5x Serializer control 01B4 C198 01B5 0198 SRCTL6x Serializer control 01B4 C19C 01B5 019C SRCTL7x Serializer control 01B4 C1A0 01B4 C1FC 01B5 01A0 01B5 01FC Reserved 01B4 C200 01B5 0200 XBUF0x Transmit buffer for serializer through configuration bus (1) 01B4 C204 01B5 0204 XBUF1x Transmit buffer for serializer through configuration bus (1) 01B4 C208 01B5 0208 XBUF2x Transmit buffer for serializer through configuration bus (1) 01B4 C20C 01B5 020C XBUF3x Transmit buffer for serializer through configuration bus (1) 01B4 C210 01B5 0210 XBUF4x Transmit buffer for serializer through configuration bus (1) 01B4 C214 01B5 0214 XBUF5x Transmit buffer for serializer through configuration bus (1) 01B4 C218 01B5 0218 XBUF6x Transmit buffer for serializer through configuration bus (1) 01B4 C21C 01B5 021C XBUF7x Transmit buffer for serializer through configuration bus (1) 01B4 C220 01B4 C27C 01B5 C220 01B5 027C Reserved 01B4 C280 01B5 0280 RBUF0x Receive buffer for serializer through configuration bus (2) 01B4 C284 01B5 0284 RBUF1x Receive buffer for serializer through configuration bus (2) 01B4 C288 01B5 0288 RBUF2x Receive buffer for serializer through configuration bus (2) 01B4 C28C 01B5 028C RBUF3x Receive buffer for serializer through configuration bus (2) 01B4 C290 01B5 0290 RBUF4x Receive buffer for serializer through configuration bus (2) 01B4 C294 01B5 0294 RBUF5x Receive buffer for serializer through configuration bus (2) 01B4 C298 01B5 0298 RBUF5x Receive buffer for serializer through configuration bus (2) 01B4 C29C 01B5 029C RBUF7x Receive buffer for serializer through configuration bus (2) 01B4 C2A0 01B4 FFFF 01B5 02A0 01B5 3FFF Reserved (1) The transmit buffers for serializers are accessible to the CPU via the peripheral bus if the XSEL bit (XFMT register). (2) The receive buffers for serializers are accessible to the CPU via the peripheral bus if the RSEL bit (RFMT register). OVERVIEW Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 4-11. I2C0 and I2C1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME AND (C6713/13B value: 0x0000 0103) I2CPID20 I2Cx peripheral identification 01B4 0038 01B4 4038 I2CPID21 (C6713/13B value: 0x0000 0005) 01B4 003C 01B4 3FFF 01B4 403C 01B4 7FFF Reserved Table 4-12. HPI Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS HPID HPI data register Host read/write access only HPIA HPI address register Host read/write access only 0188 0000 HPIC HPI control register Both Host/CPU read/write access 0188 0004 018B FFFF Reserved Table 4-13. Timer and Timer Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS TIMER TIMER Determines the operating mode of the 0194 0000 0198 0000 CTLx Timer x control register timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input 0194 0004 0198 0004 PRDx Timer x period register clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the 0194 0008 0198 0008 CNTx Timer x counter register incrementing counter. 0194 000C 0197 FFFF 0198 000C 019B FFFF Reserved Table 4-14. McBSP0 and McBSP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME AND bus. 018C 0000 0190 0000 DRRx The CPU and EDMA controller can only read this register; they cannot write to it. 3000 0000 33FF FFFF 3400 0000 37FF FFFF DRRx McBSPx data receive register via peripheral data bus 018C 0004 0190 0004 DXRx McBSPx data transmit register via configuration bus 3000 0000 33FF FFFF 3400 0000 37FF FFFF DXRx McBSPx data transmit register via peripheral data bus 018C 0008 0190 0008 SPCRx McBSPx serial port control register 018C 000C 0190 000C RCRx McBSPx receive control register Submit Documentation Feedback OVERVIEW

www.ti.com Table 4-14. McBSP0 and McBSP1 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME AND 4-15. GPIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B0 0000 GPEN GPIO enable 01B0 0004 GPDIR GPIO direction 01B0 0008 GPVAL GPIO value 01B0 000C Reserved 01B0 0010 GPDH GPIO delta high 01B0 0014 GPHM GPIO high mask 01B0 0018 GPDL GPIO delta low 01B0 001C GPLM GPIO low mask 01B0 0020 GPGC GPIO global control 01B0 0024 GPPOL GPIO interrupt polarity 01B0 0028 01B0 3FFF Reserved OVERVIEW Submit Documentation Feedback

4.5 Signal Groups GP7 IEEE Standard 1149.1 (JTAG) Emulation Reset□and Interrupts Control/Status TDI TDO TMS TCK EMU0 EMU1 NMI GP6 GP5/AMUTEIN0 GP4/AMUTEIN1 RESET Clock/PLL Oscillator CLKIN CLKMODE0 PLLHV CLKOUT2/GP[2] EMU2 EMU3 EMU4 EMU5 HHWIL/AFSR1 HCNTL0/AXR1[3] HCNTL1/AXR1[1] Data Register□Select Half-Word Select Control HPI (Host-Port□Interface) HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1] HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[1 1] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4] CLKOUT3 HD4/GP[0] (A) (A) (A) (A) (B) (B) (B) (B) (B) (C) (C) (C) (C) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 These external pins are applicable to the GDP package only. The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the external interrupt sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646). All of these pins are external interrupt sources. For more details see the External Interrupt Sources section of this data sheet. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module. Figure 4-4. CPU (DSP Core) and Peripheral Signals Submit Documentation Feedback OVERVIEW

General-Purpose Input/Output□(GPIO)□Port GP7 GP6 GP5/AMUTEIN0 GP4/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT /GP[1] HD4/GP[0] GPIO HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD1 1/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] TOUT1/AXR0[4] TOUT0/AXR0[2]Timer 1 Timer 0 Timers TINP1/AHCLKX0 TINP0/AXR0[3] CLKS1/SCL1 SCL0I2C1 I2C0 I Cs DR1/SDA1 SDA0 (A) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com The GP[15:0} pins, through interrupt sharing, are external interrupt capable via GPINT0. GP[15:0] are also external EDMA event source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources sections of this data sheet. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module. Figure 4-5. Peripheral Signals OVERVIEW Submit Documentation Feedback

ECLKOUTED[31:16] CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 CLKX1/AMUTE0 FSX1 DX1/AXR0[5] CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1 CLKS1/SCL1 AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1] CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0] CLKS0/AHCLKR0 Data Memory Map Space□Select Address Byte□Enables Memory Control EMIF (External□Memory□Interface) Receive Receive McBSP1 McBSP0 Transmit Transmit Clock Clock McBSPs (Multichannel□Buffered□Serial□Ports) ECLKIN HOLD HOLDA BUSREQ Bus Arbitration ARE/SDCAS/SSADS ED[15:0] (A) (A) (A) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 These external pins are applicable to the GDP package only. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module. Figure 4-6. Peripheral Signals Submit Documentation Feedback OVERVIEW

(Multichannel Audio□Serial□Port□0) CLKX0/ACLKX0 CLKS0/AHCLKR0 Transmit Clock Generator GP5/AMUTEIN0 Auto□Mute Logic CLKX1/AMUTE0 FSX0/AFSX0Transmit Frame□SyncFSR0/AFSR0 Receive Frame□Sync CLKR0/ACLKR0 TINP1/AHCLKX0 Receive□Clock Generator TOUT1/AXR0[4] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0] DX1/AXR0[5] TINP0/AXR0[3] CLKR1/AXR0[6] FSR1/AXR0[7] 8-Serial□Ports Flexible Partitioning Tx,□Rx,□OFF Transmit Clock□Check Circuit Receive□Clock Check□Circuit Error□Detect (see□Note□A) (Transmit/Receive□Data□Pins) (Receive□Bit□Clock) (Transmit□Bit□Clock) (Receive□Master□Clock) (Transmit□Master□Clock) (Receive□Frame□Sync□or Left/Right□□Clock) (Transmit□Frame□Sync□or Left/Right□□Clock) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com The McASP Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module. Boldface and italicized text within parentheses denotes the function of the pins in an audio system. Figure 4-7. Peripheral Signals OVERVIEW Submit Documentation Feedback

HD0/AXR1[4] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0] McASP1 (Multichannel Audio□Serial□Port□1) HDS2/AXR1[5] HAS/ACLKX1 HD5/AHCLKX1 Transmit Clock Generator HCNTL0/AXR1[3] GP4/AMUTEIN1 Auto□Mute Logic HD3/AMUTE1 HD2/AFSX1Transmit Frame□SyncHHWIL/AFSR1 Receive Frame□Sync HDS1/AXR1[6] HD1/AXR1[7] HRDY/ACLKR1 HD6/AHCLKR1 Receive□Clock Generator 8-Serial□Ports Flexible Partitioning Tx,□Rx,□OFF Transmit Clock□Check Circuit Receive□Clock Check□Circuit Error□Detect (see□Note□A) (Transmit/Receive□Data□Pins) (Receive□Bit□Clock) (Transmit□Bit□Clock) (Receive□Master□Clock) (Transmit□Master□Clock) (Receive□Frame□Sync□or Left/Right□□Clock) (Transmit□Frame□Sync□or Left/Right□□Clock) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 The McASP Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module. Boldface and italicized text within parentheses denotes the function of the pins in an audio system. Figure 4-8. Peripheral Signals Submit Documentation Feedback OVERVIEW

5.1 Device Configurations at Device Reset SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com On the C6713/13B devices, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset. Table 5-1 describes the C6713 and C6713B device configuration pins, which are set up via internal or external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, HD12 [13B only]), and CLKMODE0 pin. These configuration pins must be in the desired state until reset is released. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section of this data sheet. Table 5-1. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [13B only], and CLKMODE0) (1) CONFIGURATION GDP FUNCTIONAL [C6713B only] For a C6713BGDP The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of the endianess mode (Little/Big Endian). In Little Endian mode (HD8 1), the 8-bit or 16-bit EMIF data will be present on the ED[7:0] side of the bus. In Big Endian mode (HD8 0), the 8-bit or 16-bit EMIF data will be present on the HD12 C15 ED[31:24] side of the bus [default]. For a C6713BPYP, when Big Endian mode is selected (LENDIAN 0), for proper device operation the EMIFBE pin must be externally pulled low. This enhancement is not supported on the C6713 device. For proper C6713 device operation, do not oppose the internal pullup (IPU) resistor on this pin. This new functionality does not affect systems using the current default value of HD12 For more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode Correctness [C6713B only] portion of this data sheet. Device Endian mode (LEND) HD8 B17 System operates in Big Endian mode System operates in Little Endian mode (default) Bootmode Configuration pins (BOOTMODE) CE1 width 32-bit, HPI boot/emulation boot CE1 width 8-bit, asynchronous external ROM boot with default timings (default mode) HD[4:3] C19, C20 CE1 width 16-bit, asynchronous external ROM boot with default timings (BOOTMODE) CE1 width 32-bit, asynchronous external ROM boot with default timings For more detailed information on these bootmode configurations, see the Bootmode section of this data sheet. Clock generator input clock source select Reserved. Do not use. CLKMODE0 CLKIN square wave [default] This pin must be pulled to the correct level even after reset. (1) All other HD pins [HD [15, 13:9, 7:5, 2:0] (for 13) or HD [15, 13, 11:9, 7:5, 2:0] (for 13B)] have pullups/pulldowns (IPUs or IPDs). For proper device operation of the HD [15, 13:9, (for 13) or HD [13, 11:9, (for 13B), do not oppose these pins with external pullups/pulldowns at reset; however, the HD[6, (for 13) or HD[15, (for 13B) pins can be opposed and driven during reset. DEVICE CONFIGURATIONS Submit Documentation Feedback

5.2 Peripheral Pin Selection at Device Reset 5.3 Peripheral Selection/Device Configurations Via the DEVCFG Control Register SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Some C6713/13B peripherals share the same pins (internally MUXed) and are mutually exclusive (that is, HPI, general-purpose input/output pins GP[15:8, 0], and McASP1). HPI, McASP1, and GPIO peripherals The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or McASP1 peripheral pins and GP[15:8, pins are functionally enabled (see Table 5-2 Table 5-2. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins) (1) PERIPHERAL PERIPHERAL PIN SELECTION PINS SELECTED HPI_EN McASP1 and HPI (HD14 Pin) [173, C14] GP[15:8, HPI_EN HPI pins are disabled; McASP1 peripheral pins and GP[15:8, pins ü are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as McASP1 and GPIO pins, respectively. To use the GPIO pins, the appropriate bits in the GPEN and GPDIR registers need to be configured. HPI_EN HPI pins are enabled; McASP1 peripheral pins and GP[15:8, pins ü are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins function as HPI pins. (1) The HPI_EN (HD[14]) pin cannot be controlled via software. The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0, McBSP1, McASP0, I2C1, and timer peripherals. The DEVCFG register also offers the user control of the EMIF input clock source and the timer output pins. For more detailed information on the DEVCFG register control bits, see Table 5-3 and Table 5-4 Table 5-3. Device Configuration Register (DEVCFG) [Address Location: 0x019C0200 0x019C02FF] Reserved (1) R/W-0 Reserved (1) EKSRC TOUT1SEL TOUT0SEL MCBSP0DIS MCBSP1DIS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R Read, W Write, --n value at reset (1) Do not write non-zero values to these bit locations. (1) Do not write non-zero values to these bit locations. Submit Documentation Feedback DEVICE CONFIGURATIONS

5.4 Multiplexed Pins SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 5-4. Device Configuration Register (DEVCFG) Selection Bit Descriptions BIT NO. NAME 31:5 Reserved Reserved. Do not write non-zero values to these bit locations. EMIF input clock source bit. Determines which clock signal is used as the EMIF input clock. EKSRC SYSCLK3 (from the clock generator) is the EMIF input clock source (default). ECLKIN external pin is the EMIF input clock source. Timer output (TOUT1) pin function select bit. Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. TOUT1SEL The pin functions as a Timer output (TOUT1) pin (default). The pin functions as the McASP0 transmit/receive data pin (AXR0[4]). The Timer module is still active. Timer output (TOUT0) pin function select bit. Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. TOUT0SEL The pin functions as a Timer output (TOUT0) pin (default). The pin functions as the McASP0 transmit/receive data pin (AXR0[2]). The Timer module is still active. Multichannel Buffered Serial Port (McBSP0) disable bit. Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled. McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, MCBSP0DIS ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default). If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT mode only. McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled. Multichannel Buffered Serial Port (McBSP1) disable bit. Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled. McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 MCBSP1DIS peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default) McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 peripheral pins (AXR0[7:5] and AMUTE0) are enabled. Multiplexed (MUXed) pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of these pins are configured by software via the device configuration register (DEVCFG), and the others (specifically, the HPI pins) are configured by external pullup/pulldown resistors only at reset. The MUXed pins that are configured by software can be programmed to switch functionalities at any time. The MUXed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 5-5 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register. Table 5-6 identifies the multiplexed pins on the C6713/13B devices, shows the default (primary) function and the default settings after reset, and describes the pins, registers, etc., necessary to configure the specific multiplexed functions. DEVICE CONFIGURATIONS Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 5-5. Peripheral Pin Selection Matrix (1) SELECTION BITS PERIPHERAL PIN AVAILABILITY BIT BIT GPIO MCASP0 (2) MCASP1 MCBSP0 MCBSP1 TIMER0 TIMER1 HPI EMIF I I NAME VAL PINS AHCLKX1 AHCLKR1 GP[0:1], ACLKX1 GP[3], ACLKR1 GP[8:15] HPI_EN AFSX1 abc (boot config None AFSR1 Plus: pin) AMUTE1 GP[2] AXR1[0] ctrl d by to GP2EN bit AXR1[7] NO HPI_EN GP[0:1], (boot config None All GP[3], pin) GP[8:15] None All ACLKK0 ACLKR0 MCBSP0DI AFSX0 S (DEVCFG AFSR0 None bit) AHCLKR AXR0[0] AXR0[1] NO AMUTE0 AXR0[5] None All AXR0[6] MCBSP1DI AXR0[7] S (DEVCFG bit) AMUTE0 AXR0[5] All None AXR0[6] AXR0[7] NO TOUT0 TOUT0SEL AXR0[2] (DEVCFG NO bit) AXR0[2] TOUT0 NO TOUT1 TOUT1SEL AXR0[4] (DEVCFG NO bit) AXR0[4] TOUT1 ED[7:0]; HD8 HD12 (boot ED[7:0} side config pin) [HD8 (Little)] [13BGDP] (3) ED[31:24] side [HD8 (Big)] (1) Gray blocks indicate that the peripheral is not affected by the selection bit. (2) The McASP0 pins, AXR0[3] and AHCLKX0, are shared with the timer input pins, TINP0 and TINP1, respectively. See Table 5-6 for more detailed information. (3) For more detailed information on endianness correction, see the EMIF Big Endian Mode Correctness [C6713B only] section of this data sheet. Table 5-6. C6713/13B Device Multiplexed/Shared Pins MULTIPLEXED PIN DEFAULT NAME GDP FUNCTION DEFAULT SETTING (GPEN register bit) When the CLKOUT2 pin is enabled, the CLK2EN bit in the GP[2] function disabled, CLKOUT2 EMIF global control register (GBLCTL) controls the enabled CLKOUT2 pin. CLKOUT2/GP[2] Y12 CLKOUT2 CLK2EN CLKOUT2 held high CLK2EN CLKOUT2 enabled to clock [default]. Submit Documentation Feedback DEVICE CONFIGURATIONS

www.ti.com Table 5-6. C6713/13B Device Multiplexed/Shared Pins (continued) MULTIPLEXED PIN DEFAULT NAME GDP FUNCTION DEFAULT SETTING pins, the GPxDIR (input) GPxEN bits in the GP Enable Register and the GPxDIR GP5EN (disabled) bits in the GP Direction Register must be properly GP4EN (disabled) configured. [(GPEN register bits) GPxEN GP[x] pin enabled. GP5/AMUTEIN GP[x] function disabled] GP5 GPxDIR GP[x] pin is an input. GP4/AMUTEIN GP4 GPxDIR GP[x] pin is an output. To use AMUTEIN0/1 pin function, the GP[5]/GP[4] pins must be configured as an input, the INEN bit set to and the polarity through the INPOL bit selected in the associated McASP AMUTE register. CLKS0/AHCLKR0 By default, McBSP0 peripheral pins are enabled upon reset (McASP0 pins are disabled). DR0/AXR0[0] abc To enable the McASP0 peripheral pins, the MCBSP0DIS DX0/AXR0[1] MCBSP0DIS bit in the DEVCFG register must be set to (disabling the (DEVCFG register bit) FSR0/AFSR0 McBSP0 pin function McBSP0 peripheral pins). McASP0 pins disabled, McBSP0 pins enabled FSX0/AFSX0 CLKR0/ACLKR0 CLKX0/ACLKX0 CLKS1/SCL1 By default, McBSP1 peripheral pins are enabled upon DR1/SDA1 MCBSP1DIS reset (I2C1 and McASP0 pins are disabled). DX1/AXR0[5] (DEVCFG register bit) abc McBSP1 pin function I2C1 and McASP0 pins To enable the I2C1 and McASP0 peripheral pins, the FSR1/AXR0[7] disabled, McBSP1 pins enabled MCBSP1DIS bit in the DEVCFG register must be set to CLKR1/AXR0[6] (disabling the McBSP1 peripheral pins). CLKX1/AMUTE0 HINT /GP[1] J20 HD15/GP[15] B14 HD14/GP[14] C14 HD13/GP[13] A15 By default, the HPI peripheral pins are enabled at reset. HD12/GP[12] C15 McASP1 peripheral pins and eleven GPIO pins are HD11/GP[11] A16 disabled. HD10/GP[10] B16 HD9/GP[9] C16 To enable the McASP1 peripheral pins and the eleven HD8/GP[8] B17 GPIO pins, an external pulldown resistor must be provided on the HD14 pin setting HPI_EN at reset. HD7/GP[3] A18 HD4/GP[0] C19 HD1/AXR1[7] D20 GP enable register and the GPxDIR bits in the GP HPI_EN (HD14 pin) direction register must be properly configured. To use HD0/AXR1[4] E20 HPI (HPI enabled) these software-configurable GPIO pins, the GPxEN bits in pin function McASP1 pins and GPIO pins the HCNTL1/AXR1[1] G19 are disabled. HCNTL0/AXR1[3] G18 GPxEN GP[x] pin enabled. HR/ W /AXR1[0] G20 GPxDIR GP[x] pin is an input. HDS1 /AXR1[6] E19 GPxDIR GP[x] pin is an output. HDS2 /AXR1[5] F18 HCS /AXR1[2] F20 McASP1 pin direction is controlled by the PDIR[x] bits in the McASP1PDIR register. HD6/AHCLKR1 C17 HD5/AHCLKX1 B18 HD3/AMUTE1 C20 HD2/AFSX1 D18 HHWIL/AFSR1 H20 HRDY /ACLKR1 H19 HAS /ACLKX1 E18 DEVICE CONFIGURATIONS Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 5-6. C6713/13B Device Multiplexed/Shared Pins (continued) MULTIPLEXED PIN DEFAULT NAME GDP FUNCTION DEFAULT SETTING default, the Timer input pin is enabled (and a shared Timer McASP0PDIR (input) input until the McASP0 peripheral forces an output). TINP0/AXR0[3] input function [specifically AXR0[3] bit] abc McASP0PDIR input, output By default, the Timer output pin is enabled. abc To enable the McASP0 AXR0[2] pin, the TOUT0SEL bit in the DEVCFG register must be set to (disabling the TOUT0SEL (DEVCFG register Timer Timer peripheral output pin function). TOUT0/AXR0[2] bit) [TOUT0 pin enabled and output function abc McASP0 AXR0[2] pin disabled] The AXR2 bit in the McASP0PDIR register controls the direction (input/output) of the AXR0[2] pin. McASP0PDIR input, output By default, the Timer input and McASP0 clock function are enabled as inputs. Timer McASP0PDIR (input) TINP1/AHCLKX0 abc input function [specifically AHCLKX bit] For the McASP0 clock to function as an output: McASP0PDIR (specifically the AHCLKX bit). By default, the Timer output pin is enabled. abc To enable the McASP0 AXR0[4] pin, the TOUT1SEL bit in the DEVCFG register must be set to (disabling the TOUT1SEL (DEVCFG register Timer Timer peripheral output pin function). TOUT1/AXR0[4] bit) [TOUT1 pin enabled and output function abc McASP0 AXR0[4] pin disabled] The AXR4 bit in the McASP0PDIR register controls the direction (input/output) of the AXR0[4] pin. McASP0PDIR input, output Submit Documentation Feedback DEVICE CONFIGURATIONS

5.5 Configuration Examples EMIF ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 SCL0,□SDA0 DEVCFG□Register□Value: 0x0000□000F MCBSP0DIS□= 1 MCBSP1DIS□= 1 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . SCL1,□SDA1 AXR0[7:0] {TINP0/AXR0[3]} AXR1[7:0] AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0,□AFSR0, AFSX0 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 5-1 through Figure 5-6 illustrate examples of peripheral selections that are configurable on this device. Figure 5-1. Configuration Example A (Two I2C Two McASP GPIO) DEVICE CONFIGURATIONS Submit Documentation Feedback

ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 SCL0,□SDA0 AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 DEVCFG□Register□Value: 0x0000□000E MCBSP0DIS□= 1 MCBSP1DIS□= 0 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . DR1,□CLKS1, CLKR1,□CLKX1, FSR1,□DX1, FSX1 AXR1[7:0] AXR0[4:0] {TINP0/AXR0[3]} TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0,□AFSR0, AFSX0 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 5-2. Configuration Example B (One I2C One McBSP Two McASP GPIO) Submit Documentation Feedback DEVICE CONFIGURATIONS

ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 SCL1,□SDA1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 (DIT□Mode) SCL0,□SDA0 AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 DEVCFG□Register□Value: 0x0000□000D MCBSP0DIS□= 0 MCBSP1DIS□= 1 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . DR0,□CLKS0, CLKR0,□CLKX0, FSR0,□DX0, FSX0 AXR1[7:0] AXR0[7:2] {TINP0/AXR0[3]} AMUTE0, TINP1/AHCLKX0 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 5-3. Configuration Example C I2C McBSP McASP McASP (DIT) GPIO] DEVICE CONFIGURATIONS Submit Documentation Feedback

ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1DR1,□CLKS1, CLKR1,□CLKX1, FSR1,□DX1, FSX1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 (DIT□Mode) SCL0,□SDA0 AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 DEVCFG□Register□Value: 0x0000□000C MCBSP0DIS□= 0 MCBSP1DIS□= 0 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . DR0,□CLKS0, CLKR0,□CLKX0, FSR0,□DX0, FSX0 AXR1[7:0] AXR0[4:2] {TINP0/AXR0[3]} TINP1/AHCLKX0 TOUT0/AXR0[2] TOUT1/AXR0[4] SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 5-4. Configuration Example D I2C McBSP McASP McASP (DIT) GPIO Timers] Submit Documentation Feedback DEVICE CONFIGURATIONS

ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 SCL1,□SDA1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 McASP0 AXR0[7:0], {TINP0/AXR0[3]} DEVCFG□Register□Value: 0x0000□000F MCBSP0DIS□= 1 MCBSP1DIS□= 1 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□1 GP2EN□BIT□=□0□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . CLKOUT2 HD[15:0] HINT,□HHWIL, HRDY,□HR/W, HCNTRL1, HCNTRL0,□HCS, HDS2,□HDS1, HAS I2C0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0,□AFSR0, AFSX0 SCL0,□SDA0 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 5-5. Configuration Example E I2C HPI McASP) DEVICE CONFIGURATIONS Submit Documentation Feedback

ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 McASP0 DEVCFG□Register□Value: 0x0000□000E MCBSP0DIS□= 1 MCBSP1DIS□= 1 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□1 GP2EN□BIT□=□0□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . DR1,□CLKS1, CLKR1,□CLKX1, FSR1,□DX1, FSX1 CLKOUT2 HD[15:0] HINT,□HHWIL, HRDY,□HR/W, HCNTRL1, HCNTRL0,□HCS, HDS2,□HDS1, HAS AXR0[4:0] {TINP0/AXR0[3]} I2C0 TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0,□AFSR0, AFSX0 SCL0,□SDA0 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 5-6. Configuration Example F (One McBSP HPI One McASP) Submit Documentation Feedback DEVICE CONFIGURATIONS

5.6 Debugging Considerations TERMINAL FUNCTIONS SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com It is recommended that external connections be provided to peripheral selection/device configuration pins, including HD[14, (for 13B only), 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non configuration pins on the HPI data bus (HD[15, 13:9, 7:5, 2:0] (for 13) and HD[15, 13, 11:9, 7:5, 2:0] (for 13B)). For proper device operation of the HD[15, 13:9, (for13) or HD[13, 11:9, (for 13B), do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these HD[15, 13:9, (for 13) or HD[13, 11:9, (for 13B) non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. However, the HD[6, (for 13) or HD[15, (for 13B) non-configuration pins can be opposed and driven during reset. For the internal pullup/pulldown resistors for all device pins, see the Terminal Functions table. The Terminal Functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet. TERMINAL FUNCTIONS Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 TERMINAL FUNCTIONS PIN NO. SIGNAL NAME TYPE (1) IPD/IPU (2) I IPD Clock input Clock output at half of device speed O/Z [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed CLKOUT2/GP[2] Y12 O/Z IPD as GP[2] pin (I/O/Z). CLKOUT3 D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller Clock generator input clock source select Reserved, do not use CLKMODE0 I IPU CLKIN square wave [default] For proper device operation, this pin must be either left unconnected or externally pulled up with a 1-k Ω resistor. PLLHV A (3) Analog power (3.3 for PLL (PLL filter) JTAG EMULATION TMS I IPU JTAG test-port mode select TDO O/Z IPU JTAG test-port data out TDI I IPU JTAG test-port data in TCK I IPU JTAG test-port clock JTAG test-port reset. For IEEE Std 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data TRST I IPD sheet. EMU5 B12 I/O/Z IPU Emulation pin Reserved for future use, leave unconnected. EMU4 C11 I/O/Z IPU Emulation pin Reserved for future use, leave unconnected. EMU3 B10 I/O/Z IPU Emulation pin Reserved for future use, leave unconnected. EMU2 I/O/Z IPU Emulation pin Reserved for future use, leave unconnected. Emulation [1:0] Select the device functional mode of operation Operation: EMU[1:0]: Boundary Scan/Functional Mode (see note) Reserved EMU1 I/O/Z IPU Reserved EMU0 Emulation/Functional Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement of this data sheet) The DSP can be placed in Functional mode when the EMU[1:0] pins are configured for either boundary scan or emulation. Note: When the EMU[1:0] pins are configured for boundary scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed to operate in functional mode. For the boundary scan mode, drive EMU[1:0] and RESET pins low. RESETS AND INTERRUPTS RESET A13 I IPU Device reset. When using boundary scan mode, drive the EMU[1:0] and RESET pins low. Nonmaskable interrupt NMI C13 I IPD Edge-driven (rising edge) GP7 General-purpose input/output pins (I/O/Z), which also function as external interrupts Edge-driven GP6 Polarity independently selected via the external interrupt polarity register bits (EXTPOL.[3:0]), in addition to the GPIO registers. I/O/Z IPU GP5/ AMUTEIN0 GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the associated McASP AMUTE register. GP4/ AMUTEIN1 HOST-PORT INTERFACE (HPI) HINT /GP[1] J20 O/Z IPU Host interrupt (from DSP to host) O [default] or this pin can be programmed as a GP[1] pin (I/O/Z) HCNTL1/AXR1[1] G19 I IPU Host control: Selects between control, address, or data registers (I) [default] or McASP1 data pin (I/O/Z) HCNTL0/AXR1[3] G18 I IPU Host control: Selects between control, address, or data registers (I) [default] or McASP1 data pin (I/O/Z) Host half-word select: First or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync HHWIL/AFSR1 H20 I IPU or left/right clock (LRCLK) (I/O/Z). HR/W/AXR1[0] G20 I IPU Host read or write select I [default] or McASP1 data pin (I/O/Z) (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground (2) IPD Internal pulldown, IPU Internal pullup. [These IPD/IPU signal pins feature a 13-k Ω resistor (approximate) for the IPD or 18-k Ω resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k Ω and 2.0 k Ω respectively, should be used to pull a signal to the opposite supply rail.] (3) A Analog signal Submit Documentation Feedback TERMINAL FUNCTIONS

www.ti.com TERMINAL FUNCTIONS (continued) PIN NO. SIGNAL NAME TYPE (1) IPD/IPU (2) [default] or general-purpose input/output pins (I/O/Z) Used for transfer of data, address, and control Also controls initialization of DSP modes at reset via pullup/pulldown resistors Device Endian mode (HD8) Big Endian HD15/GP[15] B14 Little Endian HD14/GP[14] C14 Boot mode (HD[4:3]) HD13/GP[13] A15 HD12/GP[12] C15 00: CE1 width 32-bit, HPI boot/emulation boot HD11/GP[11] A16 I/O/Z IPU HD10/GP[10] B16 01: CE1 width 8-bit, asynchronous external ROM boot with default timings (default mode) HD9/GP[9] C16 10: CE1 width 16-bit, asynchronous external ROM boot with default timings HD8/GP[8] B17 HD7/GP[3] A18 11: CE1 width 32-bit, asynchronous external ROM boot with default timings HPI_EN (HD14) HPI disabled, McASP1 enabled HPI enabled, McASP1 disabled (default) Other HD pins (HD [15, 13:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For proper device operation, do not oppose these pins with external IPUs/IPDs at reset. For more details, see the Device Configurations section of this data sheet. HD6/AHCLKR1 C17 I/O/Z IPU Host-port data pin I/O/Z) [default] or McASP1 receive high-frequency master clock (I/O/Z) HD5/AHCLKX1 B18 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 transmit high-frequency master clock (I/O/Z) HD4/GP[0] C19 I/O/Z IPD Host-port data pin I/O/Z [default] or this pin can be programmed as a GP[0] pin (I/O/Z) HD3/AMUTE1 C20 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 mute output (O/Z) HD2/AFSX1 D18 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z) HD1/AXR1[7] D20 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 data pin (I/O/Z) HD0/AXR1[4] E20 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 data pin (I/O/Z) HAS /ACLKX1 E18 I IPU Host address strobe I [default] or McASP1 transmit bit clock (I/O/Z) HCS /AXR1[2] F20 I IPU Host chip select I [default] or McASP1 data pin (I/O/Z) HDS1 /AXR1[6] E19 I IPU Host data strobe I [default] or McASP1 data pin (I/O/Z) HDS2 /AXR1[5] F18 I IPU Host data strobe I [default] or McASP1 data pin (I/O/Z) HRDY /ACLKR1 H19 O/Z IPD Host ready (from DSP to host) O [default] or McASP1 receive bit clock (I/O/Z) EMIF COMMON SIGNALS TO ALL TYPES OF MEMORY (4) CE3 Memory space enables CE2 O/Z IPU Enabled by bits through of the word address CE1 W18 Only one asserted during any external data access CE0 V17 BE3 Byte-enable control BE2 Decoded from the two lowest bits of the internal address O/Z IPU Byte-write enables for most types of memory BE1 U19 Can be directly connected to SDRAM read and write mask signal (SDQM) BE0 V20 EMIF BUS ARBITRATION (4) HOLDA J18 O/Z IPU Hold-request-acknowledge to the host HOLD J17 I IPU Hold request from the host BUSREQ J19 O/Z IPU Bus request output EMIF ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL (4) ECLKIN Y11 I IPD External EMIF input clock source EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]). EKSRC ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default). ECLKOUT Y10 O/Z IPD EKSRC ECLKOUT is based on the external EMIF input clock source pin (ECLKIN) EKEN ECLKOUT held low EKEN ECLKOUT enabled to clock (default) ARE SDCAS V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe SSADS AOE SDRAS SSOE W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable AWE SDWE SSWE V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable ARDY I IPU Asynchronous memory ready input (4) To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. TERMINAL FUNCTIONS Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 TERMINAL FUNCTIONS (continued) PIN NO. SIGNAL NAME TYPE (1) IPD/IPU (2) (4) EA21 U18 EA20 Y18 EA19 W17 EA18 Y16 EA17 V16 EA16 Y15 EA15 W15 EA14 Y14 External address (word, half-word, and byte address) EA13 W14 The EMIF adjusts the address based on memory width: EA12 V14 Width Pins Address O/Z IPU EA11 W13 21:2 through EA10 V10 21:2 through EA9 21:2 through EA8 EA7 For more details on address width adjustments, see the External Memory Interface (EMIF) chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190) EA6 EA5 EA4 EA3 EA2 EMIF DATA (4) ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 I/O/Z IPU External data pins (ED[31:16] pins applicable to GDP package only) ED15 T19 ED14 T20 ED13 T18 ED12 R20 ED11 R19 ED10 P20 ED9 P18 ED8 N20 ED7 N19 ED6 N18 ED5 M20 ED4 M19 ED3 L19 ED2 L18 ED1 K19 ED0 K18 Submit Documentation Feedback TERMINAL FUNCTIONS

www.ti.com TERMINAL FUNCTIONS (continued) PIN NO. SIGNAL NAME TYPE (1) IPD/IPU (2) (McASP1) GP4/ I/O/Z IPU General-purpose input/output pin and external interrupt I/O/Z [default] or McASP1 mute input (I/O/Z) AMUTEIN1 HD3/AMUTE1 C20 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 mute output (O/Z) HRDY /ACLKR1 H19 I/O/Z IPU Host ready (from DSP to host) O [default] or McASP1 receive bit clock (I/O/Z) HD6/AHCLKR1 C17 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 receive high-frequency master clock (I/O/Z) HAS /ACLKX1 E18 I/O/Z IPU Host address strobe I [default] or McASP transmit bit clock (I/O/Z) HD5/AHCLKX1 B18 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 transmit high-frequency master clock (I/O/Z) Host half-word select first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or HHWIL/AFSR1 H20 I/O/Z IPU left/right clock (LRCLK) (I/O/Z) HD2/AFSX1 D18 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z) HD1/AXR1[7] D20 I/O/Z IPU Host-port data pin I/O/Z [default] or McASP1 TX/RX data pin (I/O/Z) HDS1 /AXR1[6] E19 I/O/Z IPU Host data strobe I [default] or McASP1 TX/RX data pin (I/O/Z) HDS2 /AXR1[5] F18 I/O/Z IPU Host data strobe I [default] or McASP1 TX/RX data pin (I/O/Z) HD0/AXR1[4] E20 I/O/Z IPU Host-port data pin (I/O/Z) [default] or McASP1 TX/RX data pin (I/O/Z) HCNTL0/AXR1[3] G18 I/O/Z IPU Host control selects between control, address, or data registers I [default] or McASP1 TX/RX data pin (I/O/Z) HCS /AXR1[2] F20 I/O/Z IPU Host chip select I [default] or McASP1 TX/RX data pin (I/O/Z) HCNTL1/AXR1[1] G19 I/O/Z IPU Host control selects between control, address, or data registers I [default] or McASP1 TX/RX data pin (I/O/Z) HR/ W /AXR1[0] G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 TX/RX data pin (I/O/Z) MULTICHANNEL AUDIO SERIAL PORT (McASP0) GP5/ I/O/Z IPU General-purpose input/output pin and external interrupt I/O/Z [default] or McASP0 mute input (I/O/Z) AMUTEIN0 CLKX1/AMUTE0 I/O/Z IPD McBSP1 transmit clock I/O/Z [default] or McASP0 mute output (O/Z) CLKR0/ACLKR0 I/O/Z IPD McBSP0 receive clock I/O/Z [default] or McASP0 receive bit clock (I/O/Z) TINP1/AHCLKX0 I/O/Z IPD Timer input I [default] or McBSP0 transmit high-frequency master clock (I/O/Z) CLKX0/ACLKX0 I/O/Z IPD McBSP0 transmit clock I/O/Z [default] or McASP0 transmit bit clock (I/O/Z) CLKS0/AHCLKR0 I/O/Z IPD McBSP0 external clock source (as opposed to internal) I [default] or McASP0 receive high-frequency master clock (I/O/Z) FSR0/AFSR0 I/O/Z IPD McBSP0 receive frame sync I/O/Z [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z) FSX0/AFSX0 I/O/Z IPD McBSP0 transmit frame sync I/O/Z [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z) FSR1/AXR0[7] I/O/Z IPD McBSP1 receive frame sync I/O/Z [default] or McASP0 TX/RX data pin (I/O/Z) CLKR1/AXR0[6] I/O/Z IPD McBSP1 receive clock I/O/Z [default] or McASP0 TX/RX data pin (I/O/Z) DX1/AXR0[5] I/O/Z IPU McBSP1 transmit data O/Z [default] or McASP0 TX/RX data pin (I/O/Z) TOUT1/AXR0[4] I/O/Z IPD Timer output O [default] or McASP0 TX/RX data pin (I/O/Z) TINP0/AXR0[3] I/O/Z IPD Timer input I [default] or McASP0 TX/RX data pin (I/O/Z) TOUT0/AXR0[2] I/O/Z IPD Timer output O [default] or McASP0 TX/RX data pin (I/O/Z) DX0/AXR0[1] I/O/Z IPU McBSP0 transmit data O/Z [default] or McASP0 TX/RX data pin (I/O/Z) DR0/AXR0[0] I/O/Z IPU McBSP0 receive data I [default] or McASP0 TX/RX data pin (I/O/Z) TIMER1 TOUT1/AXR0[4] O IPD Timer output O [default] or McASP0 TX/RX data pin (I/O/Z) TINP1/AHCLKX0 I IPD Timer input I [default] or McBSP0 transmit high-frequency master clock (I/O/Z) TIMER0 TOUT0/AXR0[2] O IPD Timer output O [default] or McASP0 TX/RX data pin (I/O/Z) TINP0/AXR0[3] I IPD Timer input I [default] or McASP0 TX/RX data pin (I/O/Z) MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) McBSP1 external clock source (as opposed to internal) I [default] or I2C1 clock (I/O/Z). This pin does not have an internal pullup or pulldown. When this pin is used as a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-k Ω CLKS1/SCL1 I resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-k Ω pullup resistor may be desirable even when an external device is driving the pin. CLKR1/AXR0[6] I/O/Z IPD McBSP1 receive clock I/O/Z [default] or McASP0 TX/RX data pin (I/O/Z) CLKX1/AMUTE0 I/O/Z IPD McBSP1 transmit clock I/O/Z [default] or McASP0 mute output (O/Z) McBSP1 receive data I [default] or I2C1 data (I/O/Z). This pin does not have an internal pullup or pulldown. When this pin is used as a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-k Ω resistor to a valid logic level. Because it DR1/SDA1 I is common for some ICs to 3-state their outputs at times, a 10-k Ω pullup resistor may be desirable even when an external device is driving the pin. DX1/AXR0[5] O/Z IPU McBSP1 transmit data O/Z [default] or McASP0 TX/RX data pin (I/O/Z) FSR1/AXR0[7] I/O/Z IPD McBSP1 receive frame sync I/O/Z [default] or McASP0 TX/RX data pin (I/O/Z) FSX1 I/O/Z IPD McBSP1 transmit frame sync TERMINAL FUNCTIONS Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 TERMINAL FUNCTIONS (continued) PIN NO. SIGNAL NAME TYPE (1) IPD/IPU (2) (McBSP0) CLKS0/AHCLKR0 I IPD McBSP0 external clock source (as opposed to internal) I [default] or McASP0 receive high-frequency master clock (I/O/Z) CLKR0/ACLKR0 I/O/Z IPD McBSP0 receive clock I/O/Z [default] or McASP0 receive bit clock (I/O/Z) CLKX0/ACLKX0 I/O/Z IPD McBSP0 transmit clock I/O/Z [default] or McASP0 transmit bit clock (I/O/Z) DR0/AXR0[0] I IPU McBSP0 receive data I [default] or McASP0 TX/RX data pin (I/O/Z) DX0/AXR0[1] O/Z IPU McBSP0 transmit data O/Z [default] or McASP0 TX/RX data pin (I/O/Z) FSR0/AFSR0 I/O/Z IPD McBSP0 receive frame sync I/O/Z [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z) FSX0/AFSX0 I/O/Z IPD McBSP0 transmit frame sync I/O/Z [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z) INTER-INTEGRATED CIRCUIT (I2C1) McBSP1 external clock source (as opposed to internal) I [default] or I2C1 clock (I/O/Z). This pin must be externally pulled up. When CLKS1/SCL1 I/O/Z this pin is used as an I C pin, the value of the pullup resistor depends on the number of devices connected to the I C bus. For more details, see the Philips I C Specification Revision 2.1 (January 2000). McBSP1 receive data I [default] or I2C1 data (I/O/Z). This pin must be externally pulled up. When this pin is used as an I C pin, the DR1/SDA1 I/O/Z value of the pullup resistor depends on the number of devices connected to the I C bus. For more details, see the Philips I C Specification Revision 2.1 (January 2000). INTER-INTEGRATED CIRCUIT (I2C0) I2C0 clock. This pin must be externally pulled up. When this pin is used as an I C pin, the value of the pull-up resistor depends on the SCL0 I/O/Z number of devices connected to the I C bus. For more details, see the Philips I C Specification Revision 2.1 (January 2000). I2C0 data. This pin must be externally pulled up. When this pin is used as an I C pin, the value of the pull-up resistor depends on the SDA0 I/O/Z number of devices connected to the I C bus. For more details, see the Philips I C Specification Revision 2.1 (January 2000). GENERAL-PURPOSE INPUT/OUTPUT (GPIO) HD15/GP[15] B14 I/O/Z IPU Host-port data pins I/O/Z [default] or general-purpose input/output pins (I/O/Z) and some function as boot configuration pins at reset. Used for transfer of data, address, and control HD14/GP[14] C14 I/O/Z IPU Also controls initialization of DSP modes at reset via pullup/pulldown resistors HD13/GP[13] A15 I/O/Z IPU abc As general-purpose input/output (GP[x]) functions, these pins are software configurable through registers. The GPxEN bits in the GP HD12/GP[12] C15 I/O/Z IPU Enable register and the GPxDIR bits in the GP Direction register must be properly configured: HD11/GP[11] A16 I/O/Z IPU abc GPxEN GP[x] pin is enabled. HD10/GP[10] B16 I/O/Z IPU GPxDIR GP[x] pin is an input. HD9/GP[9] C16 I/O/Z IPU GPxDIR GP[x] pin is an output. abc For the functionality pins, see the Host-Port Interface (HPI) portion of HD8/GP[8] B17 I/O/Z IPU this table. GP7 I/O/Z IPU General-purpose input/output pins I/O/Z that also function as external interrupts GP6 I/O/Z IPU Edge-driven GP5/A Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) I/O/Z IPU MUTEIN0 abc GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by GP4/ the INEN bit in the associated McASP AMUTE register. I/O/Z IPU AMUTEIN1 HD7/GP[3] A18 I/O/Z IPU Host-port data pin I/O/Z [default] or general-purpose input/output pin (I/O/Z) CLKOUT2/GP[2] Y12 I/O/Z IPD Clock output at half of device speed O/Z [default] or this pin can be programmed as GP[2] pin HINT /GP[1] J20 O IPU Host interrupt (from DSP to host) O [default] or this pin can be programmed as a GP[1] pin (I/O/Z) HD4/GP[0] C19 I/O/Z IPD Host-port data pin I/O/Z [default] or this pin can be programmed as a GP[0] pin (I/O/Z) RESERVED FOR TEST RSV O/Z IPU Reserved. (Leave unconnected; do not connect to power or ground.) RSV A (3) Reserved. (Leave unconnected; do not connect to power or ground.) RSV C12 O Reserved. (Leave unconnected; do not connect to power or ground.) RSV O/Z IPD Reserved. (Leave unconnected; do not connect to power or ground.) Reserved. This pin does not have an IPU. For proper C6713 device operation, the D12 pin must be externally pulled down with a RSV D12 I 10-k Ω resistor. Reserved. For new designs, it is recommended that this pin be connected directly to VC DD (core power). For old designs, this can be RSV A12 left unconnected. Reserved. For new designs, it is recommended that this pin be connected directly to V SS (ground). For old designs, this pin can be left RSV B11 unconneced. Submit Documentation Feedback TERMINAL FUNCTIONS

www.ti.com TERMINAL FUNCTIONS (continued) PIN NO. SIGNAL NAME TYPE (1) IPD/IPU (2) 3.3-V supply voltage DV DD R18 S (see the Power-Supply Decoupling section of this data sheet) U12 U16 V13 V15 V19 W12 Y17 A10 B19 C18 D11 D14 D15 F17 1.26-V supply voltage CV DD S (see the Power-Supply Decoupling section of this data sheet) K17 L17 L20 R17 U10 U11 U14 U15 V18 W19 TERMINAL FUNCTIONS Submit Documentation Feedback

6.1 Development Support SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 TERMINAL FUNCTIONS (continued) PIN NO. SIGNAL NAME TYPE (1) IPD/IPU (2) (1) The center thermal balls (J9 J12, K12, L12, M12) [shaded] are all tied to ground and act as both electrical V SS K12 GND grounds and thermal relief (thermal dissipation). K20 L10 L11 L12 M10 M11 M12 M17 N17 P17 P19 T17 U13 U17 U20 W11 W16 W20 Y13 Y19 Y20 (1) Shaded pin numbers denote the center thermal balls. TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Submit Documentation Feedback TERMINAL FUNCTIONS

6.2 Device and Development-Support Tool Nomenclature 6.2.1 Device Development Evolutionary Flow 6.2.2 Support Tool Development Evolutionary Flow SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Software Development Tools Code Composer Studio Integrated Development Environment (IDE), including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software DSP/BIOS which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools Extended Development System XDS Emulator (supports C6000 DSP multiprocessor system debug) EVM (evaluation module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site at www.ti.com For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: SMX, TMP, or SM/SMJ. TI recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SM/SMJ/TMDS). SMX Preproduction device that is not necessarily representative of the final device electrical specifications TMP Final silicon die that conforms to the device electrical specifications but has not completed quality and reliability verification SM/SMJ Fully qualified production device TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product SMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (SMX) may not be representative of a final product and TI reserves the right to change or discontinue these products without notice. SM/SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI s standard warranty applies. Predictions show that prototype devices (SMX or TMP) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GDP the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, is 200 MHz). Figure 6-1 provides a legend for reading the complete device name for any TMS320C6000 DSP family member. TERMINAL FUNCTIONS Submit Documentation Feedback

6.3 Ordering Nomenclature PREFIX ENHANCED□PLASTIC□INDICATOR SM 320 C 6713 GDP 20 SMX= Experimental□device TMP= Prototype□device TMS= Qualified□device SMJ= MIL-PRF-38535,□QML SM Commercial□processing DEVICE□FAMILY 320 = TMS320 /c228 DSP□family TECHNOLOGY PACKAGE□TYPE□(See□Note□1) C CMOS DEVICE TEMPERATURE□RANGE□(DEFAULT:□0/c176 C TO 90/c176 C) (□□□) C6000□DSP: C6713 C6713B GDP = 272-pin□plastic□BGA GFN= 256-pin□plastic□BGA GGP = 352-pin□plastic□BGA GJC= 352-pin□plastic□BGA GJL= 352-pin□plastic□BGA GLS= 384-pin□plastic□BGA GLW= 340-pin□plastic□BGA GNY = 384-pin□plastic□BGA GNZ = 352-pin□plastic□BGA GLZ= 532-pin□plastic□BGA GHK = 288-pin□plastic□MicroStar□BGA /c228 PYP = 208-pin□PowerPAD /c228 plastic□QFP 20 = 200□MHz EP DEVICE□SPEED□RANGE Blank□□=□□0 C□to□90 C□(commercial□temperature) /c176 /c176 /c176 /c176 /c176 /c176 /c45 /c176 /c176 /c45 QFP□=□Quad□Flatpack 6.4 Documentation Support SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 6-1. 320C6713 and C6713B Device Part Numbers (P/Ns) and Ordering Information (1) CORE AND I/O VOLTAGE OPERATING CASE DEVICE ORDERABLE P/N (2) DEVICE SPEED TEMPERATURE CV DD (CORE) DV DD (I/O) RANGE C6713B SM32C6713BGDPA20EP 200 MHz/1200 MFlops 1.26 V 3.3 V C to 105 C SM32C6713BGDPM30EP 300 MHz/1800 MFlops 1.4V 3.3V C to 125 C SM32C6713BGDPS20EP 200 MHz/1200 MFlops 1.26 V 3.3 V C to 105 C (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package Figure 6-1. TMS320C6000 DSP Device Nomenclature (Including SM320C6713 and C6713B Devices) Extensive documentation supports all the TMS320 DSP family generations of devices from product announcement through development. The types of documentation available include data sheets, such as this document with design specifications complete user s reference guides for all devices and tools, technical briefs, development-support tools, on-line help, and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices, except where noted, all documents are accessible through the TI web site at www.ti.com. TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. Submit Documentation Feedback TERMINAL FUNCTIONS

www.ti.com TMS320C6000 DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000 PRG Overview (literature number SPRU190) provides an overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. These C6713/13B peripherals are similar to the peripherals on the TMS320C6711 and TMS320C64x devices; therefore, see the TMS320C6711 (C6711 or C67x) peripheral information and, in some cases (where indicated), see the TMS320C6711 (C6711 or C671x) peripheral information and, in some cases (where indicated), see the C64x information in the C6000 PRG Overview (literature number SPRU190). TMS320DA6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041) describes the functionality of the McASP peripherals available on the C6713/13B device. TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233) describes the functionality of the PLL peripheral available on the C6713/13B device. TMS320C6000 DSP Inter-Integrated Circuit Module Reference Guide (literature number SPRU175) describes the functionality of the I C peripherals available on the C6713/13B device. The PowerPAD Thermally-Enhanced Package Technical Brief (literature number SLMA002) focuses on the specifics of integrating a PowerPAD package into the printed circuit board (PCB) design to make optimum use of the thermal efficiencies designed into the PowerPAD package. TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x C67x devices, associated development tools, and third-party support. Migrating from TMS320C6211(B)/C6711(B) to TMS320C6713 application report (literature number SPRA851) indicates the differences and describes the issues of interest related to the migration from the TI TMS320C6211(B)/C6711(B) GFN package to the TMS320C6713 GDP package. TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191) describes the known exceptions to the functional specifications for particular silicon revisions of the TMS320C6713 and TMS320C6713B devices. TMS320C6713/12C/11C Power Consumption Summary application report (literature number SPRA889) discusses the power consumption for user TMS320C6713/13B, TMS320C6712C/12D, and TMS320C6711C/11D DSP devices. Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site at www.ti.com Also, see the TI web site for the application report, How To Begin Development Today With the TMS320C6713 Floating-Point DSP (literature number SPRA809), which describes in more detail the similarities/differences between the C6713 and C6711 C6000 DSP devices. TERMINAL FUNCTIONS Submit Documentation Feedback

7.1 CPU Control Status Register (CSR) CPU□ID REVISION□ID 15 10 98 76 54 21 0 PWRD SAT EN PCC DCC PGIE GIE R/W-0R /C-0 R-1R /W-0 R/W-0R /W-0 R/W-0 Legend: R□□=□Readable□by□the□MVC□instruction,□R/W□=□Readable/Writeable□by□the□MVC□instruction;□W□=□Read/write;□-n□=□value□after□reset,□-x□=□undefined□value□after reset,□C□=□Clearable□by□the□MVC□instruction SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 This section provides the register information for the device. The CPU CSR contains the CPU ID and CPU Revision ID (bits 31), as well as the status of the device power-down modes [PWRD field (bits 10)], program and data cache control modes, the endian bit (EN, bit 8), and the global interrupt enable (GIE, bit and previous GIE (PGIE, bit 1). Figure 7-1 and Table 7-1 identify the bit fields in the CPU CSR. For more detailed information on the bit fields in the CPU CSR, see the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 7-1. CPU Control Status Register (CPU CSR) Submit Documentation Feedback REGISTER INFORMATION

7.2 Cache Configuration (CCFG) Register (13B) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 7-1. CPU CSR Bit Field NO. NAME 31:24 CPU ID CPU ID REV ID. Read only. Identifies which CPU is used and defines the silicon revision of the CPU. CPU ID REVISION ID (31:16) are combined for a value of: 0x0203 for C6713/13B 23:16 REVISION ID 15:10 PWRD Control power-down modes. The values are always read as zero. 000000 No power down (default) 001001 PD1, wake up by an enabled interrupt 010001 PD1, wake up by an enabled or not enabled interrupt 011010 PD2, wake up by a device reset 011100 PD3, wake up by a device reset Others Reserved SAT Saturate bit. Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false. EN Endian bit. This bit is read-only. Depicts the device endian mode. Big Endian mode Little Endian mode [default] 7:5 PCC Program cache control mode. L1D, Level program cache Cache enabled/cache accessed and updated on reads All other PCC values are reserved. 4:2 DCC Data cache control mode. L1D, Level data cache Cache enabled/2-way cache All other DCC values are reserved. PGIE Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is taken. Allows for proper nesting of interrupts. Previous GIE value is (default). Previous GIE value is GIE Global interrupt enable bit. Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt). Disables all interrupts (except the reset interrupt and NMI) [default]. Enables all interrupts (except the reset interrupt and NMI). The C6713B device includes an enhancement to the CCFG register. A P bit (CCFG.31) allows the programmer to select the priority of accesses to memory originating from the transfer crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is EDMA transfers, which move data to or from the memory. While the EDMA normally has no issue accessing memory because of the high hit rates on the L1D memory system, there are pathological cases where certain CPU behavior could block the EDMA from accessing the memory for long enough to cause a missed deadline when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit to because the EDMA will assume a higher priority than the L1D memory system when accessing memory. For more detailed information on the P-bit function and for silicon advisories concerning EDMA memory accesses blocked, see the TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191). REGISTER INFORMATION Submit Documentation Feedback

P Reserved IP ID Reserved L2MODE R/W-0 R-x W-0 W-0 R-0□0000 R/W-000 (1) A:□Unlike□the□C6713□device,□the□C6713B□device□includes□a□P□bit. Legend: R□□=□Readable;□R/W□=□Readable/Writeable;□-n□=□value□after□reset,□-x□=□undefined□value□after□reset 7.3 Interrupts and Interrupt Selector SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Unlike the C6713 device, the C6713B device includes a P bit. Figure 7-2. Cache Configuration (CCFG) Register Table 7-2. CCFG Register Bit Field NO. NAME P P L1D requests to higher priority than TC requests P TC requests to higher priority than L1D requests 30:10 Reserved Reserved. Read only, writes have no effect. Invalidate L1P bit IP Normal L1P operation All L1P lines are invalidated Invalidate L1D bit ID Normal L1D operation All L1D lines are invalidated 7:3 Reserved Reserved. Read only, writes have no effect. operation mode bits (L2MODE) 000b cache disabled (All SRAM mode) [256K SRAM] 001b 1-way cache (16K cache) [240K SRAM] 2:0 L2MODE 010b 2-way cache (32K cache) [224K SRAM] 011b 3-way cache (48K cache) [208K SRAM] 111b 4-way cache (64K cache) [192K SRAM] All others are reserved. The C67x DSP core supports prioritized interrupts, which are listed in Table 7-3 The highest priority interrupt is INT_00 (dedicated to RESET), while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts 15) are maskable and default to the interrupt source listed in Table 7-3 However, their interrupt source may be reprogrammed to any one of the sources listed in Table 7-4 (Interrupt Selector). Table 7-4 lists the selector value corresponding to each of the alternate interrupt sources. The selector choice for interrupts is made by programming the corresponding fields (listed in Table 7-3 in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers. Table 7-3. DSP Interrupts INTERRUPT DEFAULT DEFAULT DSP SELECTOR CONTROL SELECTOR VALUE INTERRUPT INTERRUPT NUMBER REGISTER (BINARY) EVENT INT_00 RESET INT_01 NMI INT_02 Reserved INT_03 Reserved Submit Documentation Feedback REGISTER INFORMATION

www.ti.com Table 7-3. DSP Interrupts (continued) INTERRUPT DEFAULT DEFAULT DSP SELECTOR CONTROL SELECTOR VALUE INTERRUPT INTERRUPT NUMBER REGISTER (BINARY) EVENT INT_04 MUXL[4:0] 00100 GPINT4 (1) INT_05 MUXL[9:5] 00101 GPINT5 (1) INT_06 MUXL[14:10] 00110 GPINT6 (1) INT_07 MUXL[20:16] 00111 GPINT7 (1) INT_08 MUXL[25:21] 01000 EDMAINT INT_09 MUXL[30:26] 01001 EMUDTDMA INT_10 MUXH[4:0] 00011 SDINT INT_11 MUXH[9:5] 01010 EMURTDXRX INT_12 MUXH[14:10] 01011 EMURTDXTX INT_13 MUXH[20:16] 00000 DSPINT INT_14 MUXH[25:21] 00001 TINT0 INT_15 MUXH[30:26] 00010 TINT1 (1) Interrupt events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, and GP7. These pins can be used as edge-sensitive EXT_INTx with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0] bits. For more information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). REGISTER INFORMATION Submit Documentation Feedback

7.4 External Interrupt Sources SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 7-4. Interrupt Selector INTERRUPT SELECTOR VALUE INTERRUPT EVENT MODULE (BINARY) 00000 DSPINT HPI 00001 TINT0 Timer 00010 TINT1 Timer 00011 SDINT EMIF 00100 GPINT4 (1) GPIO 00101 GPINT5 (1) GPIO 00110 GPINT6 (1) GPIO 00111 GPINT7 (1) GPIO 01000 EDMAINT EDMA 01001 EMUDTDMA Emulation 01010 EMURTDXRX Emulation 01011 EMURTDXTX Emulation 01100 XINT0 McBSP0 01101 RINT0 McBSP0 01110 XINT1 McBSP1 01111 RINT1 McBSP1 10000 GPINT0 GPIO 10001 Reserved 10010 Reserved 10011 Reserved 10100 Reserved 10101 Reserved 10110 I2CINT0 I2C0 10111 I2CINT1 I2C1 11000 Reserved 11001 Reserved 11010 Reserved 11011 Reserved 11100 AXINT0 McASP0 11101 ARINT0 McASP0 11110 AXINT1 McASP1 11111 ARINT1 McASP1 (1) Interrupt events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, and GP7. These pins can be used as edge-sensitive EXT_INTx with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0] bits. For more information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). The C6713/13B device supports many external interrupt sources as indicated in Table 7-5 Control of the interrupt source is done by the associated module and is made available by enabling the corresponding binary interrupt selector value (see Table 7-4 shaded rows). Because of pin multiplexing and module usage, not all external interrupt sources are available at the same time. Submit Documentation Feedback REGISTER INFORMATION

7.5 EDMA Module and EDMA Selector SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 7-5. External Interrupt Sources and Peripheral Module Control PIN NAME INTERRUPT EVENT MODULE GP[15] GPINT0 GPIO GP[14] GPINT0 GPIO GP[13 GPINT0 GPIO GP[12] GPINT0 GPIO GP[11] GPINT0 GPIO GP[10] GPINT0 GPIO GP[9] GPINT0 GPIO GP[8] GPINT0 GPIO GP[7] GPINT0 or GPINT7 GPIO GP[6] GPINT0 or GPINT6 GPIO GP[5] GPINT0 or GPINT5 GPIO GP[4] GPINT0 or GPINT4 GPIO GP[3] GPINT0 GPIO GP[2] GPINT0 GPIO GP[1] GPINT0 GPIO GP[0] GPINT0 GPIO The C67x EDMA supports up to EDMA channels. Four of the channels (channels 11) are reserved for EDMA chaining, leaving EDMA channels available to service peripheral devices. The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned EDMA selector code (see Table 7-7 By loading each EVTSELx register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA channel. Table 7-6 lists the default EDMA selector value for each EDMA channel. See Table 7-8 and Table 7-11 for the EDMA Event Selector registers and their associated bit descriptions. REGISTER INFORMATION Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 7-6. EDMA Channels EDMA SELECTOR DEFAULT SELECTOR EDMA CHANNEL DEFAULT EDMA EVENT CONTROL REGISTER VALUE (BINARY) ESEL0[5:0] 000000 DSPINT ESEL0[13:8] 000001 TINT0 ESEL0[21:16] 000010 TINT1 ESEL0[29:24] 000011 SDINT ESEL1[5:0] 000100 GPINT4 ESEL1[13:8] 000101 GPINT5 ESEL1[21:16] 000110 GPINT6 ESEL1[29:24] 000111 GPINT7 TCC8 (Chaining) TCC9 (Chaining) TCC10 (Chaining) TCC11 (Chaining) ESEL3[5:0] 001100 XEVT0 ESEL3[13:8] 001101 REVT0 ESEL3[21:16] 001110 XEVT1 ESEL3[29:24] 001111 REVT1 Submit Documentation Feedback REGISTER INFORMATION

www.ti.com Table 7-7. EDMA Selector EDMA SELECTOR CODE EDMA EVENT MODULE (BINARY) 000000 DSPINT HPI 000001 TINT0 TIMER0 000010 TINT1 TIMER1 000011 SDINT EMIF 000100 GPINT4 GPIO 000101 GPINT5 GPIO 000110 GPINT6 GPIO 000111 GPINT7 GPIO 001000 GPINT0 GPIO 001001 GPINT1 GPIO 001010 GPINT2 GPIO 001011 GPINT3 GPIO 001100 XEVT0 McBSP0 001101 REVT0 McBSP0 001110 XEVT1 McBSP1 001111 REVT1 McBSP1 010000 011111 Reserved 100000 AXEVTE0 McASP0 100001 AXEVTO0 McASP0 100010 AXEVT0 McASP0 100011 AREVTE0 McASP0 100100 AREVTO0 McASP0 100101 AREVT0 McASP0 100110 AXEVTE1 McASP1 100111 AXEVTO1 McASP1 101000 AXEVT1 McASP1 101001 AREVTE1 McASP1 101010 AREVTO1 McASP1 101011 AREVT1 McASP1 101100 I2CREVT0 I2C0 101101 I2CXEVT0 I2C0 101110 I2CREVT1 I2C1 101111 I2CXEVT1 I2C1 110000 GPINT8 GPIO 110001 GPINT9 GPIO 110010 GPINT10 GPIO 110011 GPINT11 GPIO 110100 GPINT12 GPIO 110101 GPINT13 GPIO 110110 GPINT14 GPIO 110111 GPINT15 GPIO 111000 111111 Reserved REGISTER INFORMATION Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 7-8. EDMA Event Selector Registers (ESEL0 Register (0x01A0 FF00) Reserved EVTSEL3 Reserved EVTSEL2 R R/W 0011b R R/W 0010b Reserved EVTSEL1 Reserved EVTSEL0 R R/W 0001b R R/W 0000b Legend R Read only, R/W Read/write, value at reset Table 7-9. EDMA Event Selector Registers ESEL1 Register (0x01A0 FF04) Reserved EVTSEL7 Reserved EVTSEL6 R R/W 0111b R R/W 0110b Reserved EVTSEL5 Reserved EVTSEL4 R R/W 0101b R R/W 0100b Legend R Read only, R/W Read/write, value at reset Table 7-10. EDMA Event Selector Registers ESEL3 Register (0x01A0 FF0C) Reserved EVTSEL15 Reserved EVTSEL14 R R/W 1111b R R/W 1110b Reserved EVTSEL13 Reserved EVTSEL12 R R/W 1101b R R/W 1100b Legend R Read only, R/W Read/write, value at reset Table 7-11. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) NO. NAME 31:30 23:22 Reserved Reserved. Read only, writes have no effect. 15:14 7:6 EDMA event selection bits for channel Allows mapping of the EDMA events to the EDMA channels. abc 29:24 The EVTSEL0 through EVTSEL15 bits correspond to channels to 15, respectively. These EVTSELx 21:16 fields are user selectable. By configuring the EVTSELx fields to the EDMA selector value of the desired EVTSELx 13:8 EDMA sync event number (see Table 7-7 users can map any EDMA event to the EDMA channel. 5:0 abc For example, if EVTSEL15 is programmed to 0001b (the EDMA selector code for TINT0), channel is triggered by Timer TINT0 events. Submit Documentation Feedback REGISTER INFORMATION

For□Use in□System /1,□/2, ...,□/32 ...,□/32 /1,□/2, PLL x4□to□x25 PLLEN□(PLL_CSR.[0]) ...,□/32 /1,□/2, /1,□/2, ...,□/32 /1,□/2, ...,□/32 (DSP□Core) SYSCLK1 (Peripherals) SYSCLK2 ECLKIN EKSRC□Bit (DEVCFG.[4]) EMIF SYSCLK3 CLKMODE0 (EMIF□Clock□Input) C6713/13B□DSPs PLLOUT PLLREF DIVIDER D0 OSCDIV1 DIVIDER□D1 DIVIDER□D2 DIVIDER□D3 ECLKOUT AUXCLK (Internal□Clock□Source to□McASP0□and□McASP1) 1□□□□0 PLLHV C2C1 EMI□filter +3.3 V 10 /c109F0 .1 /c109F D0EN□(PLLDIV0.[15]) ENA ENA OD1EN□(OSCDIV1.[15]) ENAENA ENAD1EN□(PLLDIV1.[15]) ENAD2EN□(PLLDIV2.[15]) ENAD3EN□(PLLDIV3.[15]) Reserved (A) (A) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com The 320C6713/13B includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different parts of the system (that is, DSP core, peripheral data bus, external memory interface, McASP, and other peripherals). Figure 8-1 shows the PLL, the PLL controller, and the clock generator logic. Dividers and must never be disabled. Never write a '0' to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers. Place all PLL external components (C1, C2, and the EMI filter) as close to the C67x DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI filter). The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV DD EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U. Figure 8-1. PLL and Clock Generator Logic PLL and PLL Controller Submit Documentation Feedback

8.1 PLL Registers SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST 1), for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST 0). For the PLL reset time value, see Table 8-1 The PLL lock time is the amount of time from when PLLRST with PLLEN (PLL out of reset, but still bypassed) to when the PLLEN bit can be safely changed to (switching from bypass to the PLL path); see Table 8-1 and Figure 8-1 Under some operating conditions, the maximum PLL lock time may vary from the specified typical value. For the PLL lock time values, see Table 8-1 Table 8-1. PLL Lock and Reset Times MIN TYP MAX UNIT PLL lock time 187.5 µ s PLL reset time 125 ns Table 8-2 shows the C6713/13B device CLKOUT signals, how and by what register control bits they are derived, and what is the default settings. For more details on the PLL, see the PLL and Clock Generator Logic diagram Figure 8-1 Table 8-2. CLKOUT Signals, Default Settings, and Control CLOCK OUTPUT DEFAULT SETTING CONTROL BIT(s) (ENABLED or DISABLED) (Register) D2EN (PLLDIV2.[15]) CLKOUT2 ON (ENABLED) SYSCLK2 selected [default] CK2EN (EMIF GBLCTL.[3]) CLKOUT3 ON (ENABLED) OD1EN (OSCDIV1.[15]) Derived from CLKIN SYSCLK3 selected [default]. ON (ENABLED); EKSRC (DEVCFG.[4]) To select ECLKIN source: ECLKOUT derived from SYSCLK3 EKEN (EMIF GBLCTL.[5]) EKSRC (DEVCFG.[4]) and EKEN (EMIF GBLCTL.[5]) The input clock (CLKIN) is directly available to the McASP modules as AUXCLK for use as an internal high-frequency clock source. The input clock (CLKIN) may also be divided down by a programmable divider OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system. Figure 8-1 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then multiplied up by a factor of x4, x5, x6, and so on, up to x25. Either the input clock (PLLEN or the PLL output (PLLEN then serves as the high-frequency reference clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may be divided down from this high-frequency clock (each with a unique divider). For example, with a 30-MHz input if the PLL output is configured for 450 MHz, the DSP core may be operated at 225 MHz (/2), while the EMIF may be configured to operate at a rate of MHz (/6). Note that there is a specific minimum and maximum reference clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 8-1 as well as for the DSP core, peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). See Table 8-3 for the PLL clocks input and output frequency ranges. Submit Documentation Feedback PLL and PLL Controller

www.ti.com Table 8-3. PLL Clock Frequency Ranges (1) (2) CLOCK SIGNAL MIN MAX UNIT PLLREF (PLLEN 100 MHz PLLOUT 140 600 MHz SYSCLK1 Device speed (DSP core) MHz SYSCLK3 (EKSRC 100 MHz AUXCLK (3) MHz (1) SYSCLK2 rate must be exactly half of SYSCLK1. (2) See also the Electrical Specification (timing requirements and switching characteristics parameters) in the section of this data sheet. (3) When the McASP module is not used, the AUXCLK maximum frequency can be any frequency up to the CLKIN maximum frequency. The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip as SYSCLK3. SYSCLK3 is derived from divider off of PLLOUT (see Figure 8-1 The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register. The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233). SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed to be half of the SYSCLK1 rate. For example, if is configured to divide-by-2 mode (/2), then must be programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 8-1 During the programming transition of Divider and Divider (resulting in SYSCLK1 and SYSCLK2 output clocks, see Figure 8-1 the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of and are to be changed from /1, (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the divider ratios of and are to be changed from /3, to /1, /2, then the PLLDIV1 register must be programmed before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final SYSCLK2 rate must be exactly half of the SYSCLK1 rate. Note that Divider and Divider must always be enabled (that is, D1EN and D2EN bits are set to in the PLLDIV1 and PLLDIV2 registers). The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should not be used to directly access the PLL Controller registers. For detailed information on the clock generator (PLL Controller registers) and the associated software bit descriptions, see Table 8-4 through Table 8-11 Table 8-4. PLL Control/Status Register (PLLCSR) (0x01B7 C100) Reserved R-0 Reserved Stable Reserved PLLRS Reserv PLLPWRD PLLEN T ed N R-0 R x R-0 RW R/W R/W RW Legend R Read only, R/W Read/write, value at reset PLL and PLL Controller Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 8-5. PLL Control/Status Register (PLLCSR) NO. NAME 31:7 Reserved Reserved. Read only, writes have no effect. Clock input stable. This bit indicates if the clock input has stabilized. STABLE Clock input not yet stable. Clock counter is not finished counting (default). Clock input stable 5:4 Reserved Reserved. Read only, writes have no effect. Asserts RESET to PLL PLLRST PLL reset released PLL reset asserted (default) Reserved Reserved. The user must write a to this bit. Select PLL power down PLLPWRDN PLL operational (default) PLL placed in power-down state PLL mode enable Bypass mode (default). PLL disabled Divider and PLL are bypassed. PLLEN SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock. PLL enabled Divider and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down from PLL output. Table 8-6. PLL Multiplier (PLLM) Control Register (0x01B7 C110) Reserved R-0 Reserved PLLM R-0 R/W 0111 Legend R Read only, R/W Read/write, value at reset Submit Documentation Feedback PLL and PLL Controller

www.ti.com Table 8-7. PLL Multiplier (PLLM) Control Register NO. NAME 31:5 Reserved Reserved. Read only, writes have no effect. PLL multiply mode [default is 0111)] 00000 Reserved 10000 x16 00001 Reserved 10001 x17 00010 Reserved 10010 x18 00011 Reserved 10011 x19 00100 10100 x20 00101 10101 x21 00110 10110 x22 00111 10111 x23 4:0 PLLM 01000 11000 x24 01001 11001 x25 01010 x10 11010 Reserved 01011 x11 11011 Reserved 01100 x12 11100 Reserved 01101 x13 11101 Reserved 01110 x14 11110 Reserved 01111 x15 11111 Reserved PLLM select values 00000 through 00011 and 11010 through 11111 are not supported. Table 8-8. PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3) (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively) Reserved R-0 DxEN Reserved PLLDIVx R/W R R/W x xxxx (1) Legend R Read only, R/W Read/write, value at reset (1) Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are 0000), 0000), 0001), and 0001), respectively. CAUTION and should never be disabled. should only be disabled if ECLKIN is used. Table 8-9. PLL Wrapper Divider x Registers (Prescaler Divider and Post-Scaler Dividers D1, D2, and D3) (1) BIT NO. NAME 31:16 Reserved Reserved. Read only, writes have no effect. Divider Dx enable (where x denotes through 3). Divider x disabled. No clock output DxEN Divider x enabled (default) These divider-enable bits are device specific and must be set to to enable. 14:5 Reserved Reserved. Read only, writes have no effect. (1) Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of must be two times slower than D1. For example, if is set to /2, then must be set to /4. PLL and PLL Controller Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 8-9. PLL Wrapper Divider x Registers (Prescaler Divider and Post-Scaler Dividers D1, D2, and D3) (continued) BIT NO. NAME (default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1, /2, and /2, respectively). 00000 10000 /17 00001 10001 /18 00010 10010 /19 00011 10011 /20 00100 10100 /21 00101 10101 /22 00110 10110 /23 4:0 PLLDIVx 00111 10111 /24 01000 11000 /25 01001 /10 11001 /26 01010 /11 11010 /27 01011 /12 11011 /28 01100 /13 11100 /29 01101 /14 11101 /30 01110 /15 11110 /31 01111 /16 11111 /32 Table 8-10. Oscillator Divider (OSCDIV1) Register (0x01B7 C124) Reserved R-0 OD1EN Reserved OSCDIV1 R/W R R/W 0111 Legend R Read only, R/W Read/write, value at reset Submit Documentation Feedback PLL and PLL Controller

www.ti.com Table 8-11. Oscillator Divider (OSCDIV1) Register NO. NAME 31:16 Reserved Reserved. Read-only; writes have no effect. Oscillator Divider enable. OD1EN Oscillator Divider disabled Oscillator Divider enabled (default) 14:5 Reserved Reserved. Read only, writes have no effect. Oscillator Divider ratio [default is 0111)] 00000 10000 /17 00001 10001 /18 00010 10010 /19 00011 10011 /20 00100 10100 /21 00101 10101 /22 00110 10110 /23 4:0 OSCDIV1 00111 10111 /24 01000 11000 /25 01001 /10 11001 /26 01010 /11 11010 /27 01011 /12 11011 /28 01100 /13 11100 /29 01101 /14 11101 /30 01110 /15 11110 /31 01111 /16 11111 /32 PLL and PLL Controller Submit Documentation Feedback

(McASP) PERIPHERALS 9.1 McASP Block Diagram SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 The 320C6713/13B device includes two multichannel audio serial port (McASP) interface peripherals (McASP1 and McASP0). The McASP is a serial port optimized for the needs of multichannel audio applications. With two McASP peripherals, the 320C6713/13B device is capable of supporting two completely independent audio zones simultaneously. Each McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. Each McASP module also includes a pool of shift registers that may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO). The transmit section of the McASP can transmit data in either a time division multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, and CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial format. Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format. However, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode, which is useful for non-audio data (for example, passing control information between two DSPs). The McASP peripherals have additional capability for flexible clock generation, and error detection/handling, as well as error management. Figure 9-1 shows the major blocks along with external signals of the 320C6713/13B McASP1 and McASP0 peripherals, and shows the eight serial data [AXR] pins for each McASP. Each McASP also includes full general-purpose I/O (GPIO) control, so any pins not needed for serial transfers can be used for general-purpose I/O. Submit Documentation Feedback MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS

Clock□Check Transmit Generator Clock Transmit ACLKX0 AHCLKX0 DIT RAM Transmit Generator Frame□Sync AFSX0 Detect Error Receive Frame□Sync GeneratorFormatter Transmit Data AMUTE0 AMUTEIN0AFSR0 Serializer□0 Serializer□1 Serializer□3 Serializer□2 Serializer□6 Serializer□7 Serializer□5 Serializer□4 (High- Frequency) Receive Clock□Check (High- Frequency) Receive Formatter Data Formatter Data Receive Serializer□4 Serializer□3 Serializer□7 Serializer□6 Serializer□5 Serializer□0 Serializer□1 Frame□Sync Generator Receive Frame□Sync Generator Transmit Transmit Generator Receive Generator Serializer□2 Error Transmit Formatter Data Clock□Check Frequency) (High- Receive Detect Frequency) Clock□Check (High- Transmit RAM DIT AMUTE1 AFSR1 ACLKR1 AMUTEIN1 AHCLKR1 Clock AFSX1 ACLKX1 AHCLKX1 Clock AXR1[0] AXR1[1] AXR1[3] AXR1[2] AXR1[6] AXR1[7] AXR1[5] AXR1[4] McASP0 McASP1 DMA Transmit DMA Transmit DMA Receive DMA Receive INDIVIDU AL LY PROGRAMMABLE□TX/RX/GPI O INDIVIDUAL LY PROGRAMMABLE□TX/RX/GPI O Control GPIO Control GPIO AXR0[0] AXR0[1] AXR0[3] AXR0[2] AXR0[6] AXR0[7] AXR0[5] AXR0[4] SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 9-1. McASP0 and McASP1 Configuration MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS Submit Documentation Feedback

9.2 Multichannel Time Division Multiplexed (TDM) Synchronous Transfer Mode 9.3 Burst Transfer Mode SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 The McASP supports a multichannel TDM synchronous transfer mode for both transmit and receive. Within this transfer mode, a wide variety of serial data formats are supported, including formats compatible with devices using the Inter-Integrated Sound (IIS) protocol. TDM synchronous transfer mode is typically used when communicating between integrated circuits, such as between a DSP and one or more ADC, DAC, codec, or S/PDIF receiver devices. In multichannel applications, it is typical to find several devices operating synchronized with each other. For example, to provide six analog outputs, three stereo DAC devices would be driven with the same bit clock and frame sync, but each stereo DAC would use a different McASP serial data pin carrying stereo data (two TDM time slots, left and right). The TDM synchronous serial transfer mode utilizes several control signals and one or more serial data signals: A bit clock signal (ACLKX for transmit, ACKLR for receive) A frame sync signal (AFSX for transmit, AFSR for receive) An (optional) high-frequency master clock (AHCLKX for transmit, AHCLKR for receive) from which the bit clock is derived One or more serial data pins (AXR for transmit and for receive) Except for the optional high-frequency master clock, all of the signals in the TDM synchronous serial transfer mode protocol are synchronous to the bit clocks (ACLKX and ACLKR). In the TDM synchronous transfer mode, the McASP continually transmits and receives data periodically (since audio ADCs and DACs operate at a fixed-data rate). The data is organized into frames, and the beginning of a frame is marked by a frame sync pulse on the AFSX, AFSR pin. In a typical audio system, one frame is transferred per sample period. To support multiple channels, the choices are to either include more time slots per frame (and therefore operate with a higher bit clock) or to keep the bit clock period constant and use additional data pins to transfer the same number of channels. For example, a particular six-channel DAC might require three McASP serial data pins; transferring two channels of data on each serial data pin during each sample period (frame). Another similar DAC may be designed to use only a single McASP serial data pin, but clocked three times faster and transferring six channels of data per sample period. The McASP is flexible enough to support either type of DAC, but a transmitter cannot be configured to do both at the same time. For multiprocessor applications, the McASP supports any number of time slots per frame (between and 32), and includes the ability to disable transfers during specific time slots. In addition, to support S/PDIF, AES-3, IEC-60958, and CP-430 receiver chips whose natural block (McASP frame) size is 384 samples; the McASP receiver supports a 384 time slot mode. The advantage to using the 384 time slot mode is that interrupts may be generated synchronous to the S/PDIF, AES-3, IEC-60958, and CP-430 receivers; for example, the last slot interrupt. The McASP also supports a burst transfer mode, which is useful for non-audio data (for example, passing control information between two DSPs). Burst transfer mode uses a synchronous serial format similar to TDM, except the frame sync is generated for each data word transferred. In addition, frame sync generation is not periodic or time driven as in TDM mode, but rather data driven. Submit Documentation Feedback MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS

9.4 Supported Bit Stream Formats for TDM and Burst Transfer Modes 9.5 Digital Audio Interface Transmitter (DIT) Transfer Mode (Transmitter Only) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com The serial data pins support a wide variety of formats. In the TDM and burst synchronous modes, the data may be transmitted/received with the following options: Time slots per frame: (burst/data driven), or 2,3...32 (TDM/time driven) Time slot size: 12, 16, 20, 24, 28, bits per time slot Data size: 12, 16, 20, 24, 28, bits (must be less than or equal to time slot) Data alignment within time slot: left or right justified Bit order: MSB or LSB first Unused bits in time slot: Padded with or extended with value of another bit Time slot delay from frame sync: 0-, 1-, or 2-bit delay The data format can be programmed independently for transmit and receive, and for McASP0 versus McASP1. In addition, the McASP can automatically realign the data as processed natively by the DSP (any format on a nibble boundary) adjusting the data in hardware to any of the supported serial bit stream formats (TDM, burst, and DIT modes). This adjustment reduces the amount of bit manipulation that the DSP must perform and simplifies software architecture. The McASP transmit section may also be configured in DIT mode where it outputs data formatted for transmission over an S/PDIF, AES-3, IEC-60958, or CP-430 standard link. These standards encode the serial data such that the equivalent of clock and frame sync are embedded within the data stream. DIT transfer mode is used as an interconnect between audio components and can transfer multichannel digital audio data over a single optical or coaxial cable. From an internal DSP standpoint, the McASP operation in DIT transfer mode is similar to the two-time-slot TDM mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble, channel status, user data, validity, and parity automatically stuffed into the bit stream by the McASP module. The McASP includes separate validity bits for even/odd subframes and two 384-bit register file modules to hold channel status and user data bits. DIT mode requires (at a minimum): One serial data pin (if the AUXCLK is used as the reference (see Figure 8-1 OR One serial data pin plus either the AHCLKX or ACLKX pin (if an external clock is needed) If additional serial data pins are used, each McASP may be used to transmit multiple encoded bit streams (one per pin). However, the bit streams will all be synchronized to the same clock and the user data, channel status, and validity information carried by each bit stream will be the same for all bit streams transmitted by the same McASP module. The McASP can also automatically realign the data as processed by the DSP (any format on a nibble boundary) in DIT mode; reducing the amount of bit manipulation that the DSP must perform and simplifying software architecture. MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS Submit Documentation Feedback

9.6 McASP Flexible Clock Generators 9.7 McASP Error Handling and Management SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 The McASP transmit and receive clock generators are identical. Each clock generator can accept a high-frequency master clock input (on the AHCLKX and AHCLKR pins). The transmit and receive bit clocks (on the ACLKX and ACLKR pins) can also be sourced externally or can be sourced internally by dividing down the high-frequency master clock input (programmable factor /1, /2, /3, ... /4096). The polarity of each bit clock is individually programmable. The frame sync pins are AFSX (transmit) and AFSR (receive). A typical usage for these pins is to carry the left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are individually programmable for either internal or external generation, either bit or slot length, and either rising or falling edge polarity. Some examples of the things that a system designer can use the McASP clocking flexibility for are: Input a high-frequency master clock (for example, 512 f S of the receiver) and receive with an internally generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of or /2. (An example application would be to receive data from a DVD at kHz but output up-sampled or decoded audio at kHz or 192 kHz.) Transmit/receive data based on sample rate (for example, 44.1 kHz) using McASP0 while transmitting and receiving at a different sample rate (for example, kHz) on McASP1. Use the DSP on-board AUXCLK to supply the system clock when the input source is an A/D converter. To support the design of a robust audio system, the McASP module includes error-checking capability for the serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that continually measures the high-frequency master clock every SYSCLK2 clock cycles. The timer value can be read to get a measurement of the high-frequency master clock frequency and has a min-max range setting that can raise an error flag if the high-frequency master clock goes out of a specified range. The user would read the high-frequency transmit master clock measurement (AHCLKX0 or AHCLKX1) by reading the XCNT field of the XCLKCHK register and the user would read the high-frequency receive master clock measurement (AHCLKR0 or AHCLKR1) by reading the RCNT field of the RCLKCHK register. Upon the detection of any one or more of the above errors (software selectable) or the assertion of the AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately mute the audio output. In addition, an interrupt may be generated if enabled based on any one or more of the error sources. Submit Documentation Feedback MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS

9.8 McASP Interrupts and EDMA Events 9.9 I C SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com The McASP transmitter and receiver sections each generate an event on every time slot. This event can be serviced by an interrupt or by the EDMA controller. When using interrupts to service the McASP, each shift register buffer has a unique address in the McASP registers space (see Table 4-1 When using the EDMA to service the McASP, the McASP DATA Port space, shown in Table 4-1 is accessed. In this case, the address least-significant bits are ignored. Writes to any address in this range access the transmitting buffers in order from lowest (serializer to highest (serializer 15), skipping over disabled and receiving serializers. Likewise, reads from any address in this space access the receiving buffers in the same order but skip over disabled and transmitting buffers. Having two I C modules on the 320C6713/13B simplifies system architecture, since one module may be used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface. NOTE I C ports are compatible with Philips I2C Specification Revision 2.1 (January 2000). The 320C6713/13B also includes two I C serial ports for control purposes. Each I C port supports: Fast mode up to 400 Kbps (no fail-safe I/O buffers) Noise filter to remove noise ns or less and 10-bit device addressing modes Master (transmit/receive) and slave (transmit/receive) functionality Events: DMA, interrupt, or polling Slew-rate limited open-drain output buffers Figure 9-2 shows a block diagram of the I2Cx module. MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS Submit Documentation Feedback

From□PLL Clock□Generator I2CCLKHx Generator Bit□Clock I2CCLKLx Noise FilterI2C□Clock SCL I2CXSRx I2CDXRx Transmit Transmit Shift Transmit Buffer I2CDRRx ShiftI2CRSRx Receive Buffer Receive Receive Filter SDA I2C□Data Noise I2COARx I2CSARx Slave Address Control Address OwnI2CMDRx I2CCNTx Mode Data Count Source Interrupt Interrupt Status I2CISRCx I2CSTRx Enable InterruptI2CIERx Interrupt/DMA I2Cx□Module NOTE:□Shading□denotes□control/status□registers. SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 9-2. I2Cx Module Block Diagram Submit Documentation Feedback MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS

10.1 General-Purpose Input/Output (GPIO) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com This section discusses the logic and power-supply configuration of the SM320C6713-EP and SM320C6713B-EP. To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP enable (GPEN) register and the GPxDIR bits in the GP direction (GPDIR) register must be properly configured. GPxEN GP[x] pin is enabled. GPxDIR GP[x] pin is an input. GPxDIR GP[x] pin is an output. where x represents one of the through GPIO pins. Figure 10-1 shows the GPIO enable bits in the GPEN register for the C6713/13B device. To use any of the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to (enabled). Default values are device-specific, so refer to Figure 10-1 for the C6713/13B default configuration. Reserved R-0 GP15EN GP14EN GP13EN GP12EN GP11EN GP10EN GP9EN GP8EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7EN GP6EN GP5EN GP4EN GP3EN GP2EN GP1EN GP0EN R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 Legend R/W Readable/Writeable; n value after reset, undefined value after reset Figure 10-1. GPIO Enable (GPEN) Register (Hex Address: 01B0 0000) Figure 10-2 shows the GPIO direction bits in the GPIO Direction (GPDIR) register. This register determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled (set to in the GPEN register. By default, all the GPIO pins are configured as input pins. Reserved R-0 GP15DIR GP14DIR GP13DIR GP12DIR GP11DIR GP10DIR GP9DIR GP8DIR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7DIR GP6DIR GP5DIR GP4DIR GP3DIR GP2DIR GP1DIR GP0DIR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend R/W Readable/Writeable; n value after reset, undefined value after reset Figure 10-2. GPIO Direction (GPDIR) Register (Hex Address: 01B0 0004) LOGIC AND POWER SUPPLY Submit Documentation Feedback

10.2 Power-Down Mode Logic PWRD Internal Clock□Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET PD3 Internal Peripherals Clock and□Dividers Distribution 320C6713/13B CLKOUT2 10.2.1 Triggering, Wake-Up, and Effects SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). Figure 10-3 shows the power-down mode logic on the C6713/13B. External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic. Figure 10-3. Power-Down Mode Logic The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 10-4 and described in Table 10-1 When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Enable or Enabled Reserved Non-Enabled PD3 PD2 PD1 Interrupt Wake Interrupt Wake R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend: R/W-x Read/write reset value Figure 10-4. PWRD Field of the CSR Submit Documentation Feedback LOGIC AND POWER SUPPLY

10.3 Power-Supply Sequencing SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account for this delay. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 10-1 summarizes all the power-down modes. Table 10-1. Characteristics of the Power-Down Modes PRWD FIELD POWER-DOWN WAKE-UP METHOD EFFECT ON CHIP OPERATION (BITS 10) MODE 000000 No power down Wake by an enabled CPU halted (except for the interrupt logic) 001001 PD1 interrupt Power-down mode blocks the internal clock inputs at the boundary of the CPU, preventing most of the CPU logic from Wake by an enabled or switching. During PD1, EDMA transactions can proceed 010001 PD1 non-enabled interrupt between peripherals and internal memory. Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being 011010 PD2 (1) Wake by a device reset halted. All register and internal RAM preserved. All functional I/O freeze in the last state when the PLL clock is turned off. Input clock to the PLL stops generating clocks. All register and internal RAM preserved. All functional I/O freeze in the last state when the PLL clock is turned off. Following 011100 PD3 (1) Wake by a device reset reset, the PLL needs time to relock, just as it does following power up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be relocked, just as it does following power up. All others Reserved (1) When entering PD2 and PD3, all functional I/Os remain in the previous state. However, for peripherals that are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications. On C6713B silicon revision 2.0 and C6713 silicon revision 1.1, the device includes a programmable PLL that allows software control of PLL bypass via the PLLEN bit in the PLLCSR register. With this enhanced functionality comes some additional considerations when entering power-down modes. The power-down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the device. However, if the PLL is bypassed (PLLEN 0), the device still receives clocks from the external clock input (CLKIN). Therefore, bypassing the PLL makes the power-down modes PD2 and PD3 ineffective. Make sure that the PLL is enabled by writing a to PLLEN bit (PLLCSR.0) before writing to either PD3 (CSR.11) or PD2 (CSR.10) to enter a power-down mode. TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time second) if the other supply is below the proper operating voltage. LOGIC AND POWER SUPPLY Submit Documentation Feedback

10.3.1 System-Level Design Considerations 10.3.2 Power-Supply Design Considerations DVDD CVDD VSS C6000 DSP Schottky Diode I/O□Supply Core□Supply GND 10.4 Power-Supply Decoupling 10.5 IEEE Std 1149.1 JTAG Compatibility Statement SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up before, and powered down after, the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board. A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 10-5 Figure 10-5. Schottky Diode Diagram Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance DSPs, the printed circuit board (PCB) should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. To properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of caps for the core supply and for the I/O supply. These caps need to be close (no more than 1.25-cm maximum distance) to the DSP to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors; therefore, physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product s production lifetime needs to be considered. The 320C6713/13B DSP requires that both TRST and RESET resets be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power-up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP boundary scan functionality. Submit Documentation Feedback LOGIC AND POWER SUPPLY

10.6 EMIF Device Speed SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com For maximum reliability, the 320C6713/13B DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST is always asserted upon power up and the DSP internal emulation logic is always properly initialized. JTAG controllers from TI actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high, but expect the use of an external pullup resistor on TRST When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET the low-to-high transition of TRST must be seen to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. The maximum EMIF speed on the C6713/13B device is 100 MHz. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all ac timings to determine if the maximum EMIF speed is achievable for a given board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the application report Using IBIS Models for Timing Analysis (literature number SPRA839). For ease of design evaluation, Table contains IBIS simulation results showing the maximum EMIF-SDRAM interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be performed to verify that all ac timings are met for the specified board layout. Other configurations are also possible, but again, timing analysis must be done to verify proper ac timings. To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals). LOGIC AND POWER SUPPLY Submit Documentation Feedback

10.7 EMIF Big Endian Mode Correctness (C6713B Only) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 10-2. C6713/13B Example Boards and Maximum EMIF Speed BOARD CONFIGURATION MAXIMUM ACHIEVABLE SDRAM SPEED GRADE EMIF INTERFACE EMIF-SDRAM TYPE BOARD TRACE COMPONENTS INTERFACE SPEED 143-MHz 32-bit SDRAM 100 MHz to 3-in traces with 1-Load 166-MHz 32-bit SDRAM For short traces, SDRAM data One bank of proper termination Short output hold time on these SDRAM one 32-bit SDRAM resistors; 183-MHz 32-bit SDRAM 55) Traces speed grades cannot meet EMIF Trace impedance ~50 Ω 200-MHz 32-bit SDRAM input hold time requirement. (1) 125-MHz 16-bit SDRAM 8E) 100 MHz 1.2 to in from EMIF to 133-MHz 16-bit SDRAM 75) 100 MHz 2-Loads One bank of each load, with proper Short 143-MHz 16-bit SDRAM 7E) 100 MHz two 16-bit SDRAMs termination resistors; Traces 167-MHz 16-bit SDRAM 6A) 100 MHz Trace impedance ~78 Ω 167-MHz 16-bit SDRAM 100 MHz For short traces, EMIF cannot 125-MHz 16-bit SDRAM 8E) meet SDRAM input hold requirement. (1) 1.2 to inches from EMIF 133-MHz 16-bit SDRAM 75) 100 MHz 3-Loads One bank of to each load, with proper Short two 32-bit SDRAMs 143-MHz 16-bit SDRAM 7E) 100 MHz termination resistors; Traces One bank of buffer 167-MHz 16-bit SDRAM 6A) 100 MHz Trace impedance ~78 Ω For short traces, EMIF cannot 167-MHz 16-bit SDRAM meet SDRAM input hold requirement. (1) 143-MHz 32-bit SDRAM MHz One bank of 166-MHz 32-bit SDRAM MHz one 32-bit-bit SDRAM, 3-Loads to in from EMIF; 183-MHz 32-bit SDRAM 55) MHz One bank of Long Traces Trace impedance ~63 Ω one 32-bit-bit SDRAM, SDRAM data output hold time One bank of buffer 200-MHz 32-bit SDRAM cannot meet EMIF input hold requirement. (1) (1) Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing requirements can be met for the particular system. The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For the C6713/13B device Little Endian is the default setting. The C6713B HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility to change the EMIF data placement on the EMIF bus. When using the default setting of HD12 for the C6713B, the EMIF will present 8-bit or 16-bit data on the ED[7:0] side of the bus if using Little Endian mode (HD8 1), and to the ED[31:24] side of the bus if using Big Endian mode. Figure 10-6 shows the mapping of 16-bit and 8-bit C6713B devices. abc EMIF DATA LINES (PINS) WHERE DATA PRESENT ED[31:24] BE3 ED[23:16] BE2 ED[15:8] BE1 ED[7:0] BE0 32-Bit Device in Any Endianness Mode 16-Bit Device in Big Endianness Mode 16-Bit Device in Little Endianness Mode 8-Bit Device in 8-Bit Device in Big Endianness Mode Little Endianness Mode Figure 10-6. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 (C6713B Only) When HD12 for the C6713B, enabling EMIF endianness correction, the EMIF will present 8-bit or 16-bit data on the ED[7:0] side of the bus, regardless of the endianess mode (see Figure 10-7 Submit Documentation Feedback LOGIC AND POWER SUPPLY

10.8 Bootmode SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com abc EMIF DATA LINES (PINS) WHERE DATA PRESENT ED[31:24] BE3 ED[23:16] BE2 ED[15:8] BE1 ED[7:0] BE0 32-Bit Device in Any Endianness Mode 16-Bit Device in Any Endianness Mode 8-Bit Device in Any Endianness Mode Figure 10-7. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 (C6713B Only) This new C6713B endianness correction functionality does not affect systems using the default value of HD12 This new C6713B feature does not affect systems operating in Little Endian mode. The C6713/13B device resets using the active-low signal RESET and the internal reset signal. While RESET is low, the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. Refer to Reset Timing for reset timing characteristics and states of device pins during reset. The release of the internal reset signal (see the Reset phase discussion in the RESET Timing section of this data sheet) starts the processor running with the prescribed device configuration and boot mode. The C6713/13B has three types of boot modes: Host boot If host boot is selected, upon release of internal reset, the CPU is internally stalled while the remainder of the device is released. During this period, an external host can initialize the CPU memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the stalled state. The CPU then begins execution from address The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally stalled. Also, DSPINT brings the CPU out of the stalled state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the stalled state the CPU needs to clear the DSPINT; otherwise, no more DSPINTs can be received. Emulation boot Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to set DSPINT to release the CPU from the stalled state. Instead, the emulator will set DSPINT if it has not been previously set so that the CPU can begin executing code from address Before beginning execution, the emulator sets a breakpoint at address This prevents the execution of invalid code by halting the CPU before executing the first instruction. Emulation boot is a good tool in the debug phase of development. EMIF boot (using default ROM timings) Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to address by the EDMA using the default ROM timings, while the CPU is internally stalled. The data should be stored in the endian format that the system is using. The boot process also lets you choose the width of the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address After completion of the block transfer, the CPU is released from the stalled state and start running from address LOGIC AND POWER SUPPLY Submit Documentation Feedback

11.1 Absolute Maximum Ratings (1) 11.2 Recommended Operating Conditions (1) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 over operating case temperature range (unless otherwise noted) VALUE UNIT Supply voltage range, CV DD (2) 0.3 to 1.8 V Supply voltage range, DV DD (2) 0.3 to V Input voltage range 0.3 to DV DD 0.5 V Output voltage range 0.3 to DV DD 0.5 V A version to 105 C Operating case temperature range T C S version to 105 M version (3) to 125 Storage temperature range, T stg to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to V SS (3) Long-term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://ti.com/ep_quality for additional information on enhanced product packaging. MIN NOM MAX UNIT CV DD Supply voltage, core referenced to V SS 1.20 1.26 1.32 V DV DD Supply voltage, I/O referenced to V SS 3.13 3.3 3.47 V V Maximum supply voltage difference, CV DD DV DD 1.32 V V Maximum supply voltage difference, DV DD CV DD 2.75 V All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and High-level RESET V IH V input voltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and 0.8 RESET Low-level V IL V input voltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 0.3 DV DD All signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 C6713 (2) High-level ECLKOUT, CLKOUT2, and CLKOUT3 I OH output mA All signals except ECLKOUT, CLKOUT2, CLKS1/SCL1, current DR1/SDA1, SCL0, and SDA0 C6713B (2) ECLKOUT and CLKOUT2 All signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 C6713 (2) ECLKOUT, CLKOUT2, and CLKOUT3 Low-level CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 I OL output mA All signals except ECLKOUT, CLKOUT2, CLKS1/SCL1, current DR1/SDA1, SCL0, and SDA0 C6713B (2) ECLKOUT and CLKOUT2 CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 (1) The core supply should be powered up before, and powered down after, the I/O supply. Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage. (2) Refers to dc (or steady state) currents only; actual switching currents are higher. For more details, see the device-specific IBIS models. Submit Documentation Feedback PARAMETRIC INFORMATION

11.3 Electrical Characteristics (1) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Recommended Operating Conditions (continued) MIN NOM MAX UNIT A version 105 T C Operating case temperature S version 105 C M version 125 over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-level output All signals except SCL1, SDA1, V OH I OH MAX 2.4 V voltage SCL0, and SDA0 All signals except SCL1, SDA1, I OL MAX 0.4 Low-level output SCL0, and SDA0 V OL V voltage SCL1, SDA1, SCL0, and SDA0 I OL MAX 0.4 All signals except SCL1, SDA1, 170 SCL0, and SDA0 I I Input current V I V SS to DV DD µ A SCL1, SDA1, SCL0, and SDA0 All signals except SCL1, SDA1, 170 SCL0, and SDA0 I OZ Off-state output current V O DV DD or V µ A SCL1, SDA1, SCL0, and SDA0 13GDPA, CV DD 1.4 945 CPU clock 300 MHz I DD2V Core supply current (2) mA 13GDPA, CV DD 1.26 560 CPU clock 200 MHz C6713/13B, DV DD 3.3 I DD3V I/O supply current (2) mA EMIF speed 100 MHz C I Input capacitance pF C o Output capacitance pF (1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. (2) Measured with average activity (50% high/50% low power) at C case temperature and 100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows: High DSP activity model: CPU: instructions/cycle with LDDW instructions [L1 data memory: 128 bits/cycle via LDDW instructions; program memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit switching)] McBSP: channels at rate Timers: timers at maximum rate Low DSP activity model: CPU: instructions/cycle with LDH instruction [L1 data memory: bits/cycle; program memory: 256 bits per cycles; L2/EMIF EDMA: None] McBSP: channels at rate Timers: timers at maximum rate The actual current draw is highly application dependent. For more details on core and I/O activity, refer to the TMS320C6713/12C/11C Power Consumption Summary application report (literature number SPRA889). PARAMETRIC INFORMATION Submit Documentation Feedback

11.4 Parameter Measurement Information 11.4.1 Timing Information Transmission Line 4.0□pF 1.85□pF Z0□=□50 (see□Note□A) Tester□Pin□Electronics Data□Sheet□Timing□Reference□Point Output Under Test 42 3.5□nH Device□Pin (see□Note□1) NOTE□A:□The□data□sheet□provides□timing□at□the□device□pin.□For□output□timing□analysis,□the□tester□pin□electronics□and□its□transmission□line□effects must□be□taken□into□account.□A□transmission□line□with□a□delay□of□2□ns□or□longer□can□be□used□to produce□the□desired□transmission□line effect.□The□transmission□line□is□intended□as□a□load□only.□It□is□not□necessary□to□add□or□subtract□the□transmission□line□delay□(2□ns□or□longer) from□the□data-sheet□timings. Input□requirements□in□this□data□sheet□are□tested□with□an□input□slew□rate□of□<4□V□per□nanosecond□(4□V/ns)□at□the□device□pin. 11.4.2 Signal Transition Levels Vref =□1.5□V Vref =□VIL MAX□(or□VOL MAX) Vref =□VIH MIN□(or VOH MIN) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 11-1. Test Load Circuit for AC Timing Measurements All input and output timing parameters are referenced to 1.5 V for both and logic levels. Figure 11-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to V IL MAX and V IH MIN for input clocks, V OL MAX and V OH MIN for output clocks. Figure 11-3. Rise and Fall Transition Time Voltage Reference Levels Submit Documentation Feedback PARAMETRIC INFORMATION

11.4.3 Timing Parameters and Board Routing Analysis ECLKOUT (Output□from□DSP) ECLKOUT (Input□to□External□Device) Control□Signals (Output□from□DSP) Control□Signals (Input□to□External□Device) Data□Signals (Output□from□External□Device) Data□Signals (Input□to□DSP) (A) (B) (B) NOTES□A:□Control□signals□include□data□for□writes. B:□Data□signals□are□generated□during□reads□from□an□external□device. SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 11-1 and Figure 11-4 Figure 11-4 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. Table 11-1. Board-Level Timings Example (see Figure 11-4 NO. 11-4. Board-Level Input/Output Timings PARAMETRIC INFORMATION Submit Documentation Feedback

11.5 Input and Output Clocks CLKIN CLKOUT2 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-2. Timing Requirements for CLKIN (1) (2) (3) See Figure 11-5 PLL MODE BYPASS MODE (PLLEN (PLLEN NO. UNIT MIN MAX MIN MAX t c(CLKI GDP-200 83.3 6.7 Cycle time, CLKIN ns GDP-300 83.3 6.7 t w(CLKI Pulse duration, CLKIN high 0.4C 0.4C ns NH) t w(CLKI Pulse duration, CLKIN low 0.4C 0.4C ns NL) t t(CLKIN Transition time, CLKIN ns (1) The reference points for the rise and fall transitions are measured at V IL MAX and V IH MIN. (2) C CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is MHz, use C ns. (3) See the PLL and PLL Controller section of this data sheet. Figure 11-5. CLKIN Table 11-3. Switching Characteristics for CLKOUT2 (1) (2) over recommended operating conditions (see Figure 11-6 NO. PARAMETER MIN MAX UNIT t c(CKO2) Cycle time, CLKOUT2 0.8 0.8 ns t w(CKO2H) Pulse duration, CLKOUT2 high (C2/2) 0.8 (C2/2) 0.8 ns t w(CKO2L) Pulse duration, CLKOUT2 low (C2/2) 0.8 (C2/2) 0.8 ns t t(CKO2) Transition time, CLKOUT2 ns (1) The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN. (2) CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period divide-by-2. Figure 11-6. CLKOUT2 Submit Documentation Feedback PARAMETRIC INFORMATION

www.ti.com Table 11-4. Switching Characteristics for CLKOUT3 (1) (2) over recommended operating conditions (see Figure 11-7 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX t c(CKO3) Cycle time, CLKOUT3 0.6 0.6 0.9 0.9 ns t w(CKO3H) Pulse duration, CLKOUT3 high (C3/2) 0.6 (C3/2) 0.6 (C3/2) 0.9 (C3/2) 0.9 ns t w(CKO3L) Pulse duration, CLKOUT3 low (C3/2) 0.6 (C3/2) 0.6 (C3/2) 0.9 (C3/2) 0.9 ns t t(CKO3) Transition time, CLKOUT3 ns t d(CLKINH-CKO3V) Delay time, CLKIN high to CLKOUT3 valid 1.5 6.5 1.5 7.5 ns (1) The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN. (2) CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the RATIO field in the PLLDIV3 register. Figure 11-7. CLKOUT3 Table 11-5. Timing Requirements for ECLKIN (1) See Figure 11-8 NO. MIN MAX UNIT t c(EKI) Cycle time, ECLKIN ns t w(EKIH) Pulse duration, ECLKIN high 4.5 ns t w(EKIL) Pulse duration, ECLKIN low 4.5 ns t t(EKI) Transition time, ECLKIN ns (1) The reference points for the rise and fall transitions are measured at V IL MAX and V IH MIN. Figure 11-8. ECLKIN PARAMETRIC INFORMATION Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-6. Switching Characteristics for ECLKOUT (1) (2) (3) over recommended operating conditions (see Figure 11-9 NO. PARAMETER MIN MAX UNIT t c (EKO) Cycle time, ECLKOUT E 0.9 E 0.9 ns t w (EKOH) Pulse duration, ECLKOUT high EH 0.9 EH 0.9 ns t w (EKOL) Pulse duration, ECLKOUT low EL 0.9 EL 0.9 ns t t (EKO) Transition time, ECLKOUT ns t d (EKIH-EKOH) Delay time, ECLKIN high to ECLKOUT high 6.5 ns t d (EKIL-EKOL) Delay time, ECLKIN low to ECLKOUT low 6.5 ns (1) The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN. (2) E ECLKIN period in ns (3) EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns. Figure 11-9. ECLKOUT Submit Documentation Feedback PARAMETRIC INFORMATION

11.6 Asynchronous Memory Timing SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-7. Timing Requirements for Asynchronous Memory Cycles (1) (2) (3) See Figure 11-10 and Figure 11-11 NO. MIN MAX UNIT t su(EDV-AREH) Setup time, EDx valid before ARE high 6.5 ns t h(AREH-EDV) Hold time, EDx valid after ARE high ns t su(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high ns t h(EKOH-ARDY) ARDY valid after ECLKOUT high 2.3 ns (1) To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (for example, pulse width 2E) to ensure setup and hold time is met. (2) RS Read setup, RST Read strobe, RH Read hold, WS Write setup, WST Write strobe, WH Write hold. These parameters are programmed via the EMIF CE space control registers. (3) E ECLKOUT period in ns Table 11-8. Switching Characteristics for Asynchronous Memory Cycles (1) (2) (3) over recommended operating condition (see Figure 11-10 and Figure 11-11 NO. PARAMETER MIN MAX UNIT t osu(SELV-AREL) Output setup time, select signals valid to ARE low RS*E 1.7 ns t oh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH*E 1.7 ns t d(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 1.5 ns t osu(SELV-AWEL) Output setup time, select signals valid to AWE low WS*E 1.7 ns t oh(AWEH-SELIV) Output hold time, AWE high to select signals and EDx invalid WH*E 1.7 ns t d(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 1.5 ns t osu(EDV-AWEL) Output setup time, ED valid to AWE low (WS 1)*E 1.7 ns (1) RS Read setup, RST Read strobe, RH Read hold, WS Write setup, WST Write strobe, WH Write hold. These parameters are programmed via the EMIF CE space control registers. (2) E ECLKOUT period in ns (3) Select signals include CEx BE[3:0] EA[21:2], and AOE PARAMETRIC INFORMATION Submit Documentation Feedback

Setup□= 2S trobe□=□3 Not□Ready Hold□= 2 BE Address Read□Data 21 ARDY ECLKOUT CEx EA[21:2] ED[31:0] AOE /SDRAS/SSOE ARE/SDCAS/SSADS BE[3:0] AWE/SDWE/SSWE (A) (A) (A) NOTE□A: / / , / / ,□and / / operate□as (identified□under□select□signals), ,□and , respectively,□during□asynchronous□memory□accesses. AOE□SDRAS□SSOE□□ARE□SDCAS□SSADS AWE□SDWE□SSWE AOE ARE AWE SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 11-10. Asynchronous Memory Read Submit Documentation Feedback PARAMETRIC INFORMATION

Setup□= 2 Strobe□=□3 Not□Ready Hold□= 2 BE Address Write□Data 1010 911 ECLKOUT CEx EA[21:2] ED[31:0] BE[3:0] ARDY AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE (A) (A) (A) NOTE□A: / / , / / ,□and / / operate□as (identified□under□select□signals), ,□and , respectively,□during□asynchronous□memory□accesses. AOE□SDRAS□SSOE□□ARE□SDCAS□SSADS AWE□SDWE□SSWE AOE ARE AWE SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 11-11. Asynchronous Memory Write PARAMETRIC INFORMATION Submit Documentation Feedback

11.7 Synchronous-Burst Memory Timing ECLKOUT CEx BE[3:0] EA[21:2] ED[31:0] ARE /SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE BE1 BE2 BE3 BE4 EA Q1 Q2 Q3 Q4 4 5 8 8 6 7 (1) (1) (1) NOTE□(1): / / , and / / operate□as during□SBSRAM□accesses.ARE□SDCAS□SSADS AWE□SDWE□SSWE SSADSAO SSOE SSWE, ,□and ,□respectively,E□SDRAS□SSOE/ / , SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-9. Timing Requirements for Synchronous-Burst SRAM Cycles (1) See Figure 11-12 NO. MIN MAX UNIT t su(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns t h(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns (1) The C6713/13B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. Table 11-10. Switching Characteristics for Synchronous-Burst SRAM Cycles (1) (2) over recommended operating conditions (see Figure 11-12 and Figure 11-13 NO. PARAMETER MIN MAX UNIT t d (EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.2 ns t d (EKOH-BEV) Delay time, ECLKOUT high to BEx valid ns t d (EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.2 ns t d (EKOH-EAV) Delay time, ECLKOUT high to EAx valid ns t d (EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.2 ns t d (EKOH-ADSV) Delay time, ECLKOUT high to ARE SDCAS SSADS valid 1.2 ns t d (EKOH-OEV) Delay time, ECLKOUT high to AOE SDRAS SSOE valid 1.2 ns t d (EKOH-EDV) Delay time, ECLKOUT high to EDx valid ns t d (EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.2 ns t d (EKOH-WEV) Delay time, ECLKOUT high to AWE SDWE SSWE valid 1.2 ns (1) The C6713/13B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. (2) ARE SDCAS SSADS AOE SDRAS SSOE and AWE SDWE SSWE operate as SSADS SSOE and SSWE respectively, during SBSRAM accesses. Figure 11-12. SBSRAM Read Timing Submit Documentation Feedback PARAMETRIC INFORMATION

BE[3:0] EA[21:2] ED[31:0] ARE /SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE BE1B E2 BE3B E4 Q1 Q2 Q3 Q4 EA NOTE□A: / / , and / / operate□as , ,□and ,□respectively,□during□SBSRAM□accesses.ARE□SDCAS□SSADS□□AO AWE□SDWE□SSWE SSADS□□SSOE SSWEE□SDRAS□SSOE/ / , (A) (A) (A) 11.8 Synchronous DRAM Timing SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 11-13. SBSRAM Write Timing Table 11-11. Timing Requirements for Synchronous DRAM Cycles (1) See Figure 11-14 NO. MIN MAX UNIT t su(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns t h(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns (1) The C6713/13B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. Table 11-12. Switching Characteristics for Synchronous DRAM Cycles (1) (2) over recommended operating conditions (see Figure 11-14 Figure 11-20 NO. PARAMETER MIN MAX UNIT t d(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.5 ns t d(EKOH-BEV) Delay time, ECLKOUT high to BEx valid ns t d(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 ns t d(EKOH-EAV) Delay time, ECLKOUT high to EAx valid ns t d(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 ns t d(EKOH-CASV) Delay time, ECLKOUT high to ARE SDCAS SSADS valid 1.5 ns t d(EKOH-EDV) Delay time, ECLKOUT high to EDX valid ns t d(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 ns t d(EKOH-WEV) Delay time, ECLKOUT high to AWE SDWE SSWE valid 1.5 ns t d(EKOH-RAV) Delay time, ECLKOUT high to AOE SDRAS SSOE valid 1.5 ns (1) The C6713/13B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. (2) ARE SDCAS SSADS AWE SDWE SSWE and AOE SDRAS SSOE operate as SDCAS SWE and SDRAS respectively, during SDRAM accesses. PARAMETRIC INFORMATION Submit Documentation Feedback

BE[3:0] EA[11:2] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE EA[21:13] BE1 BE2B E3 BE4 Bank Column D1 D2 D3 D4 READ (A) (A) (A) NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 11-14. SDRAM Read Command (CAS Latency Submit Documentation Feedback PARAMETRIC INFORMATION

BE[3:0] EA[11:2] ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE EA12 EA[21:13] BE1 BE2 BE3 BE4 Bank Column D1 D2 D3 D4 WRITE NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) ECLKOUT CEx BE[3:0] EA[21:13] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE Bank Activate Row Address Row Address EA[11:2] ACTV NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 11-15. SDRAM Write Command Figure 11-16. SDRAM ACTV Command PARAMETRIC INFORMATION Submit Documentation Feedback

BE[3:0] EA[21:13, 11:2] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE DCAB NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) ECLKOUT CEx BE[3:0] EA[21:13] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE EA[11:2] Bank DEAC NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 11-17. SDRAM DCAB Command Figure 11-18. SDRAM DEAC Command Submit Documentation Feedback PARAMETRIC INFORMATION

BE[3:0] EA[21:2] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE REFR NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) ECLKOUT CEx BE[3:0] EA[21:2] ED[31:0] AOE /SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE MRS□value MRS NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 11-19. SDRAM REFR Command Figure 11-20. SDRAM MRS Command PARAMETRIC INFORMATION Submit Documentation Feedback

11.9 HOLD HOLDA Timing HOLD HOLDA EMIF□Bus DSP□Owns□Bus External□Requestor Owns□Bus DSP□Owns□Bus C6713/13BC 6713/13B NOTE□A:□□□EMIF□bus□consists□of , ,□ED[31:0],□EA[21:2], / / ,□andCE[3:0]□□BE[3:0] AWE□SDWE□SSWEARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / . (A) 11.10 BUSREQ Timing ECLKOUT BUSREQ SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-13. Timing Requirements for HOLD HOLDA Cycles (1) See Figure 11-21 NO. MIN MAX UNIT t h(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E ns (1) E ECLKOUT period in ns Table 11-14. Switching Characteristics for HOLD HOLDA Cycles (1) (2) over recommended operating conditions (see Figure 11-21 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX t d(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance (3) (3) ns t d(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0.1 ns t d(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance ns t d(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 1.5 ns (1) E ECLKOUT period in ns (2) EMIF bus consists of CE[3:0] BE[3:0] ED[31:0], EA[21:2], ARE SDCAS SSADS AOE SDRAS SSOE and AWE SDWE SSWE (3) All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD Figure 11-21. HOLD HOLDA Timing Table 11-15. Switching Characteristics for BUSREQ Cycles over recommended operating conditions (see Figure 11-22 NO. PARAMETER MIN MAX UNIT t d(EKOH-BUSRV) Delay time, ECLKOUT high to BUSREQ valid 1.5 7.2 ns Figure 11-22. BUSREQ Submit Documentation Feedback PARAMETRIC INFORMATION

11.11 Reset Timing SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-16. Timing Requirements for RESET (1) (2) See Figure 11-23 NO. MIN MAX UNIT t w(RST) Pulse duration, RESET 100 ns t su(HD) Setup time, HD boot configuration bits valid before RESET high (3) ns t h(HD) Hold time, HD boot configuration bits valid after RESET high (3) ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For the C6713/13B device, the PLL is bypassed immediately after the device comes out of reset. The PLL controller can be programmed to change the PLL mode in software. For more detailed information on the PLL controller, see the TMS320C6000 DSP Phase-Lock Loop (PLL) Controller Peripheral Reference Guide (literature number SPRU233). (3) The boot and device configurations bits are latched asynchronously when RESET is transitioning high. The boot and device configurations bits consist of HD[14, 4:3]. Table 11-17. Switching Characteristics For RESET (1) over recommended operating conditions (see Figure 11-23 NO. PARAMETER MIN MAX UNIT 512 x Delay time, external RESET high to internal reset high and all t d(RSTH-ZV) CLKMODE0 CLKIN ns signal groups valid (2) (3) period t d(RSTL-ECKOL) Delay time, RESET low to ECLKOUT low (6713) ns t d(RSTL-ECKOL) Delay time, RESET low to ECLKOUT high impedance (6713B) ns t d(RSTH-ECKOV) Delay time, RESET high to ECLKOUT valid ns t d(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 invalid (6713) ns t d(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 high impedance (6713B) ns t d(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid ns t d(RSTL-CKO3L) Delay time, RESET low to CLKOUT3 low ns t d(RSTH-CKO3V) Delay time, RESET high to CLKOUT3 valid ns t d(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance (3) ns t d(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group (BUSREQ) invalid (3) ns t d(RSTL-Z1HZ) Delay time, RESET low to Z group high impedance (3) ns t d(RSTL-Z2HZ) Delay time, RESET low to Z group high impedance (3) ns (1) P 1/CPU clock frequency in ns. Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by For example, if the CLKIN period is ns, the CPU clock (SYSCLK1) period is ns x 160 ns. Therefore, P SYSCLK1 160 ns while internal reset is asserted. (2) The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 1). If the input clock (CLKIN) is not stable when RESET is deasserted, the actual delay time may vary. (3) EMIF Z group consists of EA[21:2], ED[31:0], CE[3:0] BE[3:0] ARE SDCAS SSADS AWE SDWE SSWE AOE SDRAS SSOE and HOLDA EMIF low group consists of BUSREQ. Z group consists of CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7], FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0, and SCL0. Z group consists of all other HPI, McASP0/1, GPIO, and I2C1 signals. PARAMETRIC INFORMATION 100 Submit Documentation Feedback

Internal□Reset Internal□SYSCLK1 Internal□SYSCLK2 Internal□SYSCLK3 CLKOUT3 RESET Phase 3 EMIF□Z□Group EMIF□Low□Group Z□Group 1 Z□Group 2 Boot□and Device Configuration Pins

6713 ECLKOUT

6713□CLKOUT2 6713B□ECLKOUT 6713B□CLKOUT2 (A) (A) (A) (A) (B) NOTES□A:□EMIF□Z□group□consists□of□EA[21:2],□ED[31:0], , , / / , / / , / / ,□and . Z□group□1□consists□of□CLKR0/ACLKR0,□CLKR1/AXR0[6],□CLKX0/ACLKX0,□CLKX1/AMUTE0,□FSR0/AFSR0,□FSR1/AXR0[7],□FSX0/AFSX0,□FSX1, DX0/AXR0[1],□DX1/AXR0[5],□TOUT0/AXR0[2],□TOUT1/AXR0[4],□SDA0,□and□SCL0. Z□group□2□consists□of□All□other□HPI,□McASP0/1,□GPIO,□and□I2C1□signals. B:□Boot□and□device□configurations□consist□of:□HD[14,□8,□4:3]. CE[3:0]□□BE[3:0]□□ARE□SDCAS□SSADS□□AWE□SDWE□SSWE□□AOE□SDRAS□SSOE HOLDA EMIF□low□group□consists□of□BUSREQ. SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 11-23. Reset Timing Reset Phase The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8. Reset Phase The RESET pin is deasserted but the internal reset is stretched. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8. Reset Phase Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin (when EKSRC bit [default]). CLKOUT3 is running at CLKIN frequency divide-by-8. Submit Documentation Feedback PARAMETRIC INFORMATION 101

11.12 External Interrupt Timing EXT_INT,□NMI SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-18. Timing Requirements for External Interrupts (1) See Figure 11-24 NO. MIN MAX UNIT Width of the NMI interrupt pulse low ns t w(ILOW) Width of the EXT_INT interrupt pulse low ns Width of the NMI interrupt pulse high ns t w(IHIGH) Width of the EXT_INT interrupt pulse high ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. Figure 11-24. External/NMI Interrupt PARAMETRIC INFORMATION 102 Submit Documentation Feedback

11.13 Multichannel Audio Serial Port (McASP) Timing SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-19. Timing Requirements for McASP See Figure 11-25 and Figure 11-26 6713 6713B NO. UNIT MIN MAX MIN MAX t c(AHCKRX) Cycle time, AHCLKR/X ns t w(AHCKRX) Pulse duration, AHCLKR/X high or low 7.5 7.5 ns t c(ACKRX) Cycle time, ACLKR/X ACLKR/X ext ns t w(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X ext ns ACLKR/X int ns Setup time, AFSR/X input valid before ACLKR/X t su(AFRXC-ACKRX) latches data ACLKR/X ext ns ACLKR/X int ns Hold time, AFSR/X input valid after ACLKR/X t h(ACKRX-AFRX) latches data ACLKR/X ext ns ACLKR/X int 10.2 ns Setup time, AXR input valid before ACLKR/X t su(AXR-ACKRX) latches data ACLKR/X ext ns ACLKR/X int ns Hold time, AXR input valid after ACLKR/X latches t h(ACKRX-AXR) data ACLKR/X ext ns Table 11-20. Switching Characteristics for McASP (1) over recommended operating conditions (see Figure 11-25 and Figure 11-26 NO. PARAMETER MIN MAX UNIT t c(AHCKRX) Cycle time, AHCLKR/X ns t w(AHCKRX) Pulse duration, AHCLKR/X high or low (AH/2) 2.5 ns t c(ACKRX) Cycle time, ACLKR/X ACLKR/X int ns t w(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X int (AH/2) 2.5 ns ACLKR/X int ns Delay time, ACLKR/X transmit edge to AFSX/R t d(ACKRX-AFRX) output valid ACLKR/X ext ns ACLKR/X int ns t d(ACKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X ext ns ACLKR/X int ns Disable time, AXR high impedance following last data t dis(ACKRX AXRHZ) bit from ACLKR/X transmit edge ACLKR/X ext ns (1) AH AHCLKR/X period in ns; A ACLKR/X period in ns Submit Documentation Feedback PARAMETRIC INFORMATION 103

A0 A1 B0 B1 A30A 31 B30B 31 C0 C1 C2 C3 C31 AHCLKR/X□(Falling□Edge□Polarity) AHCLKR/X□(Rising□Edge□Polarity) ACLKR/X□(Falling□Edge□Polarity) ACLKR/X□(Rising□Edge□Polarity) AFSR/X□(Bit□Width,□0□Bit□Delay) AFSR/X□(Bit□Width,□1□Bit□Delay) AFSR/X□(Bit□Width,□2□Bit□Delay) AFSR/X□(Slot□Width,□0□Bit□Delay) AFSR/X□(Slot□Width,□1□Bit□Delay) AFSR/X□(Slot□Width,□2□Bit□Delay) AXR[n]□(Data□In/Receive) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 11-25. McASP Input Timings PARAMETRIC INFORMATION 104 Submit Documentation Feedback

A0 A1 B0 B1 A30A 31 B30B 31 C0 C1 C2 C3 C31 AHCLKR/X□(Falling□Edge□Polarity) AHCLKR/X□(Rising□Edge□Polarity) ACLKR/X□(Falling□Edge□Polarity) ACLKR/X□(Rising□Edge□Polarity) AFSR/X□□(Bit□Width,□0□Bit□Delay) AFSR/X□(Bit□Width,□1□Bit□Delay) AFSR/X□(Bit□Width,□2□Bit□Delay) AFSR/X□(Slot□Width,□0□Bit□Delay) AFSR/X□(Slot□Width,□1□Bit□Delay) AFSR/X□(Slot□Width,□2□Bit□Delay) AXR[n]□(Data□Out/Transmit) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 11-26. McASP Output Timings Submit Documentation Feedback PARAMETRIC INFORMATION 105

11.14 Inter-Integrated Circuits Timing 6 14 Stop Start Repeated Start Stop SDA SCL 11 9 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-21. Timing Requirements for I C (1) See Figure 11-27 STANDARD FAST MODE MODE NO. UNIT MIN MAX MIN MAX t c(SCL) Cycle time, SCL 2.5 µ s Setup time, SCL high before SDA low (for a repeated t su(SCLH-SDAL) 4.7 0.6 µ s START condition) Hold time, SCL low after SDA low (for a START and a t h(SCLL-SDAL) 0.6 µ s repeated START condition) t w(SCLL) Pulse duration, SCL low 4.7 1.3 µ s t w(SCLH) Pulse duration, SCL high 0.6 µ s t su(SDAV-SDLH) Setup time, SDA valid before SCL high 250 100 (2) ns Hold time, t h(SDA-SDLL) (3) (3) 0.9 (4) µ s SDA valid after SCL low (for I C bus devices) Pulse duration, t w(SDAH) 4.7 1.3 µ s SDA high between STOP and START conditions t r(SDA) Rise time, SDA 1000 0.1C b (5) 300 ns t r(SCL) Rise time, SCL 1000 0.1C b (5) 300 ns t f(SDA) Fall time, SDA 300 0.1C b (5) 300 ns t f(SCL) Fall time, SCL 300 0.1C b (5) 300 ns Setup time, t su(SCLH-SDAH) 0.6 µ s SCL high before SDA high (for STOP condition) t SP) Pulse duration, spike (must be suppressed) ns C b (5) Capacitive load for each bus line 400 400 pF (1) The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement t su (SDA SCLH) 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r max t su (SDA SCLH) 1000 250 1250 ns (according to the standard-mode I C-bus specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum t h(SDA SCLL) has only to be met if the device does not stretch the low period w(SCLL) of the SCL signal. (5) C b total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times are allowed. Figure 11-27. I C Receive PARAMETRIC INFORMATION 106 Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-22. Switching Characteristics for I C (1) over recommended operating conditions (see Figure 11-28 STANDARD FAST MODE MODE NO. PARAMETER MIN MAX MIN MAX UNIT t c(SCL) Cycle time, SCL 2.5 µ s Delay time, SCL high to SDA low (for a repeated START t d(SCLH-SDAL) 4.7 0.6 µ s condition) Delay time, SDA low to SCL low (for a START and a repeated t d(SDAL-SCLL) 0.6 µ s START condition) t w(SCLL) Pulse duration, SCL low 4.7 1.3 µ s t w(SCLH) Pulse duration, SCL high 0.6 µ s t d(SDAV-SDLH) Delay time, SDA valid to SCL high 250 100 ns Valid time, t v(SDLL-SDAV) 0.9 µ s SDA valid after SCL low (for I C bus devices) Pulse duration, t w(SDAH) 4.7 1.3 µ s SDA high between STOP and START conditions t r(SDA) Rise time, SDA 1000 0.1C b (1) 300 ns t r(SCL) Rise time, SCL 1000 0.1C b (1) 300 ns t f(SDA) Fall time, SDA 300 0.1C b (1) 300 ns t f(SCL) Fall time, SCL 300 0.1C b (1) 300 ns Delay time, t d(SCLH-SDAH) 0.6 µ s SCL high to SDA high (for STOP condition) C b Capacitance for each I2C pin pF (1) C b total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 11-28. I C Transmit Timings Submit Documentation Feedback PARAMETRIC INFORMATION 107

11.15 Host-Port Interface Timing SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-23. Timing Requirements for Host-Port Interface Cycles (1) (2) See Figure 11-29 Figure 11-32 6713 6713B NO. UNIT MIN MAX MIN MAX t su(SELV-HSTBL) Setup time, select signals valid before HSTROBE low (3) ns t h(HSTBL-SELV) Hold time, select signals valid after HSTROBE low (3) ns Pulse duration, HSTROBE low (host read access) 10P 5.8 ns t w(HSTBL) Pulse duration, HSTROBE low (host write access) ns t w(HSTBH) Pulse duration, HSTROBE high between consecutive accesses ns t su(SELV-HASL) Setup time, select signals valid before HAS low (3) ns t h(HASL-SELV) Hold time, select signals valid after HAS low (3) ns t su(HDV-HSTBH) Setup time, host data valid before HSTROBE high ns t h(HSTBH-HDV) Hold time, host data valid after HSTROBE high ns Hold time, HSTROBE low after HRDY low. HSTROBE should not t h(HRDYL-HSTBL) be inactivated until HRDY is active (low); otherwise, HPI writes will ns not complete properly. t su(HASL-HSTBL) Setup time, HAS low before HSTROBE low ns t h(HSTBL-HASL) Hold time, HAS low after HSTROBE low ns (1) HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 [NOT( HDS1 XOR HDS2 OR HCS (2) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (3) Select signals include HCNTL[1:0], HR/ W and HHWIL. PARAMETRIC INFORMATION 108 Submit Documentation Feedback

1st□halfword2 nd□halfword 51786 51785 916 2121 2121 HAS HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□(output) HRDY (case□1) HRDY (case□2) 3(A) NOTE□A: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR .HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-24. Switching Characteristics for Host-Port Interface Cycles (1) (2) over recommended operating conditions (see Figure 11-29 Figure 11-32 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX t d(HCS-HRDY) Delay time, HCS to HRDY (3) ns t d(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high (4) ns t d(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an ns HPI read t d(HDV-HRDYL) Delay time, HD valid to HRDY low ns t oh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high ns t d(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance ns t d(HSTBL-HDV) Delay time, HSTROBE low to HD valid 10P 5.8 12.5 ns t d(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high (5) ns (1) HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 [NOT( HDS1 XOR HDS2 OR HCS (2) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (3) HCS enables HRDY and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. (4) This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. (5) This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. Figure 11-29. HPI Read Timing HAS Not Used, Tied High) Submit Documentation Feedback PARAMETRIC INFORMATION 109

HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□(output) HRDY (case□1) HRDY (case□2) 1st□half-word 2nd□half-word 5178 51785 916 111011 10 19 19 1818 (B) (A) NOTES□A:□For□correct□operation,□strobe□the signal□only□once□per active□cycle. B: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR . HAS HSTROBE HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS 1st□halfword 2nd□halfword 5175 1HAS HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□□(input) HRDY (A) NOTE□A: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR .HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 11-30. HPI Read Timing HAS Used) Figure 11-31. HPI Write Timing HAS Not Used, Tied High) PARAMETRIC INFORMATION 110 Submit Documentation Feedback

1st□half-word 2nd□half-word 5175 13121312 HAS HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□□(input) HRDY 1919 18 18 (A) (B) NOTES□A:□For□correct□operation,□strobe□the signal□only□once□per active□cycle. B: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR . HAS HSTROBE HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Figure 11-32. HPI Write Timing HAS Used) Submit Documentation Feedback PARAMETRIC INFORMATION 111

11.16 Multichannel Buffered Serial Port (McBSP) Timing SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-25. Timing Requirements for McBSP (1) (2) See Figure 11-33 NO. PARAMETER MIN MAX UNIT t c(CKRX) Cycle time, CLKR/X CLKR/X ext (3) ns t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5 t c(CKRX) (4) ns CLKR int ns Setup time, external FSR high before CLKR t su(FRH-CKRL) low CLKR ext ns CLKR int ns t h(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext ns CLKR int ns t su(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext ns CLKR int ns t h(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext ns CLKX int ns Setup time, external FSX high before CLKX t su(FXH-CKXL) low CLKX ext ns CLKX int ns t h(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext ns (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (3) The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is Mbps for 167-MHz and 225-MHz CPU clocks or Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the ac timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz 6.7 ns), use ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at MHz 16.67 ns), use ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM FSXM and CLKRM FSRM in data delay or mode (R/XDATDLY 01b or 10b) and the other device the McBSP communicates to is a slave. (4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of duty cycle. PARAMETRIC INFORMATION 112 Submit Documentation Feedback

www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-26. Switching Characteristics for McBSP (1) (2) over recommended operating conditions (see Figure 11-33 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX Delay time, CLKS high to CLKR/X high for t d(CKSH-CKRXH) 1.8 1.8 ns internal CLKR/X generated from CLKS input t c(CKRX) Cycle time, CLKR/X CLKR/X int (3) (4) (3) (4) ns Pulse duration, CLKR/X high or t w(CKRX) CLKR/X int C (5) C (5) C (5) C (5) ns CLKR/X low Delay time, CLKR high to internal t d(CKRH-FRV) CLKRint ns FSR valid CLKX int ns Delay time, CLKX high to internal t d(CKXH-FXV) FSX valid CLKX ext ns Disable time, DX high impedance CLKX int ns t dis(CKXH-DXHZ) following last data bit from CLKX CLKX ext 1.5 1.5 ns high CLKX int 3.2 (6) (6) 3.2 (6) (6) ns t d(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 0.5 (6) 0.5 (6) (6) ns (6) Delay time, FSX high to DX valid FSX int 1.5 4.5 7.5 ns t d(FXH-DXV) ONLY applies when in data delay FSX ext 11.5 ns (XDATDLY 00b) mode (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Minimum delay times also represent minimum output hold times. (3) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (4) The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is Mbps for 167-MHz and 225-MHz CPU clocks or Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz 6.7 ns), use ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at MHz 16.67 ns), use ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM FSXM and CLKRM FSRM in data delay or mode (R/XDATDLY 01b or 10b) and the other device the McBSP communicates to is a slave. (5) C H or L S sample rate generator input clock if CLKSM 1/CPU clock frequency) S sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H CLKX high pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L CLKX low pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zeroCLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see note above). (6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA in SPCR. If DXENA then If DXENA then 2P, 4P. Submit Documentation Feedback PARAMETRIC INFORMATION 113

Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 1312 CLKS CLKR FSR□(int) FSR□(ext) DR CLKX FSX□(int) FSX□(ext) FSX□(XDATDLY=00b) DX CLKS FSR□external CLKR/X□(no□need□to□resync) CLKR/X□(needs□resync) SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Figure 11-33. McBSP Timings Table 11-27. Timing Requirements for FSR When GSYNC See Figure 11-34 NO. MIN MAX UNIT t su(FRH-CKSH) Setup time, FSR high before CLKS high ns t h(CKSH-FRH) Hold time, FSR high after CLKS high ns Figure 11-34. FSR Timing When GSYNC Table 11-28. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP 10b, CLKXP (1) (2) See Figure 11-35 MASTER SLAVE NO. UNIT MIN MAX MIN MAX t su(DRV-CKXL) Setup time, DR valid before CLKX low ns t h(CKXL-DRV) Hold time, DR valid after CLKX low 12P ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV PARAMETRIC INFORMATION 114 Submit Documentation Feedback

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-29. Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP 10b, CLKXP (1) (2) over recommended operating conditions (see Figure 11-35 6713 6713B NO. PARAMETER MASTER (3) SLAVE MASTER (3) SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX Hold time, FSX low after CLKX ns t h(CKXL-FXL) T T T T low (4) Delay time, FSX low to CLKX ns t d(FXL-CKXH) L L L L high (5) t d(CKXH-DXV) Delay time, CLKX high to DX ns 10P 10P valid Disable time, DX high t dis(CKXL-DXHZ) impedance following last data L L L L ns bit from CLKX low Disable time, DX high t dis(FXH-DXHZ) impedance following last data ns 1.5 bit from FSX high t d(FXL-DXV) Delay time, FSX low to DX valid ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (3) S Sample rate generator input clock if CLKSM 1/CPU clock frequency) S Sample rate generator input clock Sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) T CLKX period CLKGDV) S H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H CLKX high pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L CLKX low pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero (4) FSRP FSXP As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM FSXM CLKRM FSRM for master McBSP. CLKXM CLKRM FSXM FSRM for slave McBSP. (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 11-35. McBSP Timing as SPI Master or Slave: CLKSTP 10b, CLKXP Table 11-30. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP 11b, CLKXP (1) (2) See Figure 11-36 MASTER SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX t su(DRV-CKXH) Setup time, DR valid before CLKX high ns t h(CKXH-DRV) Hold time, DR valid after CLKX high 12P ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV Submit Documentation Feedback PARAMETRIC INFORMATION 115

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) 376 CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-31. Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP 11b, CLKXP (1) (2) over recommended operating conditions (see Figure 11-36 6713 6713B NO. PARAMETER MASTER (3) SLAVE MASTER (3) SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX Hold time, FSX low after t h(CKXL-FXL) L L L L ns CLKX low (4) Delay time, FSX low to t d(FXL-CKXH) T T T T ns CLKX high (5) Delay time, CLKX low to DX t d(CKXL-DXV) 10P 10P ns valid Disable time, DX high t dis(CKXL-DXHZ) impedance following last 10P 10P ns 1.5 data bit from CLKX low Delay time, FSX low to DX t d(FXL-DXV) H H H H 6.5 ns valid (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (3) S Sample rate generator input clock if CLKSM 1/CPU clock frequency) S Sample rate generator input clock Sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) T CLKX period CLKGDV) S H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H CLKX high pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L CLKX low pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero (4) FSRP FSXP As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM FSXM CLKRM FSRM for master McBSP. CLKXM CLKRM FSXM FSRM for slave McBSP. (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 11-36. McBSP as SPI Master or Slave: CLKSTP 11b, CLKXP PARAMETRIC INFORMATION 116 Submit Documentation Feedback

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-32. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP 10b, CLKXP (1) (2) See Figure 11-37 MASTER SLAVE NO. UNIT MIN MAX MIN MAX t su(DRV-CKXH) Setup time, DR valid before CLKX high ns t h(CKXH-DRV) Hold time, DR valid after CLKX high 12P ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV Table 11-33. Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP 10b, CLKXP (1) (2) over recommended operating conditions (see Figure 11-37 6713 6713B NO. PARAMETER MASTER (3) SLAVE MASTER (3) SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX Hold time, FSX low after CLKX ns t h (CKXH-FXL) T T T T high (4) Delay time, FSX low to CLKX H ns t d (FXL-CKXL) H H H low (5) t d (CKXL-DXV) Delay time, CLKX low to DX valid 10P 10P ns Disable time, DX high impedance H H t dis (CKXH-DXHZ) following last data bit from CLKX H H ns 3.6 high Disable time, DX high impedance t dis (FXH-DXHZ) following last data bit from FSX ns 1.5 high t d (FXL-DXV) Delay time, FSX low to DX valid ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (3) S Sample rate generator input clock if CLKSM 1/CPU clock frequency) S Sample rate generator input clock Sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) T CLKX period CLKGDV) S H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H CLKX high pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L CLKX low pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero (4) FSRP FSXP As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM FSXM CLKRM FSRM for master McBSP. CLKXM CLKRM FSXM FSRM for slave McBSP. (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 11-37. McBSP as SPI Master or Slave: CLKSTP 10b, CLKXP Submit Documentation Feedback PARAMETRIC INFORMATION 117

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) 376 CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-34. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP 11b, CLKXP (1) (2) See Figure 11-38 MASTER SLAVE NO. UNIT MIN MAX MIN MAX t su(DRV-CKXH) Setup time, DR valid before CLKX high ns t h(CKXH-DRV) Hold time, DR valid after CLKX high 12P ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV Table 11-35. Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP 11b, CLKXP (1) (2) over recommended operating conditions (see Figure 11-38 6713 6713B NO. PARAMETER MASTER (3) SLAVE MASTER (3) SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX Hold time, FSX low after CLKX H H H ns t h(CKXH-FXL) T high (4) Delay time, FSX low to CLKX ns t d(FXL-CKXL) T T T H low (5) Delay time, CLKX high to DX ns t d(CKXH-DXV) 10P 10P valid Disable time, DX high impedance t dis(CKXH-DXHZ) following last data bit from CLKX 3.6 10P 10P ns 1.5 high t d(FXL-DXV) Delay time, FSX low to DX valid L L L L 6.5 ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (3) S Sample rate generator input clock if CLKSM 1/CPU clock frequency) S Sample rate generator input clock Sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) T CLKX period CLKGDV) S H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H CLKX high pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L CLKX low pulse width (CLKGDV 1)/2 S if CLKGDV is odd or zero (4) FSRP FSXP As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM FSXM CLKRM FSRM for master McBSP. CLKXM CLKRM FSXM FSRM for slave McBSP. (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 11-38. McBSP as SPI Master or Slave: CLKSTP 11b, CLKXP PARAMETRIC INFORMATION 118 Submit Documentation Feedback

11.17 Timer Timing TINPx TOUTx SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-36. Timing Requirements for Timer Inputs (1) See Figure 11-39 NO. MIN MAX UNIT t w(TINPH) Pulse duration, TINP high ns t w(TINPL) Pulse duration, TINP low ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. Table 11-37. Switching Characteristics for Timer Inputs (1) over recommended operating conditions (see Figure 11-39 NO. PARAMETER MIN MAX UNIT t w(TOUTH) Pulse duration, TOUT high ns t w(TOUTL) Pulse duration, TOUT low ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. Figure 11-39. Timer Submit Documentation Feedback PARAMETRIC INFORMATION 119

11.18 General-Purpose Input/Output (GPIO) Port Timing GPIx GPOx SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com Table 11-38. Timing Requirements for GPIO Inputs (1) (2) See Figure 11-40 NO. MIN MAX UNIT t w(GPIH) Pulse duration, GPIx high ns t w(GPIL) Pulse duration, GPIx low ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access the GPIO register through the CFGBUS. Table 11-39. Switching Characteristics for GPIO Inputs (1) (2) over recommended operating conditions (see Figure 11-40 NO. PARAMETER MIN MAX UNIT t w(GPOH) Pulse duration, GPOx high 12P ns t w(GPOL) Pulse duration, GPOx low 12P ns (1) P 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P 3.3 ns. (2) The number of CFGBUS cycles between two back-to-back CFGBUS writes to the GPIO register is SYSCLK1 cycles; therefore, the minimum GPOx pulse width is 12P. Figure 11-40. GPIO Port Timing PARAMETRIC INFORMATION 120 Submit Documentation Feedback

11.19 JTAG Test Port Timing TCK TDO TDI/TMS/TRST SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 Table 11-40. Timing Requirements for JTAG Test Port See Figure 11-41 NO. MIN MAX UNIT t c(TCK) Cycle time, TCK ns t su(TDIV- Setup time, TDI/TMS/ TRST valid before TCK high ns TCKH) t h(TCKH-TDIV) Hold time, TDI/TMS/ TRST valid after TCK high ns Table 11-41. Switching Characteristics for JTAG Test Port over recommended operating conditions (see Figure 11-41 NO. PARAMETER MIN MAX UNIT t d(TCKL-TDOV) Delay time, TCK low to TDO valid ns Figure 11-41. JTAG Test-Port Timing Submit Documentation Feedback PARAMETRIC INFORMATION 121

12.1 Mechanical Information 12.2 Packaging Information SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H AUGUST 2003 REVISED SEPTEMBER 2008 www.ti.com The following table shows the thermal resistance characteristics for the GDP package. Table 12-1. Thermal Resistance Characteristics (S-PBGA Package) for GDP Air Flow NO C/W (m/s) (1) Two Signals, Two Planes (4-Layer Board) R θ JC Junction-to-case 9.7 N/A Psi JT Junction-to-package top 1.5 0.0 R θ JB Junction-to-board N/A R θ JA Junction-to-free air 0.0 R θ JA Junction-to-free air 0.5 R θ JA Junction-to-free air 1.0 R θ JA Junction-to-free air 2.0 R θ JA Junction-to-free air 4.0 Psi JB Junction-to-board 0.0 (1) m/s meters per second For proper device thermal performance, the thermal pad must be soldered to an external ground thermal plane. The following packaging information and addendum reflect the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document. MECHANICAL DATA 122 Submit Documentation Feedback

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