SMX320C6713GNYM20EP

Texas Instruments

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

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Datasheet sections

1 FEATURES
2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
3 DEVICE INFORMATION
3.1 Description
3.2 DeviceCharacteristics
3.3 FunctionalBlockand CPU (DSP Core)Diagram
4 OVERVIEW
4.1 CPU (DSP Core)Description
4.2 Memory Map Summary
4.3 L2 Memory StructureExpanded
4.4 PeripheralRegisterDescriptions
4.5 SignalGroups Description
5 DEVICE CONFIGURATIONS
5.1 DeviceConfigurationsatDeviceReset
5.2 PeripheralPinSelectionatDeviceReset
5.3 PeripheralSelection/DeviceConfigurationsViatheDEVCFG ControlRegister
5.4 MultiplexedPins
5.5 ConfigurationExamples
5.6 DebuggingConsiderations
6 TERMINAL FUNCTIONS
6.1 DevelopmentSupport
6.2 Deviceand Development-SupportToolNomenclature
6.2.1 DeviceDevelopmentEvolutionaryFlow
6.2.2 SupportToolDevelopmentEvolutionaryFlow
6.3 OrderingNomenclature
6.4 DocumentationSupport
7 REGISTER INFORMATION
7.1 CPU ControlStatusRegister(CSR) Description
7.2 Cache Configuration(CCFG) RegisterDescription(13B)
7.3 Interruptsand InterruptSelector
7.4 ExternalInterruptSources
7.5 EDMA Module and EDMA Selector
8 PLL and PLL Controller
8.1 PLL Registers
9 MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS
9.1 McASP BlockDiagram
9.2 MultichannelTime DivisionMultiplexed(TDM) SynchronousTransferMode
9.3 BurstTransferMode
9.4 SupportedBitStream FormatsforTDM and BurstTransferModes
9.5 DigitalAudioInterfaceTransmitter(DIT)TransferMode (TransmitterOnly)
9.6 McASP FlexibleClockGenerators
9.7 McASP ErrorHandlingand Management
9.8 McASP Interruptsand EDMA Events
9.9 I2C
10 LOGIC AND POWER SUPPLY
2 Contents Copyright© 2003–2009,Texas InstrumentsIncorporated

FLOATING-POINT DIGITAL SIGNAL PROCESSORS Data Manual PRODUCTION DATA informationiscurrentas of publicationdate. Products conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters. LiteratureNumber: SGUS049I August2003–RevisedSeptember 2009

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com ListofFigures

4 ListofFigures Copyright© 2003–2009,Texas InstrumentsIncorporated

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com ListofTables 8-8 PLL Wrapper Dividerx Registers(PLLDIV0,PLLDIV1,PLLDIV2,and PLLDIV3) 8-9 PLL Wrapper Dividerx Registers

6 ListofTables Copyright© 2003–2009,Texas InstrumentsIncorporated

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com

8 ListofTables Copyright© 2003–2009,Texas InstrumentsIncorporated

www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 FLOATING-POINTDIGITALSIGNALPROCESSORS Check forSamples: SM320C6713-EP

1 FEATURES

HighestPerformance FloatingPointDigital • 32 BitExternalMemory Interface(EMIF) SignalProcessors (DSPs):C6713/C6713B – GluelessInterfacetoSRAM, EPROM, Flash, – Eight32 BitInstructions/Cycle SBSRAM, and SDRAM – 32/64BitData Word – 512M Byte TotalAddressable External Memory Space– 200 and 300 MHz Clock Rate
Enhanced DirectMemory Access (EDMA)– 5 InstructionCycle Times Controller(16IndependentChannels)– 2400/1800and 1600/1200MIPS/MFLOPS
16 BitHost PortInterface(HPI)– Rich PeripheralSet,OptimizedforAudio
Two MultichannelAudio SerialPorts(McASPs)– HighlyOptimizedC/C++ Compiler – Two IndependentClock Zones Each• Advanced Very Long InstructionWord (VLIW) (One TX and One RX)320C67x ™ DSP Core – EightSerialData Pins Per Port:Individually– EightIndependentFunctionalUnits: Assignabletoany oftheClock Zones• Two ALUs (FixedPoint) – Wide VarietyofI2S™ and SimilarBitStream• Four ALUs (FloatingPointand Fixed FormatsPoint) – IntegratedDigitalAudio InterfaceTransmitter• Two Multipliers(FloatingPointand Fixed (DIT)Point) – ExtensiveErrorChecking and Recovery– Load StoreArchitectureWith 32 32-Bit • Two Inter-IntegratedCircuitBus (I2C ™ Bus)GeneralPurpose Registers Multi-Masterand SlaveInterfaces– InstructionPacking Reduces Code Size • Two MultichannelBufferedSerialPorts:– AllInstructionsConditional – SerialPeripheralInterface(SPI)• InstructionSet Features – High Speed TDM Interface– NativeInstructionsforIEEE 754 – AC97 Interface– Byte Addressable (8/16/32BitData) • Two 32 BitGeneralPurpose Timers– 8 BitOverflowProtection • DedicatedGPIO Module With 16 Pins (External– Saturation;Bit-FieldExtract,Set,Clear; InterruptCapable)Bit-Counting;Normalization • FlexiblePhase Locked Loop (PLL)Based Clock• L1/L2Memory Architecture GeneratorModule– 4K Byte L1P Program Cache (Direct-Mapped) • IEEE-1149.1(JTAG)(1)Boundary-Scan– 4K Byte L1D Data Cache (2-Way) Compatible – 256K Byte L2 Memory Total:64K-Byte L2 • 272 Ball,BallGridArrayPackage (GDP)UnifiedCache/Mapped RAM, and 192K Byte • 0.13μm/6 LevelCopper MetalProcessAdditionalL2 Mapped RAM – CMOS Technology• Device Configuration • 3.3V I/Os,1.26V Internal– Boot Mode: HPI,8/16/32BitROM Boot (1) IEEE Standard1149.1-1990Standard-Test-AccessPortand – Endianness:LittleEndian,Big Endian BoundaryScan Architecture. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2320C67x,TMS320C67x, TMS320C6000, eXpressDSP, Code Composer Studio,DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x,C67x aretrademarksofTexas Instruments. Copyright© 2003–2009,Texas InstrumentsIncorporated FEATURES 9 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

break• ControlledBaseline

Extended Product LifeCycle• One Assembly/TestSite
Extended Product-Change Notification• One FabricationSite
Product Traceability• AvailableinMilitary(–55°C/125°C) Temperature Range (2) (2) Custom temperaturerangesavailable 3320C67x,TMS320C67x, TMS320C6000, eXpressDSP, Code Composer Studio,DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x,C67x aretrademarksofTexas Instruments. 10 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Copyright© 2003–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

Y W V U T R P N M L K J H G F E D C B A EA20DVDDEA18EA16EA14VSS CLKOUT2/ GP[2]ECLKINECLKOUTEA9EA7DVDDEA2ARDYBE2 ED18VSSVSS VSS CVDD DVDD ED17 VSS CE2 EA4 EA6 DVDD AOE SDRAS SSOE AWE SDWE SSWE ARE SDCAS SSADS VSS DVDD EA11 EA13 EA15 VSS EA19 CE1 CVDD VSS BE0DVDDCVDDCE0EA17DVDDEA12DVDDEA10EA8EA5EA3CE3BE3ED16CVDDED19ED20 ED22 ED28 SCL0 FSX1 CLKR1/ AXR0[6] DR1/ SDA1 DR0/ AXR0[0] DX0/ AXR0[1] FSR1/ AXR0[7] DVDD ED24 ED21 ED29 SDA0 DX1 AXR0[5] CLKX1/ AMUTE0 CLKS1/ SCL1 GP[5] (EXT_INT5) AMUTEIN0 GP[4] (EXT_INT4) AMUTEIN1 GP[7] (EXT_INT7) GP[6] (EXT_INT6) CLKS0 AHCLKR0 ED27 ED25 ED23 ED30 ED31 ED26 DVDD EA21 BE1 VSSVSS VSS VSS CVDD VSS CVDD VSS DVDD CVDD DVDD VSS VSS VSS VSSCVDD CVDDCVDD CVDDDVDD DVDD VSS VSS VSS CVDD CVDD CVDD VSS ED13 ED6 ED9 DVDD ED2 ED0 DVDD ED15 ED7 VSS ED11 ED3 ED1 ED4 ED14 ED8 ED10 ED12 CVDD VSS ED5 HOLD HINT/ GP[1] HRDY/ ACLKR[1] HCS/ AXR1[1] HAS/ ACLKX1 HDS/ AXR1[6] HDS2/ AXR1[5] HCNTL1/ AXR1[1] HCNTL0/ AXR1[3] HD6/ AHCLKR1 HD9/ GP[9] HD5/ AHCLKX1 HD12/ GP[12] HD14/ GP[14] HD15/ GP[15] HD13/ GP[13] HD11/ GP[11] HD10/ GP[10] HD8/ GP[8] HD7/ GP[3] HD4/ GP[0] HD2/ AFSX1 HD3/ AMUTE1 HD1/ AXR1[7] HHWIL/ AFSR[1] HD0/ AXR1[4] HR/ / AXR1[0] W HOLDA BUS REQ VSS VSS VSS VSS VSS DVDD CVDD CVDD VSS CVDD DVDD FSR0/ AFSR0 CLKR0/ ACLKR0 CLKX0/ ACLKX0 TOUT0/ AXR0[2] TOUT1/ AXR0[4] TINP0/ AXR0[3] TINP1/ AHCLKX0 FSX0/ AFSX0 VSS VSS VSS DVDD DVDD CVDD CVDD CVDD CVDD CVDD DVDD VSS VSS VSS VSS VSS VSSVSS EMU2 CLKIN CLK MODE0 PLLHV RSV RSV CVDD VSS TRST TCK TDI TMS CVDD CVDD CVDD CVDD CVDD CVDD DVDD DVDD DVDDDVDD RSV RSV RSV RSV VSS VSS VSS TD0 CVDD EMU1 EMU0 CLKOUT3 DVDD EMU3 CVDD VSS VSS VSS VSS VSS VSS VSS RSV EMU4 EMU5 NMI RESET DVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Shading□denotes□the□GDP□package□pin□functions□that□drop□out□on□the□PYP□package. SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

3 DEVICE INFORMATION

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table3-1.TerminalAssignments for272-BallGDP Package (inOrder ofBallNo.) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME A1 VSS C1 GP5/AMUTEIN0 A2 VSS C2 GP4/AMUTEIN1 A3 CLKIN C3 CV DD A4 CV DD C4 CLKMODE0 A5 RSV C5 PLLHV A6 TCK C6 VSS A7 TDI C7 CV DD A8 TDO C8 VSS A9 CV DD C9 VSS A10 CV DD C10 DV DD A11 VSS C11 EMU4 A12 RSV (connecteddirectlytoCV DD ) C12 RSV A13 RESET C13 NMI A14 VSS C14 HD14/GP[14] A15 HD13/GP[13] C15 HD12/GP[12] A16 HD11/GP[11] C16 HD9/GP[9] A17 DV DD C17 HD6/AHCLKR1 A18 HD7/GP[3] C18 CV DD A19 VSS C19 HD4/GP[0] A20 VSS C20 HD3/AMUTE1 B1 VSS D1 DV DD B2 CV DD D2 GP6 B3 DV DD D3 EMU2 B4 VSS D4 VSS B5 RSV D5 CV DD B6 TRST D6 CV DD B7 TMS D7 RSV B8 DV DD D8 VSS B9 EMU1 D9 EMU0 B10 EMU3 D10 CLKOUT3 B11 RSV (connecteddirectlytoVSS ) D11 CV DD B12 EMU5 D12 RSV B13 DV DD D13 VSS B14 HD15/GP[15] D14 CV DD B15 VSS D15 CV DD B16 HD10/GP[10] D16 DV DD B17 HD8/GP[8] D17 VSS B18 HD5/AHCLKX1 D18 HD2/AFSX1 B19 CV DD D19 DV DD B20 VSS D20 HD1/AXR1[7] E1 CLKS1/SCL1 J17 HOLD E2 VSS J18 HOLDA E3 GP[7]/(EXP_INT7) J19 BUSREQ E4 VSS J20 HINT/GP[1] E17 VSS K1 CV DD E18 HAS/ACLKX1 K2 VSS E19 HDS1/AXR1[6] K3 CLKS0/AHCLKR0 E20 HD0/AXR1[4] K4 CV DD F1 TOUT1/AXR0[4] K9 VSS F2 TINP1/AHCLKX0 K10 VSS

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table3-1.TerminalAssignments for272-BallGDP Package (inOrder ofBallNo.)(continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME F3 DV DD K11 VSS F4 CV DD K12 VSS F17 CV DD K17 CV DD F18 HDS2/AXR1[5] K18 ED0 F19 VSS K19 ED1 F20 HCS/AXR1[2] K20 VSS G1 TOUT0/AXR0[2] L1 FSX1 G2 TINP0/AXR0[3] L2 DX1/AXR0[5] G3 CLKX0/ACLKX0 L3 CLKX1/AMUTE0 G4 VSS L4 CV DD G17 VSS L9 VSS G18 HCNTL0/AXR1[3] L10 VSS G19 HCNTL1/AXR1[1] L11 VSS G20 HR/W/AXR1[0] L12 VSS H1 FSX0/AFSX0 L17 CV DD H2 DX0/AXR0[1] L18 ED2 H3 CLKR0/ACLKR0 L19 ED3 H4 VSS L20 CV DD H17 VSS M1 CLKR1/AXR0[6] H18 DV DD M2 DR1/SDA1 H19 HRDY/ACLKR1 M3 FSR1/AXR0[7] H20 HHWIL/AFSR1 M4 VSS J1 DR0/AXR0[0] M9 VSS J2 DV DD M10 VSS J3 FSR0/AFSR0 M11 VSS J4 VSS M12 VSS J9 VSS M17 VSS J10 VSS M18 DV DD J11 VSS M19 ED4 J12 VSS M20 ED5 N1 SCL0 U9 VSS N2 SDA0 U10 CV DD N3 ED31 U11 CV DD N4 VSS U12 DV DD N17 VSS U13 VSS N18 ED6 U14 CV DD N19 ED7 U15 CV DD N20 ED8 U16 DV DD P1 ED28 U17 VSS P2 ED29 U18 EA21 P3 ED30 U19 BE1 P4 VSS U20 VSS P17 VSS V1 ED20 P18 ED9 V2 ED19 P19 VSS V3 CV DD P20 ED10 V4 ED16 R1 DV DD V5 BE3 R2 ED27 V6 CE3 R3 ED26 V7 EA3 R4 CV DD V8 EA5 R17 CV DD V9 EA8 Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE INFORMATION 13 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table3-1.TerminalAssignments for272-BallGDP Package (inOrder ofBallNo.)(continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME R18 DV DD V10 EA10 R19 ED11 V11 ARE/SDCAS/ SSADS R20 ED12 V12 AWE/ SDWE/ SSWE T1 ED24 V13 DV DD T2 ED25 V14 EA17 T3 DV DD V15 DV DD T4 VSS V16 EA T17 VSS V17 CE0 T18 ED13 V18 CV DD T19 ED15 V19 DV DD T20 ED14 V20 BE0 U1 ED22 W1 VSS U2 ED21 W2 CV DD U3 ED23 W3 DV DD U4 VSS W4 ED17 U5 DV DD W5 VSS U6 CV DD W6 CE2 U7 DV DD W7 EA4 U8 VSS W8 EA6 W9 DV DD Y5 ARDY W10 AOE/ SDRAS/ SSOE Y6 EA2 W11 VSS Y7 DV DD W12 DV DD Y8 EA7 W13 EA11 Y9 EA9 W14 EA13 Y10 ECLKOUT W15 EA15 Y11 ECLKIN W16 VSS Y12 CLKOUT2/GP[2] W17 EA19 Y13 VSS W18 CE1 Y14 EA14 W19 CV DD Y15 EA16 W20 VSS Y16 EA18 Y1 VSS Y17 DV DD Y2 VSS Y18 EA20 Y3 ED18 Y19 VSS Y4 BE2 Y20 VSS

3.1 Description

The TMS320C67x ™ DSPs (includingthe SM320C6713 and SM320C6713B devices)compose the floating-pointDSP generationintheTMS320C6000 ™ DSP platform.The C6713 and C6713B devicesare based on the high-performance,advanced very-long-instruction-word(VLIW) architecturedevelopedby Texas Instruments(TI),making thisDSP an excellentchoice for multichanneland multifunction applications.Throughoutthe remainderof thisdocument, the SM320C6713 and SM320C6713B are referredtoas 320C67x or C67x or 13/13B where generic,and where specific,theirindividualfulldevice partnumbers areused orabbreviatedas C6713, C6713B, 13,or13B,and so forth. Operatingat 225 MHz, the C6713/13B deliversup to 1350 millionfloating-pointoperationsper second (MFLOPS), 1800 millioninstructionspersecond (MIPS),and withdualfixed-/floating-pointmultipliersup to 450 millionmultiply-accumulateoperationspersecond (MMACS). Operatingat 300 MHz, the C6713B deliversup to 1800 millionfloating-pointoperationsper second (MFLOPS), 2400 millioninstructionspersecond (MIPS),and withdualfixed-/floating-pointmultipliersup to 600 millionmultiply-accumulateoperationspersecond (MMACS).

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 The C6713/13B has a richperipheralsetthatincludestwo multichannelaudioserialports(McASPs),two multichannelbufferedserialports(McBSPs), two inter-integratedcircuit(I2C) buses, one dedicated general-purposeinput/output(GPIO) module,two general-purposetimers,a host-portinterface(HPI),and a gluelessexternalmemory interface(EMIF) capable of interfacingto SDRAM, SBSRAM, and asynchronousperipherals. The two McASP interfacemodules each supportone transmitand one receiveclockzone.Each ofthe McASPs has eightserialdatapinsthatcan be individuallyallocatedtoany ofthetwo zones.The serial portsupportstime-divisionmultiplexingon each pinfrom2 to32 timeslots.The C6713/13B has sufficient bandwidthtosupportall16 serialdatapinstransmittinga 192-kHz stereosignal.Serialdataineach zone may be transmittedand receivedon multipleserialdatapinssimultaneouslyand formattedina multitude ofvariationson thePhilipsInter-ICSound (I2S) format. Inaddition,theMcASP transmittermay be programmed tooutputmultipleS/PDIF,IEC60958,AES-3, and CP-430 encoded datachannelssimultaneously,witha singleRAM containingthefullimplementationof userdataand channelstatusfields. The McASP also providesextensiveerror-checkingand recoveryfeatures,such as the bad clock detectioncircuitforeach high-frequencymaster clock,which verifiesthatthe master clockiswithina programmed frequencyrange. The two I2C portson the 320C6713/13B allowthe DSP to easilycontrolperipheraldevicesand communicate witha hostprocessor.Inaddition,thestandardmultichannelbufferedserialport(McBSP) may be used tocommunicatewithserialperipheralinterface(SPI™ )mode peripheraldevices. The 320C6713/13B devicehas two bootmodes — fromtheHPI orfromexternalasynchronousROM. For more detailedinformation,see theBootmode sectionofthisdatasheet. The TMS320C67x DSP generationis supportedby the TI eXpressDSP ™ set of industrybenchmark developmenttools,includinga highlyoptimizingC/C++ Compiler,theCode Composer Studio™ Integrated Development Environment(IDE),JTAG-based emulationand real-timedebugging,and theDSP/BIOS ™ kernel. Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE INFORMATION 15 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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3.2 Device Characteristics

Table3-2providesan overviewoftheC6713/C6713B DSPs. The tableshows significantfeaturesofeach device,includingthecapacityofon-chipRAM, theperipherals,theexecutiontime,and thepackage type withpin count.For more detailson the C67x™ DSP devicepartnumbers and partnumbering,see Table6-1and Figure6-1. Table3-2.CharacteristicsoftheC6713 and C6713B Processor C6713/C6713B INTERNAL CLOCK (FLOATING-POINT DSPs)HARDWARE FEATURES SOURCE GDP EMIF SYSCLK3 orECLKIN 1 (32bit) EDMA CPU clockfrequency 1(16channels) Peripherals HPI (16bit) SYSCLK2 1Not allperipheralpinsareavailableatthe AUXCLK,same time.(Formore details,see the McASPs 2SYSCLK2 (1) DeviceConfigurationssection.) Peripheralperformanceisdependenton I2Cs SYSCLK2 2 chip-levelconfiguration. McBSPs SYSCLK2 2 32-bittimers ofSYSCLK2 2 GPIO module SYSCLK2 1 On-chipmemory Size(Bytes) 264K 4K-Byte(KB)L1 program(L1P)cache 4KB L1 data(L1D)cacheOrganization 64KB unifiedL2 cache/mapped RAM 192KB L2 mapped RAM CPU ID+CPU Rev ID ControlStatusRegister(CSR[31:16]) 0x0203 BSDL file FortheC6713/13B BSDL file,contactyourfieldsalesrepresentative. Frequency MHz 200 Time ns 5 ns Core (V) 1.26V (C6713/C6713B) Voltage I/O(V) 3.3V Prescaler /1,/2,/3,...,/32 Clockgeneratoroptions Multiplier ×4,×5,×6,...,×25 Postscaler /1,/2,/3,...,/32 Package 27 mm × 27 mm 272-ballBGA (GDP) Processtechnology μm 0.13 Productstatus(2) Productpreview(PP) PD (13)Advance information(AI) Productiondata(PD) (1) AUXCLK istheMcASP internalhigh-frequencyclocksourceforserialtransfers.SYSCLK2 istheMcASP systemclockused fortheclock check(high-frequency)circuit. (2) PRODUCT PREVIEW informationconcernsproductsintheformativeordesignphase ofdevelopment.Characteristicdataand other specificationsaredesigngoals.Texas Instrumentsreservestherighttochange ordiscontinuetheseproductswithoutnotice. ADVANCE INFORMATION concernsnew productsinthesamplingorpreproductionphase ofdevelopment.Characteristicdataand otherspecificationsaresubjecttochange withoutnotice. PRODUCTION DATA informationiscurrentas ofpublicationdate.ProductsconformtospecificationsperthetermsofTexas Instrumentsstandardwarranty.Productionprocessingdoes notnecessarilyincludetestingofallparameters.

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Data□Path B B□Register□File Instruction□Fetch Instruction□Dispatch Instruction□Decode Data□Path A A□Register□File Power-Down Logic .L1 (A) (A) (A) (A) (A) (A) L1P□Cache Direct□Mapped 4K□Bytes□Total Control Registers Control Logic L1D□Cache 2-Way Set□Associative 4K□Bytes In-Circuit Emulation Interrupt Control C6713/13B Digital□Signal□Processors Enhanced DMA Controller (16 channel) L2□Cache/ Memory 4□Banks 64K□Bytes T otal (up□to 4-Way) Clock□Generator□and□PLL x4□through□x25□Multiplier /1□through□/32□Dividers Memory 192K Bytes EMIF McASP1 McASP0 McBSP1 McBSP0 I2C1 I2C0 Timer□1 Timer□0 GPIO HPI Pin□Multiplexing NOTE□A: In□addition□to□fixed-point□instructions,□these□functional□units□execute□floating-point□instructions. EMIF□interfaces□to: McBSPs□interface□to: McASPs□interface□to: SDRAM/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 SPI□control□port I S□multichannel□ADC,□DAC,□codec,□DIR SBSRAM High-speed□TDM□codecs DIT :□□Multiple□outputs SRAM AC97□codecs ROM/flash□and Serial□EEPROM I/O□devices SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

3.3 FunctionalBlock and CPU (DSP Core)Diagram

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4 OVERVIEW

4.1 CPU (DSP Core)Description

The 320C6713/13B floating-pointdigitalsignalprocessorisbased on the C67x CPU. The CPU fetches advanced very-longinstructionwords (VLIW)(256bitswide)tosupplyup toeight32-bitinstructionstothe eightfunctionalunitsduringeveryclockcycle.The VLIW architecturefeaturescontrolsby whichalleight unitsdo nothave tobe suppliedwithinstructionsiftheyare notreadytoexecute.The firstbitofevery 32-bitinstructiondeterminesifthenextinstructionbelongstothesame executepacketas theprevious instruction,or whetheritshouldbe executedinthefollowingclockas a partofthenextexecutepacket. Fetch packets are always 256 bitswide; however, the execute packets can vary in size.The variable-lengthexecutepacketsarea key memory-savingfeature,distinguishingtheC67x CPU fromother VLIW architectures. The CPU featurestwo setsoffunctionalunits.Each setcontainsfourunitsand a registerfile.One set two registerfileseach contain16 32-bitregistersfora totalof32 general-purposeregisters.The two sets offunctionalunits,alongwithtwo registerfiles,compose sidesA and B oftheCPU (seetheFunctional Blockand CPU (DSP Core)Diagram and Figure4-1).The fourfunctionalunitson each sideoftheCPU can freelysharethe16 registersbelongingtothatside.Additionally,each sidefeaturesa singledatabus connectedtoalltheregisterson theotherside,by whichthetwo setsoffunctionalunitscan accessdata fromtheregisterfileson theoppositeside.Whileregisteraccessby functionalunitson thesame sideof the CPU as the registerfilecan serviceallthe unitsina singleclockcycle,registeraccess usingthe registerfileacrosstheCPU supportsone readand one writepercycle. The C67x CPU executesallC62x instructions.InadditiontoC62x fixed-pointinstructions,thesixoutof remainingtwo functionalunits(.D1and .D2)alsoexecutethenew LDDW instruction,whichloads64 bits perCPU sidefora totalof128 bitspercycle. Anotherkey featureof the C67x CPU isthe load/storearchitecture,where allinstructionsoperateon registers(as opposed to data in memory). Two sets of data-addressingunits(.D1 and .D2) are responsibleforalldatatransfersbetween theregisterfilesand thememory. The dataaddressdrivenby the.D unitsallowsdataaddressesgeneratedfromone registerfiletobe used toloadorstoredatatoor from theotherregisterfile.The C67x CPU supportsa varietyofindirectaddressingmodes usingeither linear-orcircular-addressingmodes with5-or15-bitoffsets.Allinstructionsareconditional,and most can access any one of the 32 registers.Some registers,however, are singledout to supportspecific addressingor toholdtheconditionforconditionalinstructions(iftheconditionisnotautomaticallytrue). The two .M functionalunitsare dedicatedformultiplies.The two .S and .L functionalunitsperforma generalsetofarithmetic,logical,and branchfunctionswithresultsavailableeveryclockcycle. The processingflowbegins when a 256-bit-wideinstructionfetchpacket is fetchedfrom a program memory. The 32-bitinstructionsdestinedfortheindividualfunctionalunitsare chainedtogetherby 1 bits intheleastsignificantbit(LSB)positionoftheinstructions.The instructionsthatarechainedtogetherfor simultaneousexecution(uptoeightintotal)compose an executepacket.A 0 intheLSB ofan instruction breaksthechain,effectivelyplacingtheinstructionsthatfollowitinthenextexecutepacket.Ifan execute packetcrossesthefetch-packetboundary(256bitswide),theassemblerplacesitinthenextfetchpacket, whiletheremainderofthecurrentfetchpacketispadded withNOP instructions.The number ofexecute packetswithina fetchpacket can vary from one to eight.Execute packetsare dispatchedto their respectivefunctionalunitsat the rateof one per clockcycleand the next 256-bitfetchpacketisnot fetcheduntilalltheexecutepacketsfromthecurrentfetchpackethave been dispatched.Afterdecoding, the instructionssimultaneouslydriveallactivefunctionalunitsfora maximum executionrateof eight instructionseveryclockcycle.Whilemost resultsarestoredin32-bitregisters,theycan be subsequently moved tomemory as bytesor half-wordsas well.Allloadand storeinstructionsare byte,half-word,or word addressable.

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long□dst long□dst dst dst dst dst dst dst dst src2 src2 src2 src2 src2 src2 src2 long□src long□src long□dst long□dst long□src .L2 .S2 .M2 .D2 .D1 .M1 .S1 .L1 Control Register□File DA1 DA2 ST1 LD1□32□LSB LD2□32□LSB LD2□32□MSB Data□Path□A Data□Path□B Register File□A (A0−A15) Register File□B (B0−B15) LD1□32□MSB ST2 (A) (A) (A) (A) (A) (A) SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 A. Inadditiontofixed-pointinstructions,thesefunctionalunitsexecutefloating-pointinstructions. Figure4-1.320C67x ™ CPU (DSP Core)Data Paths

4.2 Memory Map Summary

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table4-1.320C6713/13B Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE InternalRAM (L2) 192K 0000 0000 0002 FFFF InternalRAM/Cache 64K 0003 0000 0003 FFFF Reserved 24M – 256K 0004 0000 017F FFFF ExternalMemory Interface(EMIF)Registers 256K 0180 0000 0183 FFFF L2 Registers 128K 0184 0000 0185 FFFF Reserved 128K 0186 0000 0187 FFFF HPI Registers 256K 0188 0000 018B FFFF McBSP 0 Registers 256K 018C 0000 018F FFFF McBSP 1 Registers 256K 0190 0000 0193 FFFF Timer0 Registers 256K 0194 0000 0197 FFFF Timer1 Registers 256K 0198 0000 019B FFFF InterruptSelectorRegisters 512 019C 0000 019C 01FF DeviceConfigurationRegisters 4 019C 0200 019C 0203 Reserved 256K − 516 019C 0204 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 01A3 FFFF Reserved 768K 01A4 0000 01AF FFFF GPIO Registers 16K 01B0 0000 01B0 3FFF Reserved 240K 01B0 4000 01B3 FFFF I2C0 Registers 16K 01B4 0000 01B4 3FFF I2C1 Registers 16K 01B4 4000 01B4 7FFF Reserved 16K 01B4 8000 01B4 BFFF McASP0 Registers 16K 01B4 C000 01B4 FFFF McASP1 Registers 16K 01B5 0000 01B5 3FFF Reserved 160K 01B5 4000 01B7 BFFF PLL Registers 8K 01B7 C000 01B7 DFFF Reserved 264K 01B7 E000 01BB FFFF EmulationRegisters 256K 01BC 0000 01BF FFFF Reserved 4M 01C0 0000 01FF FFFF QDMA Registers 52 0200 0000 0200 0033 Reserved 16M − 52 0200 0034 02FF FFFF Reserved 720M 0300 0000 2FFF FFFF McBSP0 Data Port 64M 3000 0000 33FF FFFF McBSP1 Data Port 64M 3400 0000 37FF FFFF Reserved 64M 3800 0000 3BFF FFFF McASP0 Data Port 1M 3C00 0000 3C0F FFFF McASP1 Data Port 1M 3C10 0000 3C1F FFFF Reserved 1G + 62M 3C20 0000 7FFF FFFF EMIF CE0 (1) 256M 8000 0000 8FFF FFFF EMIF CE1 (1) 256M 9000 0000 9FFF FFFF EMIF CE2 (1) 256M A000 0000 AFFF FFFF EMIF CE3 (1) 256M B000 0000 BFFF FFFF Reserved 1G C000 0000 FFFF FFFF (1) The number ofEMIF addresspins(EA[21:2])limitsthemaximum addressablememory (SDRAM) to128MB perCE space.

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0x0000□0000 011010001 111 0x0003□0000 000 L2□Mode L2□Memory Block□□Base Address 0x0003□C000 0x0003□8000 0x0003□4000 0x0003□FFFF 16K1-WayCache 32K 2-Way□Cache48K□3-W ay□Cache 64K□4-W ay□Cache 256K□SRAM□(All) 240K□SRAM 224K□SRAM 208K□SRAM 192K□SRAM 192K-Byte□RAM 16K-Byte□RAM 16K-Byte□RAM 16K-Byte□RAM 16K-Byte□RAM SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

4.3 L2 Memory StructureExpanded

Figure4-2shows thedetailoftheL2 memory structure. Figure4-2.L2 Memory Configuration Copyright© 2003–2009,Texas InstrumentsIncorporated OVERVIEW 21 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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4.4 PeripheralRegisterDescriptions

Table 4-2 throughTable 4-15 identifythe peripheralregistersforthe C6713/C6713B devicesby their registernames, acronyms,and hex addressor hex addressrange.For more detailedinformationon the registercontentsand bitnames and theirrespectivedescriptions,see the specificperipheralreference guide listedin the TMS320C6000 DSP PeripheralsOverview Reference Guide (literaturenumber SPRU190 ). Table4-2.EMIF Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 GBLCTL EMIF globalcontrol 0180 0004 CECTL1 EMIF CE1 space control 0180 0008 CECTL0 EMIF CE0 space control 0180 000C — Reserved 0180 0010 CECTL2 EMIF CE2 space control 0180 0014 CECTL3 EMIF CE3 space control 0180 0018 SDCTL EMIF SDRAM control 0180 001C SDTIM EMIF SDRAM refreshcontrol 0180 0020 SDEXT EMIF SDRAM extension 0180 0024−0183 FFFF — Reserved

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table4-3.L2 Cache Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 CCFG Cache configuration 0184 4000 L2WBAR L2 writebackbase addressregister 0184 4004 L2WWC L2 writebackword count 0184 4010 L2WIBAR L2 writeback-invalidatebase addressregister 0184 4014 L2WIWC L2 writeback-invalidateword count 0184 4020 L1PIBAR L1P invalidatebase addressregister 0184 4024 L1PIWC L1P invalidateword count 0184 4030 L1DWIBAR L1D writeback-invalidatebase addressregister 0184 4034 L1DWIWC L1D writeback-invalidateword count 0184 5000 L2WB L2 writebackall 0184 5004 L2WBINV L2 writeback-invalidateall 0184 8200 MAR0 Memory attributeregister0.ControlsCE0 range8000 0000 80FF FFFF 0184 8204 MAR1 Memory attributeregister1.ControlsCE0 range8100 0000 81FF FFFF 0184 8208 MAR2 Memory attributeregister2.ControlsCE0 range8200 0000 82FF FFFF 0184 820C MAR3 Memory attributeregister3.ControlsCE0 range8300 0000 83FF FFFF 0184 8240 MAR4 Memory attributeregister4.ControlsCE1 range9000 0000 90FF FFFF 0184 8244 MAR5 Memory attributeregister5.ControlsCE1 range9100 0000 91FF FFFF 0184 8248 MAR6 Memory attributeregister6.ControlsCE1 range9200 0000 92FF FFFF 0184 824C MAR7 Memory attributeregister7.ControlsCE1 range9300 0000 93FF FFFF 0184 8280 MAR8 Memory attributeregister8.ControlsCE2 rangeA000 0000 A0FF FFFF 0184 8284 MAR9 Memory attributeregister9.ControlsCE2 rangeA100 0000 A1FF FFFF 0184 8288 MAR10 Memory attributeregister10.ControlsCE2 rangeA200 0000 A2FF FFFF 0184 828C MAR11 Memory attributeregister11.ControlsCE2 rangeA300 0000 A3FF FFFF 0184 82C0 MAR12 Memory attributeregister12.ControlsCE3 rangeB000 0000 B0FF FFFF 0184 82C4 MAR13 Memory attributeregister13.ControlsCE3 rangeB100 0000 B1FF FFFF 0184 82C8 MAR14 Memory attributeregister14.ControlsCE3 rangeB200 0000 B2FF FFFF 0184 82CC MAR15 Memory attributeregister15.ControlsCE3 rangeB300 0000 B3FF FFFF 0184 82D0 −0185 FFFF — Reserved Table4-4.InterruptSelectorRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS SelectswhichinterruptsdriveCPU interrupts019C 0000 MUXH Interruptmultiplexerhigh 10–15 (INT10−INT15) SelectswhichinterruptsdriveCPU interrupts019C 0004 MUXL Interruptmultiplexerlow 4−9 (INT04−INT09) Setsthepolarityoftheexternalinterrupts019C 0008 EXTPOL Externalinterruptpolarity (EXT_INT4−EXT_INT7) 019C 000C −019F FFFF — Reserved Copyright© 2003–2009,Texas InstrumentsIncorporated OVERVIEW 23 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

Word□0 EDMA□Channel□Options□Parameter□(OPT) OPT Word□1 EDMA□Channel□Source□Address□(SRC) SRC Word□2 Array/Frame□Count□(FRMCNT) Element□Count□(ELECNT) CNT Word□3 EDMA□Channel□Destination□Address□(DST) DST Word□4 Array/Frame□Index□(FRMIDX) Element□Index□(ELEIDX) IDX Word□5 Element□Count□Reload□(ELERLD) Link□Address□(LINK) RLD SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table4-5.Device Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Allowstheusertocontrolperipheral selection.Thisregisteralsoofferstheuser controloftheEMIF inputclocksource.For019C 0200 DEVCFG Deviceconfiguration more detailedinformationon thedevice configurationregister,see theDevice Configurationssectionofthisdatasheet. 019C 0204−019F FFFF — Reserved IdentifieswhichCPU and definesthesilicon revisionoftheCPU. Thisregisteralsooffers theusercontrolofdeviceoperation.FormoreN/A CSR CPU controlstatusregister detailedinformationon theCPU Control StatusRegister,see theCPU CSR Register descriptionsectionofthisdatasheet. Table4-6.EDMA Parameter RAM (1) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0000 01A0 0017 — ParametersforEvent0 (6words)orReload/Linkparametersforotherevent 01A0 0018 01A0 002F — ParametersforEvent1 (6words)orReload/Linkparametersforotherevent 01A0 0030 01A0 0047 — ParametersforEvent2 (6words)orReload/Linkparametersforotherevent 01A0 0048 01A0 005F — ParametersforEvent3 (6words)orReload/Linkparametersforotherevent 01A0 0060 01A0 0077 — ParametersforEvent4 (6words)orReload/Linkparametersforotherevent 01A0 0078 01A0 008F — ParametersforEvent5 (6words)orReload/Linkparametersforotherevent 01A0 0090 01A0 00A7 — ParametersforEvent6 (6words)orReload/Linkparametersforotherevent 01A0 00A8 01A0 00BF — ParametersforEvent7 (6words)orReload/Linkparametersforotherevent 01A0 00C0 01A0 00D7 — ParametersforEvent8 (6words)orReload/Linkparametersforotherevent 01A0 00D8 01A0 00EF — ParametersforEvent9 (6words)orReload/Linkparametersforotherevent 01A0 00F0 01A0 00107 — ParametersforEvent10 (6words)orReload/Linkparametersforotherevent 01A0 0108 01A0 011F — ParametersforEvent11 (6words)orReload/Linkparametersforotherevent 01A0 0120 01A0 0137 — ParametersforEvent12 (6words)orReload/Linkparametersforotherevent 01A0 0138 01A0 014F — ParametersforEvent13 (6words)orReload/Linkparametersforotherevent 01A0 0150 01A0 0167 — ParametersforEvent14 (6words)orReload/Linkparametersforotherevent 01A0 0168 01A0 017F — ParametersforEvent15 (6words)orReload/Linkparametersforotherevent 01A0 0180 01A0 0197 — Reload/linkparametersforEvent0−15 01A0 0198 01A0 01AF — Reload/linkparametersforEvent0−15 01A0 07E0 01A0 07F7 — Reload/linkparametersforEvent0−15 01A0 07F8 01A0 07FF — Scratchpad area(twowords) (1) The C6713/13B devicehas 85 EDMA parameterstotal:16 Event/Reloadparametersand 69 Reload-onlyparameters. Formore detailson theEDMA parameterRAM six-wordparameterentrystructure,see Figure4-3. Figure4-3.EDMA Channel Parameter Entries(SixWords) forEach EDMA Event

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table4-7.EDMA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0800−01A0 FEFC — Reserved 01A0 FF00 ESEL0 EDMA eventselector0 01A0 FF04 ESEL1 EDMA eventselector1 01A0 FF08−01A0 FF0B — Reserved 01A0 FF0C ESEL3 EDMA eventselector3 01A0 FF1F −01A0 FFDC — Reserved 01A0 FFE0 PQSR Priorityqueue statusregister 01A0 FFE4 CIPR Channelinterruptpendingregister 01A0 FFE8 CIER Channelinterruptenableregister 01A0 FFEC CCER Channelchainenableregister 01A0 FFF0 ER Eventregister 01A0 FFF4 EER Eventenableregister 01A0 FFF8 ECR Eventclearregister 01A0 FFFC ESR Eventsetregister 01A1 0000−01A3 FFFF — Reserved Table4-8.Quick DMA (QDMA) and Pseudo Registers(1) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0200 0000 QOPT QDMA optionsparameter 0200 0004 QSRC QDMA sourceaddress 0200 0008 QCNT QDMA framecount 0200 000C QDST QDMA destinationaddress 0200 0010 QIDX QDMA index 0200 0014−0200 001C — Reserved 0200 0020 QSOPT QDMA pseudo options 0200 0024 QSSRC QDMA pseudo sourceaddress 0200 0028 QSCNT QDMA pseudo framecount 0200 002C QSDST QDMA pseudo destinationaddress 0200 0030 QSIDX QDMA pseudo index (1) AlltheQDMA and Pseudo registersarewriteaccessibleonly. Table4-9.PLL ControllerRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C000 PLLPID Peripheralidentification (C6713/13Bvalue:0x00010801 forPLL Controller) 01B7 C004 −01B7 C0FF — Reserved 01B7 C100 PLLCSR PLL control/statusregister 01B7 C104 −01B7 C10F — Reserved 01B7 C110 PLLM PLL multipliercontrol 01B7 C114 PLLDIV0 PLL controllerdivider0 01B7 C118 PLLDIV1 PLL controllerdivider1 01B7 C11C PLLDIV2 PLL controllerdivider2 01B7 C120 PLLDIV3 PLL controllerdivider3 Copyright© 2003–2009,Texas InstrumentsIncorporated OVERVIEW 25 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table4-9.PLL ControllerRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C124 OSCDIV1 Oscillatordivider1 01B7 C128 −01B7 DFFF — Reserved Table4-10.McASP0 and McASP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME AND DESCRIPTION McASP0 McASP1 McASPx receivebufferorMcASPx transmitbufferviatheperipheral 3C00 0000−3C00 FFFF 3C10 0000−3C10 FFFF RBUF/XBUFx databus.Used when RSEL orXSEL bits= 0 (thesebitsarelocated intheRFMT orXFMT registers,respectively). Peripheralidentification01B4 C000 01B5 0000 MCASPPIDx [13/13Bvalue:0x00100101 forMcASP0 and forMcASP1] 01B4 C004 01B5 0004 PWRDEMUx Power down and emulationmanagement 01B4 C008 01B5 0008 — Reserved 01B4 C00C 01B5 000C — Reserved 01B4 C010 01B5 0010 PFUNCx Pinfunction 01B4 C014 01B5 0014 PDIRx Pindirection 01B4 C018 01B5 0018 PDOUTx Pindataout Pindatain/dataset 01B4 C01C 01B5 001C PDIN/PDSETx Read returns:PDIN Writesaffect:PDSET 01B4 C020 01B5 0020 PDCLRx Pindataclear 01B4 C024 −01B4 C040 01B5 0024−01B5 0040 — Reserved 01B4 C044 01B5 0044 GBLCTLx Globalcontrol 01B4 C048 01B5 0048 AMUTEx Mute control 01B4 C04C 01B5 004C DLBCTLx Digitalloopbackcontrol 01B4 C050 01B5 0050 DITCTLx DIT mode control 01B4 C054 −01B4 C05C 01B5 0054−01B5 005C — Reserved AliasofGBLCTL containingonlyReceiverResetbits;allows01B4 C060 01B5 0060 RGBLCTLx transmittobe resetindependentlyfromreceive 01B4 C064 01B5 0064 RMASKx Receiverformatunitbitmask 01B4 C068 01B5 0068 RFMTx Receivebitstreamformat 01B4 C06C 01B5 006C AFSRCTLx Receiveframesynccontrol 01B4 C070 01B5 0070 ACLKRCTLx Receiveclockcontrol 01B4 C074 01B5 0074 AHCLKRCTLx High-frequencyreceiveclockcontrol 01B4 C078 01B5 0078 RTDMx ReceiveTDM slot0−31 01B4 C07C 01B5 007C RINTCTLx Receiverinterruptcontrol 01B4 C080 01B5 0080 RSTATx Status− receiver 01B4 C084 01B5 0084 RSLOTx CurrentreceiveTDM slot 01B4 C088 01B5 0088 RCLKCHKx Receiverclockcheckcontrol 01B4 C08C −01B4 C09C 01B5 008C −01B5 009C — Reserved AliasofGBLCTL containingonlyTransmitterResetbits;allows01B4 C0A0 01B5 00A0 XGBLCTLx transmittobe resetindependentlyfromreceive 01B4 C0A4 01B5 00A4 XMASKx Transmitformatunitbitmask 01B4 C0A8 01B5 00A8 XFMTx Transmitbitstreamformat 01B4 C0AC 01B5 00AC AFSXCTLx Transmitframesynccontrol 01B4 C0B0 01B5 00B0 ACLKXCTLx Transmitclockcontrol 01B4 C0B4 01B5 00B4 AHCLKXCTLx High-frequencyTransmitclockcontrol 01B4 C0B8 01B5 00B8 XTDMx TransmitTDM slot0−31 01B4 C0BC 01B5 00BC XINTCTLx Transmitinterruptcontrol 01B4 C0C0 01B5 00C0 XSTATx Status− transmitter 01B4 C0C4 01B5 00C4 XSLOTx CurrenttransmitTDM slot 01B4 C0C8 01B5 00C8 XCLKCHKx Transmitclockcheckcontrol

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table4-10.McASP0 and McASP1 Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME AND DESCRIPTION McASP0 McASP1 01B4 C0D0 −01B4 C0FC 01B5 00CC −01B5 00FC — Reserved 01B4 C100 01B5 0100 DITCSRA0x Left(evenTDM slot)channelstatusregisterfile 01B4 C104 01B5 0104 DITCSRA1x Left(evenTDM slot)channelstatusregisterfile 01B4 C108 01B5 0108 DITCSRA2x Left(evenTDM slot)channelstatusregisterfile 01B4 C10C 01B5 0108 DITCSRA3x Left(evenTDM slot)channelstatusregisterfile 01B4 C110 01B5 0110 DITCSRA4x Left(evenTDM slot)channelstatusregisterfile 01B4 C114 01B5 0114 DITCSRA5x Left(evenTDM slot)channelstatusregisterfile 01B4 C118 01B5 0118 DITCSRB0x Right(oddTDM slot)channelstatusregisterfile 01B4 C11C 01B5 011C DITCSRB1x Right(oddTDM slot)channelstatusregisterfile 01B4 C120 01B5 0120 DITCSRB2x Right(oddTDM slot)channelstatusregisterfile 01B4 C124 01B5 0124 DITCSRB3x Right(oddTDM slot)channelstatusregisterfile 01B4 C128 01B5 0128 DITCSRB4x Right(oddTDM slot)channelstatusregisterfile 01B4 C12C 01B5 012C DITCSRB5x Right(oddTDM slot)channelstatusregisterfile 01B4 C130 01B5 0130 DITUDRA0x Left(evenTDM slot)userdataregisterfile 01B4 C134 01B5 0134 DITUDRA1x Left(evenTDM slot)userdataregisterfile 01B4 C138 01B5 0138 DITUDRA2x Left(evenTDM slot)userdataregisterfile 01B4 C13C 01B5 013C DITUDRA3x Left(evenTDM slot)userdataregisterfile 01B4 C140 01B5 0140 DITUDRA4x Left(evenTDM slot)userdataregisterfile 01B4 C144 01B5 0144 DITUDRA5x Left(evenTDM slot)userdataregisterfile 01B4 C148 01B5 0148 DITUDRB0x Right(oddTDM slot)userdataregisterfile 01B4 C14C 01B5 014C DITUDRB1x Right(oddTDM slot)userdataregisterfile 01B4 C150 01B5 0150 DITUDRB2x Right(oddTDM slot)userdataregisterfile 01B4 C154 01B5 0154 DITUDRB3x Right(oddTDM slot)userdataregisterfile 01B4 C158 01B5 0158 DITUDRB4x Right(oddTDM slot)userdataregisterfile 01B4 C15C 01B5 015C DITUDRB5x Right(oddTDM slot)userdataregisterfile 01B4 C160 −01B4 C17C 01B5 0160−01B5 017C — Reserved 01B4 C180 01B5 0180 SRCTL0x Serializer0 control 01B4 C184 01B5 0184 SRCTL1x Serializer1 control 01B4 C188 01B5 0188 SRCTL2x Serializer2 control 01B4 C18C 01B5 018C SRCTL3x Serializer3 control 01B4 C190 01B5 0190 SRCTL4x Serializer4 control 01B4 C194 01B5 0194 SRCTL5x Serializer5 control 01B4 C198 01B5 0198 SRCTL6x Serializer6 control 01B4 C19C 01B5 019C SRCTL7x Serializer7 control 01B4 C1A0 −01B4 C1FC 01B5 01A0−01B5 01FC — Reserved 01B4 C200 01B5 0200 XBUF0x Transmitbufferforserializer0 throughconfigurationbus(1) 01B4 C204 01B5 0204 XBUF1x Transmitbufferforserializer1 throughconfigurationbus(1) 01B4 C208 01B5 0208 XBUF2x Transmitbufferforserializer2 throughconfigurationbus(1) 01B4 C20C 01B5 020C XBUF3x Transmitbufferforserializer3 throughconfigurationbus(1) 01B4 C210 01B5 0210 XBUF4x Transmitbufferforserializer4 throughconfigurationbus(1) 01B4 C214 01B5 0214 XBUF5x Transmitbufferforserializer5 throughconfigurationbus(1) 01B4 C218 01B5 0218 XBUF6x Transmitbufferforserializer6 throughconfigurationbus(1) 01B4 C21C 01B5 021C XBUF7x Transmitbufferforserializer7 throughconfigurationbus(1) 01B4 C220 −01B4 C27C 01B5 C220 −01B5 027C — Reserved 01B4 C280 01B5 0280 RBUF0x Receivebufferforserializer0 throughconfigurationbus(2) 01B4 C284 01B5 0284 RBUF1x Receivebufferforserializer1 throughconfigurationbus(2) 01B4 C288 01B5 0288 RBUF2x Receivebufferforserializer2 throughconfigurationbus(2) 01B4 C28C 01B5 028C RBUF3x Receivebufferforserializer3 throughconfigurationbus(2) (1) The transmitbuffersforserializers0−7 areaccessibletotheCPU viatheperipheralbus iftheXSEL bit= 1 (XFMT register). (2) The receivebuffersforserializers0−7 areaccessibletotheCPU viatheperipheralbus iftheRSEL bit= 1 (RFMT register). Copyright© 2003–2009,Texas InstrumentsIncorporated OVERVIEW 27 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table4-10.McASP0 and McASP1 Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME AND DESCRIPTION McASP0 McASP1 01B4 C290 01B5 0290 RBUF4x Receivebufferforserializer4 throughconfigurationbus(2) 01B4 C294 01B5 0294 RBUF5x Receivebufferforserializer5 throughconfigurationbus(2) 01B4 C298 01B5 0298 RBUF5x Receivebufferforserializer6 throughconfigurationbus(2) 01B4 C29C 01B5 029C RBUF7x Receivebufferforserializer7 throughconfigurationbus(2) 01B4 C2A0 −01B4 FFFF 01B5 02A0−01B5 3FFF — Reserved Table4-11.I2C0 and I2C1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME AND DESCRIPTION I2C0 I2C1 01B4 0000 01B4 4000 I2COARx I2Cxown addressregister 01B4 0004 01B4 4004 I2CIERx I2Cxinterruptenableregister 01B4 0008 01B4 4008 I2CSTRx I2Cxinterruptstatusregister 01B4 000C 01B4 400C I2CCLKLx I2Cxclocklow-timedivider 01B4 0010 01B4 4010 I2CCLKHx I2Cxclockhigh-timedivider 01B4 0014 01B4 4014 I2CCNTx I2Cxdatacount 01B4 0018 01B4 4018 I2CDRRx I2Cxdatareceiveregister 01B4 001C 01B4 401C I2CSARx I2Cxslaveaddressregister 01B4 0020 01B4 4020 I2CDXRx I2Cxdatatransmitregister 01B4 0024 01B4 4024 I2CMDRx I2Cxmode register 01B4 0028 01B4 4028 I2CISRCx I2Cxinterruptsource 01B4 002C 01B4 402C — Reserved 01B4 0030 01B4 4030 I2CPSCx I2Cxprescaler I2CPID10 I2Cxperipheralidentification101B4 0034 01B4 4034 I2CPID11 (C6713/13Bvalue:0x0000 0103) I2CPID20 I2Cxperipheralidentification201B4 0038 01B4 4038 I2CPID21 (C6713/13Bvalue:0x0000 0005) 01B4 003C −01B4 3FFF 01B4 403C −01B4 7FFF — Reserved Table4-12.HPI Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS — HPID HPI dataregister Hostread/writeaccessonly — HPIA HPI addressregister Hostread/writeaccessonly 0188 0000 HPIC HPI controlregister BothHost/CPU read/writeaccess 0188 0004−018B FFFF — Reserved Table4-13.Timer 0 and Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS TIMER 0 TIMER 1 Determinestheoperatingmode ofthe 0194 0000 0198 0000 CTLx Timerx controlregister timer,monitorsthetimerstatus,and controlsthefunctionoftheTOUT pin. Containsthenumber oftimerinput 0194 0004 0198 0004 PRDx Timerx periodregister clockcyclestocount.Thisnumber controlstheTSTAT signalfrequency. Containsthecurrentvalueofthe0194 0008 0198 0008 CNTx Timerx counterregister incrementingcounter. 0194 000C −0197 FFFF 0198 000C −019B FFFF — Reserved

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table4-14.McBSP0 and McBSP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME AND DESCRIPTION McBSP0 McBSP1 McBSPx datareceiveregisterviaconfigurationbus. 018C 0000 0190 0000 DRRx The CPU and EDMA controllercan onlyreadthisregister;they cannotwritetoit. 3000 0000−33FF FFFF 3400 0000−37FF FFFF DRRx McBSPx datareceiveregisterviaperipheraldatabus 018C 0004 0190 0004 DXRx McBSPx datatransmitregisterviaconfigurationbus 3000 0000−33FF FFFF 3400 0000−37FF FFFF DXRx McBSPx datatransmitregisterviaperipheraldatabus 018C 0008 0190 0008 SPCRx McBSPx serialportcontrolregister 018C 000C 0190 000C RCRx McBSPx receivecontrolregister 018C 0010 0190 0010 XCRx McBSPx transmitcontrolregister 018C 0014 0190 0014 SRGRx McBSPx sample rategeneratorregister 018C 0018 0190 0018 MCRx McBSPx multichannelcontrolregister 018C 001C 0190 001C RCERx McBSPx receivechannelenableregister 018C 0020 0190 0020 XCERx McBSPx transmitchannelenableregister 018C 0024 0190 0024 PCRx McBSPx pincontrolregister 018C 0028−018F FFFF 0190 0028−0193 FFFF — Reserved Table4-15.GPIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B0 0000 GPEN GPIO enable 01B0 0004 GPDIR GPIO direction 01B0 0008 GPVAL GPIO value 01B0 000C — Reserved 01B0 0010 GPDH GPIO deltahigh 01B0 0014 GPHM GPIO highmask 01B0 0018 GPDL GPIO deltalow 01B0 001C GPLM GPIO lowmask 01B0 0020 GPGC GPIO globalcontrol 01B0 0024 GPPOL GPIO interruptpolarity 01B0 0028−01B0 3FFF — Reserved Copyright© 2003–2009,Texas InstrumentsIncorporated OVERVIEW 29 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

GP7 IEEE Standard 1149.1 (JTAG) Emulation Reset□and Interrupts Control/Status TDI TDO TMS TCK EMU0 EMU1 NMI GP6 GP5/AMUTEIN0 GP4/AMUTEIN1 RESET Clock/PLL Oscillator CLKIN CLKMODE0 PLLHV CLKOUT2/GP[2] EMU2 EMU3 EMU4 EMU5 HHWIL/AFSR1 HCNTL0/AXR1[3] HCNTL1/AXR1[1] Data Register□Select Half-Word Select Control HPI (Host-Port□Interface) HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1] HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[1 1] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4] CLKOUT3 HD4/GP[0] (A) (A) (A) (A) (B) (B) (B) (B) (B) (C) (C) (C) (C) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com

4.5 SignalGroups Description

A. These externalpinsareapplicabletotheGDP package only. B. The GP[15:0]pins,throughinterruptsharing,are externalinterruptcapableviaGPINT0. For more details,see the externalinterruptsourcessectionof thisdata sheet.For more detailson interruptsharing,see theTMS320C6000 DSP InterruptSelectorReferenceGuide (literaturenumber SPRU646 ). C. Allofthesepinsare externalinterruptsources.For more detailssee theExternalInterruptSources sectionofthis datasheet. D. On multiplexedpins,boldfacetextdenotestheactivefunctionofthepinforthatparticularperipheralmodule. Figure4-4.CPU (DSP Core)and PeripheralSignals

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General-Purpose Input/Output□(GPIO)□Port GP7 GP6 GP5/AMUTEIN0 GP4/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT /GP[1] HD4/GP[0] GPIO HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD1 1/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] TOUT1/AXR0[4] TOUT0/AXR0[2]Timer 1 Timer 0 Timers TINP1/AHCLKX0 TINP0/AXR0[3] CLKS1/SCL1 SCL0I2C1 I2C0 I Cs DR1/SDA1 SDA0 (A) SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 A. The GP[15:0}pins,throughinterruptsharing,are externalinterruptcapableviaGPINT0. GP[15:0]are alsoexternal EDMA eventsourcecapable.Formore details,see theExternalInterruptSourcesand ExternalEDMA EventSources sectionsofthisdatasheet. B. On multiplexedpins,boldfacetextdenotestheactivefunctionofthepinforthatparticularperipheralmodule. Figure4-5.PeripheralSignals Copyright© 2003–2009,Texas InstrumentsIncorporated OVERVIEW 31 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

ECLKOUTED[31:16] CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 CLKX1/AMUTE0 FSX1 DX1/AXR0[5] CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1 CLKS1/SCL1 AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1] CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0] CLKS0/AHCLKR0 Data Memory Map Space□Select Address Byte□Enables Memory Control EMIF (External□Memory□Interface) Receive Receive McBSP1 McBSP0 Transmit Transmit Clock Clock McBSPs (Multichannel□Buffered□Serial□Ports) ECLKIN HOLD HOLDA BUSREQ Bus Arbitration ARE/SDCAS/SSADS ED[15:0] (A) (A) (A) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com A. These externalpinsareapplicabletotheGDP package only. B. On multiplexedpins,boldfacetextdenotestheactivefunctionofthepinforthatparticularperipheralmodule. Figure4-6.PeripheralSignals

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(Multichannel Audio□Serial□Port□0) CLKX0/ACLKX0 CLKS0/AHCLKR0 Transmit Clock Generator GP5/AMUTEIN0 Auto□Mute Logic CLKX1/AMUTE0 FSX0/AFSX0Transmit Frame□SyncFSR0/AFSR0 Receive Frame□Sync CLKR0/ACLKR0 TINP1/AHCLKX0 Receive□Clock Generator TOUT1/AXR0[4] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0] DX1/AXR0[5] TINP0/AXR0[3] CLKR1/AXR0[6] FSR1/AXR0[7] 8-Serial□Ports Flexible Partitioning Tx,□Rx,□OFF Transmit Clock□Check Circuit Receive□Clock Check□Circuit Error□Detect (see□Note□A) (Transmit/Receive□Data□Pins) (Receive□Bit□Clock) (Transmit□Bit□Clock) (Receive□Master□Clock) (Transmit□Master□Clock) (Receive□Frame□Sync□or Left/Right□□Clock) (Transmit□Frame□Sync□or Left/Right□□Clock) SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 A. The McASP ErrorDetectfunctiondetectsunderruns,overruns,early/lateframesyncs,DMA errors,and externalmute input. B. On multiplexedpins,boldfacetextdenotestheactivefunctionofthepinforthatparticularperipheralmodule. C. Boldfaceand italicizedtextwithinparenthesesdenotesthefunctionofthepinsinan audiosystem. Figure4-7.PeripheralSignals Copyright© 2003–2009,Texas InstrumentsIncorporated OVERVIEW 33 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

HD0/AXR1[4] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0] McASP1 (Multichannel Audio□Serial□Port□1) HDS2/AXR1[5] HAS/ACLKX1 HD5/AHCLKX1 Transmit Clock Generator HCNTL0/AXR1[3] GP4/AMUTEIN1 Auto□Mute Logic HD3/AMUTE1 HD2/AFSX1Transmit Frame□SyncHHWIL/AFSR1 Receive Frame□Sync HDS1/AXR1[6] HD1/AXR1[7] HRDY/ACLKR1 HD6/AHCLKR1 Receive□Clock Generator 8-Serial□Ports Flexible Partitioning Tx,□Rx,□OFF Transmit Clock□Check Circuit Receive□Clock Check□Circuit Error□Detect (see□Note□A) (Transmit/Receive□Data□Pins) (Receive□Bit□Clock) (Transmit□Bit□Clock) (Receive□Master□Clock) (Transmit□Master□Clock) (Receive□Frame□Sync□or Left/Right□□Clock) (Transmit□Frame□Sync□or Left/Right□□Clock) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com A. The McASP ErrorDetectfunctiondetectsunderruns,overruns,early/lateframesyncs,DMA errors,and externalmute input. B. On multiplexedpins,boldfacetextdenotestheactivefunctionofthepinforthatparticularperipheralmodule. C. Boldfaceand italicizedtextwithinparenthesesdenotesthefunctionofthepinsinan audiosystem. Figure4-8.PeripheralSignals

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5 DEVICE CONFIGURATIONS

On the C6713/13B devices,bootmode and certaindevice configurations/peripheralselectionsare determined at device reset, while other device configurations/peripheralselections are software-configurableviathe deviceconfigurationsregister(DEVCFG) [addresslocation0x019C0200] afterdevicereset.

5.1 Device ConfigurationsatDevice Reset

Table 5-1 describesthe C6713 and C6713B deviceconfigurationpins,which are setup viainternalor externalpullup/pulldownresistorsthroughthe HPI data pins (HD[4:3],HD8, HD12 [13B only]),and CLKMODE0 pin.These configurationpinsmust be inthedesiredstateuntilresetisreleased.For proper deviceoperation,do notoppose theHD [13,11:9,7,1,0]pinswithexternalpullups/pulldownsatreset. For more detailson thesedeviceconfigurationpins,see theTerminalFunctionstableand theDebugging Considerationssectionofthisdatasheet. Table5-1.Device ConfigurationsPins atDevice Reset (HD[4:3],HD8, HD12 [13B only],and CLKMODE0) (1) CONFIGURATION GDP FUNCTIONAL DESCRIPTIONPIN EMIF BigEndianmode correctness(EMIFBE) [C6713B only] Fora C6713BGDP : 0 – The EMIF datawillalwaysbe presentedon theED[7:0]sideofthebus,regardlessofthe endianessmode (Little/BigEndian). 1 – InLittleEndianmode (HD8 = 1),the8-bitor16-bitEMIF datawillbe presenton the ED[7:0]sideofthebus. InBigEndianmode (HD8 = 0),the8-bitor16-bitEMIF datawillbe presenton the HD12 (2) C15 ED[31:24]sideofthebus [default]. Fora C6713BPYP, when BigEndianmode isselected(LENDIAN = 0),forproperdeviceoperationthe EMIFBE pinmust be externallypulledlow. Thisenhancement isnot supportedon theC6713 device. ForproperC6713 deviceoperation,do not oppose theinternalpullup(IPU)resistoron thispin. Thisnew functionalitydoes not affectsystemsusingthecurrentdefaultvalueofHD12 = 1.Formore detailedinformationon thebigendianmode correctness,see theEMIF BigEndianMode Correctness [C6713B only]portionofthisdatasheet. DeviceEndianmode (LEND) HD8 B17 0 – System operatesinBigEndianmode 1 – System operatesinLittleEndianmode (default) Bootmode Configurationpins(BOOTMODE) 00 – HPI boot/Emulationboot 01 – CE1 width8-bit,asynchronousexternalROM bootwithdefaulttimings(defaultmode) HD[4:3] C19, C20 10 – CE1 width16-bit,asynchronousexternalROM bootwithdefaulttimings(BOOTMODE) (2) 11 – CE1 width32-bit,asynchronousexternalROM bootwithdefaulttimings Formore detailedinformationon thesebootmode configurations,see theBootmode sectionofthis datasheet. Clockgeneratorinputclocksourceselect 0 – Reserved.Do notuse. CLKMODE0 C4 1 – CLKIN squarewave [default] Thispinmust be pulledtothecorrectleveleven afterreset. (1) AllotherHD pinsHD [15,13:9,7:5,2:0orHD 15,13,11:9,7:5,2:0]have pullups/pulldowns(IPUsorIPDs).For properdeviceoperationoftheHD 15,13:9,7,1,0orHD 13,11:9,7,1,0,do not oppose thesepinswithexternal pullups/pulldownsatreset;however,theHD6,5,2orHD15,6,5,2 pinscan be opposed and drivenduringreset. (2) IPD = Internalpulldown,IPU = Internalpullup.To oppose thesupplyrailon theseIPD/IPUsignalpins,use externalpulluporpulldown resistorsno greaterthan4.4kΩ and 2.0kΩ,respectively. Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE CONFIGURATIONS 35 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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5.2 PeripheralPin SelectionatDevice Reset

Some C6713/13B peripheralssharethesame pins(internallyMUXed) and aremutuallyexclusive(thatis, HPI,general-purposeinput/outputpinsGP[15:8,3,1,0],and McASP1).

HPI,McASP1, and GPIO peripherals The HPI_EN (HD14 pin)islatchedatreset.ThispinselectswhethertheHPI peripheralpinsor McASP1 peripheralpinsand GP[15:8,3,1,0]pinsarefunctionallyenabled(seeTable5-2). Table5-2.HPI_EN (HD14 Pin)PeripheralSelection(HPIor McASP1, and SelectGPIO Pins)(1) PERIPHERAL PERIPHERAL PIN SELECTION PINS SELECTED

DESCRIPTION

HPI_EN McASP1 andHPI(HD14 Pin)[173,C14] GP[15:8,3,1,0] HPI_EN = 0 HPI pinsaredisabled;McASP1 peripheralpinsand GP[15:8,3,1,0]pins 0 ü areenabled.AllmultiplexedHPI/McASP1 and HPI/GPIO pinsfunctionas McASP1 and GPIO pins,respectively.To use theGPIO pins,the appropriatebitsintheGPEN and GPDIR registersneed tobe configured. HPI_EN = 1 HPI pinsareenabled;McASP1 peripheralpinsand GP[15:8,3,1,0]pins1 ü aredisabled[default].AllmultiplexedHPI/McASP1 and HPI/GPIO pins functionas HPI pins. (1) The HPI_EN (HD[14])pincannot be controlledviasoftware.

5.3 PeripheralSelection/DeviceConfigurationsViatheDEVCFG ControlRegister

The deviceconfigurationregister(DEVCFG) allowstheusertocontrolthepinavailabilityoftheMcBSP0, McBSP1, McASP0, I2C1,and timerperipherals.The DEVCFG registeralsoofferstheusercontrolofthe EMIF inputclocksourceand thetimeroutputpins.For more detailedinformationon theDEVCFG register controlbits,see Table5-3and Table5-4. Table5-3.Device ConfigurationRegister(DEVCFG) [Address Location:0x019C0200 −0x019C02FF] 31 16 Reserved(1) R/W-0 15 5 4 3 2 1 0 Reserved(1) EKSRC TOUT1SEL TOUT0SEL MCBSP0DIS MCBSP1DIS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write,--n= valueatreset (1) Do not writenon-zerovaluestothesebitlocations.

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table5-4.Device ConfigurationRegister(DEVCFG) SelectionBitDescriptions BIT NO. NAME DESCRIPTION 31:5 Reserved Reserved.Do not writenon-zerovaluestothesebitlocations. EMIF inputclocksourcebit. Determineswhichclocksignalisused as theEMIF inputclock. 4 EKSRC 0 = SYSCLK3 (fromtheclockgenerator)istheEMIF inputclocksource(default). 1 = ECLKIN externalpinistheEMIF inputclocksource. Timer1 output(TOUT1) pinfunctionselectbit. SelectsthepinfunctionoftheTOUT1/AXR0[4] externalpinindependentoftherestoftheperipheral selectionbitsintheDEVCFG register. 3 TOUT1SEL 0 = The pinfunctionsas a Timer1 output(TOUT1) pin(default). 1 = The pinfunctionsas theMcASP0 transmit/receivedatapin4 (AXR0[4]).The Timer1 module isstillactive. Timer0 output(TOUT0) pinfunctionselectbit. SelectsthepinfunctionoftheTOUT0/AXR0[2] externalpinindependentoftherestoftheperipheral selectionbitsintheDEVCFG register. 2 TOUT0SEL 0 = The pinfunctionsas a Timer0 output(TOUT0) pin(default). 1 = The pinfunctionsas theMcASP0 transmit/receivedatapin2 (AXR0[2]).The Timer0 module isstillactive. MultichannelBufferedSerialPort0 (McBSP0) disablebit. SelectswhetherMcBSP0 ortheMcASP0 multiplexedperipheralpinsareenabledordisabled. 0 = McBSP0 peripheralpinsareenabled,McASP0 peripheralpins(AHCLKR0, ACLKR0, 1 MCBSP0DIS ACLKX0, AXR0[0],AXR0[1],AFSR0, and AFSX0) aredisabled(default). IftheMcASP0 datapinsareavailable,theMcASP0 peripheralisfunctionalforDIT mode only. 1 = McBSP0 peripheralpinsaredisabled,McASP0 peripheralpins(AHCLKR0, ACLKR0, ACLKX0, AXR0[0],AXR0[1],AFSR0, and AFSX0) areenabled. MultichannelBufferedSerialPort1 (McBSP1) disablebit. SelectswhetherMcBSP1 orI2C1 and McASP0 multiplexedperipheralpinsareenabledordisabled. 0 = McBSP1 peripheralpinsareenabled,I2C1 peripheralpins(SCL1 and SDA1) and McASP00 MCBSP1DIS peripheralpins(AXR0[7:5]and AMUTE0) aredisabled(default) 1 = McBSP1 peripheralpinsaredisabled,I2C1 peripheralpins(SCL1 and SDA1) and McASP0 peripheralpins(AXR0[7:5]and AMUTE0) areenabled.

5.4 MultiplexedPins

Multiplexed(MUXed) pins are pins thatare shared by more than one peripheraland are internally multiplexed.Most of these pins are configuredby softwarevia the device configurationregister (DEVCFG), and theothers(specifically,theHPI pins)areconfiguredby externalpullup/pulldownresistors only at reset.The MUXed pins that are configuredby softwarecan be programmed to switch functionalitiesatany time.The MUXed pinsthatare configuredby externalpullup/pulldownresistorsare mutuallyexclusive;only one peripheralhas primarycontrolof the functionof these pins afterreset. Table 5-5 summarizes the peripheralpinsaffectedby the HPI_EN (HD14 pin)and DEVCFG register. Table5-6 identifiesthemultiplexedpinson theC6713/13B devices,shows thedefault(primary)function and the defaultsettingsafterreset,and describesthe pins,registers,etc.,necessaryto configurethe specificmultiplexedfunctions. Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE CONFIGURATIONS 37 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table5-5.PeripheralPin SelectionMatrix(1) SELECTION BITS PERIPHERAL PIN AVAILABILITY BIT BIT GPIOMCASP0 (2) MCASP1 MCBSP0 MCBSP1 TIMER0 TIMER1 HPI EMIFI2C0 I2C1NAME VAL PINS AHCLKX1 AHCLKR1 GP[0:1], ACLKX1 GP[3], ACLKR1 GP[8:15]HPI_EN AFSX1 abc(bootconfig 0 NoneAFSR1 Plus:pin) AMUTE1 GP[2] AXR1[0] ctrl’d by to GP2EN bit AXR1[7] NOHPI_EN GP[0:1],(bootconfig 1 None All GP[3],pin) GP[8:15]

0 None All

S (DEVCFG AFSR01 Nonebit) AHCLKR AXR0[0] AXR0[1] NO AMUTE0

0 AXR0[5] None All

AXR0[6]MCBSP1DI AXR0[7]S (DEVCFG bit) AMUTE0 AXR0[5]1 All NoneAXR0[6] AXR0[7] NO0 TOUT0TOUT0SEL AXR0[2] (DEVCFG NObit) 1 AXR0[2] TOUT0 NO TOUT10TOUT1SEL AXR0[4] (DEVCFG NObit) 1 AXR0[4] TOUT1 HD12 (boot ED[7:0}sideconfigpin) [HD8 = 1 (Little)][13BGDP] (3)

1 ED[31:24]side

[HD8 = 0 (Big)] (1) Gray blocksindicatethattheperipheralisnotaffectedby theselectionbit. (2) The McASP0 pins,AXR0[3]and AHCLKX0, aresharedwiththetimerinputpins,TINP0 and TINP1,respectively.See Table5-6for more detailedinformation. (3) Formore detailedinformationon endiannesscorrection,see theEMIF BigEndianMode Correctness[C6713B only]sectionofthisdata sheet. Table5-6.C6713/13B Device Multiplexed/SharedPins MULTIPLEXED PIN DEFAULT NAME GDP FUNCTION DEFAULT SETTING DESCRIPTION GP2EN = 0 (GPEN registerbit) When theCLKOUT2 pinisenabled,theCLK2EN bitinthe GP[2]functiondisabled,CLKOUT2 EMIF globalcontrolregister(GBLCTL) controlsthe enabled CLKOUT2 pin.CLKOUT2/GP[2] Y12 CLKOUT2 CLK2EN = 0: CLKOUT2 heldhigh CLK2EN = 1: CLKOUT2 enabledtoclock[default].

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table5-6.C6713/13B Device Multiplexed/SharedPins (continued) MULTIPLEXED PIN DEFAULT NAME GDP FUNCTION DEFAULT SETTING DESCRIPTION No Function To use thesesoftware-configurableGPIO pins,the GPxDIR = 0 (input) GPxEN bitsintheGP EnableRegisterand theGPxDIR GP5EN = 0 (disabled) bitsintheGP DirectionRegistermust be properly GP4EN = 0 (disabled) configured. [(GPEN registerbits) GPxEN = 1: GP[x]pinenabled.GP5/AMUTEIN GP[x]functiondisabled]0 C1 GP5 GPxDIR = 0: GP[x]pinisan input.GP4/AMUTEIN C2 GP4 1 GPxDIR = 1: GP[x]pinisan output. To use AMUTEIN0/1 pinfunction,theGP[5]/GP[4]pins must be configuredas an input,theINEN bitsetto1,and thepolaritythroughtheINPOL bitselectedinthe associatedMcASP AMUTE register. CLKS0/AHCLKR0 K3 By default,McBSP0 peripheralpinsareenabledupon reset(McASP0 pinsaredisabled).DR0/AXR0[0] J1 abc To enabletheMcASP0 peripheralpins,theMCBSP0DISDX0/AXR0[1] H2 MCBSP0DIS = 0 bitintheDEVCFG registermust be setto1 (disablingthe(DEVCFG registerbit)FSR0/AFSR0 J3 McBSP0 pinfunction McBSP0 peripheralpins).McASP0 pinsdisabled, McBSP0 pinsenabledFSX0/AFSX0 H1 CLKR0/ACLKR0 H3 CLKX0/ACLKX0 G3 CLKS1/SCL1 E1 By default,McBSP1 peripheralpinsareenableduponDR1/SDA1 M2 MCBSP1DIS = 0 reset(I2C1and McASP0 pinsaredisabled). DX1/AXR0[5] L2 (DEVCFG registerbit) abcMcBSP1 pinfunction I2C1 and McASP0 pins To enabletheI2C1 and McASP0 peripheralpins,theFSR1/AXR0[7] M3 disabled,McBSP1 pinsenabled MCBSP1DIS bitintheDEVCFG registermust be setto1 CLKR1/AXR0[6] M1 (disablingtheMcBSP1 peripheralpins). CLKX1/AMUTE0 L3 HINT/GP[1] J20 HD15/GP[15] B14 HD14/GP[14] C14 HD13/GP[13] A15 By default,theHPI peripheralpinsareenabledatreset.HD12/GP[12] C15 McASP1 peripheralpinsand elevenGPIO pinsare HD11/GP[11] A16 disabled. HD10/GP[10] B16 HD9/GP[9] C16 To enabletheMcASP1 peripheralpinsand theeleven HD8/GP[8] B17 GPIO pins,an externalpulldownresistormust be provided on theHD14 pinsettingHPI_EN = 0 atreset.HD7/GP[3] A18 HD4/GP[0] C19 HD1/AXR1[7] D20 GP enableregisterand theGPxDIR bitsintheGP HPI_EN (HD14 pin)= 1 directionregistermust be properlyconfigured.To useHD0/AXR1[4] E20 HPI (HPIenabled) thesesoftware-configurableGPIO pins,theGPxEN bitsin pinfunction McASP1 pinsand 11 GPIO pins theHCNTL1/AXR1[1] G19 aredisabled. HCNTL0/AXR1[3] G18 GPxEN = 1: GP[x]pinenabled. HR/W/AXR1[0] G20 GPxDIR = 0: GP[x]pinisan input. HDS1/AXR1[6] E19 GPxDIR = 1: GP[x]pinisan output. HDS2/AXR1[5] F18 HCS/AXR1[2] F20 McASP1 pindirectioniscontrolledby thePDIR[x]bitsin theMcASP1PDIR register.HD6/AHCLKR1 C17 HD5/AHCLKX1 B18 HD3/AMUTE1 C20 HD2/AFSX1 D18 HHWIL/AFSR1 H20 HRDY/ACLKR1 H19 HAS/ACLKX1 E18 Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE CONFIGURATIONS 39 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table5-6.C6713/13B Device Multiplexed/SharedPins (continued) MULTIPLEXED PIN DEFAULT NAME GDP FUNCTION DEFAULT SETTING DESCRIPTION By default,theTimer0 inputpinisenabled(anda shared Timer0 McASP0PDIR = 0 (input) inputuntiltheMcASP0 peripheralforcesan output).TINP0/AXR0[3] G2 inputfunction [specificallyAXR0[3]bit] abc McASP0PDIR = 0 input,= 1 output By default,theTimer0 outputpinisenabled. abc To enabletheMcASP0 AXR0[2]pin,theTOUT0SEL bitin theDEVCFG registermust be setto1 (disablingtheTOUT0SEL = 0 (DEVCFG registerTimer0 Timer0 peripheraloutputpinfunction).TOUT0/AXR0[2] G1 bit)[TOUT0 pinenabledandoutputfunction abcMcASP0 AXR0[2]pindisabled] The AXR2 bitintheMcASP0PDIR registercontrolsthe direction(input/output)oftheAXR0[2]pin. McASP0PDIR = 0 input,= 1 output By default,theTimer1 inputand McASP0 clockfunction areenabledas inputs.Timer1 McASP0PDIR = 0 (input)TINP1/AHCLKX0 F2 abcinputfunction [specificallyAHCLKX bit] FortheMcASP0 clocktofunctionas an output: McASP0PDIR = 1 (specificallytheAHCLKX bit). By default,theTimer1 outputpinisenabled. abc To enabletheMcASP0 AXR0[4]pin,theTOUT1SEL bitin theDEVCFG registermust be setto1 (disablingtheTOUT1SEL = 0 (DEVCFG registerTimer1 Timer1 peripheraloutputpinfunction).TOUT1/AXR0[4] F1 bit)[TOUT1 pinenabledandoutputfunction abcMcASP0 AXR0[4]pindisabled] The AXR4 bitintheMcASP0PDIR registercontrolsthe direction(input/output)oftheAXR0[4]pin. McASP0PDIR = 0 input,= 1 output

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ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 SCL0,□SDA0 DEVCFG□Register□Value: 0x0000□000F MCBSP0DIS□= 1 MCBSP1DIS□= 1 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . SCL1,□SDA1 AXR0[7:0] {TINP0/AXR0[3]} AXR1[7:0] AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0,□AFSR0, AFSX0 SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

5.5 ConfigurationExamples

Figure5-1 throughFigure5-6 illustrateexamples of peripheralselectionsthatare configurableon this device. Figure5-1.ConfigurationExample A (Two I2C + Two McASP + GPIO) Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE CONFIGURATIONS 41 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 SCL0,□SDA0 AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 DEVCFG□Register□Value: 0x0000□000E MCBSP0DIS□= 1 MCBSP1DIS□= 0 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . DR1,□CLKS1, CLKR1,□CLKX1, FSR1,□DX1, FSX1 AXR1[7:0] AXR0[4:0] {TINP0/AXR0[3]} TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0,□AFSR0, AFSX0 SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure5-2.ConfigurationExample B (One I2C + One McBSP + Two McASP + GPIO)

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ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 SCL1,□SDA1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 (DIT□Mode) SCL0,□SDA0 AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 DEVCFG□Register□Value: 0x0000□000D MCBSP0DIS□= 0 MCBSP1DIS□= 1 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . DR0,□CLKS0, CLKR0,□CLKX0, FSR0,□DX0, FSX0 AXR1[7:0] AXR0[7:2] {TINP0/AXR0[3]} AMUTE0, TINP1/AHCLKX0 SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure5-3.ConfigurationExample C [2I2C + 1 McBSP + 1 McASP + 1 McASP (DIT)+ GPIO] Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE CONFIGURATIONS 43 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1DR1,□CLKS1, CLKR1,□CLKX1, FSR1,□DX1, FSX1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset I2C0 GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP[0], GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 GP[15:8,□3:1] McASP0 (DIT□Mode) SCL0,□SDA0 AFSX1,□AFSR1,□ACLKX1, ACLKR1,□AHCLKR1, AHCLKX1,□AMUTE1 DEVCFG□Register□Value: 0x0000□000C MCBSP0DIS□= 0 MCBSP1DIS□= 0 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□0 GP2EN□BIT□=□1□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . DR0,□CLKS0, CLKR0,□CLKX0, FSR0,□DX0, FSX0 AXR1[7:0] AXR0[4:2] {TINP0/AXR0[3]} TINP1/AHCLKX0 TOUT0/AXR0[2] TOUT1/AXR0[4] SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure5-4.ConfigurationExample D [1I2C + 2 McBSP + 1 McASP + 1 McASP (DIT)+ GPIO + Timers]

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ED□[31:16], ED[15:0] CE[3:0],□□BE[3:0], HOLDA,□HOLD, BUSREQ,□ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 SCL1,□SDA1 McBSP0 TIMER1 TIMER0 Clock, System, EMU,□and Reset GPIO and EXT_INT McASP1 CLKIN,□CLKOUT3,□CLKMODE0, PLLHV,□TMS,□TDO,□TDI,□TCK, TRST ,□EMU[5:3,1,0],□RESET, NMI GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 McASP0 AXR0[7:0], {TINP0/AXR0[3]} DEVCFG□Register□Value: 0x0000□000F MCBSP0DIS□= 1 MCBSP1DIS□= 1 TOUT0SEL□=□1 TOUT1SEL□=□1 EKSRC□=□0 HPI_EN(HD14)□=□1 GP2EN□BIT□=□0□(enabling□GPEN.[2]) EA[21:2] Shading□denotes□a□peripheral□module□not□available□for□this□configuration . CLKOUT2 HD[15:0] HINT,□HHWIL, HRDY,□HR/W, HCNTRL1, HCNTRL0,□HCS, HDS2,□HDS1, HAS I2C0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0,□AFSR0, AFSX0 SCL0,□SDA0 SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure5-5.ConfigurationExample E (1I2C + HPI + 1 McASP) Copyright© 2003–2009,Texas InstrumentsIncorporated DEVICE CONFIGURATIONS 45 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

ED [31:16], ED[15:0] HOLDA, HOLD, BUSREQ, ECLKIN , ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY HPI I2C1 McBSP1 McBSP0 TIMER1 TIMER0 Clock, System , EMU, and Reset GPIO and EXT_INT McASP1 CLKIN, CLKOUT3, CLKMODE0 , PLLHV, TMS, TDO, TDI, TCK, TRST , EMU[5:3,1,0], RESET, NMI GP4/AMUTEIN1, GP5/AMUTEIN0, GP6, GP7 McASP0 DEVCFG Register V alue: 0x0000 000E MCBSP0DIS = 1 MCBSP1DIS = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (enabling GPEN.[2]) EA[21:2] Shading denotes a peripheral module not available for this configuration . DR1, CLKS1, CLKR1, CLKX1 , FSR1, DX1, FSX1 CLKOUT2 HD[15:0] HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS AXR0[4:0] {TINP0/AXR0[3]} I2C0 TINP1/AHCLKX0, AHCLKR0 , ACLKR0 , ACLKX0, AFSR0 , AFSX0 SCL0, SDA0 SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure5-6.ConfigurationExample F (One McBSP + HPI + One McASP)

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5.6 Debugging Considerations

Itisrecommended thatexternalconnectionsbe providedtoperipheralselection/deviceconfigurationpins, includingHD[14, 8,12 (for13B only),4,3],and CLKMODE0. Althoughinternalpullupresistorsexiston thesepins,providingexternalconnectivityadds convenienceto the user indebuggingand flexibilityin switchingoperatingmodes. Internalpullup/pulldownresistorsalsoexiston the non−configurationpinson the HPI data bus (HD15, 13:9,7:5,2:0and HD15,13,11:9,7:5,2:0).For properdeviceoperationoftheHD15, 13:9,7,1,0orHD13,11:9,7,1,0,do notoppose theinternalpullup/pulldownresistors on thesenon-configurationpinswithexternalpullup/pulldownresistorsat reset.Ifan externalcontroller providessignalstotheseHD15,13:9,7,1,0orHD13,11:9,7,1,0 non-configuration pins,thesesignalsmust be driventothedefaultstateofthepinsatreset,ornotbe drivenatall.For the listof routedout,3-stated,or not-drivenpinsrecommended forexternalpullup/pulldownresistors,and internalpullup/pulldownresistorsforalldevicespins,etc.,see TerminalFunctions.However,theHD6,5, 2orHD15,6,5,2 non-configurationpinscan be opposed and drivenduringreset. Fortheinternalpullup/pulldownresistorsforalldevicepins,see theTerminalFunctionstable.

6 TERMINAL FUNCTIONS

The TerminalFunctionstableidentifiestheexternalsignalnames, theassociatedpin(ball)numbers along withthemechanicalpackage designator,thepintype(I,O/Z,or I/O/Z),whetherthepinhas any internal pullup/pulldownresistorsand a functionalpin description.For more detailedinformationon device configuration,peripheralselection,multiplexed/sharedpins,and debuggingconsiderations,see theDevice Configurationssectionofthisdatasheet. Copyright© 2003–2009,Texas InstrumentsIncorporated TERMINAL FUNCTIONS 47 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com TERMINAL FUNCTIONS PIN IPD/IPUNO.SIGNAL NAME TYPE (1) DESCRIPTION(2) GDP CLOCK/PLL CONFIGURATION CLKIN A3 I IPD Clockinput Clockoutputathalfofdevicespeed (O/Z)[default](SYSCLK2 internalsignalfromtheclockgenerator)orthispincan be programmedCLKOUT2/GP[2] Y12 O/Z IPD as GP[2]pin(I/O/Z). CLKOUT3 D10 O IPD Clockoutputprogrammableby OSCDIV1 registerinthePLL controller Clockgeneratorinputclocksourceselect 0:Reserved,do notuse CLKMODE0 C4 I IPU 1:CLKIN squarewave [default] Forproperdeviceoperation,thispinmust be eitherleftunconnectedorexternallypulledup witha 1-kΩ resistor. PLLHV C5 A (3) Analogpower (3.3V) forPLL (PLL filter) JTAG EMULATION TMS B7 I IPU JTAG test-portmode select TDO A8 O/Z IPU JTAG test-portdataout TDI A7 I IPU JTAG test-portdatain TCK A6 I IPU JTAG test-portclock JTAG test-portreset.ForIEEE Std1149.1JTAG compatibility,see theIEEE 1149.1JTAG CompatibilityStatementsectionofthisdataTRST B6 I IPD sheet. EMU5 B12 I/O/Z IPU Emulationpin5.Reservedforfutureuse,leaveunconnected. EMU4 C11 I/O/Z IPU Emulationpin4.Reservedforfutureuse,leaveunconnected. EMU3 B10 I/O/Z IPU Emulationpin3.Reservedforfutureuse,leaveunconnected. EMU2 D3 I/O/Z IPU Emulationpin2.Reservedforfutureuse,leaveunconnected. Emulation[1:0]

Selectthedevicefunctionalmode ofoperation Operation:EMU[1:0]:

00 BoundaryScan/FunctionalMode (seenote)

01 Reserved

EMU1 B9 10 ReservedI/O/Z IPUEMU0 D9 11 Emulation/FunctionalMode [default](seetheIEEE 1149.1JTAG CompatibilityStatementofthisdata sheet) The DSP can be placedinFunctionalmode when theEMU[1:0]pinsareconfiguredforeitherboundaryscan oremulation. Note:When theEMU[1:0]pinsareconfiguredforboundaryscan mode, theinternalpulldown(IPD)on theTRST signalmust notbe opposed tooperateinfunctionalmode. Fortheboundaryscan mode, driveEMU[1:0]and RESET pinslow. RESETS AND INTERRUPTS RESET A13 I — Devicereset.When usingboundaryscan mode, drivetheEMU[1:0]and RESET pinslow. Nonmaskable interrupt NMI C13 I IPD

Edge-driven(risingedge) GP7 E3 General-purposeinput/outputpins(I/O/Z),whichalsofunctionas externalinterrupts
Edge-drivenGP6 D2
Polarityindependentlyselectedviatheexternalinterruptpolarityregisterbits(EXTPOL.[3:0]),inadditiontotheGPIO registers. I/O/Z IPUGP5/ C1AMUTEIN0 GP[4]and GP[5]pinsalsofunctionas AMUTEIN1 McASP1 mute inputand AMUTEIN0 McASP0 mute input,respectively,ifenabledby theINEN bitintheassociatedMcASP AMUTE register.GP4/ C2AMUTEIN1 HOST-PORT INTERFACE (HPI) HINT/GP[1] J20 O/Z IPU Hostinterrupt(fromDSP tohost)(O )[default]orthispincan be programmed as a GP[1]pin(I/O/Z) HCNTL1/AXR1[1] G19 I IPU Hostcontrol:Selectsbetween control,address,ordataregisters(I)[default]orMcASP1 datapin1 (I/O/Z) HCNTL0/AXR1[3] G18 I IPU Hostcontrol:Selectsbetween control,address,ordataregisters(I)[default]orMcASP1 datapin3 (I/O/Z) Hosthalf-wordselect:Firstorsecond half-word(notnecessarilyhighorloworder)(I)[default]orMcASP1 receiveframesyncHHWIL/AFSR1 H20 I IPU orleft/rightclock(LRCLK) (I/O/Z). HR/W/AXR1[0] G20 I IPU Hostreadorwriteselect(I)[default]orMcASP1 datapin0 (I/O/Z) (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground (2) IPD = Internalpulldown,IPU = Internalpullup.[TheseIPD/IPUsignalpinsfeaturea 13-kΩ resistor(approximate)fortheIPD or18-kΩ resistor(approximate)fortheIPU.An externalpulluporpulldownresistorno greaterthan4.4kΩ and 2.0kΩ,respectively,shouldbe used topulla signaltotheoppositesupplyrail.] (3) A = Analogsignal

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 TERMINAL FUNCTIONS (continued) PIN IPD/IPUNO.SIGNAL NAME TYPE (1) DESCRIPTION(2) GDP Host-portdatapins(I/O/Z)[default]orgeneral-purposeinput/outputpins(I/O/Z)

Used fortransferofdata,address,and control
AlsocontrolsinitializationofDSP modes atresetviapullup/pulldownresistors – DeviceEndianmode (HD8) 0:BigEndian 1:LittleEndianHD15/GP[15] B14 HD14/GP[14] C14 – Bootmode (HD[4:3])HD13/GP[13] A15 HD12/GP[12] C15 00:HPI boot/emulationboot HD11/GP[11] A16 I/O/Z IPU 01:CE1 width8-bit,asynchronousexternalROM bootwithdefaulttimings(defaultmode)HD10/GP[10] B16 HD9/GP[9] C16 10:CE1 width16-bit,asynchronousexternalROM bootwithdefaulttimings HD8/GP[8] B17 11:CE1 width32-bit,asynchronousexternalROM bootwithdefaulttimingsHD7/GP[3] A18 – HPI_EN (HD14) 0:HPI disabled,McASP1 enabled 1:HPI enabled,McASP1 disabled(default) OtherHD pins(HD [15,13:9,7:5,2:0]have pullups/pulldowns(IPUs/IPDs).Forproperdeviceoperation,do not oppose thesepins withexternalpullups/pulldownsatreset;however,theHD[15,6,5,2]pinscan be opposed and drivenatreset.Formore details,see theDeviceConfigurationssectionofthisdatasheet. HD6/AHCLKR1 C17 I/O/Z IPU Host-portdatapin6 (I/O/Z)[default]orMcASP1 receivehigh-frequencymasterclock(I/O/Z) HD5/AHCLKX1 B18 I/O/Z IPU Host-portdatapin5 (I/O/Z)[default]orMcASP1 transmithigh-frequencymasterclock(I/O/Z) HD4/GP[0] C19 I/O/Z IPD Host-portdatapin4 (I/O/Z)[default]orthispincan be programmed as a GP[0]pin(I/O/Z) HD3/AMUTE1 C20 I/O/Z IPU Host-portdatapin3 (I/O/Z)[default]orMcASP1 mute output(O/Z) HD2/AFSX1 D18 I/O/Z IPU Host-portdatapin2 (I/O/Z)[default]orMcASP1 transmitframesyncorleft/rightclock(LRCLK) (I/O/Z) HD1/AXR1[7] D20 I/O/Z IPU Host-portdatapin1 (I/O/Z)[default]orMcASP1 datapin7 (I/O/Z) HD0/AXR1[4] E20 I/O/Z IPU Host-portdatapin0 (I/O/Z)[default]orMcASP1 datapin4 (I/O/Z) HAS/ACLKX1 E18 I IPU Hostaddressstrobe(I)[default]orMcASP1 transmitbitclock(I/O/Z) HCS/AXR1[2] F20 I IPU Hostchipselect(I)[default]orMcASP1 datapin2 (I/O/Z) HDS1/AXR1[6] E19 I IPU Hostdatastrobe1 (I)[default]orMcASP1 datapin6 (I/O/Z) HDS2/AXR1[5] F18 I IPU Hostdatastrobe2 (I)[default]orMcASP1 datapin5 (I/O/Z) HRDY/ACLKR1 H19 O/Z IPD Hostready(fromDSP tohost)(O )[default]orMcASP1 receivebitclock(I/O/Z) EMIF — COMMON SIGNALS TO ALL TYPES OF MEMORY (4) CE3 V6 Memory space enablesCE2 W6 O/Z IPU • Enabledby bits28 through31 oftheword address CE1 W18 • Onlyone assertedduringany externaldataaccess CE0 V17 BE3 V5 Byte-enablecontrol BE2 Y4 • Decoded fromthetwo lowestbitsoftheinternaladdressO/Z IPU • Byte-writeenablesformost typesofmemoryBE1 U19
Can be directlyconnectedtoSDRAM readand writemask signal(SDQM)BE0 V20 EMIF — BUS ARBITRATION (4) HOLDA J18 O/Z IPU Hold-request-acknowledgetothehost HOLD J17 I IPU Holdrequestfromthehost BUSREQ J19 O/Z IPU Bus requestoutput EMIF — ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL (4) ECLKIN Y11 I IPD ExternalEMIF inputclocksource EMIF outputclockdepends on theEKSRC bit(DEVCFG.[4])and on EKEN bit(GBLCTL.[5]). EKSRC = 0 ECLKOUT isbased on theinternalSYSCLK3 signalfromtheclockgenerator(default). ECLKOUT Y10 O/Z IPD EKSRC = 1 ECLKOUT isbased on theexternalEMIF inputclocksourcepin(ECLKIN) EKEN = 0 ECLKOUT heldlow EKEN = 1 ECLKOUT enabledtoclock(default) ARE/SDCAS/ V11 O/Z IPU Asynchronousmemory readenable/SDRAM column-addressstrobe/SBSRAM addressstrobeSSADS AOE/ SDRAS/ SSOE W10 O/Z IPU Asynchronousmemory outputenable/SDRAM row-addressstrobe/SBSRAM outputenable AWE/ SDWE/ SSWE V12 O/Z IPU Asynchronousmemory writeenable/SDRAM writeenable/SBSRAM writeenable ARDY Y5 I IPU Asynchronousmemory readyinput (4) To maintainsignalintegrityfortheEMIF signals,serialterminationresistorsshouldbe insertedintoallEMIF outputsignallines. Copyright© 2003–2009,Texas InstrumentsIncorporated TERMINAL FUNCTIONS 49 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com TERMINAL FUNCTIONS (continued) PIN IPD/IPUNO.SIGNAL NAME TYPE (1) DESCRIPTION(2) GDP EMIF — ADDRESS (4) EA21 U18 EA20 Y18 EA19 W17 EA18 Y16 EA17 V16 EA16 Y15 EA15 W15 EA14 Y14 Externaladdress(word,half-word,and byteaddress) EA13 W14 The EMIF adjuststheaddressbased on memory width: EA12 V14 Width Pins Address O/Z IPU EA11 W13 32 21:2 21 through2 EA10 V10 16 21:2 20 through1 EA9 Y9 8 21:2 19 through0 EA8 V9 EA7 Y8 Formore detailson addresswidthadjustments,see theExternalMemory Interface(EMIF)chapteroftheTMS320C6000 Peripherals ReferenceGuide (literaturenumber SPRU190 )EA6 W8 EA5 V8 EA4 W7 EA3 V7 EA2 Y6 EMIF — DATA (4) ED31 N3 ED30 P3 ED29 P2 ED28 P1 ED27 R2 ED26 R3 ED25 T2 ED24 T1 ED23 U3 ED22 U1 ED21 U2 ED20 V1 ED19 V2 ED18 Y3 ED17 W4 ED16 V4 I/O/Z IPU Externaldatapins(ED[31:16]pinsapplicabletoGDP package only) ED15 T19 ED14 T20 ED13 T18 ED12 R20 ED11 R19 ED10 P20 ED9 P18 ED8 N20 ED7 N19 ED6 N18 ED5 M20 ED4 M19 ED3 L19 ED2 L18 ED1 K19 ED0 K18

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 TERMINAL FUNCTIONS (continued) PIN IPD/IPUNO.SIGNAL NAME TYPE (1) DESCRIPTION(2) GDP MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1) GP4/ C2 I/O/Z IPU General-purposeinput/outputpin4 and externalinterrupt4 (I/O/Z)[default]orMcASP1 mute input(I/O/Z)AMUTEIN1 HD3/AMUTE1 C20 I/O/Z IPU Host-portdatapin3 (I/O/Z)[default]orMcASP1 mute output(O/Z) HRDY/ACLKR1 H19 I/O/Z IPU Hostready(fromDSP tohost)(O )[default]orMcASP1 receivebitclock(I/O/Z) HD6/AHCLKR1 C17 I/O/Z IPU Host-portdatapin6 (I/O/Z)[default]orMcASP1 receivehigh-frequencymasterclock(I/O/Z) HAS/ACLKX1 E18 I/O/Z IPU Hostaddressstrobe(I)[default]orMcASP 1 transmitbitclock(I/O/Z) HD5/AHCLKX1 B18 I/O/Z IPU Host-portdatapin5 (I/O/Z)[default]orMcASP1 transmithigh-frequencymasterclock(I/O/Z) Hosthalf-wordselect− firstorsecond half-word(notnecessarilyhighorloworder)(I)[default]orMcASP1 receiveframesyncorHHWIL/AFSR1 H20 I/O/Z IPU left/rightclock(LRCLK) (I/O/Z) HD2/AFSX1 D18 I/O/Z IPU Host-portdatapin2 (I/O/Z)[default]orMcASP1 transmitframesyncorleft/rightclock(LRCLK) (I/O/Z) HD1/AXR1[7] D20 I/O/Z IPU Host-portdatapin1 (I/O/Z)[default]orMcASP1 TX/RX datapin7 (I/O/Z) HDS1/AXR1[6] E19 I/O/Z IPU Hostdatastrobe1 (I)[default]orMcASP1 TX/RX datapin6 (I/O/Z) HDS2/AXR1[5] F18 I/O/Z IPU Hostdatastrobe2 (I)[default]orMcASP1 TX/RX datapin5 (I/O/Z) HD0/AXR1[4] E20 I/O/Z IPU Host-portdatapin0 (I/O/Z)[default]orMcASP1 TX/RX datapin4 (I/O/Z) HCNTL0/AXR1[3] G18 I/O/Z IPU Hostcontrol− selectsbetween control,address,ordataregisters(I)[default]orMcASP1 TX/RX datapin3 (I/O/Z) HCS/AXR1[2] F20 I/O/Z IPU Hostchipselect(I)[default]orMcASP1 TX/RX datapin2 (I/O/Z) HCNTL1/AXR1[1] G19 I/O/Z IPU Hostcontrol− selectsbetween control,address,ordataregisters(I)[default]orMcASP1 TX/RX datapin1 (I/O/Z) HR/W/AXR1[0] G20 I/O/Z IPU Hostreadorwriteselect(I)[default]orMcASP1 TX/RX datapin0 (I/O/Z) MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) GP5/ C1 I/O/Z IPU General-purposeinput/outputpin5 and externalinterrupt5 (I/O/Z)[default]orMcASP0 mute input(I/O/Z)AMUTEIN0 CLKX1/AMUTE0 L3 I/O/Z IPD McBSP1 transmitclock(I/O/Z)[default]orMcASP0 mute output(O/Z) CLKR0/ACLKR0 H3 I/O/Z IPD McBSP0 receiveclock(I/O/Z)[default]orMcASP0 receivebitclock(I/O/Z) TINP1/AHCLKX0 F2 I/O/Z IPD Timer1 input(I)[default]orMcBSP0 transmithigh-frequencymasterclock(I/O/Z) CLKX0/ACLKX0 G3 I/O/Z IPD McBSP0 transmitclock(I/O/Z)[default]orMcASP0 transmitbitclock(I/O/Z) CLKS0/AHCLKR0 K3 I/O/Z IPD McBSP0 externalclocksource(asopposed tointernal)(I)[default]orMcASP0 receivehigh-frequencymasterclock(I/O/Z) FSR0/AFSR0 J3 I/O/Z IPD McBSP0 receiveframesync(I/O/Z)[default]orMcASP0 receiveframesyncorleft/rightclock(LRCLK) (I/O/Z) FSX0/AFSX0 H1 I/O/Z IPD McBSP0 transmitframesync(I/O/Z)[default]orMcASP0 transmitframesyncorleft/rightclock(LRCLK) (I/O/Z) FSR1/AXR0[7] M3 I/O/Z IPD McBSP1 receiveframesync(I/O/Z)[default]orMcASP0 TX/RX datapin7 (I/O/Z) CLKR1/AXR0[6] M1 I/O/Z IPD McBSP1 receiveclock(I/O/Z)[default]orMcASP0 TX/RX datapin6 (I/O/Z) DX1/AXR0[5] L2 I/O/Z IPU McBSP1 transmitdata(O/Z)[default]orMcASP0 TX/RX datapin5 (I/O/Z) TOUT1/AXR0[4] F1 I/O/Z IPD Timer1 output(O )[default]orMcASP0 TX/RX datapin4 (I/O/Z) TINP0/AXR0[3] G2 I/O/Z IPD Timer0 input(I)[default]orMcASP0 TX/RX datapin3 (I/O/Z) TOUT0/AXR0[2] G1 I/O/Z IPD Timer0 output(O )[default]orMcASP0 TX/RX datapin2 (I/O/Z) DX0/AXR0[1] H2 I/O/Z IPU McBSP0 transmitdata(O/Z)[default]orMcASP0 TX/RX datapin1 (I/O/Z) DR0/AXR0[0] J1 I/O/Z IPU McBSP0 receivedata(I)[default]orMcASP0 TX/RX datapin0 (I/O/Z) TIMER1 TOUT1/AXR0[4] F1 O IPD Timer1 output(O )[default]orMcASP0 TX/RX datapin4 (I/O/Z) Timer1 input(I)[default]orMcBSP0 transmithigh-frequencymasterclock(I/O/Z).Thispindefaultsas Timer1 input(I)and McASPTINP1/AHCLKX0 F2 I IPD transmithigh−frequencymasterclockinput(I). TIMER0 TOUT0/AXR0[2] G1 O IPD Timer0 output(O )[default]orMcASP0 TX/RX datapin2 (I/O/Z) TINP0/AXR0[3] G2 I IPD Timer0 input(I)[default]orMcASP0 TX/RX datapin3 (I/O/Z) MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) McBSP1 externalclocksource(asopposed tointernal)(I)[default]orI2C1 clock(I/O/Z).Thispindoes nothave an internalpullupor pulldown.When thispinisused as a McBSP pin,thispinshouldeitherbe drivenexternallyatalltimesorbe pulledup witha 10-kΩCLKS1/SCL1 E1 I — resistortoa validlogiclevel.Because itiscommon forsome ICsto3-statetheiroutputsattimes,a 10-kΩ pullupresistormay be desirableeven when an externaldeviceisdrivingthepin. CLKR1/AXR0[6] M1 I/O/Z IPD McBSP1 receiveclock(I/O/Z)[default]orMcASP0 TX/RX datapin6 (I/O/Z) CLKX1/AMUTE0 L3 I/O/Z IPD McBSP1 transmitclock(I/O/Z)[default]orMcASP0 mute output(O/Z) McBSP1 receivedata(I)[default]orI2C1 data(I/O/Z).Thispindoes nothave an internalpulluporpulldown.When thispinisused as a McBSP pin,thispinshouldeitherbe drivenexternallyatalltimesorbe pulledup witha 10-kΩ resistortoa validlogiclevel.BecauseDR1/SDA1 M2 I — itiscommon forsome ICsto3-statetheiroutputsattimes,a 10-kΩ pullupresistormay be desirableeven when an externaldeviceis drivingthepin. DX1/AXR0[5] L2 O/Z IPU McBSP1 transmitdata(O/Z)[default]orMcASP0 TX/RX datapin5 (I/O/Z) FSR1/AXR0[7] M3 I/O/Z IPD McBSP1 receiveframesync(I/O/Z)[default]orMcASP0 TX/RX datapin7 (I/O/Z) FSX1 L1 I/O/Z IPD McBSP1 transmitframesync Copyright© 2003–2009,Texas InstrumentsIncorporated TERMINAL FUNCTIONS 51 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com TERMINAL FUNCTIONS (continued) PIN IPD/IPUNO.SIGNAL NAME TYPE (1) DESCRIPTION(2) GDP MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0/AHCLKR0 K3 I IPD McBSP0 externalclocksource(asopposed tointernal)(I)[default]orMcASP0 receivehigh-frequencymasterclock(I/O/Z) CLKR0/ACLKR0 H3 I/O/Z IPD McBSP0 receiveclock(I/O/Z)[default]orMcASP0 receivebitclock(I/O/Z) CLKX0/ACLKX0 G3 I/O/Z IPD McBSP0 transmitclock(I/O/Z)[default]orMcASP0 transmitbitclock(I/O/Z) DR0/AXR0[0] J1 I IPU McBSP0 receivedata(I)[default]orMcASP0 TX/RX datapin0 (I/O/Z) DX0/AXR0[1] H2 O/Z IPU McBSP0 transmitdata(O/Z)[default]orMcASP0 TX/RX datapin1 (I/O/Z) FSR0/AFSR0 J3 I/O/Z IPD McBSP0 receiveframesync(I/O/Z)[default]orMcASP0 receiveframesyncorleft/rightclock(LRCLK) (I/O/Z) FSX0/AFSX0 H1 I/O/Z IPD McBSP0 transmitframesync(I/O/Z)[default]orMcASP0 transmitframesyncorleft/rightclock(LRCLK) (I/O/Z) INTER-INTEGRATED CIRCUIT 1 (I2C1) McBSP1 externalclocksource(asopposed tointernal)(I)[default]orI2C1 clock(I/O/Z).Thispinmust be externallypulledup.When CLKS1/SCL1 E1 I/O/Z — thispinisused as an I2C pin,thevalueofthepullupresistordepends on thenumber ofdevicesconnectedtotheI2C bus.Formore details,see thePhilipsI2C SpecificationRevision2.1(January2000). McBSP1 receivedata(I)[default]orI2C1 data(I/O/Z).Thispinmust be externallypulledup.When thispinisused as an I2C pin,the DR1/SDA1 M2 I/O/Z — valueofthepullupresistordepends on thenumber ofdevicesconnectedtotheI2C bus.Formore details,see thePhilipsI2C SpecificationRevision2.1(January2000). INTER-INTEGRATED CIRCUIT 0 (I2C0) I2C0 clock.Thispinmust be externallypulledup.When thispinisused as an I2C pin,thevalueofthepull-upresistordepends on theSCL0 N1 I/O/Z — number ofdevicesconnectedtotheI2C bus.Formore details,see thePhilipsI2C SpecificationRevision2.1(January2000). I2C0 data.Thispinmust be externallypulledup.When thispinisused as an I2C pin,thevalueofthepull-upresistordepends on theSDA0 N2 I/O/Z — number ofdevicesconnectedtotheI2C bus.Formore details,see thePhilipsI2C SpecificationRevision2.1(January2000). GENERAL-PURPOSE INPUT/OUTPUT (GPIO) HD15/GP[15] B14 I/O/Z IPU Host-portdatapins(I/O/Z)[default]orgeneral-purposeinput/outputpins(I/O/Z)and some functionas bootconfigurationpinsatreset.

Used fortransferofdata,address,and controlHD14/GP[14] C14 I/O/Z IPU
AlsocontrolsinitializationofDSP modes atresetviapullup/pulldownresistorsHD13/GP[13] A15 I/O/Z IPU abc As general-purposeinput/output(GP[x])functions,thesepinsaresoftwareconfigurablethroughregisters.The GPxEN bitsintheGPHD12/GP[12] C15 I/O/Z IPU Enableregisterand theGPxDIR bitsintheGP Directionregistermust be properlyconfigured: HD11/GP[11] A16 I/O/Z IPU abc GPxEN = 1;GP[x]pinisenabled.HD10/GP[10] B16 I/O/Z IPU GPxDIR = 0;GP[x]pinisan input. HD9/GP[9] C16 I/O/Z IPU GPxDIR = 1;GP[x]pinisan output. abc ForthefunctionalitydescriptionoftheHost-portdatapinsorthebootconfigurationpins,see theHost-PortInterface(HPI)portionofHD8/GP[8] B17 I/O/Z IPU thistable. GP7 E3 I/O/Z IPU General-purposeinput/outputpins(I/O/Z)thatalsofunctionas externalinterrupts GP6 D2 I/O/Z IPU • Edge-driven GP5/AM • PolarityindependentlyselectedviatheExternalInterruptPolarityRegisterbits(EXTPOL.[3:0])C1 I/O/Z IPUUTEIN0 abc GP[4]and GP[5]pinsalsofunctionas AMUTEIN1 McASP1 mute inputand AMUTEIN0 McASP0 mute input,respectively,ifenabledbyGP4/ theINEN bitintheassociatedMcASP AMUTE register.C2 I/O/Z IPUAMUTEIN1 HD7/GP[3] A18 I/O/Z IPU Host-portdatapin7 (I/O/Z)[default]orgeneral-purposeinput/outputpin3 (I/O/Z) CLKOUT2/GP[2] Y12 I/O/Z IPD Clockoutputathalfofdevicespeed (O/Z)[default]orthispincan be programmed as GP[2]pin HINT/GP[1] J20 O IPU Hostinterrupt(fromDSP tohost)(O )[default]orthispincan be programmed as a GP[1]pin(I/O/Z) HD4/GP[0] C19 I/O/Z IPD Host-portdatapin4 (I/O/Z)[default]orthispincan be programmed as a GP[0]pin(I/O/Z) RESERVED FOR TEST RSV A5 O/Z IPU Reserved.(Leaveunconnected;do not connecttopower orground.) RSV B5 A (3) — Reserved.(Leaveunconnected;do not connecttopower orground.) RSV C12 O — Reserved.(Leaveunconnected;do not connecttopower orground.) RSV D7 O/Z IPD Reserved.(Leaveunconnected;do not connecttopower orground.) Reserved.Thispindoes not have an IPU.ForproperC6713 deviceoperation,theD12 pinmust be externallypulleddown withaRSV D12 I — 10-kΩ resistor. Reserved.Fornew designs,itisrecommended thatthispinbe connecteddirectlytoCV DD (corepower).Forolddesigns,thiscan beRSV A12 — — leftunconnected. Reserved.Fornew designs,itisrecommended thatthispinbe connecteddirectlytoVSS (ground).Forolddesigns,thispincan be leftRSV B11 — — unconneced.

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 TERMINAL FUNCTIONS (continued) PIN IPD/IPUNO.SIGNAL NAME TYPE (1) DESCRIPTION(2) GDP SUPPLY VOLTAGE PINS A17 B13 C10 D16 D19 H18 M18 R1 3.3-VsupplyvoltageDV DD R18 S — (seethePower-SupplyDecouplingsectionofthisdatasheet)T3 U12 U16 V13 V15 V19 W12 Y17 A10 B19 C18 D11 D14 D15 F17 K1 1.26-VsupplyvoltageCV DD S —K4 (seethePower-SupplyDecouplingsectionofthisdatasheet) K17 L17 L20 R17 U10 U11 U14 U15 V18 W19 Copyright© 2003–2009,Texas InstrumentsIncorporated TERMINAL FUNCTIONS 53 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com TERMINAL FUNCTIONS (continued) PIN IPD/IPUNO.SIGNAL NAME TYPE (1) DESCRIPTION(2) GDP GROUND PINS A11 A14 A19 A20 B15 B20 D13 D17 E17 F19 G17 H17 J10 J11 J12 K10 K11 Ground pins(1).The centerthermalballs(J9−J12,K9−K12,L9−L12,M9 −M12) [shaded]arealltiedtogroundand actas bothelectricalVSS K12 GND — groundsand thermalrelief(thermaldissipation).K20 L10 L11 L12 M10 M11 M12 M17 N17 P17 P19 T17 U13 U17 U20 W11 W16 W20 Y13 Y19 Y20 (1) Shaded pinnumbers denotethecenterthermalballs.

6.1 Development Support

TIoffersan extensivelineofdevelopmenttoolsfortheTMS320C6000 ™ DSP platform,includingtoolsto evaluatetheperformanceoftheprocessors,generatecode,developalgorithmimplementations,and fully integrateand debug softwareand hardwaremodules. The followingproductssupportdevelopmentofC6000 ™ DSP-based applications:

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Code Composer Studio™ IntegratedDevelopmentEnvironment(IDE),includingEditor
C/C++/AssemblyCode Generation,and Debug plusadditionaldevelopmenttools
Scalable,Real-TimeFoundationSoftware( DSP/BIOS ™ ),which providesthe basicrun-timetarget softwareneeded tosupportany DSP application. Hardware Development Tools
Extended Development System ( XDS ™ ) Emulator(supportsC6000 DSP multiprocessorsystem debug)
EVM (evaluationmodule) For a completelistingofdevelopment-supporttoolsfortheTMS320C6000 DSP platform,visittheTexas Instrumentsweb siteatwww.ti.com.For informationon pricingand availability,contactthenearestTIfield salesofficeorauthorizeddistributor.

6.2 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall TMS320 ™ DSP devicesand supporttools.Each TMS320 DSP commercialfamilymember has one of threeprefixes:SMX, TMP, or SM/SMJ. TI recommends two of threepossibleprefixdesignatorsfor supporttools:TMDX and TMDS. These prefixesrepresentevolutionarystagesof productdevelopment from engineering prototypes (SMX/TMDX) through fully qualifiedproduction devices/tools (SM/SMJ/TMDS).

6.2.1 Device Development EvolutionaryFlow

SMX Preproductiondevicethatisnotnecessarilyrepresentativeofthefinaldevice electricalspecifications TMP Finalsilicondiethatconformstothedeviceelectricalspecificationsbuthas not completedqualityand reliabilityverification SM/SMJ Fullyqualifiedproductiondevice

6.2.2 Support Tool Development EvolutionaryFlow

TMDX Development-supportproductthathas notyetcompletedTexas Instruments internalqualificationtesting TMDS Fullyqualifieddevelopment-supportproduct SMX and TMP devicesand TMDX development-supporttoolsare shippedwithappropriatedisclaimers describingtheirlimitationsand intendeduses.Experimentaldevices(SMX) may notbe representativeofa finalproductand TIreservestherighttochange ordiscontinuetheseproductswithoutnotice. SM/SMJ devicesand TMDS development-supporttoolshave been characterizedfully,and thequalityand reliabilityofthedevicehave been demonstratedfully.TI’s standardwarrantyapplies. Predictionsshow thatprototypedevices(SMX or TMP) have a greaterfailureratethan the standard productiondevices.TI recommends thatthesedevicesnot be used inany productionsystem because theirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesaretobe used. TI devicenomenclaturealso includesa suffixwiththe devicefamilyname. This suffixindicatesthe package type(forexample,GDP ),the temperaturerange (forexample,blankisthe defaultcommercial temperaturerange),and thedevicespeed rangeinmegahertz(forexample,20 is200 MHz). Figure6-1 providesa legendforreadingthecompletedevicename forany TMS320C6000 DSP family member. Copyright© 2003–2009,Texas InstrumentsIncorporated TERMINAL FUNCTIONS 55 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

PREFIX ENHANCED PLASTIC INDICA TOR SM 320 C 6713 GDP 20 SMX= Experimental device TMP= Prototype device TMS= Qualified device SMJ= MIL-PRF-38535, QML SM High Rel (non-38535) DEVICE FAMILY 320 = TMS320ä DSP family TECHNOLOGY PACKAGE TYPE (See Note 1) C CMOS DEVICE TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) ( ) C6000 DSP: C6713 C6713B GDP = 272-pin plastic BGA GFN= 256-pin plastic BGA GGP = 352-pin plastic BGA GJC= 352-pin plastic BGA GJL= 352-pin plastic BGA GLS= 384-pin plastic BGA GLW= 340-pin plastic BGA GNY = 384-pin plastic BGA GNZ = 352-pin plastic BGA GLZ= 532-pin plastic BGA GHK = 288-pin plastic MicroStar BGA TM PYP = 208-pin PowerP AD TM plastic QFP 20 = 200 MHz EP DEVICE SPEED RANGE Blank = 0°C to 90°C (commercial temperature) A = 40°C to 105°C (extended temperature) M = –55°C to 125°C (extended temperature) S = -55°C to 105°C (extended temperature) NOTE (1): BGA = Ball Grid Array QFP = Quad Flatpack For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this the TI website (www.ti.com). document or SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table6-1.320C6713 and C6713B Device PartNumbers (P/Ns)and OrderingInformation(1) CORE AND I/OVOLTAGE OPERATING CASE DEVICE ORDERABLE P/N (2) DEVICE SPEED TEMPERATURE CV DD (CORE) DV DD (I/O) RANGE C6713B SM32C6713BGDPA20EP 200 MHz/1200 MFlops 1.26V 3.3V –40°C to105°C SM32C6713BGDPM30EP 300 MHz/1800 MFlops 1.4V 3.3V –55°C to125°C SM32C6713BGDPS20EP 200 MHz/1200 MFlops 1.26V 3.3V –55°C to105°C (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI Web siteatwww.ti.com. (2) Package drawings,standardpackingquantities,thermaldata,symbolization,and PCB designguidelinesareavailableat www.ti.com/sc/package

6.3 OrderingNomenclature

Figure6-1.TMS320C6000 ™ DSP Device Nomenclature (IncludingSM320C6713 and C6713B Devices)

6.4 Documentation Support

Extensivedocumentationsupportsallthe TMS320 DSP familygenerationsof devicesfrom product announcement throughapplicationsdevelopment.The types of documentationavailableincludedata sheets,such as thisdocument withdesignspecificationscompleteuser’s referenceguidesforalldevices and tools,technicalbriefs,development-supporttools,on-linehelp, and hardware and software applications.The followingisa brief,descriptivelistofsupportdocumentationspecifictotheC6000 DSP devices,exceptwhere noted,alldocuments areaccessiblethroughtheTIweb siteatwww.ti.com.

TMS320C6000 ™ CPU and InstructionSetReferenceGuide (literaturenumber SPRU189 )describes theC6000 CPU (DSP core)architecture,instructionset,pipeline,and associatedinterrupts.

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TMS320C6000 ™ DSP PeripheralsOverviewReferenceGuide [hereafterreferredtoas theC6000 PRG Overview](literaturenumber SPRU190 )providesan overviewand brieflydescribesthe functionalityoftheperipheralsavailableon theC6000 DSP platformofdevices.Thisdocument also includesa tablelistingtheperipheralsavailableon theC6000 devicesalongwithliteraturenumbers and hyperlinkstotheassociatedperipheraldocuments.These C6713/13B peripheralsaresimilarto theperipheralson theTMS320C6711 and TMS320C64x devices;therefore,see theTMS320C6711 (C6711 orC67x) peripheralinformationand,insome cases(whereindicated),see theTMS320C6711 (C6711 orC671x) peripheralinformationand,insome cases(whereindicated),see theC64x informationintheC6000 ™ PRG Overview(literaturenumber SPRU190 ).
TMS320DA6000 ™ DSP MultichannelAudioSerialPort(McASP) ReferenceGuide (literaturenumber SPRU041 )describesthefunctionalityoftheMcASP peripheralsavailableon theC6713/13B device.
TMS320C6000 ™ DSP Software-ProgrammablePhase-LockedLoop (PLL)ControllerReferenceGuide (literaturenumber SPRU233 )describesthefunctionalityofthePLL peripheralavailableon the C6713/13B device.
TMS320C6000 ™ DSP Inter-IntegratedCircuit(I2C) Module ReferenceGuide (literaturenumber SPRU175 )describesthefunctionalityoftheI2C peripheralsavailableon theC6713/13B device.
The PowerPAD ™ Thermally-EnhancedPackage TechnicalBrief(literaturenumber SLMA002 )focuses on thespecificsofintegratinga PowerPAD package intotheprintedcircuitboard(PCB) designto make optimum use ofthethermalefficienciesdesignedintothePowerPAD package.
TMS320C6000 ™ TechnicalBrief(literaturenumber SPRU197 )givesan introductiontotheC62x™ / C67x™ devices,associateddevelopmenttools,and third-partysupport.
MigratingfromTMS320C6211(B)/C6711(B)toTMS320C6713 applicationreport(literaturenumber SPRA851 )indicatesthedifferencesand describestheissuesofinterestrelatedtothemigrationfrom theTITMS320C6211(B)/C6711(B)GFN package totheTMS320C6713 GDP package.
TMS320C6713, TMS320C6713B DigitalSignalProcessorsSiliconErrata(literaturenumber SPRZ191 ) describestheknown exceptionstothefunctionalspecificationsforparticularsiliconrevisionsofthe TMS320C6713 and TMS320C6713B devices.
TMS320C6713/12C/11C Power ConsumptionSummary applicationreport(literaturenumber SPRA889 )discussesthepower consumptionforuserapplicationswiththeTMS320C6713/13B, TMS320C6712C/12D, and TMS320C6711C/11D DSP devices.
UsingIBISModels forTimingAnalysisapplicationreport(literaturenumber SPRA839 )describeshow toproperlyuse IBISmodels toattainaccuratetiminganalysisfora givensystem. The toolssupportdocumentationiselectronicallyavailablewithintheCode Composer StudioIntegrated Development Environment(IDE).For a completelistingof C6000 DSP latestdocumentation,visitthe Texas Instrumentsweb siteatwww.ti.com.Also,see theTI web sitefortheapplicationreport,How To Begin Development Today With the TMS320C6713 Floating-PointDSP (literaturenumber SPRA809 ), which describesinmore detailthe similarities/differencesbetween the C6713 and C6711 C6000 DSP devices. Copyright© 2003–2009,Texas InstrumentsIncorporated TERMINAL FUNCTIONS 57 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

CPU□ID REVISION□ID 15 10 98 76 54 21 0 PWRD SAT EN PCC DCC PGIE GIE R/W-0R /C-0 R-1R /W-0 R/W-0R /W-0 R/W-0 Legend: R□□=□Readable□by□the□MVC□instruction,□R/W□=□Readable/Writeable□by□the□MVC□instruction;□W□=□Read/write;□-n□=□value□after□reset,□-x□=□undefined□value□after reset,□C□=□Clearable□by□the□MVC□instruction SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com

7 REGISTER INFORMATION

Thissectionprovidestheregisterinformationforthedevice.

7.1 CPU ControlStatusRegister(CSR) Description

The CPU CSR containstheCPU ID and CPU RevisionID (bits16−31),as wellas thestatusofthedevice power-down modes [PWRD field(bits15−10)],program and data cache controlmodes, the endianbit (EN, bit8),and the globalinterruptenable(GIE,bit0) and previousGIE (PGIE,bit1).Figure7-1 and Table7-1identifythebitfieldsintheCPU CSR. For more detailedinformationon thebitfieldsintheCPU CSR, see theTMS320C6000 DSP Peripherals OverviewReferenceGuide (literaturenumber SPRU190 )and theTMS320C6000 CPU and InstructionSet ReferenceGuide (literaturenumber SPRU189 ). Figure7-1.CPU ControlStatusRegister(CPU CSR)

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table7-1.CPU CSR BitFieldDescription BitNO. NAME DESCRIPTION 31:24 CPU ID CPU ID + REV ID.Read only.IdentifieswhichCPU isused and definesthesiliconrevisionoftheCPU. CPU ID + REVISION ID (31:16)arecombined fora valueof:0x0203 forC6713/13B23:16 REVISION ID 15:10 PWRD Controlpower-down modes. The valuesarealwaysreadas zero. 000000 = No power down (default) 001001 = PD1, wake up by an enabledinterrupt 010001 = PD1, wake up by an enabledornotenabledinterrupt 011010 = PD2, wake up by a devicereset 011100 = PD3, wake up by a devicereset Others = Reserved 9 SAT Saturatebit. Setwhen any unitperformsa saturate.Thisbitcan be clearedonlyby theMVC instructionand can be setonly by a functionalunit.The setby thea functionalunithas priorityovera clear(bytheMVC instruction)ifthey occuron thesame cycle.The saturatebitissetone fullcycle(onedelayslot)aftera saturateoccurs.Thisbit willnotbe modifiedby a conditionalinstructionwhose conditionisfalse. 8 EN Endianbit.Thisbitisread-only.Depictsthedeviceendianmode. 0 = BigEndianmode 1 = LittleEndianmode [default] 7:5 PCC Program cache controlmode. L1D, Level1 programcache 000/010 = Cache enabled/cacheaccessedand updatedon reads AllotherPCC valuesarereserved. 4:2 DCC Data cache controlmode. L1D, Level1 datacache 000/010 = Cache enabled/2-waycache AllotherDCC valuesarereserved. 1 PGIE PreviousGIE (globalinterruptenable);savestheGlobalInterruptEnable(GIE)when an interruptistaken. Allowsforpropernestingofinterrupts. 0 = PreviousGIE valueis0 (default). 1 = PreviousGIE valueis1. 0 GIE Globalinterruptenablebit. Enables(1)ordisables(0)allinterruptsexcepttheresetinterruptand NMI (nonmaskableinterrupt). 0 = Disablesallinterrupts(excepttheresetinterruptand NMI) [default]. 1 = Enablesallinterrupts(excepttheresetinterruptand NMI).

7.2 Cache Configuration(CCFG) RegisterDescription(13B)

The C6713B deviceincludesan enhancement to the CCFG register.A P bit(CCFG.31) allowsthe programmer to selectthe priorityof accesses to L2 memory originatingfrom the transfercrossbar(TC) over accesses originatingfrom the L1D memory system.An importantclassof TC accesses isEDMA transfers,whichmove datatoorfromtheL2 memory. WhiletheEDMA normallyhas no issueaccessing L2 memory because ofthehighhitrateson theL1D memory system,therearepathologicalcases where certainCPU behaviorcouldblocktheEDMA from accessingtheL2 memory forlongenough tocause a missed deadlinewhen transferringdata to a peripheralsuch as the McASP or McBSP. This can be avoidedby settingtheP bitto1 because theEDMA willassume a higherprioritythantheL1D memory systemwhen accessingL2 memory. For more detailedinformationon the P-bitfunctionand forsiliconadvisoriesconcerningEDMA L2 memory accesses blocked,see the TMS320C6713, TMS320C6713B DigitalSignalProcessorsSilicon Errata(literaturenumber SPRZ191 ). Copyright© 2003–2009,Texas InstrumentsIncorporated REGISTER INFORMATION 59 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

P Reserved IP ID Reserved L2MODE R/W-0 R-x W-0 W-0 R-0□0000 R/W-000 (1) A:□Unlike□the□C6713□device,□the□C6713B□device□includes□a□P□bit. Legend: R□□=□Readable;□R/W□=□Readable/Writeable;□-n□=□value□after□reset,□-x□=□undefined□value□after□reset SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com A. UnliketheC6713 device,theC6713B deviceincludesa P bit. Figure7-2.Cache Configuration(CCFG) Register Table7-2.CCFG RegisterBitFieldDescription BIT NO. NAME DESCRIPTION L1D requestorprioritytoL2 bit

31 P P = 0:L1D requeststoL2 higherprioritythanTC requests

P = 1:TC requeststoL2 higherprioritythanL1D requests 30:10 Reserved Reserved.Read only,writeshave no effect. InvalidateL1P bit

9 IP 0 = Normal L1P operation

1 = AllL1P linesareinvalidated InvalidateL1D bit

8 ID 0 = Normal L1D operation

1 = AllL1D linesareinvalidated 7:3 Reserved Reserved.Read only,writeshave no effect. L2 operationmode bits(L2MODE) 000b = L2 cache disabled(AllSRAM mode) [256KSRAM] 001b = 1-way cache (16K L2 cache)/[240KSRAM] 2:0 L2MODE 010b = 2-way cache (32K L2 cache)/[224KSRAM] 011b = 3-way cache (48K L2 cache)/[208KSRAM] 111b = 4-way cache (64K L2 cache)/[192KSRAM] Allothersarereserved.

7.3 Interruptsand InterruptSelector

The C67x DSP coresupports16 prioritizedinterrupts,which are listedinTable7-3.The highestpriority interruptisINT_00 (dedicatedtoRESET), whilethelowestpriorityisINT_15.The firstfourinterruptsare non-maskableand fixed.The remaininginterrupts(4−15)aremaskable and defaulttotheinterruptsource listedinTable7-3.However,theirinterruptsourcemay be reprogrammed toany one ofthesourceslisted inTable7-4(InterruptSelector).Table7-4 liststheselectorvaluecorrespondingtoeach ofthealternate interruptsources.The selectorchoiceforinterrupts4−15 ismade by programming the corresponding fields(listedin Table 7-3) in the MUXH (address0x019C0000) and MUXL (address0x019C0004) registers. Table7-3.DSP Interrupts INTERRUPT DEFAULT DEFAULTDSP SELECTOR CONTROL SELECTOR VALUE INTERRUPTINTERRUPT NUMBER REGISTER (BINARY) EVENT INT_00 — — RESET INT_01 — — NMI INT_02 — — Reserved INT_03 — — Reserved

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table7-3.DSP Interrupts(continued) INTERRUPT DEFAULT DEFAULTDSP SELECTOR CONTROL SELECTOR VALUE INTERRUPTINTERRUPT NUMBER REGISTER (BINARY) EVENT INT_04 MUXL[4:0] 00100 GPINT4 (1) INT_05 MUXL[9:5] 00101 GPINT5 (1) INT_06 MUXL[14:10] 00110 GPINT6 (1) INT_07 MUXL[20:16] 00111 GPINT7 (1) INT_08 MUXL[25:21] 01000 EDMAINT INT_09 MUXL[30:26] 01001 EMUDTDMA INT_10 MUXH[4:0] 00011 SDINT INT_11 MUXH[9:5] 01010 EMURTDXRX INT_12 MUXH[14:10] 01011 EMURTDXTX INT_13 MUXH[20:16] 00000 DSPINT INT_14 MUXH[25:21] 00001 TINT0 INT_15 MUXH[30:26] 00010 TINT1 (1) InterrupteventsGPINT4, GPINT5, GPINT6, and GPINT7 areoutputsfromtheGPIO module (GP). They originatefromthedevicepinsGP4/AMUTEIN1,GP5/AMUTEIN0, GP6,and GP7.These pinscan be used as edge-sensitiveEXT_INTx with polaritycontrolledby theExternalInterruptPolarityRegister(EXTPOL.[3:0]).The correspondingpins must firstbe enabledintheGPIO module by settingthecorrespondingenablebitsintheGP Enable Register(GPEN.[7:4]),and configuringthem as inputsintheGP DirectionRegister(GPDIR.[7:4]). These interruptscan be controlledthroughtheGPIO module inadditiontothesimpleEXTPOL.[3:0] bits.Formore informationon interruptcontrolviatheGPIO module,see theTMS320C6000 ™ DSP General-PurposeInput/Output(GPIO)ReferenceGuide (literaturenumber SPRU584 ). Copyright© 2003–2009,Texas InstrumentsIncorporated REGISTER INFORMATION 61 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table7-4.InterruptSelector INTERRUPT SELECTOR VALUE INTERRUPT EVENT MODULE(BINARY)

00000 DSPINT HPI

00001 TINT0 Timer0

00010 TINT1 Timer1

00011 SDINT EMIF

00100 GPINT4 (1) GPIO

00101 GPINT5 (1) GPIO

00110 GPINT6 (1) GPIO

00111 GPINT7 (1) GPIO

01000 EDMAINT EDMA

01001 EMUDTDMA Emulation

01010 EMURTDXRX Emulation

01011 EMURTDXTX Emulation

01100 XINT0 McBSP0

01101 RINT0 McBSP0

01110 XINT1 McBSP1

01111 RINT1 McBSP1

10000 GPINT0 GPIO

10001 Reserved —

10010 Reserved —

10011 Reserved —

10100 Reserved —

10101 Reserved —

10110 I2CINT0 I2C0

10111 I2CINT1 I2C1

11000 Reserved —

11001 Reserved —

11010 Reserved —

11011 Reserved —

11100 AXINT0 McASP0

11101 ARINT0 McASP0

11110 AXINT1 McASP1

11111 ARINT1 McASP1

(1) InterrupteventsGPINT4, GPINT5, GPINT6, and GPINT7 areoutputsfromtheGPIO module (GP). They originatefromthedevicepinsGP4/AMUTEIN1,GP5/AMUTEIN0, GP6,and GP7.These pinscan be used as edge-sensitiveEXT_INTx with polaritycontrolledby theExternalInterruptPolarityRegister(EXTPOL.[3:0]).The correspondingpins must firstbe enabledintheGPIO module by settingthecorrespondingenablebitsintheGP Enable Register(GPEN.[7:4]),and configuringthem as inputsintheGP DirectionRegister(GPDIR.[7:4]). These interruptscan be controlledthroughtheGPIO module inadditiontothesimpleEXTPOL.[3:0] bits.Formore informationon interruptcontrolviatheGPIO module,see theTMS320C6000 ™ DSP General-PurposeInput/Output(GPIO)ReferenceGuide (literaturenumber SPRU584 ).

7.4 ExternalInterruptSources

The C6713/13B devicesupportsmany externalinterruptsourcesas indicatedinTable7-5.Controlofthe interruptsourceisdone by theassociatedmodule and ismade availableby enablingthecorresponding binaryinterruptselectorvalue(see Table 7-4 shaded rows).Because of pin multiplexingand module usage,notallexternalinterruptsourcesareavailableatthesame time.

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table7-5.ExternalInterruptSources and PeripheralModule Control PIN NAME INTERRUPT EVENT MODULE GP[15] GPINT0 GPIO GP[14] GPINT0 GPIO GP[13 GPINT0 GPIO GP[12] GPINT0 GPIO GP[11] GPINT0 GPIO GP[10] GPINT0 GPIO GP[9] GPINT0 GPIO GP[8] GPINT0 GPIO GP[7] GPINT0 orGPINT7 GPIO GP[6] GPINT0 orGPINT6 GPIO GP[5] GPINT0 orGPINT5 GPIO GP[4] GPINT0 orGPINT4 GPIO GP[3] GPINT0 GPIO GP[2] GPINT0 GPIO GP[1] GPINT0 GPIO GP[0] GPINT0 GPIO

7.5 EDMA Module and EDMA Selector

The C67x EDMA supportsup to 16 EDMA channels.Four of the 16 channels(channels8−11) are reservedforEDMA chaining,leaving12 EDMA channelsavailabletoserviceperipheraldevices. The EDMA selectorregistersthatcontroltheEDMA channelsservicingperipheraldevicesare locatedat addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selectorregisterscontrolthemapping oftheEDMA eventstotheEDMA channels.Each EDMA eventhas an assignedEDMA selectorcode (seeTable7-7).By loadingeach EVTSELx registerfieldwithan EDMA selectorcode,userscan map any desiredEDMA eventtoany specifiedEDMA channel.Table7-6liststhe defaultEDMA selectorvalueforeach EDMA channel. See Table7-8and Table7-11fortheEDMA EventSelectorregistersand theirassociatedbitdescriptions. Copyright© 2003–2009,Texas InstrumentsIncorporated REGISTER INFORMATION 63 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table7-6.EDMA Channels EDMA SELECTOR DEFAULT SELECTOREDMA CHANNEL DEFAULT EDMA EVENTCONTROL REGISTER VALUE (BINARY)

0 ESEL0[5:0] 000000 DSPINT

1 ESEL0[13:8] 000001 TINT0

2 ESEL0[21:16] 000010 TINT1

3 ESEL0[29:24] 000011 SDINT

4 ESEL1[5:0] 000100 GPINT4

5 ESEL1[13:8] 000101 GPINT5

6 ESEL1[21:16] 000110 GPINT6

7 ESEL1[29:24] 000111 GPINT7

8 — — TCC8 (Chaining) 9 — — TCC9 (Chaining) 10 — — TCC10 (Chaining) 11 — — TCC11 (Chaining)

12 ESEL3[5:0] 001100 XEVT0

13 ESEL3[13:8] 001101 REVT0

14 ESEL3[21:16] 001110 XEVT1

15 ESEL3[29:24] 001111 REVT1

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table7-7.EDMA Selector EDMA SELECTOR CODE EDMA EVENT MODULE(BINARY)

000000 DSPINT HPI

000001 TINT0 TIMER0

000010 TINT1 TIMER1

000011 SDINT EMIF

000100 GPINT4 GPIO

000101 GPINT5 GPIO

000110 GPINT6 GPIO

000111 GPINT7 GPIO

001000 GPINT0 GPIO

001001 GPINT1 GPIO

001010 GPINT2 GPIO

001011 GPINT3 GPIO

001100 XEVT0 McBSP0

001101 REVT0 McBSP0

001110 XEVT1 McBSP1

001111 REVT1 McBSP1

010000−011111 Reserved

100000 AXEVTE0 McASP0

100001 AXEVTO0 McASP0

100010 AXEVT0 McASP0

100011 AREVTE0 McASP0

100100 AREVTO0 McASP0

100101 AREVT0 McASP0

100110 AXEVTE1 McASP1

100111 AXEVTO1 McASP1

101000 AXEVT1 McASP1

101001 AREVTE1 McASP1

101010 AREVTO1 McASP1

101011 AREVT1 McASP1

101100 I2CREVT0 I2C0

101101 I2CXEVT0 I2C0

101110 I2CREVT1 I2C1

101111 I2CXEVT1 I2C1

110000 GPINT8 GPIO

110001 GPINT9 GPIO

110010 GPINT10 GPIO

110011 GPINT11 GPIO

110100 GPINT12 GPIO

110101 GPINT13 GPIO

110110 GPINT14 GPIO

110111 GPINT15 GPIO

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table7-8.EDMA Event SelectorRegisters(ESEL0 Register(0x01A0 FF00) 31 30 29 28 27 24 23 22 21 20 19 16 Reserved EVTSEL3 Reserved EVTSEL2 R –0 R/W −00 0011b R −0 R/W −00 0010b 15 14 13 12 11 8 7 6 5 4 3 0 Reserved EVTSEL1 Reserved EVTSEL0 R –0 R/W −00 0001b R −0 R/W −00 0000b Legend :R = Read only,R/W = Read/write,-n= valueatreset Table7-9.EDMA Event SelectorRegisters— ESEL1 Register(0x01A0 FF04) 31 30 29 28 27 24 23 22 21 20 19 16 Reserved EVTSEL7 Reserved EVTSEL6 R –0 R/W −00 0111b R −0 R/W −00 0110b 15 14 13 12 11 8 7 6 5 4 3 0 Reserved EVTSEL5 Reserved EVTSEL4 R –0 R/W −00 0101b R −0 R/W −00 0100b Legend :R = Read only,R/W = Read/write,-n= valueatreset Table7-10.EDMA Event SelectorRegisters— ESEL3 Register(0x01A0 FF0C) 31 30 29 28 27 24 23 22 21 20 19 16 Reserved EVTSEL15 Reserved EVTSEL14 R –0 R/W −00 1111b R −0 R/W −00 1110b 15 14 13 12 11 8 7 6 5 4 3 0 Reserved EVTSEL13 Reserved EVTSEL12 R –0 R/W −00 1101b R −0 R/W −00 1100b Legend :R = Read only,R/W = Read/write,-n= valueatreset Table7-11.EDMA Event SelectionRegisters(ESEL0, ESEL1, and ESEL3) Description BIT NO. NAME DESCRIPTION 31:30 23:22 Reserved Reserved.Read only,writeshave no effect.15:14 7:6 EDMA eventselectionbitsforchannelx.Allowsmapping oftheEDMA eventstotheEDMA channels. abc 29:24 The EVTSEL0 throughEVTSEL15 bitscorrespondtochannels0 to15,respectively.These EVTSELx 21:16 fieldsareuserselectable.By configuringtheEVTSELx fieldstotheEDMA selectorvalueofthedesiredEVTSELx13:8 EDMA synceventnumber (seeTable7-7),userscan map any EDMA eventtotheEDMA channel. 5:0 abc Forexample,ifEVTSEL15 isprogrammed to00 0001b (theEDMA selectorcode forTINT0),channel15 istriggeredby Timer0 TINT0 events.

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For□Use in□System /1,□/2, ...,□/32 ...,□/32 /1,□/2, PLL x4□to□x25 PLLEN□(PLL_CSR.[0]) ...,□/32 /1,□/2, /1,□/2, ...,□/32 /1,□/2, ...,□/32 (DSP□Core) SYSCLK1 (Peripherals) SYSCLK2 ECLKIN EKSRC□Bit (DEVCFG.[4]) EMIF SYSCLK3 CLKMODE0 (EMIF□Clock□Input) C6713/13B□DSPs PLLOUT PLLREF DIVIDER D0 OSCDIV1 DIVIDER□D1 DIVIDER□D2 DIVIDER□D3 ECLKOUT AUXCLK (Internal□Clock□Source to□McASP0□and□McASP1) 1□□□□0 PLLHV C2C1 EMI□filter +3.3 V 10 /c109F0 .1 /c109F D0EN□(PLLDIV0.[15]) ENA ENA OD1EN□(OSCDIV1.[15]) ENAENA ENAD1EN□(PLLDIV1.[15]) ENAD2EN□(PLLDIV2.[15]) ENAD3EN□(PLLDIV3.[15]) Reserved (A) (A) SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

8 PLL and PLL Controller

The 320C6713/13B includesa PLL and a flexiblePLL controllerperipheralconsistingofa prescaler(D0) and fourdividers(OSCDIV1, D1, D2, and D3).The PLL controllerisabletogeneratedifferentclocksfor differentpartsofthesystem (thatis,DSP core,peripheraldatabus,externalmemory interface,McASP, and otherperipherals).Figure8-1shows thePLL,thePLL controller,and theclockgeneratorlogic. A. DividersD1 and D2 must neverbe disabled.Never writea '0'totheD1EN orD2EN bitsinthePLLDIV1 and PLLDIV2 registers. B. PlaceallPLL externalcomponents (C1,C2, and theEMI filter)as closetotheC67x DSP deviceas possible.For the bestperformance,TI recommends thatallthe PLL externalcomponents be on a singlesideof the board without jumpers,switches,orcomponents otherthantheones shown. C. For reducedPLL jitter,maximize thespacingbetween switchingsignalsand thePLL externalcomponents (C1,C2, and theEMI filter). D. The 3.3-VsupplyfortheEMI filtermust be fromthesame 3.3-Vpower planesupplyingtheI/Ovoltage,DV DD . E. EMI filtermanufacturerTDK partnumber ACF451832-333,-223,-153,-103.Panasonicpartnumber EXCCET103U. Figure8-1.PLL and Clock GeneratorLogic Copyright© 2003–2009,Texas InstrumentsIncorporated PLL and PLL Controller 67 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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8.1 PLL Registers

The PLL resettimeistheamount ofwaittimeneeded when resettingthePLL (writingPLLRST = 1),for thePLL toproperlyreset,beforebringingthePLL outofreset(writingPLLRST = 0).For thePLL reset timevalue,see Table8-1.The PLL locktimeistheamount oftimefromwhen PLLRST = 0 withPLLEN = 0 (PLL outofreset,butstillbypassed)towhen thePLLEN bitcan be safelychanged to1 (switchingfrom bypasstothePLL path);see Table8-1and Figure8-1. Under some operatingconditions,themaximum PLL locktimemay varyfromthespecifiedtypicalvalue. ForthePLL locktimevalues,see Table8-1. Table8-1.PLL Lock and Reset Times MIN TYP MAX UNIT PLL locktime 75 187.5 μs PLL resettime 125 ns Table8-2 shows theC6713/13B deviceCLKOUT signals,how and by what registercontrolbitstheyare derived,and what isthedefaultsettings.For more detailson thePLL, see thePLL and ClockGenerator Logicdiagram(Figure8-1). Table8-2.CLKOUT Signals,DefaultSettings,and Control CLOCK OUTPUT DEFAULT SETTING CONTROL BIT(s) DESCRIPTIONSIGNAL NAME (ENABLED or DISABLED) (Register) D2EN = 1 (PLLDIV2.[15])CLKOUT2 ON (ENABLED) SYSCLK2 selected[default]CK2EN = 1 (EMIF GBLCTL.[3]) CLKOUT3 ON (ENABLED) OD1EN = 1 (OSCDIV1.[15]) DerivedfromCLKIN SYSCLK3 selected[default]. ON (ENABLED); EKSRC = 0 (DEVCFG.[4]) To selectECLKIN source:ECLKOUT derivedfromSYSCLK3 EKEN = 1 (EMIF GBLCTL.[5]) EKSRC = 1 (DEVCFG.[4])and EKEN = 1 (EMIF GBLCTL.[5]) The inputclock(CLKIN) isdirectlyavailableto the McASP modules as AUXCLK foruse as an internal high-frequencyclocksource.The inputclock(CLKIN) may alsobe divideddown by a programmable dividerOSCDIV1 (/1,/2,/3,...,/32)and outputon theCLKOUT3 pinforotheruse inthesystem. Figure8-1shows thattheinputclocksourcemay be divideddown by dividerPLLDIV0 (/1,/2,...,/32)and thenmultipliedup by a factorofx4,x5,x6,and so on,up tox25. Eitherthe inputclock(PLLEN = 0) or the PLL output(PLLEN = 1) then servesas the high-frequency referenceclockforthe restof the DSP system.The DSP core clock,the peripheralbus clock,and the EMIF clockmay be divideddown from thishigh-frequencyclock(each witha unique divider).For example,witha 30-MHz inputifthePLL outputisconfiguredfor450 MHz, theDSP coremay be operated at225 MHz (/2),whiletheEMIF may be configuredtooperateata rateof75 MHz (/6).Note thatthereis a specificminimum and maximum referenceclock(PLLREF) and outputclock(PLLOUT) forthe block labeledPLL inFigure8-1,as wellas fortheDSP core,peripheralbus,and EMIF. The clockgenerator must notbe configuredtoexceed any oftheseconstraints(certaincombinationsofexternalclockinput, internaldividers,and PLL multiplyratiosmightnotbe supported).See Table8-3forthePLL clocksinput and outputfrequencyranges.

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table8-3.PLL Clock Frequency Ranges (1)(2) CLOCK SIGNAL MIN MAX UNIT PLLREF (PLLEN = 1) 12 100 MHz PLLOUT 140 600 MHz SYSCLK1 — Devicespeed (DSP core) MHz SYSCLK3 (EKSRC = 0) — 100 MHz AUXCLK — 50(3) MHz (1) SYSCLK2 ratemust be exactlyhalfofSYSCLK1. (2) See alsotheElectricalSpecification(timingrequirementsand switchingcharacteristicsparameters)in theInputand OutputClockssectionofthisdatasheet. (3) When theMcASP module isnotused,theAUXCLK maximum frequencycan be any frequencyup to theCLKIN maximum frequency. The EMIF itselfmay be clockedby an externalreferenceclockviatheECLKIN pinor can be generated on-chipas SYSCLK3. SYSCLK3 isderivedfrom dividerD3 offof PLLOUT (see Figure8-1).The EMIF clockselectionisprogrammableviatheEKSRC bitintheDEVCFG register. The settingsforthe PLL multiplierand each of the dividersin the clockgenerationblockmay be reconfiguredviasoftwareatrun time.IfeithertheinputtothePLL changes due toD0, CLKMODE0, or CLKIN, orifthePLL multiplierischanged,thensoftwaremust enterbypass firstand stayinbypass until thePLL has had enough timetolock(seeelectricalspecifications).For theprogrammingprocedure,see theTMS320C6000 ™ DSP Software-ProgrammablePhase-LockedLoop (PLL)ControllerReferenceGuide (literaturenumber SPRU233 ). SYSCLK2 is the internalclocksource forperipheralbus control.SYSCLK2 (DividerD2) must be programmed tobe halfoftheSYSCLK1 rate.For example,ifD1 isconfiguredtodivide-by-2mode (/2), thenD2 must be programmed todivide-by-4mode (/4).SYSCLK2 isalsotieddirectlytoCLKOUT2 pin (seeFigure8-1). Duringthe programming transitionof DividerD1 and DividerD2 (resultinginSYSCLK1 and SYSCLK2 outputclocks,see Figure8-1),the orderof programming the PLLDIV1 and PLLDIV2 registersmust be observedtoensurethatSYSCLK2 alwaysrunsathalftheSYSCLK1 rateor slower.For example,ifthe dividerratiosofD1 and D2 aretobe changed from/1,/2(respectively)to/5,/10(respectively)then,the PLLDIV2 registermust be programmed beforethePLLDIV1 register.The transitionratiosbecome /1,/2; /1,/10;and then/5,/10.IfthedividerratiosofD1 and D2 aretobe changed from/3,/6to/1,/2,thenthe PLLDIV1 registermust be programmed beforethePLLDIV2 register.The transitionratios,forthiscase, become /3,/6;/1,/6;and then/1,/2.The finalSYSCLK2 ratemust be exactlyhalfoftheSYSCLK1 rate. Note thatDividerD1 and DividerD2 must always be enabled(thatis,D1EN and D2EN bitsaresetto1 in thePLLDIV1 and PLLDIV2 registers). The PLL Controllerregistersshouldbe modifiedonlyby theCPU orviaemulation.The HPI shouldnot be used todirectlyaccessthePLL Controllerregisters. For detailedinformationon theclockgenerator(PLL Controllerregisters)and theassociatedsoftwarebit descriptions,see Table8-4throughTable8-11. Copyright© 2003–2009,Texas InstrumentsIncorporated PLL and PLL Controller 69 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table8-4.PLL Control/StatusRegister(PLLCSR) (0x01B7 C100) 31 28 27 24 23 20 19 16 Reserved R-0 15 12 11 8 7 6 5 4 3 2 1 0 Reserved Stable Reserved PLLRS Reserv PLLPWRD PLLEN T ed N R-0 R –x R-0 RW −1 R/W −0 R/W −0b RW −0 Legend :R = Read only,R/W = Read/write,-n= valueatreset Table8-5.PLL Control/StatusRegister(PLLCSR) Description BIT NO. NAME DESCRIPTION 31:7 Reserved Reserved.Read only,writeshave no effect. Clockinputstable.Thisbitindicatesiftheclockinputhas stabilized. 6 STABLE 0: Clockinputnotyetstable.Clockcounterisnotfinishedcounting(default). 1: Clockinputstable 5:4 Reserved Reserved.Read only,writeshave no effect. AssertsRESET toPLL

3 PLLRST 0: PLL resetreleased

1: PLL resetasserted(default) 2 Reserved Reserved.The usermust writea 0 tothisbit. SelectPLL power down

1 PLLPWRDN 0: PLL operational(default)

1: PLL placedinpower-down state PLL mode enable 0: Bypass mode (default).PLL disabledDividerD0 and PLL arebypassed. 0 PLLEN SYSCLK1/SYSCLK2/SYSCLK3 aredivideddown directlyfrominputreferenceclock. 1: PLL enabledDividerD0 and PLL arenotbypassed.SYSCLK1/SYSCLK2/SYSCLK3 are divideddown fromPLL output. Table8-6.PLL Multiplier(PLLM) ControlRegister(0x01B7 C110) 31 28 27 24 23 20 19 16 Reserved R-0 15 12 11 8 7 5 4 0 Reserved PLLM R-0 R/W −0 0111 Legend :R = Read only,R/W = Read/write,-n= valueatreset

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table8-7.PLL Multiplier(PLLM) ControlRegisterDescription BIT NO. NAME DESCRIPTION 31:5 Reserved Reserved.Read only,writeshave no effect. PLL multiplymode [defaultisx7 (00111)] 00000 = Reserved 10000 = x16 00001 = Reserved 10001 = x17 00010 = Reserved 10010 = x18 00011 = Reserved 10011 = x19 00100 = x4 10100 = x20 00101 = x5 10101 = x21 00110 = x6 10110 = x22 00111 = x7 10111 = x23 4:0 PLLM 01000 = x8 11000 = x24 01001 = x9 11001 = x25 01010 = x10 11010 = Reserved 01011 = x11 11011 = Reserved 01100 = x12 11100 = Reserved 01101 = x13 11101 = Reserved 01110 = x14 11110 = Reserved 01111 = x15 11111 = Reserved PLLM selectvalues00000 through00011 and 11010 through11111 arenotsupported. Table8-8.PLL Wrapper Dividerx Registers(PLLDIV0,PLLDIV1, PLLDIV2, and PLLDIV3) (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively) 31 28 27 24 23 20 19 16 Reserved R-0 15 14 12 11 8 7 5 4 0 DxEN Reserved PLLDIVx R/W −1 R −0 R/W −x xxxx(1) Legend :R = Read only,R/W = Read/write,-n= valueatreset (1) DefaultvaluesforthePLLDIV0,PLLDIV1,PLLDIV2,and PLLDIV3 bitsare/1(00000),/1(00000),/2(00001),and /2(00001), respectively. CAUTION D1 and D2 should never be disabled.D3 should onlybe disabledifECLKIN isused. Table8-9.PLL Wrapper Dividerx Registers (PrescalerDividerD0 and Post-ScalerDividersD1, D2, and D3) Description(1) BIT NO. NAME DESCRIPTION 31:16 Reserved Reserved.Read only,writeshave no effect. DividerDx enable(wherex denotes0 through3). 0: Dividerx disabled.No clockoutput

15 DxEN

1: Dividerx enabled(default) These divider-enablebitsaredevicespecificand must be setto1 toenable. 14:5 Reserved Reserved.Read only,writeshave no effect. (1) Note thatSYSCLK2 must runathalftherateofSYSCLK1. Therefore,thedividerratioofD2 must be two timesslowerthanD1. For example,ifD1 issetto/2,thenD2 must be setto/4. Copyright© 2003–2009,Texas InstrumentsIncorporated PLL and PLL Controller 71 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table8-9.PLL Wrapper Dividerx Registers (PrescalerDividerD0 and Post-ScalerDividersD1, D2, and D3) Description(1) (continued) BIT NO. NAME DESCRIPTION PLL dividerratio(defaultvaluesforthePLLDIV0,PLLDIV1,PLLDIV2,and PLLDIV3 bitsare/1,/1,/2, and /2,respectively). 00000 = /1 10000 = /17 00001 = /2 10001 = /18 00010 = /3 10010 = /19 00011 = /4 10011 = /20 00100 = /5 10100 = /21 00101 = /6 10101 = /22 00110 = /7 10110 = /23 4:0 PLLDIVx 00111 = /8 10111 = /24 01000 = /9 11000 = /25 01001 = /10 11001 = /26 01010 = /11 11010 = /27 01011 = /12 11011 = /28 01100 = /13 11100 = /29 01101 = /14 11101 = /30 01110 = /15 11110 = /31 01111 = /16 11111 = /32 Table8-10.OscillatorDivider1 (OSCDIV1) Register(0x01B7 C124) 31 28 27 24 23 20 19 16 Reserved R-0 15 14 12 11 8 7 5 4 0 OD1EN Reserved OSCDIV1 R/W −1 R −0 R/W −0 0111 Legend :R = Read only,R/W = Read/write,-n= valueatreset

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table8-11.OscillatorDivider1 (OSCDIV1) RegisterDescription BIT NO. NAME DESCRIPTION 31:16 Reserved Reserved.Read-only;writeshave no effect. OscillatorDivider1 enable.

15 OD1EN 0: OscillatorDivider1 disabled

1: OscillatorDivider1 enabled(default) 14:5 Reserved Reserved.Read only,writeshave no effect. OscillatorDivider1 ratio[defaultis/8(00111)] 00000 = /1 10000 = /17 00001 = /2 10001 = /18 00010 = /3 10010 = /19 00011 = /4 10011 = /20 00100 = /5 10100 = /21 00101 = /6 10101 = /22 00110 = /7 10110 = /23 4:0 OSCDIV1 00111 = /8 10111 = /24 01000 = /9 11000 = /25 01001 = /10 11001 = /26 01010 = /11 11010 = /27 01011 = /12 11011 = /28 01100 = /13 11100 = /29 01101 = /14 11101 = /30 01110 = /15 11110 = /31 01111 = /16 11111 = /32 Copyright© 2003–2009,Texas InstrumentsIncorporated PLL and PLL Controller 73 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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9 MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS

The 320C6713/13B deviceincludestwo multichannelaudio serialport(McASP) interfaceperipherals (McASP1 and McASP0). The McASP is a serialportoptimizedforthe needs of multichannelaudio applications.With two McASP peripherals,the 320C6713/13B device is capable of supportingtwo completelyindependentaudiozones simultaneously. Each McASP consistsof a transmitand receivesection.These sectionscan operate completely independentlywith differentdata formats,separatemaster clocks,bitclocks,and frame syncs or alternatively,thetransmitand receivesectionsmay be synchronized.Each McASP module alsoincludes a poolof 16 shiftregistersthatmay be configuredto operateas eithertransmitdata,receivedata,or general-purposeI/O(GPIO). The transmitsectionof the McASP can transmitdata in eithera time divisionmultiplexed(TDM) synchronousserialformator ina digitalaudiointerface(DIT)formatwhere thebitstreamisencoded for S/PDIF,AES-3, IEC-60958,and CP-430 transmission.The receivesectionof the McASP supportsthe TDM synchronousserialformat. Each McASP can supportone transmitdataformat(eithera TDM formatorDIT format)and one receive formatat a time.Alltransmitshiftregistersuse the same formatand allreceiveshiftregistersuse the same format.However,thetransmitand receiveformatsneed notbe thesame. Both the transmitand receivesectionsof the McASP also supportburstmode, which is usefulfor non-audiodata(forexample,passingcontrolinformationbetween two DSPs). The McASP peripheralshave additionalcapabilityfor flexibleclock generation,and error detection/handling,as wellas errormanagement.

9.1 McASP Block Diagram

Figure9-1 shows the major blocksalong withexternalsignalsof the 320C6713/13B McASP1 and McASP0 peripherals,and shows the eightserialdata [AXR] pinsforeach McASP. Each McASP also includesfullgeneral-purposeI/O(GPIO) control,so any pinsnotneeded forserialtransferscan be used forgeneral-purposeI/O.

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Clock□Check Transmit Generator Clock Transmit ACLKX0 AHCLKX0 DIT RAM Transmit Generator Frame□Sync AFSX0 Detect Error Receive Frame□Sync GeneratorFormatter Transmit Data AMUTE0 AMUTEIN0AFSR0 Serializer□0 Serializer□1 Serializer□3 Serializer□2 Serializer□6 Serializer□7 Serializer□5 Serializer□4 (High- Frequency) Receive Clock□Check (High- Frequency) Receive Formatter Data Formatter Data Receive Serializer□4 Serializer□3 Serializer□7 Serializer□6 Serializer□5 Serializer□0 Serializer□1 Frame□Sync Generator Receive Frame□Sync Generator Transmit Transmit Generator Receive Generator Serializer□2 Error Transmit Formatter Data Clock□Check Frequency) (High- Receive Detect Frequency) Clock□Check (High- Transmit RAM DIT AMUTE1 AFSR1 ACLKR1 AMUTEIN1 AHCLKR1 Clock AFSX1 ACLKX1 AHCLKX1 Clock AXR1[0] AXR1[1] AXR1[3] AXR1[2] AXR1[6] AXR1[7] AXR1[5] AXR1[4] McASP0 McASP1 DMA Transmit DMA Transmit DMA Receive DMA Receive INDIVIDUAL LY PROGRAMMABLE□TX/RX/GPI O INDIVIDUAL LY PROGRAMMABLE□TX/RX/GPI O Control GPIO Control GPIO AXR0[0] AXR0[1] AXR0[3] AXR0[2] AXR0[6] AXR0[7] AXR0[5] AXR0[4] SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure9-1.McASP0 and McASP1 Configuration Copyright© 2003–2009,Texas InstrumentsIncorporated MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS 75 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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9.2 MultichannelTime DivisionMultiplexed(TDM) Synchronous TransferMode

The McASP supportsa multichannelTDM synchronoustransfermode forboth transmitand receive. Withinthistransfermode, a widevarietyofserialdataformatsaresupported,includingformatscompatible withdevicesusingtheInter-IntegratedSound (IIS)protocol. TDM synchronoustransfermode istypicallyused when communicatingbetween integratedcircuits,such as between a DSP and one or more ADC, DAC, codec,or S/PDIF receiverdevices.In multichannel applications,itistypicaltofindseveraldevicesoperatingsynchronizedwitheach other.For example,to providesixanalogoutputs,threestereoDAC deviceswould be drivenwiththesame bitclockand frame sync,buteach stereoDAC would use a differentMcASP serialdatapincarryingstereodata(twoTDM timeslots,leftand right). The TDM synchronousserialtransfermode utilizesseveralcontrolsignalsand one or more serialdata signals:

A bitclocksignal(ACLKX fortransmit,ACKLR forreceive)
A framesyncsignal(AFSX fortransmit,AFSR forreceive)
An (optional)high-frequencymasterclock(AHCLKX fortransmit,AHCLKR forreceive)fromwhichthe bitclockisderived
One ormore serialdatapins(AXR fortransmitand forreceive) Except forthe optionalhigh-frequencymaster clock,allof the signalsin the TDM synchronousserial transfermode protocolaresynchronoustothebitclocks(ACLKX and ACLKR). IntheTDM synchronoustransfermode, theMcASP continuallytransmitsand receivesdataperiodically (sinceaudioADCs and DACs operateata fixed-datarate).The dataisorganizedintoframes,and the beginningofa frameismarked by a framesyncpulseon theAFSX, AFSR pin. Ina typicalaudiosystem,one frame istransferredper sample period.To supportmultiplechannels,the choicesaretoeitherincludemore timeslotsperframe(andthereforeoperatewitha higherbitclock)orto keep thebitclockperiodconstantand use additionaldatapinstotransferthesame number ofchannels. For example,a particularsix-channelDAC mightrequirethreeMcASP serialdatapins;transferringtwo channelsofdataon each serialdatapinduringeach sample period(frame).AnothersimilarDAC may be designedtouse onlya singleMcASP serialdatapin,butclockedthreetimesfasterand transferringsix channelsofdataper sample period.The McASP isflexibleenough tosupporteithertypeofDAC, buta transmittercannotbe configuredtodo bothatthesame time. For multiprocessorapplications,theMcASP supportsany number oftimeslotsperframe(between2 and 32),and includestheabilitytodisabletransfersduringspecifictimeslots. In addition,to supportS/PDIF, AES-3, IEC-60958,and CP-430 receiverchipswhose naturalblock (McASP frame)sizeis384 samples;theMcASP receiversupportsa 384 timeslotmode. The advantage tousingthe384 timeslotmode isthatinterruptsmay be generatedsynchronoustotheS/PDIF,AES-3, IEC-60958,and CP-430 receivers;forexample,thelastslotinterrupt.

9.3 BurstTransferMode

The McASP alsosupportsa bursttransfermode, whichisusefulfornon-audiodata(forexample,passing controlinformationbetween two DSPs). Bursttransfermode uses a synchronousserialformatsimilarto TDM, except the frame sync is generatedforeach data word transferred.In addition,frame sync generationisnotperiodicortimedrivenas inTDM mode, butratherdatadriven.

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9.4 Supported BitStream Formats forTDM and BurstTransferModes

The serialdatapinssupporta wide varietyofformats.IntheTDM and burstsynchronousmodes, thedata may be transmitted/receivedwiththefollowingoptions:

Time slotsperframe:1 (burst/datadriven),or2,3...32(TDM/timedriven)
Time slotsize:8,12,16,20,24,28,32 bitspertimeslot
Data size:8,12,16,20,24,28,32 bits(mustbe lessthanorequaltotimeslot)
Data alignmentwithintimeslot:leftorrightjustified
Bitorder:MSB orLSB first
Unused bitsintimeslot:Padded with0,1 orextendedwithvalueofanotherbit
Time slotdelayfromframesync:0-,1-,or2-bitdelay The data formatcan be programmed independentlyfortransmitand receive,and forMcASP0 versus McASP1. In addition,the McASP can automaticallyrealignthe data as processednativelyby the DSP (anyformaton a nibbleboundary)adjustingthedatainhardwaretoany ofthesupportedserialbitstream formats(TDM, burst,and DIT modes).Thisadjustmentreducestheamount ofbitmanipulationthatthe DSP must performand simplifiessoftwarearchitecture.

9.5 DigitalAudio InterfaceTransmitter(DIT)TransferMode (TransmitterOnly)

The McASP transmitsectionmay alsobe configuredinDIT mode where itoutputsdata formattedfor transmissionoveran S/PDIF,AES-3, IEC-60958,or CP-430 standardlink.These standardsencode the serialdatasuch thattheequivalentofclockand frame sync are embedded withinthedatastream.DIT transfermode isused as an interconnectbetween audiocomponents and can transfermultichanneldigital audiodataovera singleopticalorcoaxialcable. From an internalDSP standpoint,theMcASP operationinDIT transfermode issimilartothetwo-time-slot TDM mode, but the data transmittedisoutputas a bi-phasemark encoded bitstream withpreamble, channelstatus,user data,validity,and parityautomaticallystuffedintothe bitstream by the McASP module.The McASP includesseparatevaliditybitsforeven/oddsubframesand two 384-bitregisterfile modules toholdchannelstatusand userdatabits. DIT mode requires(ata minimum):

One serialdatapin(iftheAUXCLK isused as thereference(seeFigure8-1) OR
One serialdatapinpluseithertheAHCLKX orACLKX pin(ifan externalclockisneeded) Ifadditionalserialdatapinsareused,each McASP may be used totransmitmultipleencoded bitstreams (one per pin).However, the bitstreamswillallbe synchronizedto the same clockand the user data, channelstatus,and validityinformationcarriedby each bitstream willbe the same forallbitstreams transmittedby thesame McASP module. The McASP can alsoautomaticallyrealignthe data as processedby the DSP (any formaton a nibble boundary)in DIT mode; reducingthe amount of bitmanipulationthatthe DSP must perform and simplifyingsoftwarearchitecture. Copyright© 2003–2009,Texas InstrumentsIncorporated MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS 77 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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9.6 McASP FlexibleClock Generators

The McASP transmitand receiveclockgeneratorsare identical.Each clockgeneratorcan accept a high-frequencymasterclockinput(ontheAHCLKX and AHCLKR pins). The transmitand receivebitclocks(on theACLKX and ACLKR pins)can alsobe sourcedexternallyor can be sourcedinternallyby dividingdown thehigh-frequencymasterclockinput(programmablefactor/1, The frame sync pinsare AFSX (transmit)and AFSR (receive).A typicalusage forthesepinsistocarry the left-rightclock(LRCLK) signalwhen transmittingand receivingstereodata.The frame sync signals areindividuallyprogrammableforeitherinternalorexternalgeneration,eitherbitorslotlength,and either risingorfallingedge polarity. Some examplesofthethingsthata systemdesignercan use theMcASP clockingflexibilityforare:

Inputa high-frequencymasterclock(forexample,512 fS ofthereceiver)and receivewithan internally generatedbitclockratioof/8,whiletransmittingwithan internallygeneratedbitclockratioof/4or/2. (An example applicationwould be to receivedata from a DVD at 48 kHz but outputup-sampledor decoded audioat96 kHz or192 kHz.)
Transmit/receivedatabased on sample rate(forexample,44.1kHz) usingMcASP0 whiletransmitting and receivingata differentsample rate(forexample,48 kHz)on McASP1.
Use theDSP on-boardAUXCLK tosupplythesystemclockwhen theinputsourceisan A/D converter.

9.7 McASP ErrorHandlingand Management

To supportthedesignofa robustaudiosystem,theMcASP module includeserror-checkingcapabilityfor the serialprotocol,data underrun,and data overrun.In addition,each McASP includesa timerthat continuallymeasures thehigh-frequencymasterclockevery32 SYSCLK2 clockcycles.The timervalue can be read to get a measurement of the high-frequencymaster clockfrequencyand has a min-max rangesettingthatcan raisean errorflagifthehigh-frequencymasterclockgoes outofa specifiedrange. The userwould readthehigh-frequencytransmitmasterclockmeasurement (AHCLKX0 orAHCLKX1) by readingthe XCNT fieldof the XCLKCHK registerand the user would read the high-frequencyreceive master clockmeasurement (AHCLKR0 or AHCLKR1) by readingthe RCNT fieldof the RCLKCHK register. Upon thedetectionofany one or more oftheabove errors(softwareselectable)or theassertionofthe AMUTE_IN pin,theAMUTE outputpinmay be assertedtoa highorlow level(selectable)toimmediately mute theaudiooutput.Inaddition,an interruptmay be generatedifenabledbased on any one ormore of theerrorsources.

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9.8 McASP Interruptsand EDMA Events

The McASP transmitterand receiversectionseach generatean eventon everytimeslot.Thiseventcan be servicedby an interruptorby theEDMA controller. When usinginterruptstoservicetheMcASP, each shiftregisterbufferhas a uniqueaddressintheMcASP registersspace (seeTable4-1). When usingthe EDMA to servicethe McASP, the McASP DATA Portspace,shown in Table 4-1, is accessed.Inthiscase,theaddressleast-significantbitsare ignored.Writestoany addressinthisrange access thetransmittingbuffersinorderfrom lowest(serializer0) tohighest(serializer15),skippingover disabledand receivingserializers.Likewise,reads from any addressinthisspace access the receiving buffersinthesame orderbutskipoverdisabledand transmittingbuffers.

9.9 I2C

Having two I2C modules on the320C6713/13B simplifiessystem architecture,sinceone module may be used by the DSP to controllocalperipheralsICs (DACs, ADCs, etc.)whilethe othermay be used to communicatewithothercontrollersina systemortoimplementa userinterface. NOTE I2C portsarecompatiblewithPhilipsI2C SpecificationRevision2.1(January2000). The 320C6713/13B alsoincludestwo I2C serialportsforcontrolpurposes.Each I2C portsupports:

Fastmode up to400 Kbps (nofail-safeI/Obuffers)
Noisefiltertoremove noise50 ns orless
7-and 10-bitdeviceaddressingmodes
Master(transmit/receive)and slave(transmit/receive)functionality
Events:DMA, interrupt,orpolling
Slew-ratelimitedopen-drainoutputbuffers Figure9-2shows a blockdiagramoftheI2Cxmodule. Copyright© 2003–2009,Texas InstrumentsIncorporated MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS 79 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

From□PLL Clock□Generator I2CCLKHx Generator Bit□Clock I2CCLKLx Noise FilterI2C□Clock SCL I2CXSRx I2CDXRx Transmit Transmit Shift Transmit Buffer I2CDRRx ShiftI2CRSRx Receive Buffer Receive Receive Filter SDA I2C□Data Noise I2COARx I2CSARx Slave Address Control Address OwnI2CMDRx I2CCNTx Mode Data Count Source Interrupt Interrupt Status I2CISRCx I2CSTRx Enable InterruptI2CIERx Interrupt/DMA I2Cx□Module NOTE:□Shading□denotes□control/status□registers. SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure9-2.I2Cx Module Block Diagram

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10 LOGIC AND POWER SUPPLY

This sectiondiscusses the logicand power-supplyconfigurationof the SM320C6713-EP and SM320C6713B-EP.

10.1 General-PurposeInput/Output(GPIO)

To use theGP[15:0]software-configurableGPIO pins,theGPxEN bitsintheGP enable(GPEN) register and theGPxDIR bitsintheGP direction(GPDIR) registermust be properlyconfigured. GPxEN = 1 GP[x]pinisenabled. GPxDIR = 0 GP[x]pinisan input. GPxDIR = 1 GP[x]pinisan output. where x representsone ofthe15 through0 GPIO pins. Figure10-1 shows theGPIO enablebitsintheGPEN registerfortheC6713/13B device.To use any of theGPx pinsas general-purposeinput/outputfunctions,thecorrespondingGPxEN bitmust be setto1 (enabled).Defaultvalues are device-specific,so referto Figure 10-1 for the C6713/13B default configuration. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 GP15EN GP14EN GP13EN GP12EN GP11EN GP10EN GP9EN GP8EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 GP7EN GP6EN GP5EN GP4EN GP3EN GP2EN GP1EN GP0EN R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 Legend :R/W = Readable/Writeable;-n = valueafterreset,-x= undefinedvalueafterreset Figure10-1.GPIO Enable (GPEN) Register(Hex Address: 01B0 0000) Figure 10-2 shows the GPIO directionbitsin the GPIO Direction(GPDIR) register.This register determinesifa givenGPIO pinisan inputoran outputprovidingthecorrespondingGPxEN bitisenabled (setto1)intheGPEN register.By default,alltheGPIO pinsareconfiguredas inputpins. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 GP15DIR GP14DIR GP13DIR GP12DIR GP11DIR GP10DIR GP9DIR GP8DIR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 GP7DIR GP6DIR GP5DIR GP4DIR GP3DIR GP2DIR GP1DIR GP0DIR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend :R/W = Readable/Writeable;-n = valueafterreset,-x= undefinedvalueafterreset Figure10-2.GPIO Direction(GPDIR) Register(Hex Address: 01B0 0004) Copyright© 2003–2009,Texas InstrumentsIncorporated LOGIC AND POWER SUPPLY 81 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

Internal Clock□Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET PD3 Internal Peripherals Clock and□Dividers Distribution 320C6713/13B CLKOUT2 SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com For more detailedinformationon general-purposeinputs/outputs(GPIOs),see the TMS320C6000 DSP General-PurposeInput/Output(GPIO)ReferenceGuide (literaturenumber SPRU584 ).

10.2 Power-Down Mode Logic

Figure10-3shows thepower-down mode logicon theC6713/13B. A. Externalinputclocks,withtheexceptionofCLKIN and CLKOUT3, arenotgatedby thepower-down mode logic. Figure10-3.Power-Down Mode Logic

10.2.1 Triggering,Wake-Up, and Effects

The deviceincludesa programmablePLL whichallowssoftwarecontrolofPLL bypass viathePLLEN bit in the PLLCSR register.With thisenhanced functionalitycome some additionalconsiderationswhen enteringpower-down modes. The power-down modes (PD2 and PD3) functionby disablingthePLL tostopclockstotheC6713 device. However, ifthePLL isbypassed (PLLEN = 0),thedevicewillstillreceiveclocksfrom theexternalclock input(CLKIN).Therefore,bypassingthePLL makes thepower-down modes PD2 and PD3 ineffective. The PLL needs tobe enabledby writinga “1”toPLLEN bit(PLLCSR.0) beforebeingabletoentereither PD3 (CSR.11)orPD2 (CSR.10)inorderforthesemodes tohave an effect. For theTMS320C6713B deviceitisrecommended touse thePLLPWDN bit(PLLCSR.1) toentera deep power−down stateequivalenttoPD3 sincethePLLPWDN bittakesfulladvantageofthePLL power−down feature. The power-down modes (PD1,PD2 and PD3) and theirwake-up methods areprogrammed by settingthe PWRD field(bits15−10) of the controlstatusregister(CSR). The PWRD fieldof the CSR isshown in Figure10-4 and describedinTable10-1.When writingtotheCSR, allbitsofthePWRD fieldshouldbe setatthesame time.Logic0 shouldbe used when writingtothereservedbit(bit15)ofthePWRD field. The CSR isdiscussedindetailintheTMS320C6000 CPU and InstructionSet ReferenceGuide (literature number SPRU189 ).

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 31 16 15 14 13 12 11 10 9 8 Enableor EnabledReserved Non-Enabled PD3 PD2 PD1InterruptWakeInterruptWake R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 0 Legend: R/W-x = Read/writeresetvalue Figure10-4.PWRD FieldoftheCSR A delayof up to nineclockcyclesmay occurafterthe instructionthatsetsthe PWRD bitsinthe CSR beforethePD mode takeseffect.As bestpractice,NOPs shouldbe padded afterthePWRD bitsaresetin theCSR toaccountforthisdelay. IfPD1 mode isterminatedby a non-enabledinterrupt,the program executionreturnsto the instruction where PD1 tookeffect.IfPD1 mode isterminatedby an enabledinterrupt,theinterruptserviceroutinewill be executedfirst,thentheprogram executionreturnstotheinstructionwhere PD1 tookeffect.Inthecase withan enabledinterrupt,theGIE bitintheCSR and theNMIE bitintheinterruptenableregister(IER) must alsobe setfortheinterruptserviceroutinetoexecute;otherwise,executionreturnstotheinstruction where PD1 tookeffectupon PD1 mode terminationby an enabledinterrupt. PD2 and PD3 modes can onlybe abortedby devicereset.Table10-1 summarizes allthepower-down modes. Table10-1.CharacteristicsofthePower-Down Modes PRWD FIELD POWER-DOWN WAKE-UP METHOD EFFECT ON CHIP OPERATION(BITS15−10) MODE

000000 No power down — —

Wake by an enabled CPU halted(exceptfortheinterruptlogic)001001 PD1 interrupt Power-down mode blockstheinternalclockinputsatthe boundaryoftheCPU, preventingmost oftheCPU logicfrom Wake by an enabledor switching.DuringPD1, EDMA transactionscan proceed010001 PD1 non-enabledinterrupt between peripheralsand internalmemory. OutputclockfromPLL ishalted,stoppingtheinternalclock structurefromswitchingand resultingintheentirechipbeing 011010 PD2 (1) Wake by a devicereset halted.Allregisterand internalRAM contentsarepreserved. AllfunctionalI/Ofreezeinthelaststatewhen thePLL clockis turnedoff. InputclocktothePLL stopsgeneratingclocks.Allregisterand internalRAM contentsarepreserved.AllfunctionalI/Ofreeze inthelaststatewhen thePLL clockisturnedoff.Following reset,thePLL needs timetorelock,justas itdoes following011100 PD3 (1) Wake by a devicereset power up.Wake-up fromPD3 takeslongerthanwake-up from PD2 because thePLL needs tobe relocked,justas itdoes followingpower up.Itisrecommended touse thePLLPWDN bit(PLLCSR.1)as an alternativetoPD3. Allothers Reserved — — (1) When enteringPD2 and PD3, allfunctionalI/Osremaininthepreviousstate.However,forperipheralsthatareasynchronousinnature orperipheralswithan externalclocksource,outputsignalsmay transitioninresponsetostimuluson theinputs.Under theseconditions, peripheralswillnotoperateaccordingtospecifications.

10.3 Power-Supply Sequencing

TIDSPs do notrequirespecificpower sequencingbetween thecoresupplyand theI/Osupply.However, systems shouldbe designedto ensure thatneithersupplyispowered up forextendedperiodsof time (>1 second)iftheothersupplyisbelowtheproperoperatingvoltage. Copyright© 2003–2009,Texas InstrumentsIncorporated LOGIC AND POWER SUPPLY 83 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

I/O□Supply Core□Supply GND SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com

10.3.1 System-LevelDesign Considerations

System-leveldesign considerations,such as bus contention,may requiresupply sequencing to be implemented.Inthiscase,thecoresupplyshouldbe powered up before,and powered down after,theI/O buffers.ThisistoensurethattheI/Obuffersreceivevalidinputsfrom thecorebeforetheoutputbuffers arepowered up,thuspreventingbus contentionwithotherchipson theboard.

10.3.2 Power-Supply Design Considerations

A dual-powersupplywithsimultaneoussequencingcan be used toeliminatethedelaybetween coreand I/Opower up.A Schottkydiodecan alsobe used totiethecorerailtotheI/Orail(seeFigure10-5). Figure10-5.SchottkyDiode Diagram Core and I/Osupplyvoltageregulatorsshouldbe locatedclosetotheDSP (orDSP array)tominimize inductanceand resistanceinthepower deliverypath.Additionally,when designingforhigh-performance applicationsutilizingtheC6000 platformofDSPs, theprintedcircuitboard(PCB) shouldincludeseparate power planesforcore,I/O,and ground,allbypassedwithhigh-qualitylow-ESL/ESR capacitors.

10.4 Power-Supply Decoupling

To properlydecouplethesupplyplanesfrom system noise,placeas many capacitors(caps)as possible closetotheDSP. Assuming 0603 caps,theusershouldbe abletofita totalof60 caps— 30 forthecore supplyand 30 fortheI/Osupply.These caps need tobe close(nomore than1.25-cmmaximum distance) to the DSP to be effective.Physicallysmallercaps are better,such as 0402, but the sizeneeds to be evaluatedfrom a yield/manufacturingpoint-of-view.Parasiticinductancelimitsthe effectivenessof the decouplingcapacitors;therefore,physicallysmallercapacitorsshould be used whilemaintainingthe largestavailablecapacitancevalue.As withthe selectionof any component, verificationof capacitor availabilityovertheproduct’s productionlifetimeneeds tobe considered. 10.5 IEEE Std 1149.1JTAG CompatibilityStatement The 320C6713/13B DSP requiresthatbothTRST and RESET resetsbe assertedupon power up tobe properlyinitialized.WhileRESET initializestheDSP core,TRST initializestheDSP emulationlogic.Both resetsarerequiredforproperoperation. NOTE TRST issynchronousand must be clockedby TCLK; otherwise,BSCAN may notrespond as expectedafterTRST isasserted.

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 WhilebothTRST and RESET need tobe assertedupon power-up,onlyRESET needs tobe releasedfor theDSP tobootproperly.TRST may be assertedindefinitelyfornormaloperation,keepingtheJTAG port interfaceand DSP emulationlogicintheresetstate. TRST onlyneeds to be releasedwhen itisnecessaryto use a JTAG controllerto debug the DSP or exercisetheDSP boundaryscan functionality. The TMS320C6713B DSP includesan internalpulldown(IPD)on theTRST pintoensurethatTRST will always be assertedupon power up and the DSP ’s internalemulationlogicwillalways be properly initializedwhen thispinisnotroutedout.JTAG controllersfrom Texas InstrumentsactivelydriveTRST high.However, some third-partyJTAG controllersmay not driveTRST highbut expectthe use of an externalpullupresistoron TRST. When usingthistypeofJTAG controller,assertTRST toinitializethe DSP afterpowerup and externallydriveTRST highbeforeattemptingany emulationor boundary scan operations. FollowingthereleaseofRESET, thelow-to-hightransitionofTRST must be “seen” tolatchthestateof EMU1 and EMU0. The EMU[1:0]pinsconfigurethedeviceforeitherboundaryscan mode or emulation mode. Formore detailedinformation,see theterminalfunctionssectionofthisdatasheet. NOTE Note: The DESIGN −WARNING sectionof the TMS320C6713B BSDL filecontains informationand constraintsregardingproperdeviceoperationwhilein boundary scan mode. For more detailedinformationon theC6713B JTAG emulation,see theTMS320C6000 DSP Designingfor JTAG EmulationReferenceGuide (literaturenumber SPRU641 ).

10.6 EMIF Device Speed

The maximum EMIF speed on the C6713/13B deviceis100 MHz. TI recommends utilizingI/O buffer informationspecification(IBIS)to analyzeallac timingsto determineifthe maximum EMIF speed is achievablefora givenboard layout.To properlyuse IBISmodels toattainaccuratetiminganalysisfora given system, see the applicationreportUsing IBIS Models forTiming Analysis(literaturenumber SPRA839 ). For ease of design evaluation,Table 10-2 containsIBIS simulationresultsshowing the maximum EMIF-SDRAM interfacespeeds forthegivenexample boards(TYPE) and SDRAM speed grades.Timing analysisshouldbe performedto verifythatallac timingsare met forthe specifiedboard layout.Other configurationsarealsopossible,butagain,timinganalysismust be done toverifyproperac timings. To maintainsignalintegrity,serialterminationresistorsshouldbe insertedintoallEMIF outputsignallines (seetheTerminalFunctionstablefortheEMIF outputsignals). Copyright© 2003–2009,Texas InstrumentsIncorporated LOGIC AND POWER SUPPLY 85 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table10-2.C6713/13B Example Boards and Maximum EMIF Speed BOARD CONFIGURATION MAXIMUM ACHIEVABLE SDRAM SPEED GRADEEMIF INTERFACE EMIF-SDRAMTYPE BOARD TRACECOMPONENTS INTERFACE SPEED 143-MHz 32-bitSDRAM (−7) 100 MHz 1-to3-intraceswith1-Load 166-MHz 32-bitSDRAM (−6) Forshorttraces,SDRAM dataOne bank of properterminationShort outputholdtimeon theseSDRAMone 32-bitSDRAM resistors; 183-MHz 32-bitSDRAM (−55)Traces speed gradescannotmeet EMIFTraceimpedance ~50 Ω 200-MHz 32-bitSDRAM (−5) inputholdtimerequirement.(1) 125-MHz 16-bitSDRAM (−8E) 100 MHz 1.2to3 infromEMIF to 133-MHz 16-bitSDRAM (−75) 100 MHz2-Loads One bank of each load,withproperShort 143-MHz 16-bitSDRAM (−7E) 100 MHztwo 16-bitSDRAMs terminationresistors;Traces 167-MHz 16-bitSDRAM (−6A) 100 MHzTraceimpedance ~78 Ω 167-MHz 16-bitSDRAM (−6) 100 MHz Forshorttraces,EMIF cannot 125-MHz 16-bitSDRAM (−8E) meet SDRAM inputhold requirement.(1) 1.2to3 inchesfromEMIF 133-MHz 16-bitSDRAM (−75) 100 MHz3-Loads One bank of toeach load,withproperShort two 16-bitSDRAMs 143-MHz 16-bitSDRAM (−7E) 100 MHzterminationresistors;Traces One bank ofbuffer 167-MHz 16-bitSDRAM (−6A) 100 MHzTraceimpedance ~78 Ω Forshorttraces,EMIF cannot 167-MHz 16-bitSDRAM (−6) meet SDRAM inputhold requirement.(1) 143-MHz 32-bitSDRAM (−7) 83 MHz One bank of 166-MHz 32-bitSDRAM (−6) 83 MHz one 32-bit-bitSDRAM,3-Loads 4 to7 infromEMIF; 183-MHz 32-bitSDRAM (−55) 83 MHzOne bank ofLong Traces Traceimpedance ~63 Ωone 32-bit-bitSDRAM, SDRAM dataoutputholdtime One bank ofbuffer 200-MHz 32-bitSDRAM (−5) cannotmeet EMIF inputhold requirement.(1) (1) Resultsarebased on IBISsimulationsforthegivenexample boards(TYPE).Timinganalysisshouldbe performedtodetermineiftiming requirementscan be met fortheparticularsystem.

10.7 EMIF Big Endian Mode Correctness(C6713B Only)

The HD8 pindeviceendianmode (LENDIAN) selectstheendianmode ofoperation(LittleorBigEndian). FortheC6713/13B deviceLittleEndianisthedefaultsetting. The C6713B HD12 pin(EMIF BigEndianMode Correctness)[EMIFBE] enhancement allowstheflexibility tochange theEMIF dataplacementon theEMIF bus. When usingthedefaultsettingofHD12 = 1 fortheC6713B, theEMIF willpresent8-bitor16-bitdataon theED[7:0]sideofthebus ifusingLittleEndianmode (HD8 = 1),and totheED[31:24]sideofthebus if usingBigEndianmode. Figure10-6shows themapping of16-bitand 8-bitC6713B devices. abc EMIF DATA LINES (PINS)WHERE DATA PRESENT ED31:24 ED23:16 ED15:8 ED7:0 32-BitDeviceinAny EndiannessMode 16-BitDeviceinBigEndiannessMode 16-BitDeviceinLittleEndiannessMode 8-BitDevicein 8-BitDevicein BigEndiannessMode LittleEndiannessMode Figure10-6.16/8-BitEMIF Big Endian Mode CorrectnessMapping (HD12 = 1)(C6713B Only) When HD12 = 0 forthe C6713B, enablingEMIF endiannesscorrection,the EMIF willpresent8-bitor 16-bitdataon theED[7:0]sideofthebus,regardlessoftheendianessmode (seeFigure10-7)

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 abc EMIF DATA LINES (PINS)WHERE DATA PRESENT ED31:24 ED23:16 ED15:8 ED7:0 32-BitDeviceinAny EndiannessMode 16-BitDeviceinAny EndiannessMode 8-BitDevicein Any EndiannessMode Figure10-7.16/8-BitEMIF Big Endian Mode CorrectnessMapping (HD12 = 0)(C6713B Only) Thisnew C6713B endiannesscorrectionfunctionalitydoes notaffectsystems usingthedefaultvalueof HD12 = 1. Thisnew C6713B featuredoes notaffectsystemsoperatinginLittleEndianmode.

10.8 Bootmode

The C6713/13B deviceresetsusingthe active-lowsignalRESET and the internalresetsignal.While RESET islow,theinternalresetisalsoassertedand thedeviceisheldinresetand isinitializedtothe prescribedresetstate.Referto Reset Timingforresettimingcharacteristicsand statesof devicepins duringreset.The releaseof the internalresetsignal(see the Reset phase 3 discussioninthe RESET Timingsectionof thisdata sheet)startsthe processorrunningwiththe prescribeddeviceconfiguration and bootmode. The C6713/13B has threetypesofbootmodes:

Hostboot Ifhostbootisselected,upon releaseofinternalreset,theCPU isinternallystalledwhiletheremainder ofthedeviceisreleased.Duringthisperiod,an externalhostcan initializetheCPU memory space as necessarythroughthehostinterface,includinginternalconfigurationregisters,such as thosethat controltheEMIF orotherperipherals.Once thehostisfinishedwithallnecessaryinitialization,itmust settheDSPINT bitintheHPIC registertocompletethebootprocess.Thistransitioncausestheboot configurationlogictobringtheCPU outofthestalledstate.The CPU thenbeginsexecutionfrom address0.The DSPINT conditionisnotlatchedby theCPU, because itoccurswhiletheCPU isstill internallystalled.Also,DSPINT bringstheCPU outofthestalledstateonlyifthehostbootprocessis selected.Allmemory may be writtentoand readby thehost.Thisallowsforthehosttoverifywhat it sends totheDSP ifrequired.AftertheCPU isoutofthestalledstate,theCPU needs toclearthe DSPINT; otherwise,no more DSPINTs can be received.
Emulationboot Emulationbootmode isa variationofhostboot.Inthismode, itisnotnecessaryfora hosttoload code ortosetDSPINT toreleasetheCPU fromthestalledstate.Instead,theemulatorwillsetDSPINT ifithas notbeen previouslysetso thattheCPU can beginexecutingcode fromaddress0.Before beginningexecution,theemulatorsetsa breakpointataddress0.Thispreventstheexecutionof invalidcode by haltingtheCPU beforeexecutingthefirstinstruction.Emulationbootisa good toolin thedebug phase ofdevelopment.
EMIF boot(usingdefaultROM timings) Upon thereleaseofinternalreset,the1K-ByteROM code locatedinthebeginningofCE1 iscopiedto address0 by theEDMA usingthedefaultROM timings,whiletheCPU isinternallystalled.The data shouldbe storedintheendianformatthatthesystemisusing.The bootprocessalsoletsyou choose thewidthoftheROM. Inthiscase,theEMIF automaticallyassemblesconsecutive8-bitbytesor16-bit half-wordstoformthe32-bitinstructionwords tobe copied.The transferisautomaticallydone by the EDMA as a single-frameblocktransferfromtheROM toaddress0.Aftercompletionoftheblock transfer,theCPU isreleasedfromthestalledstateand startrunningfromaddress0. Copyright© 2003–2009,Texas InstrumentsIncorporated LOGIC AND POWER SUPPLY 87 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11 PARAMETRIC INFORMATION

11.1 AbsoluteMaximum Ratings(1)

overoperatingcase temperaturerange(unlessotherwisenoted) VALUE UNIT Supplyvoltagerange,CV DD (2) –0.3to1.8 V Supplyvoltagerange,DV DD (2) –0.3to4 V Inputvoltagerange −0.3toDV DD + 0.5 V Outputvoltagerange −0.3toDV DD + 0.5 V A version –40 to105 Operatingcase temperaturerangeTC S version –55 to105 M version(3) –55 to125 Storagetemperaturerange,Tstg –60 to150 °C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagevaluesarewithrespecttoVSS . (3) Long-termhightemperaturestorageand/orextendeduse atmaximum recommended operatingconditionsmay resultina reductionof overalldevicelife.See http://ti.com/ep_qualityforadditionalinformationon enhanced productpackaging.

11.2 Recommended OperatingConditions(1)

CV DD Supplyvoltage,corereferencedtoVSS 1.20 1.26 1.32 V DV DD Supplyvoltage,I/OreferencedtoVSS 3.13 3.3 3.47 V V(C – D) Maximum supplyvoltagedifference,CV DD − DV DD 1.32 V V(D – C) Maximum supplyvoltagedifference,DV DD − CV DD 2.75 V AllsignalsexceptCLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and 2High-level RESETVIH Vinputvoltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2 AllsignalsexceptCLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and 0.8 RESETLow-levelVIL Vinputvoltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 0.3× DV DD AllsignalsexceptECLKOUT, CLKOUT2, CLKOUT3, –8CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0C6713 (2) High-level ECLKOUT, CLKOUT2, and CLKOUT3 –16 IOH output mA AllsignalsexceptECLKOUT, CLKOUT2, CLKS1/SCL1,current –8DR1/SDA1, SCL0, and SDA0C6713B (2) ECLKOUT and CLKOUT2 –16 AllsignalsexceptECLKOUT, CLKOUT2, CLKOUT3, 8CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 C6713 (2) ECLKOUT, CLKOUT2, and CLKOUT3 16 Low-level CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 3 IOL output mA AllsignalsexceptECLKOUT, CLKOUT2, CLKS1/SCL1,current 8DR1/SDA1, SCL0, and SDA0 C6713B (2) ECLKOUT and CLKOUT2 16 CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 3 VOS Maximum voltageduringovershoot(See Figure11-4) 4(3) V (1) The coresupplyshouldbe powered up before,and powered down after,theI/Osupply.Systems shouldbe designedtoensurethat neithersupplyispowered up foran extendedperiodoftimeiftheothersupplyisbelowtheproperoperatingvoltage. (2) Referstodc (orsteadystate)currentsonly;actualswitchingcurrentsarehigher.Formore details,see thedevice-specificIBISmodels. (3) The absolutemaximum ratingsshouldnotbe exceeded formore than30% ofthecycleperiod.

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Recommended OperatingConditions(1) (continued) MIN NOM MAX UNIT VUS Maximum voltageduringundershoot(See Figure11-5) –0.7(3) V A version –40 105 TC Operatingcase temperature S version –55 105 °C M version –55 125

11.3 ElectricalCharacteristics(1)

overrecommended rangesofsupplyvoltageand operatingcase temperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-leveloutput AllsignalsexceptSCL1, SDA1,VOH IOH = MAX 2.4 Vvoltage SCL0, and SDA0 AllsignalsexceptSCL1, SDA1, IOL = MAX 0.4Low-leveloutput SCL0, and SDA0VOL Vvoltage SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 AllsignalsexceptSCL1, SDA1, ±170SCL0, and SDA0II Inputcurrent VI= VSS toDV DD μA SCL1, SDA1, SCL0, and SDA0 ±10 AllsignalsexceptSCL1, SDA1, ±170SCL0, and SDA0IOZ Off-stateoutputcurrent VO = DV DD or0 V μA SCL1, SDA1, SCL0, and SDA0 ±10 13GDPA, CV DD = 1.4V, 945CPU clock= 300 MHz IDD2V Core supplycurrent(2) mA 13GDPA, CV DD = 1.26V, 560CPU clock= 200 MHz C6713/13B,DV DD = 3.3V,IDD3V I/Osupplycurrent(2) 75 mAEMIF speed = 100 MHz C I Inputcapacitance 7 pF C o Outputcapacitance 7 pF (1) Fortestconditionsshown as MIN, MAX, orNOM, use theappropriatevaluespecifiedintherecommended operatingconditionstable. (2) Measured withaverageactivity(50% high/50%lowpower)at25°C case temperatureand 100-MHz EMIF. Thismodel representsa deviceperforminghigh-DSP-activityoperations50% ofthetime,and theremainderperforminglow-DSP-activityoperations.The high/low-DSP-activitymodels aredefinedas follows: HighDSP activitymodel: CPU: 8 instructions/cyclewith2 LDDW instructions[L1datamemory: 128 bits/cycleviaLDDW instructions;L1 programmemory: 256 bits/cycle;L2/EMIF EDMA: 50% writes,50% readsto/fromSDRAM (50% bitswitching)] McBSP: 2 channelsatE1 rate Timers:2 timersatmaximum rate Low DSP activitymodel: CPU: 2 instructions/cyclewith1 LDH instruction[L1datamemory: 16 bits/cycle;L1 programmemory: 256 bitsper4 cycles;L2/EMIF EDMA: None] McBSP: 2 channelsatE1 rate Timers:2 timersatmaximum rate The actualcurrentdraw ishighlyapplicationdependent.Formore detailson coreand I/Oactivity,refertotheTMS320C6713/12C/11C Power ConsumptionSummary applicationreport(literaturenumber SPRA889 ). Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 89 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

4.0□pF 1.85□pF Z0□=□50 (see□Note□A) Tester□Pin□Electronics Data□Sheet□Timing□Reference□Point Output Under Test 42 3.5□nH Device□Pin (see□Note□1) NOTE□A:□The□data□sheet□provides□timing□at□the□device□pin.□For□output□timing□analysis,□the□tester□pin□electronics□and□its□transmission□line□effects must□be□taken□into□account.□A□transmission□line□with□a□delay□of□2□ns□or□longer□can□be□used□to produce□the□desired□transmission□line effect.□The□transmission□line□is□intended□as□a□load□only.□It□is□not□necessary□to□add□or□subtract□the□transmission□line□delay□(2□ns□or□longer) from□the□data-sheet□timings. Input□requirements□in□this□data□sheet□are□tested□with□an□input□slew□rate□of□<4□V□per□nanosecond□(4□V/ns)□at□the□device□pin. Vref =□1.5□V Vref =□VIL MAX□(or□VOL MAX) Vref =□VIH MIN□(or VOH MIN) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com

11.4 Parameter Measurement Information

11.4.1 Timing Information

Figure11-1.TestLoad CircuitforAC Timing Measurements

11.4.2 SignalTransitionLevels

Allinputand outputtimingparametersarereferencedto1.5V forboth0 and 1 logiclevels. Figure11-2.Inputand Output VoltageReferenceLevelsforAC Timing Measurements Allriseand falltransitiontimingparametersare referencedtoVIL MAX and VIH MIN forinputclocks,VOL MAX and VOH MIN foroutputclocks. Figure11-3.Rise and FallTransitionTime VoltageReferenceLevels

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VOS (max) VIH (min) Minimum Risetime Waveform Valid Region t = 0.3 tc (max)† Ground = the peripheral cycle time.† tc t = 0.3 tc(max)† VIL (max) Ground VUS (max) = the peripheral cycle time.† tc SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

11.4.3 AC TransientRise/FallTime Specifications

Figure11-4 and Figure11-5 show the AC transientspecificationsforriseand falltime.For device-specific informationon thesevalues,refertotheRecommended OperatingConditionssectionofthisdatasheet. Figure11-4.AC TransientSpecificationRise Time Figure11-5.AC TransientSpecificationFallTime Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 91 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

(Output□from□DSP) ECLKOUT (Input□to□External□Device) Control□Signals (Output□from□DSP) Control□Signals (Input□to□External□Device) Data□Signals (Output□from□External□Device) Data□Signals (Input□to□DSP) (A) (B) (B) NOTES□A:□Control□signals□include□data□for□writes. B:□Data□signals□are□generated□during□reads□from□an□external□device. SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com

11.4.4 Timing Parameters and Board Routing Analysis

The timingparametervaluesspecifiedinthisdata sheetdo not includedelaysby board routings.As a good board designpractice,such delaysmust always be taken intoaccount.Timing valuesmay be adjustedby increasing/decreasingsuch delays.TI recommends utilizingthe availableI/O bufferinformationspecification (IBIS)models to analyzethe timingcharacteristicscorrectly.To properlyuse IBIS models to attainaccurate timinganalysisfora givensystem,see theUsing IBISModels forTimingAnalysisapplicationreport(literature number SPRA839 ).Ifneeded,externallogichardwaresuch as buffersmay be used tocompensate any timing differences. For inputs,timingismost impactedby theround-trippropagationdelayfromtheDSP totheexternaldeviceand fromtheexternaldevicetotheDSP. Thisround-tripdelaytendstonegativelyimpacttheinputsetuptimemargin, butalsotendstoimprovetheinputholdtimemargins(seeTable11-1and Figure11-6). Figure11-6 representsa generaltransferbetween theDSP and an externaldevice.The figurealsorepresents boardroutedelaysand how theyareperceivedby theDSP and theexternaldevice. Table11-1.Board-LevelTimings Example (see Figure11-6) NO. DESCRIPTION

1 Clockroutedelay

2 Minimum DSP holdtime

3 Minimum DSP setuptime

4 Externaldeviceholdtimerequirement

5 Externaldevicesetuptimerequirement

6 Controlsignalroutedelay

7 Externaldeviceholdtime

8 Externaldeviceaccesstime

9 DSP holdtimerequirement

10 DSP setuptimerequirement

11 Data routedelay

Figure11-6.Board-LevelInput/OutputTimings

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11.5 Inputand Output Clocks

Table11-2.Timing Requirements forCLKIN (1)(2)(3) See Figure11-7 PLL MODE BYPASS MODE (PLLEN = 1) (PLLEN = 0)NO. UNIT MIN MAX MIN MAX tc(CLKIN) GDP-200 5 83.3 6.7

1 Cycletime,CLKIN ns

GDP-300 4 83.3 6.7 2 tw(CLKINH) Pulseduration,CLKIN high 0.4C 0.4C ns 3 tw(CLKINL) Pulseduration,CLKIN low 0.4C 0.4C ns 4 tt(CLKIN) Transitiontime,CLKIN 5 5 ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. (2) C = CLKIN cycletimeinnanoseconds(ns).Forexample,when CLKIN frequencyis40 MHz, use C = 25 ns. (3) See thePLL and PLL Controllersectionofthisdatasheet. Figure11-7.CLKIN Table11-3.SwitchingCharacteristicsforCLKOUT2 (1)(2) overrecommended operatingconditions(seeFigure11-8) NO. PARAMETER MIN MAX UNIT 1 tc(CKO2) Cycletime,CLKOUT2 C2 – 0.8 C2 + 0.8 ns 2 tw(CKO2H) Pulseduration,CLKOUT2 high (C2/2)– 0.8 (C2/2)+ 0.8 ns 3 tw(CKO2L) Pulseduration,CLKOUT2 low (C2/2)– 0.8 (C2/2)+ 0.8 ns 4 tt(CKO2) Transitiontime,CLKOUT2 2 ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) C2 = CLKOUT2 periodinns.CLKOUT2 periodisdeterminedby thePLL controlleroutputSYSCLK2 period,whichmust be settoCPU perioddivide-by-2. Figure11-8.CLKOUT2 Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 93 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table11-4.SwitchingCharacteristicsforCLKOUT3 (1)(2) overrecommended operatingconditions(seeFigure11-9) 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(CKO3) Cycletime,CLKOUT3 C3 – 0.6 C3 + 0.6 C3 – 0.9 C3 + 0.9 ns 2 tw(CKO3H) Pulseduration,CLKOUT3 high (C3/2)– 0.6 (C3/2)+ 0.6 (C3/2)– 0.9 (C3/2)+ 0.9 ns 3 tw(CKO3L) Pulseduration,CLKOUT3 low (C3/2)– 0.6 (C3/2)+ 0.6 (C3/2)– 0.9 (C3/2)+ 0.9 ns 4 tt(CKO3) Transitiontime,CLKOUT3 2 3 ns 5 td(CLKINH-CKO3V) Delaytime,CLKIN hightoCLKOUT3 valid 1.5 6.5 1.5 7.5 ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) C3 = CLKOUT3 periodinns.CLKOUT3 periodisa divide-downoftheCPU clock,configurableviatheRATIO fieldinthePLLDIV3 register. Figure11-9.CLKOUT3 Table11-5.Timing Requirements forECLKIN (1) See Figure11-10 NO. MIN MAX UNIT 1 tc(EKI) Cycletime,ECLKIN 10 ns 2 tw(EKIH) Pulseduration,ECLKIN high 4.5 ns 3 tw(EKIL) Pulseduration,ECLKIN low 4.5 ns 4 tt(EKI) Transitiontime,ECLKIN 3 ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. Figure11-10.ECLKIN

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table11-6.SwitchingCharacteristicsforECLKOUT (1)(2)(3) overrecommended operatingconditions(seeFigure11-11) NO. PARAMETER MIN MAX UNIT 1 tc (EKO) Cycletime,ECLKOUT E – 0.9 E + 0.9 ns 2 tw (EKOH) Pulseduration,ECLKOUT high EH – 0.9 EH + 0.9 ns 3 tw (EKOL) Pulseduration,ECLKOUT low EL – 0.9 EL + 0.9 ns 4 tt(EKO) Transitiontime,ECLKOUT 2 ns 5 td (EKIH-EKOH) Delaytime,ECLKIN hightoECLKOUT high 1 6.5 ns 6 td (EKIL-EKOL) Delaytime,ECLKIN lowtoECLKOUT low 1 6.5 ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) E = ECLKIN periodinns (3) EH isthehighperiodofECLKIN inns and EL isthelowperiodofECLKIN inns. Figure11-11.ECLKOUT Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 95 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11.6 Asynchronous Memory Timing

Table11-7.Timing Requirements forAsynchronous Memory Cycles(1)(2)(3) See Figure11-12and Figure11-13 NO. MIN MAX UNIT 3 tsu(EDV-AREH) Setuptime,EDx validbeforeARE high 6.5 ns 4 th(AREH-EDV) Holdtime,EDx validafterARE high 1 ns 6 tsu(ARDY-EKOH) Setuptime,ARDY validbeforeECLKOUT high 3 ns 7 th(EKOH-ARDY) ARDY validafterECLKOUT high 2.3 ns (1) To ensuredatasetuptime,simplyprogramthestrobewidthwideenough.ARDY isinternallysynchronized.The ARDY signalis recognizedinthecycleforwhichthesetupand holdtimeismet.To use ARDY as an asynchronousinput,thepulsewidthoftheARDY signalshouldbe wideenough (forexample,pulsewidth= 2E) toensuresetupand holdtimeismet. (2) RS = Read setup,RST = Read strobe,RH = Read hold,WS = Writesetup,WST = Writestrobe,WH = Writehold.These parameters areprogrammed viatheEMIF CE space controlregisters. (3) E = ECLKOUT periodinns Table11-8.SwitchingCharacteristicsforAsynchronous Memory Cycles(1)(2)(3) overrecommended operatingcondition(seeFigure11-12and Figure11-13) NO. PARAMETER MIN MAX UNIT 1 tosu(SELV-AREL) Outputsetuptime,selectsignalsvalidtoARE low RS*E – 1.7 ns 2 toh(AREH-SELIV) Outputholdtime,ARE hightoselectsignalsinvalid RH*E – 1.7 ns 5 td(EKOH-AREV) Delaytime,ECLKOUT hightoARE valid 1.5 7 ns 8 tosu(SELV-AWEL) Outputsetuptime,selectsignalsvalidtoAWE low WS*E – 1.7 ns 9 toh(AWEH-SELIV) Outputholdtime,AWE hightoselectsignalsand EDx invalid WH*E – 1.7 ns 10 td(EKOH-AWEV) Delaytime,ECLKOUT hightoAWE valid 1.5 7 ns 11 tosu(EDV-AWEL) Outputsetuptime,ED validtoAWE low (WS – 1)*E– 1.7 ns (1) RS = Read setup,RST = Read strobe,RH = Read hold,WS = Writesetup,WST = Writestrobe,WH = Writehold.These parameters areprogrammed viatheEMIF CE space controlregisters. (2) E = ECLKOUT periodinns (3) SelectsignalsincludeCEx, BE[3:0],EA[21:2],and AOE.

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Setup□= 2S trobe□=□3 Not□Ready Hold□= 2 BE Address Read□Data 21 ARDY ECLKOUT CEx EA[21:2] ED[31:0] AOE /SDRAS/SSOE ARE/SDCAS/SSADS BE[3:0] AWE/SDWE/SSWE (A) (A) (A) NOTE□A: / / , / / ,□and / / operate□as (identified□under□select□signals), ,□and , respectively,□during□asynchronous□memory□accesses. AOE□SDRAS□SSOE□□ARE□SDCAS□SSADS AWE□SDWE□SSWE AOE ARE AWE SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure11-12.Asynchronous Memory Read Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 97 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

Setup□= 2 Strobe□=□3 Not□Ready Hold□= 2 BE Address Write□Data 1010 911 ECLKOUT CEx EA[21:2] ED[31:0] BE[3:0] ARDY AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE (A) (A) (A) NOTE□A: / / , / / ,□and / / operate□as (identified□under□select□signals), ,□and , respectively,□during□asynchronous□memory□accesses. AOE□SDRAS□SSOE□□ARE□SDCAS□SSADS AWE□SDWE□SSWE AOE ARE AWE SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure11-13.Asynchronous Memory Write

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BE[3:0] EA[21:2] ED[31:0] ARE /SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE BE1 BE2 BE3 BE4 EA Q1 Q2 Q3 Q4 4 5 8 8 6 7 (1) (1) (1) NOTE□(1): / / , and / / operate□as during□SBSRAM□accesses.ARE□SDCAS□SSADS AWE□SDWE□SSWE SSADSAO SSOE SSWE, ,□and ,□respectively,E□SDRAS□SSOE/ / , SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

11.7 Synchronous-Burst Memory Timing

Table11-9.Timing Requirements forSynchronous-Burst SRAM Cycles(1) See Figure11-14 NO. MIN MAX UNIT 6 tsu(EDV-EKOH) Setuptime,readEDx validbeforeECLKOUT high 1.5 ns 7 th(EKOH-EDV) Holdtime,readEDx validafterECLKOUT high 2.5 ns (1) The C6713/13B SBSRAM interfacetakesadvantageoftheinternalburstcounterintheSBSRAM. Accessesdefaulttoincrementing 4-wordbursts,butrandom burstsand decrementingburstsaredone by interruptingburstsinprogress.Allbursttypescan sustain continuousdataflow. Table11-10.SwitchingCharacteristicsforSynchronous-Burst SRAM Cycles(1)(2) overrecommended operatingconditions(seeFigure11-14and Figure11-15) NO. PARAMETER MIN MAX UNIT 1 td (EKOH-CEV) Delaytime,ECLKOUT hightoCEx valid 1.2 7 ns 2 td (EKOH-BEV) Delaytime,ECLKOUT hightoBEx valid 7 ns 3 td (EKOH-BEIV) Delaytime,ECLKOUT hightoBEx invalid 1.2 ns 4 td (EKOH-EAV) Delaytime,ECLKOUT hightoEAx valid 7 ns 5 td (EKOH-EAIV) Delaytime,ECLKOUT hightoEAx invalid 1.2 ns 8 td (EKOH-ADSV) Delaytime,ECLKOUT hightoARE/SDCAS/ SSADS valid 1.2 7 ns 9 td (EKOH-OEV) Delaytime,ECLKOUT hightoAOE/ SDRAS/ SSOE valid 1.2 7 ns 10 td (EKOH-EDV) Delaytime,ECLKOUT hightoEDx valid 7 ns 11 td (EKOH-EDIV) Delaytime,ECLKOUT hightoEDx invalid 1.2 ns 12 td (EKOH-WEV) Delaytime,ECLKOUT hightoAWE/ SDWE/ SSWE valid 1.2 7 ns (1) The C6713/13B SBSRAM interfacetakesadvantageoftheinternalburstcounterintheSBSRAM. Accessesdefaulttoincrementing 4-wordbursts,butrandom burstsand decrementingburstsaredone by interruptingburstsinprogress.Allbursttypescan sustain continuousdataflow. (2) ARE/SDCAS/ SSADS, AOE/ SDRAS/ SSOE, and AWE/ SDWE/ SSWE operateas SSADS, SSOE, and SSWE, respectively,during SBSRAM accesses. Figure11-14.SBSRAM Read Timing Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 99 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

BE[3:0] EA[21:2] ED[31:0] ARE /SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE BE1B E2 BE3B E4 Q1 Q2 Q3 Q4 EA NOTE□A: / / , and / / operate□as , ,□and ,□respectively,□during□SBSRAM□accesses.ARE□SDCAS□SSADS□□AO AWE□SDWE□SSWE SSADS□□SSOE SSWEE□SDRAS□SSOE/ / , (A) (A) (A) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure11-15.SBSRAM WriteTiming

11.8 Synchronous DRAM Timing

Table11-11.Timing Requirements forSynchronous DRAM Cycles(1) See Figure11-16 NO. MIN MAX UNIT 6 tsu(EDV-EKOH) Setuptime,readEDx validbeforeECLKOUT high 1.5 ns 7 th(EKOH-EDV) Holdtime,readEDx validafterECLKOUT high 2.5 ns (1) The C6713/13B SDRAM interfacetakesadvantageoftheinternalburstcounterintheSDRAM. Accessesdefaulttoincrementing4-word bursts,butrandom burstsand decrementingburstsaredone by interruptingburstsinprogress.Allbursttypescan sustaincontinuous dataflow. Table11-12.SwitchingCharacteristicsforSynchronous DRAM Cycles(1)(2) overrecommended operatingconditions(seeFigure11-16— Figure11-22) NO. PARAMETER MIN MAX UNIT 1 td(EKOH-CEV) Delaytime,ECLKOUT hightoCEx valid 1.5 7 ns 2 td(EKOH-BEV) Delaytime,ECLKOUT hightoBEx valid 7 ns 3 td(EKOH-BEIV) Delaytime,ECLKOUT hightoBEx invalid 1.5 ns 4 td(EKOH-EAV) Delaytime,ECLKOUT hightoEAx valid 7 ns 5 td(EKOH-EAIV) Delaytime,ECLKOUT hightoEAx invalid 1.5 ns 8 td(EKOH-CASV) Delaytime,ECLKOUT hightoARE/SDCAS/ SSADS valid 1.5 7 ns 9 td(EKOH-EDV) Delaytime,ECLKOUT hightoEDX valid 7 ns 10 td(EKOH-EDIV) Delaytime,ECLKOUT hightoEDx invalid 1.5 ns 11 td(EKOH-WEV) Delaytime,ECLKOUT hightoAWE/ SDWE/ SSWE valid 1.5 7 ns 12 td(EKOH-RAV) Delaytime,ECLKOUT hightoAOE/ SDRAS/ SSOE valid 1.5 7 ns (1) The C6713/13B SDRAM interfacetakesadvantageoftheinternalburstcounterintheSDRAM. Accessesdefaulttoincrementing4-word bursts,butrandom burstsand decrementingburstsaredone by interruptingburstsinprogress.Allbursttypescan sustaincontinuous dataflow. (2) ARE/SDCAS/ SSADS, AWE/ SDWE/ SSWE and AOE/ SDRAS/ SSOE operateas SDCAS, SWE, and SDRAS, respectively,duringSDRAM accesses.

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BE[3:0] EA[11:2] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE EA[21:13] BE1 BE2B E3 BE4 Bank Column D1 D2 D3 D4 READ (A) (A) (A) NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure11-16.SDRAM Read Command (CAS Latency 3) Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 101 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

BE[3:0] EA[11:2] ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE EA12 EA[21:13] BE1 BE2 BE3 BE4 Bank Column D1 D2 D3 D4 WRITE NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) ECLKOUT CEx BE[3:0] EA[21:13] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE Bank Activate Row Address Row Address EA[11:2] ACTV NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure11-17.SDRAM WriteCommand Figure11-18.SDRAM ACTV Command

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BE[3:0] EA[21:13, 11:2] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE DCAB NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) ECLKOUT CEx BE[3:0] EA[21:13] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE EA[11:2] Bank DEAC NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure11-19.SDRAM DCAB Command Figure11-20.SDRAM DEAC Command Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 103 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

BE[3:0] EA[21:2] ED[31:0] EA12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE REFR NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) ECLKOUT CEx BE[3:0] EA[21:2] ED[31:0] AOE /SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE MRS□value MRS NOTE□A: / / and operate□as , ,□and ,□respectively,□during□SDRAM□accesses.AWE□SDWE□SSWE, SDCAS□□SDWE SDRASARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / (A) (A) (A) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure11-21.SDRAM REFR Command Figure11-22.SDRAM MRS Command

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EMIF□Bus DSP□Owns□Bus External□Requestor Owns□Bus DSP□Owns□Bus C6713/13BC 6713/13B NOTE□A:□□□EMIF□bus□consists□of , ,□ED[31:0],□EA[21:2], / / ,□andCE[3:0]□□BE[3:0] AWE□SDWE□SSWEARE□SDCAS□SSADS AOE□SDRAS□SSOE/ / , / / . (A) ECLKOUT BUSREQ SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009

11.9 HOLD/ HOLDA Timing

Table11-13.Timing Requirements forHOLD/ HOLDA Cycles(1) See Figure11-23 NO. MIN MAX UNIT 3 th(HOLDAL-HOLDL) Holdtime,HOLD lowafterHOLDA low E ns (1) E = ECLKOUT periodinns Table11-14.SwitchingCharacteristicsforHOLD/ HOLDA Cycles(1)(2) overrecommended operatingconditions(seeFigure11-23) 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX 1 td(HOLDL-EMHZ) Delaytime,HOLD lowtoEMIF Bus highimpedance 2E (3) 2E (3) ns 2 td(EMHZ-HOLDAL) Delaytime,EMIF Bus highimpedance toHOLDA low –0.1 2E 0 2E ns 4 td(HOLDH-EMLZ) Delaytime,HOLD hightoEMIF Bus lowimpedance 2E 7E 2E 7E ns 5 td(EMLZ-HOLDAH) Delaytime,EMIF Bus lowimpedance toHOLDA high –1.5 2E 0 2E ns (1) E = ECLKOUT periodinns (2) EMIF bus consistsofCE[3:0],BE[3:0],ED[31:0],EA[21:2],ARE/SDCAS/ SSADS, AOE/ SDRAS/ SSOE, and AWE/ SDWE/ SSWE. (3) AllpendingEMIF transactionsareallowedtocompletebeforeHOLDA isasserted.Ifno bus transactionsareoccurring,thenthe minimum delaytimecan be achieved.Also,bus holdcan be indefinitelydelayedby settingNOHOLD = 1. Figure11-23.HOLD/ HOLDA Timing

11.10 BUSREQ Timing

Table11-15.SwitchingCharacteristicsforBUSREQ Cycles overrecommended operatingconditions(seeFigure11-24) NO. PARAMETER MIN MAX UNIT 1 td(EKOH-BUSRV) Delaytime,ECLKOUT hightoBUSREQ valid 1.5 7.2 ns Figure11-24.BUSREQ Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 105 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11.11 Reset Timing

Table11-16.Timing Requirements forRESET (1)(2) See Figure11-25 NO. MIN MAX UNIT 1 tw(RST) Pulseduration,RESET 100 ns 13 tsu(HD) Setuptime,HD bootconfigurationbitsvalidbeforeRESET high(3) 2P ns 14 th(HD) Holdtime,HD bootconfigurationbitsvalidafterRESET high(3) 2P ns (1) P = 1/CPU clockfrequencyinns.Forexample,when runningpartsat300 MHz, use P = 3.3ns. (2) FortheC6713/13B device,thePLL isbypassedimmediatelyafterthedevicecomes outofreset.The PLL controllercan be programmed tochange thePLL mode insoftware.Formore detailedinformationon thePLL controller,see theTMS320C6000 DSP Phase-LockLoop (PLL)ControllerPeripheralReferenceGuide (literaturenumber SPRU233 ). (3) The bootand deviceconfigurationsbitsarelatchedasynchronouslywhen RESET istransitioninghigh.The bootand device configurationsbitsconsistofHD[14,8,4:3]. Table11-17.SwitchingCharacteristicsFor RESET (1) overrecommended operatingconditions(seeFigure11-25) NO. PARAMETER MIN MAX UNIT 512 xDelaytime,externalRESET hightointernalresethighand all2 td(RSTH-ZV) CLKMODE0 = 1 CLKIN nssignalgroupsvalid(2)(3) period 3a td(RSTL-ECKOL) Delaytime,RESET lowtoECLKOUT low(6713) 0 ns 3b td(RSTL-ECKOL) Delaytime,RESET lowtoECLKOUT highimpedance (6713B) 0 ns 4 td(RSTH-ECKOV) Delaytime,RESET hightoECLKOUT valid 6P ns 5a td(RSTL-CKO2IV) Delaytime,RESET lowtoCLKOUT2 invalid(6713) 0 ns 5b td(RSTL-CKO2IV) Delaytime,RESET lowtoCLKOUT2 highimpedance (6713B) 0 ns 6 td(RSTH-CKO2V) Delaytime,RESET hightoCLKOUT2 valid 6P ns 7 td(RSTL-CKO3L) Delaytime,RESET lowtoCLKOUT3 low 0 ns 8 td(RSTH-CKO3V) Delaytime,RESET hightoCLKOUT3 valid 6P ns 9 td(RSTL-EMIFZHZ) Delaytime,RESET lowtoEMIF Z grouphighimpedance(3) 0 ns 10 td(RSTL-EMIFLIV) Delaytime,RESET lowtoEMIF lowgroup(BUSREQ) invalid(3) 0 ns 11 td(RSTL-Z1HZ) Delaytime,RESET lowtoZ group1 highimpedance(3) 0 ns 12 td(RSTL-Z2HZ) Delaytime,RESET lowtoZ group2 highimpedance(3) 0 ns (1) P = 1/CPU clockfrequencyinns.Note thatwhileinternalresetisassertedlow,theCPU clock(SYSCLK1) periodisequaltotheinput clock(CLKIN)periodmultipliedby 8.Forexample,iftheCLKIN periodis20 ns,theCPU clock(SYSCLK1) periodis20 ns x 8 = 160 ns. Therefore,P = SYSCLK1 = 160 ns whileinternalresetisasserted. (2) The internalresetisstretchedexactly512 x CLKIN cyclesifCLKIN isused (CLKMODE0 = 1).Iftheinputclock(CLKIN)isnotstable when RESET isdeasserted,theactualdelaytimemay vary. (3) EMIF Z groupconsistsofEA[21:2],ED[31:0],CE[3:0],BE[3:0],ARE/SDCAS/ SSADS, AWE/ SDWE/ SSWE, AOE/ SDRAS/ SSOE, and HOLDA. EMIF lowgroupconsistsofBUSREQ. Z group1 consistsofCLKR0/ACLKR0, CLKR1/AXR0[6],CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7], FSX0/AFSX0, FSX1, DX0/AXR0[1],DX1/AXR0[5],TOUT0/AXR0[2],TOUT1/AXR0[4],SDA0, and SCL0. Z group2 consistsofallotherHPI,McASP0/1, GPIO, and I2C1 signals.

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Internal□Reset Internal□SYSCLK1 Internal□SYSCLK2 Internal□SYSCLK3 CLKOUT3 RESET Phase 3 EMIF□Z□Group EMIF□Low□Group Z□Group 1 Z□Group 2 Boot□and Device Configuration Pins

6713 ECLKOUT

6713□CLKOUT2 6713B□ECLKOUT 6713B□CLKOUT2 (A) (A) (A) (A) (B) NOTES□A:□EMIF□Z□group□consists□of□EA[21:2],□ED[31:0], , , / / , / / , / / ,□and . Z□group□1□consists□of□CLKR0/ACLKR0,□CLKR1/AXR0[6],□CLKX0/ACLKX0,□CLKX1/AMUTE0,□FSR0/AFSR0,□FSR1/AXR0[7],□FSX0/AFSX0,□FSX1, DX0/AXR0[1],□DX1/AXR0[5],□TOUT0/AXR0[2],□TOUT1/AXR0[4],□SDA0,□and□SCL0. Z□group□2□consists□of□All□other□HPI,□McASP0/1,□GPIO,□and□I2C1□signals. B:□Boot□and□device□configurations□consist□of:□HD[14,□8,□4:3]. CE[3:0]□□BE[3:0]□□ARE□SDCAS□SSADS□□AWE□SDWE□SSWE□□AOE□SDRAS□SSOE HOLDA EMIF□low□group□consists□of□BUSREQ. SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure11-25.Reset Timing Reset Phase 1: The RESET pin isasserted.Duringthistime,allinternalclocksare runningat the CLKIN frequencydivide-by-8.The CPU isalsorunningattheCLKIN frequencydivide-by-8. Reset Phase 2: The RESET pinisdeassertedbuttheinternalresetisstretched.Duringthistime,allinternal clocksare runningat the CLKIN frequencydivide-by-8.The CPU is also runningat the CLKIN frequency divide-by-8. Reset Phase 3:Both theRESET pinand internalresetare deasserted.Duringthistime,allinternalclocksare runningat theirdefaultdivide-downfrequencyof CLKIN. The CPU clock(SYSCLK1) is runningat CLKIN frequency.The peripheralclock(SYSCLK2) isrunningatCLKIN frequencydivide-by-2.The EMIF internalclock source (SYSCLK3) isrunningat CLKIN frequencydivide-by-2.SYSCLK3 isreflectedon the ECLKOUT pin (when EKSRC bit= 0 [default]).CLKOUT3 isrunningatCLKIN frequencydivide-by-8. Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 107 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11.12 ExternalInterruptTiming

Table11-18.Timing Requirements forExternalInterrupts(1) See Figure11-26 NO. MIN MAX UNIT WidthoftheNMI interruptpulselow 2P ns 1 tw(ILOW) WidthoftheEXT_INT interruptpulselow 4P ns WidthoftheNMI interruptpulsehigh 2P ns 2 tw(IHIGH) WidthoftheEXT_INT interruptpulsehigh 4P ns (1) P = 1/CPU clockfrequencyinns.Forexample,when runningpartsat300 MHz, use P = 3.3ns. Figure11-26.External/NMIInterrupt

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11.13 MultichannelAudio SerialPort(McASP) Timing

Table11-19.Timing Requirements forMcASP See Figure11-27and Figure11-28 6713 6713B NO. UNIT MIN MAX MIN MAX 1 tc(AHCKRX) Cycletime,AHCLKR/X 20 20 ns 2 tw(AHCKRX) Pulseduration,AHCLKR/X highorlow 7.5 7.5 ns Greaterof3 tc(ACKRX) Cycletime,ACLKR/X ACLKR/X ext 33 ns2P (1)or33 4 tw(ACKRX) Pulseduration,ACLKR/X highorlow ACLKR/X ext 14 14 ns ACLKR/X int 6 6 nsSetuptime,AFSR/X inputvalidbefore5 tsu(AFRXC-ACKRX) ACLKR/X latchesdata ACLKR/X ext 3 3 ns ACLKR/X int 0 0 nsHoldtime,AFSR/X inputvalidafter6 th(ACKRX-AFRX) ACLKR/X latchesdata ACLKR/X ext 3 3 ns ACLKR/X int 10.2 8 nsSetuptime,AXR inputvalidbeforeACLKR/X7 tsu(AXR-ACKRX) latchesdata ACLKR/X ext 6 3 ns ACLKR/X int 1 1 nsHoldtime,AXR inputvalidafterACLKR/X8 th(ACKRX-AXR) latchesdata ACLKR/X ext 3 3 ns (1) P = SYSCLK2 period Table11-20.SwitchingCharacteristicsforMcASP (1) overrecommended operatingconditions(seeFigure11-27and Figure11-28) NO. PARAMETER MIN MAX UNIT 9 tc(AHCKRX) Cycletime,AHCLKR/X 20 ns 10 tw(AHCKRX) Pulseduration,AHCLKR/X highorlow (AH/2)– 2.5 ns tc(ACKRX) Greaterof11 Cycletime,ACLKR/X ACLKR/X int ns2P (2)or33 12 tw(ACKRX) Pulseduration,ACLKR/X highorlow ACLKR/X int (AH/2)– 2.5 ns ACLKR/X int –1 5 nsDelaytime,ACLKR/X transmitedge toAFSX/R13 td(ACKRX-AFRX) outputvalid ACLKR/X ext 0 10 ns ACLKR/X int –1 5 ns 14 td(ACKX-AXRV) Delaytime,ACLKX transmitedge toAXR outputvalid ACLKR/X ext 0 10 ns ACLKR/X int –1 10 nsDisabletime,AXR highimpedance followinglastdata15 tdis(ACKRX−AXRHZ) bitfromACLKR/X transmitedge ACLKR/X ext –1 10 ns (1) AH = AHCLKR/X periodinns;A = ACLKR/X periodinns (2) P = SYSCLK2 period Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 109 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

A0 A1 B0 B1 A30A 31 B30B 31 C0 C1 C2 C3 C31 AHCLKR/X□(Falling□Edge□Polarity) AHCLKR/X□(Rising□Edge□Polarity) ACLKR/X□(Falling□Edge□Polarity) ACLKR/X□(Rising□Edge□Polarity) AFSR/X□(Bit□Width,□0□Bit□Delay) AFSR/X□(Bit□Width,□1□Bit□Delay) AFSR/X□(Bit□Width,□2□Bit□Delay) AFSR/X□(Slot□Width,□0□Bit□Delay) AFSR/X□(Slot□Width,□1□Bit□Delay) AFSR/X□(Slot□Width,□2□Bit□Delay) AXR[n]□(Data□In/Receive) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure11-27.McASP InputTimings

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A0 A1 B0 B1 A30A 31 B30B 31 C0 C1 C2 C3 C31 AHCLKR/X□(Falling□Edge□Polarity) AHCLKR/X□(Rising□Edge□Polarity) ACLKR/X□(Falling□Edge□Polarity) ACLKR/X□(Rising□Edge□Polarity) AFSR/X□□(Bit□Width,□0□Bit□Delay) AFSR/X□(Bit□Width,□1□Bit□Delay) AFSR/X□(Bit□Width,□2□Bit□Delay) AFSR/X□(Slot□Width,□0□Bit□Delay) AFSR/X□(Slot□Width,□1□Bit□Delay) AFSR/X□(Slot□Width,□2□Bit□Delay) AXR[n]□(Data□Out/Transmit) SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure11-28.McASP Output Timings Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 111 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11.14 Inter-IntegratedCircuits(I2C) Timing

Table11-21.Timing Requirements forI2C (1) See Figure11-29 STANDARD FAST MODE MODENO. UNIT MIN MAX MIN MAX 1 tc(SCL) Cycletime,SCL 10 2.5 μs Setuptime,SCL highbeforeSDA low(fora repeated2 tsu(SCLH-SDAL) 4.7 0.6 μsSTART condition) Holdtime,SCL lowafterSDA low(fora START and a3 th(SCLL-SDAL) 4 0.6 μsrepeatedSTART condition) 4 tw(SCLL) Pulseduration,SCL low 4.7 1.3 μs 5 tw(SCLH) Pulseduration,SCL high 4 0.6 μs 6 tsu(SDAV-SDLH) Setuptime,SDA validbeforeSCL high 250 100(2) ns Holdtime,7 th(SDA-SDLL) 0(3) 0(3) 0.9(4) μsSDA validafterSCL low(forI2C bus devices) Pulseduration,8 tw(SDAH) 4.7 1.3 μsSDA highbetween STOP and START conditions 9 tr(SDA) Risetime,SDA 1000 20 + 0.1Cb (5) 300 ns 10 tr(SCL) Risetime,SCL 1000 20 + 0.1Cb (5) 300 ns 11 tf(SDA) Falltime,SDA 300 20 + 0.1Cb (5) 300 ns 12 tf(SCL) Falltime,SCL 300 20 + 0.1Cb (5) 300 ns Setuptime,13 tsu(SCLH-SDAH) 4 0.6 μsSCL highbeforeSDA high(forSTOP condition) 14 tw( SP) Pulseduration,spike(mustbe suppressed) 0 50 ns

15 C b

(5) Capacitiveloadforeach bus line 400 400 pF (1) The I2C pinsSDA and SCL do notfeaturefail-safeI/Obuffers.These pinscouldpotentiallydraw currentwhen thedeviceispowered down. (2) A fast-modeI2C-bus devicecan be used ina standard-modeI2C-bus system,buttherequirementtsu (SDA −SCLH) ≥ 250 ns must then be met.Thiswillautomaticallybe thecase ifthedevicedoes notstretchtheLOW periodoftheSCL signal.Ifsuch a devicedoes stretch theLOW periodoftheSCL signal,itmust outputthenextdatabittotheSDA linetr max + tsu (SDA −SCLH) = 1000 + 250 = 1250 ns (accordingtothestandard-modeI2C-bus specification)beforetheSCL lineisreleased. (3) A devicemust internallyprovidea holdtimeofatleast300 ns fortheSDA signal(referredtotheVIH min oftheSCL signal)tobridgethe undefinedregionofthefallingedge ofSCL. (4) The maximum th(SDA −SCLL) has onlytobe met ifthedevicedoes notstretchthelowperiod[tw(SCLL)]oftheSCL signal. (5) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfalltimesareallowed. Figure11-29.I2C Receive

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www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table11-22.SwitchingCharacteristicsforI2C (1) overrecommended operatingconditions(seeFigure11-30) STANDARD FAST MODE MODE NO. PARAMETER MIN MAX MIN MAX UNIT 16 tc(SCL) Cycletime,SCL 10 2.5 μs Delaytime,SCL hightoSDA low(fora repeatedSTART17 td(SCLH-SDAL) 4.7 0.6 μscondition) Delaytime,SDA lowtoSCL low(fora START and a repeated18 td(SDAL-SCLL) 4 0.6 μsSTART condition) 19 tw(SCLL) Pulseduration,SCL low 4.7 1.3 μs 20 tw(SCLH) Pulseduration,SCL high 4 0.6 μs 21 td(SDAV-SDLH) Delaytime,SDA validtoSCL high 250 100 ns Validtime,22 tv(SDLL-SDAV) 0 0 0.9 μsSDA validafterSCL low(forI2C bus devices) Pulseduration,23 tw(SDAH) 4.7 1.3 μsSDA highbetween STOP and START conditions 24 tr(SDA) Risetime,SDA 1000 20 + 0.1Cb (1) 300 ns 25 tr(SCL) Risetime,SCL 1000 20 + 0.1Cb (1) 300 ns 26 tf(SDA) Falltime,SDA 300 20 + 0.1Cb (1) 300 ns 27 tf(SCL) Falltime,SCL 300 20 + 0.1Cb (1) 300 ns Delaytime,28 td(SCLH-SDAH) 4 0.6 μsSCL hightoSDA high(forSTOP condition)

30 C b Capacitanceforeach I2C pin 10 10 pF

(1) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfall-timesareallowed. Figure11-30.I2C TransmitTimings Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 113 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11.15 Host-PortInterfaceTiming

Table11-23.Timing Requirements forHost-PortInterfaceCycles(1)(2) See Figure11-31— Figure11-34 6713 6713B NO. UNIT MIN MAX MIN MAX 1 tsu(SELV-HSTBL) Setuptime,selectsignalsvalidbeforeHSTROBE low(3) 5 5 ns 2 th(HSTBL-SELV) Holdtime,selectsignalsvalidafterHSTROBE low(3) 4 4 ns Pulseduration,HSTROBE low(hostread access) 10P + 5.8 4P ns 3 tw(HSTBL) Pulseduration,HSTROBE low(hostwriteaccess) 4P 4P ns 4 tw(HSTBH) Pulseduration,HSTROBE highbetween consecutiveaccesses 4P 4P ns 10 tsu(SELV-HASL) Setuptime,selectsignalsvalidbeforeHAS low(3) 5 5 ns 11 th(HASL-SELV) Holdtime,selectsignalsvalidafterHAS low(3) 3 3 ns 12 tsu(HDV-HSTBH) Setuptime,hostdatavalidbeforeHSTROBE high 5 5 ns 13 th(HSTBH-HDV) Holdtime,hostdatavalidafterHSTROBE high 3 3 ns Holdtime,HSTROBE lowafterHRDY low.HSTROBE shouldnot 14 th(HRDYL-HSTBL) be inactivateduntilHRDY isactive(low);otherwise,HPI writeswill 2 2 ns notcompleteproperly. 18 tsu(HASL-HSTBL) Setuptime,HAS lowbeforeHSTROBE low 2 2 ns 19 th(HSTBL-HASL) Holdtime,HAS lowafterHSTROBE low 2 2 ns (1) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (2) P = 1/CPU clockfrequencyinns.Forexample,when runningpartsat300 MHz, use P = 3.3ns. (3) SelectsignalsincludeHCNTL[1:0],HR/W, and HHWIL.

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1st□halfword2 nd□halfword 51786 51785 916 2121 2121 HAS HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□(output) HRDY (case□1) HRDY (case□2) 3(A) NOTE□A: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR .HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table11-24.SwitchingCharacteristicsforHost-PortInterfaceCycles(1)(2) overrecommended operatingconditions(seeFigure11-31— Figure11-34) 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX 5 td(HCS-HRDY) Delaytime,HCS toHRDY (3) 1 15 1 12 ns 6 td(HSTBL-HRDYH) Delaytime,HSTROBE lowtoHRDY high(4) 3 15 3 12 ns td(HSTBL-HDLZ) Delaytime,HSTROBE lowtoHD lowimpedance foran7 2 2 nsHPI read 8 td(HDV-HRDYL) Delaytime,HD validtoHRDY low 2P – 4 2P – 4 ns 9 toh(HSTBH-HDV) Outputholdtime,HD validafterHSTROBE high 3 12 3 12 ns 15 td(HSTBH-HDHZ) Delaytime,HSTROBE hightoHD highimpedance 2 12 3 12 ns 16 td(HSTBL-HDV) Delaytime,HSTROBE lowtoHD valid 3 10P + 5.8 3 12.5 ns 17 td(HSTBH-HRDYH) Delaytime,HSTROBE hightoHRDY high(5) 3 15 3 12 ns (1) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (2) P = 1/CPU clockfrequencyinns.Forexample,when runningpartsat300 MHz, use P = 3.3ns. (3) HCS enablesHRDY, and HRDY isalwayslowwhen HCS ishigh.The case where HRDY goes highwhen HCS fallsindicatesthatHPI isbusy completinga previousHPID writeorREAD withautoincrement. (4) Thisparameterisused duringan HPID read.Atthebeginningofthefirsthalf-wordtransferon thefallingedge ofHSTROBE, theHPI sends therequesttotheEDMA internaladdressgenerationhardware,and HRDY remainshighuntiltheEDMA internaladdress generationhardwareloadstherequesteddataintoHPID. (5) Thisparameterisused afterthesecond half-wordofan HPID writeorautoincrementread.HRDY remainslowiftheaccessisnotan HPID writeorautoincrementread.ReadingorwritingtoHPIC orHPIA does notaffecttheHRDY signal. Figure11-31.HPI Read Timing (HAS Not Used, TiedHigh) Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 115 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□(output) HRDY (case□1) HRDY (case□2) 1st□half-word 2nd□half-word 5178 51785 916 111011 10 19 19 1818 (B) (A) NOTES□A:□For□correct□operation,□strobe□the signal□only□once□per active□cycle. B: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR . HAS HSTROBE HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS 1st□halfword 2nd□halfword 5175 1HAS HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□□(input) HRDY (A) NOTE□A: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR .HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Figure11-32.HPI Read Timing (HAS Used) Figure11-33.HPI WriteTiming (HAS Not Used, TiedHigh)

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1st□half-word 2nd□half-word 5175 13121312 HAS HCNTL[1:0] HR/W HHWIL HSTROBE HCS HD[15:0]□□(input) HRDY 1919 18 18 (A) (B) NOTES□A:□For□correct□operation,□strobe□the signal□only□once□per active□cycle. B: refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR . HAS HSTROBE HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Figure11-34.HPI WriteTiming (HAS Used) Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 117 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11.16 MultichannelBufferedSerialPort(McBSP) Timing

Table11-25.Timing Requirements forMcBSP (1)(2) See NO. PARAMETER MIN MAX UNIT 2 tc(CKRX) Cycletime,CLKR/X CLKR/X ext 2P (3) ns 3 tw(CKRX) Pulseduration,CLKR/X highorCLKR/X low CLKR/X ext 0.5*tc(CKRX) – 1(4) ns CLKR int 9 nsSetuptime,externalFSR highbeforeCLKR5 tsu(FRH-CKRL) low CLKR ext 1 ns CLKR int 6 ns 6 th(CKRL-FRH) Holdtime,externalFSR highafterCLKR low CLKR ext 3 ns CLKR int 8 ns 7 tsu(DRV-CKRL) Setuptime,DR validbeforeCLKR low CLKR ext 0 ns CLKR int 3 ns 8 th(CKRL-DRV) Holdtime,DR validafterCLKR low CLKR ext 4 ns CLKX int 9 nsSetuptime,externalFSX highbeforeCLKX10 tsu(FXH-CKXL) low CLKX ext 1 ns CLKX int 6 ns 11 th(CKXL-FXH) Holdtime,externalFSX highafterCLKX low CLKX ext 3 ns (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) P = 1/CPU clockfrequencyinns.Forexample,when runningpartsat300 MHz, use P = 3.3ns. (3) The minimum CLKR/X periodistwicetheCPU cycletime(2P)and notfasterthan75 Mbps (13.3ns).Thismeans thatthemaximum bit rateforcommunicationsbetween theMcBSP and otherdevicesis75 Mbps for167-MHz and 225-MHz CPU clocksor50 Mbps for 100-MHz CPU clock;where theMcBSP iseitherthemasterortheslave.Care must be takentoensurethattheac timingsspecifiedin thisdatasheetaremet.The maximum bitrateforMcBSP-to-McBSP communicationsis67 Mbps; therefore,theminimum CLKR/X clock cycleiseithertwicetheCPU cycletime(2P),or15 ns (67MHz), whichevervalueislarger.Forexample,when runningpartsat 150 MHz (P = 6.7ns),use 15 ns as theminimum CLKR/X clockcycle(bysettingtheappropriateCLKGDV ratioorexternalclock source).When runningpartsat60 MHz (P = 16.67ns),use 2P = 33 ns (30MHz) as theminimum CLKR/X clockcycle.The maximum bitrateforMcBSP-to-McBSP communicationsapplieswhen theserialportisa masteroftheclockand framesyncs(withCLKR connectedtoCLKX, FSR connectedtoFSX, CLKXM = FSXM = 1,and CLKRM = FSRM = 0)indatadelay1 or2 mode (R/XDATDLY = 01b or10b)and theotherdevicetheMcBSP communicatestoisa slave. (4) Thisparameterappliestothemaximum McBSP frequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle.

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Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 1312 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) DX 1313 SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table11-26.SwitchingCharacteristicsforMcBSP overrecommended operatingconditions(see) 6713 6713B NO. PARAMETER UNIT MIN MAX MIN MAX Delaytime,CLKS hightoCLKR/X highfor1 td(CKSH-CKRXH) 1.8 10 1.8 10 nsinternalCLKR/X generatedfromCLKS input 2 tc(CKRX) Cycletime,CLKR/X CLKR/X int 2P 2P ns Pulseduration,CLKR/X highor3 tw(CKRX) CLKR/X int C – 1 C + 1 C – 1 C + 1 nsCLKR/X low Delaytime,CLKR hightointernal4 td(CKRH-FRV) CLKRint –2 3 –2 3 nsFSR valid CLKX int –2 3 –2 3 nsDelaytime,CLKX hightointernal9 td(CKXH-FXV) FSX valid CLKX ext 2 9 2 9 ns Disabletime,DX highimpedance CLKX int –1 4 –1 4 ns 12 tdis(CKXH-DXHZ) followinglastdatabitfromCLKX CLKX ext 1.5 10 1.5 10 nshigh CLKX int –3.2+ D1 4 + D2 –3.2+ D1 4 + D2 ns 13 td(CKXH-DXV) Delaytime,CLKX hightoDX valid CLKX ext 0.5+ D1 10 + D2 0.5+ D1 10 + D2 ns Delaytime,FSX hightoDX valid FSX int –1.5 4.5 –1 7.5 ns 14 td(FXH-DXV) ONLY applieswhen indatadelay0 FSX ext 2 9 2 11.5 ns(XDATDLY = 00b)mode Figure11-35.McBSP Timings Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 119 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

FSR□external CLKR/X□(no□need□to□resync) CLKR/X□(needs□resync) SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table11-27.Timing Requirements forFSR When GSYNC = 1 See NO. MIN MAX UNIT 1 tsu(FRH-CKSH) Setuptime,FSR highbeforeCLKS high 4 ns 2 th(CKSH-FRH) Holdtime,FSR highafterCLKS high 4 ns Figure11-36.FSR Timing When GSYNC = 1 Table11-28.Timing Requirements forMcBSP as SPI Master or Slave: CLKSTP = 10b,CLKXP = 0 See MASTER SLAVE NO. UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setuptime,DR validbeforeCLKX low 12 2 – 6P ns 5 th(CKXL-DRV) Holdtime,DR validafterCLKX low 4 5 + 12P ns

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Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table11-29.SwitchingCharacteristicsforMcBSP as SPI Master or Slave: CLKSTP = 10b,CLKXP = 0 overrecommended operatingconditions(see) 6713 6713B NO. PARAMETER MASTER SLAVE MASTER SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX

1 Holdtime,FSX lowafterCLKX nsth(CKXL-FXL) T – 2 T + 3 T – 2 T + 3low

2 Delaytime,FSX lowtoCLKX nstd(FXL-CKXH) L – 2 L + 3 L – 2 L + 3high

3 td(CKXH-DXV) Delaytime,CLKX hightoDX ns–3 4 6P + 2 10P + 17 –3 4 6P + 2 10P + 17valid Disabletime,DX high 6 tdis(CKXL-DXHZ) impedance followinglastdata L – 4 L + 3 L – 2 L + 3 ns bitfromCLKX low Disabletime,DX high 2P +7 tdis(FXH-DXHZ) impedance followinglastdata 6P + 17 2P + 3 6P + 17 ns1.5bitfromFSX high 8 td(FXL-DXV) Delaytime,FSX lowtoDX valid 4P + 2 8P + 17 4P + 2 8P + 17 ns Figure11-37.McBSP Timing as SPI Master or Slave:CLKSTP = 10b,CLKXP = 0 Table11-30.Timing Requirements forMcBSP as SPI Master or Slave: CLKSTP = 11b,CLKXP = 0 See MASTER SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setuptime,DR validbeforeCLKX high 12 2 – 6P ns 5 th(CKXH-DRV) Holdtime,DR validafterCLKX high 4 5 + 12P ns Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 121 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) 376 CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table11-31.SwitchingCharacteristicsforMcBSP as SPI Master or Slave: CLKSTP = 11b,CLKXP = 0 overrecommended operatingconditions(see) 6713 6713B NO. PARAMETER MASTER SLAVE MASTER SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX Holdtime,FSX lowafter1 th(CKXL-FXL) L – 2 L + 3 L – 2 L + 3 nsCLKX low Delaytime,FSX lowto2 td(FXL-CKXH) T – 2 T + 3 T – 2 T + 3 nsCLKX high Delaytime,CLKX lowtoDX3 td(CKXL-DXV) –3 4 6P + 2 10P + 17 –3 4 6P + 2 10P + 17 nsvalid Disabletime,DX high 6P +6 tdis(CKXL-DXHZ) impedance followinglast – 4 4 10P + 17 – 2 4 6P + 3 10P + 17 ns1.5databitfromCLKX low Delaytime,FSX lowtoDX7 td(FXL-DXV) H – 2 H + 4 4P + 2 8P + 17 H – 2 H + 6.5 4P + 2 8P + 17 nsvalid Figure11-38.McBSP as SPI Master or Slave:CLKSTP = 11b,CLKXP = 0

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Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 Table11-32.Timing Requirements forMcBSP as SPI Master or Slave: CLKSTP = 10b,CLKXP = 1 See MASTER SLAVE NO. UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setuptime,DR validbeforeCLKX high 12 2 – 6P ns 5 th(CKXH-DRV) Holdtime,DR validafterCLKX high 4 5 + 12P ns Table11-33.SwitchingCharacteristicsforMcBSP as SPI Master or Slave: CLKSTP = 10b,CLKXP = 1 overrecommended operatingconditions(see) 6713 6713B NO. PARAMETER MASTER SLAVE MASTER SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX Holdtime,FSX lowafterCLKX ns1 th (CKXH-FXL) T – 2 T + 3 T – 2 T + 3high H + ns2 td (FXL-CKXL) Delaytime,FSX lowtoCLKX low H – 2 H – 2 H + 33 3 td (CKXL-DXV) Delaytime,CLKX lowtoDX valid –3 4 6P + 2 10P + 17 –3 4 6P + 2 10P + 17 ns Disabletime,DX highimpedance H – H +6 tdis(CKXH-DXHZ) followinglastdatabitfromCLKX H – 2 H + 3 ns3.6 3high Disabletime,DX highimpedance 2P +7 tdis(FXH-DXHZ) followinglastdatabitfromFSX 6P + 17 2P + 3 6P + 17 ns1.5high 8 td (FXL-DXV) Delaytime,FSX lowtoDX valid 4P + 2 8P + 17 4P + 2 8P + 17 ns Figure11-39.McBSP as SPI Master or Slave:CLKSTP = 10b,CLKXP = 1 Table11-34.Timing Requirements forMcBSP as SPI Master or Slave:CLKSTP = 11b,CLKXP = 1 See MASTER SLAVE NO. UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setuptime,DR validbeforeCLKX high 12 2 – 6P ns 5 th(CKXH-DRV) Holdtime,DR validafterCLKX high 4 5 + 12P ns Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 123 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) 376 CLKX FSX DX DR SM320C6713-EP SM320C6713B-EP SGUS049I –AUGUST 2003–REVISED SEPTEMBER 2009 www.ti.com Table11-35.SwitchingCharacteristicsforMcBSP as SPI Master or Slave: CLKSTP = 11b,CLKXP = 1 overrecommended operatingconditions(see) 6713 6713B NO. PARAMETER MASTER SLAVE MASTER SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX Holdtime,FSX lowafterCLKX H – H + H – ns1 th(CKXH-FXL) T + 3high 2 3 2 2 td(FXL-CKXL) Delaytime,FSX lowtoCLKX low T – 2 T + 3 T – 2 H + 3 ns Delaytime,CLKX hightoDX ns3 td(CKXH-DXV) –3 4 6P + 2 10P + 17 –3 4 6P + 2 10P + 17valid Disabletime,DX highimpedance 6P +6 tdis(CKXH-DXHZ) followinglastdatabitfromCLKX – 3.6 4 10P + 17 – 2 4 6P + 3 10P + 17 ns1.5high 7 td(FXL-DXV) Delaytime,FSX lowtoDX valid L – 2 L + 4 4P + 2 8P + 17 L – 2 L + 6.5 4P + 2 8P + 17 ns Figure11-40.McBSP as SPI Master or Slave:CLKSTP = 11b,CLKXP = 1

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11.17 Timer Timing

Table11-36.Timing Requirements forTimer Inputs See NO. MIN MAX UNIT 1 tw(TINPH) Pulseduration,TINP high 2P ns 2 tw(TINPL) Pulseduration,TINP low 2P ns Table11-37.SwitchingCharacteristicsforTimer Inputs overrecommended operatingconditions(see) NO. PARAMETER MIN MAX UNIT 3 tw(TOUTH) Pulseduration,TOUT high 4P – 3 ns 4 tw(TOUTL) Pulseduration,TOUT low 4P – 3 ns Figure11-41.Timer Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 125 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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11.18 General-PurposeInput/Output(GPIO)PortTiming

Table11-38.Timing Requirements forGPIO Inputs See NO. MIN MAX UNIT 1 tw(GPIH) Pulseduration,GPIx high 4P ns 2 tw(GPIL) Pulseduration,GPIx low 4P ns Table11-39.SwitchingCharacteristicsforGPIO Inputs overrecommended operatingconditions(see) NO. PARAMETER MIN MAX UNIT 3 tw(GPOH) Pulseduration,GPOx high 12P – 3 ns 4 tw(GPOL) Pulseduration,GPOx low 12P – 3 ns Figure11-42.GPIO PortTiming

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11.19 JTAG TestPortTiming

Table11-40.Timing Requirements forJTAG TestPort See NO. MIN MAX UNIT 1 tc(TCK) Cycletime,TCK 35 ns tsu(TDIV-3 Setuptime,TDI/TMS/TRST validbeforeTCK high 10 ns TCKH) 4 th(TCKH-TDIV) Holdtime,TDI/TMS/TRST validafterTCK high 7 ns Table11-41.SwitchingCharacteristicsforJTAG TestPort overrecommended operatingconditions(see) NO. PARAMETER MIN MAX UNIT 2 td(TCKL-TDOV) Delaytime,TCK lowtoTDO valid 0 15 ns Figure11-43.JTAG Test-PortTiming Copyright© 2003–2009,Texas InstrumentsIncorporated PARAMETRIC INFORMATION 127 SubmitDocumentationFeedback ProductFolderLink(s):SM320C6713-EP

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12 MECHANICAL DATA

12.1 MechanicalInformation

The followingtableshows thethermalresistancecharacteristicsfortheGDP package. Table12-1.Thermal ResistanceCharacteristics(S-PBGA Package) forGDP AirFlowNO °C/W (m/s) Two Signals,Two Planes (4-LayerBoard) 1 R θJC Junction-to-case 9.7 N/A 2 PsiJT Junction-to-packagetop 1.5 0.0

3 R θJB Junction-to-board 19 N/A

4 R θJA Junction-to-freeair 22 0.0 5 R θJA Junction-to-freeair 21 0.5 6 R θJA Junction-to-freeair 20 1.0 7 R θJA Junction-to-freeair 19 2.0 8 R θJA Junction-to-freeair 18 4.0 9 PsiJB Junction-to-board 16 0.0

12.2 Packaging Information

For properdevicethermalperformance,thethermalpad must be solderedtoan externalgroundthermal plane.The followingpackaginginformationand addendum reflectthemost currentreleaseddataavailable forthe designateddevice(s).Thisdata issubjectto change withoutnoticeand withoutrevisionof this document.

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Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SM320C6713GDPS20EP OBSOLETE BGA GDP 272 TBD Call TI Call TI SM32C6713BGDPA20EP ACTIVE BGA GDP 272 40 TBD Call TI Level-3-220C-168 HR SM32C6713BGDPM30EP ACTIVE BGA GDP 272 1 TBD SNPB Level-3-220C-168 HR SM32C6713BGDPS20EP ACTIVE BGA GDP 272 40 TBD Call TI Level-3-220C-168 HR V62/04603-02XA ACTIVE BGA GDP 272 40 TBD Call TI Level-3-220C-168 HR V62/04603-03XA ACTIVE BGA GDP 272 40 TBD Call TI Level-3-220C-168 HR V62/04603-04XA ACTIVE BGA GDP 272 1 TBD SNPB Level-3-220C-168 HR V62/4603-04XA ACTIVE BGA GDP 272 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2009 Addendum-Page 1

MPBG274 – MAY 2002 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GDP (S–PBGA–N272) PLASTIC BALL GRID ARRAY 2468 2 0 1816141210 M E A C B D G F H K J L W R N P U T V Y 3 57 9 11 171513 19 0,635 0,635 26,80SQ 23,80 24,20SQ 27,20 24,13 TYP 0,57 0,65 0,60 0,90 Seating Plane 0,50 0,70 2,57 MAX 0,15 0,10 A1 Corner 1,27 1,27 4204396/A 04/02 Bottom View 1,12 1,22 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151

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Product Information

SMX320C6713GNYM20EP specifications and overview.

Summary

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

Description

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

Source title SMX320C6713GNYM20EP Datasheet(PDF) - Texas Instruments

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