SMX320C6201BS14

SMJ320C6701_07 TI | Alldatasheet

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Technical content

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Highest Performance Floating-Point Digital Signal Processor (DSP) SMJ320C6701 – 7-, 6-ns Instruction Cycle Time – 140-, 167-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – Up to 1 GFLOPS Performance – Pin-Compatible With ’C6201 Fixed-Point DSP /C0068SMJ: QML Processing to MIL-PRF-38535 /C0068SM: Standard Processing /C0068Operating Temperature Ranges – Extended (W) –55°C to 115°C – Extended (S) –40°C to 90°C /C0068VelociTI Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core – Eight Highly Independent Functional Units: – Four ALUs (Floating- and Fixed-Point) – Two ALUs (Fixed-Point) – Two Multipliers (Floating- and Fixed-Point) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional /C0068Instruction Set Features – Hardware Support for IEEE Single-Precision Instructions – Hardware Support for IEEE Double-Precision Instructions – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization /C00681M-Bit On-Chip SRAM – 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) – 512K-Bit Dual-Access Internal Data (64K Bytes) /C006832-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM and SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM /C0068Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel /C006816-Bit Host-Port Interface (HPI) – Access to Entire Memory Map /C0068Two Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral-Interface (SPI) Compatible (Motorola ) /C0068Two 32-Bit General-Purpose Timers /C0068Flexible Phase-Locked-Loop (PLL) Clock Generator /C0068IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible /C0068429-Pin Ceramic Ball Grid Array (CBGA) Package (GLP Suffix) /C00680.18-µm/5-Level Metal Process – CMOS Technology /C00683.3-V I/Os, 1.9-V Internal Copyright  2001, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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description

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI ), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation. TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation.

the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the ’C6701 Processors

2 Mutichannel Buffered Serial Ports (McBSP)

2 General-Purpose Timers

3.3 V I/O

1 Block Program/Cache

2 Blocks of 8 Banks

† These functional units execute floating-point instructions.

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The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional and CPU block diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

† These functional units execute floating-point instructions. Figure 1. SMJ320C67x CPU Data Paths

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Figure 2. CPU and Peripheral Signals

Figure 3. Peripheral Signals

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION CLOCK/PLL CLKIN A14 I Clock Input CLKOUT1 Y6 O Clock output at full device speed CLKOUT2 V9 O Clock output at half of device speed CLKMODE1 B17 I Clock mode select CLKMODE0 C17 I • Selects whether the output clock frequency = input clock freq x4 or x1 PLLFREQ3 C13 PLL frequency range (3, 2, and 1) PLLFREQ2 G11 I • The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins. PLLFREQ1 F11 I PLLV ‡ D12 A§ PLL analog VCC connection for the low-pass filter PLLG ‡ G10 A§ PLL analog GND connection for the low-pass filter PLLF C12 A§ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS K19 I JTAG test port mode select (features an internal pull-up) TDO R12 O/Z JTAG test port data out TDI R13 I JTAG test port data in (features an internal pull-up) TCK M20 I JTAG test port clock TRST N18 I JTAG test port reset (features an internal pull-down) EMU1 R20 I/O/Z Emulation pin 1, pull-up with a dedicated 20-kΩ resistor¶ EMU0 T18 I/O/Z Emulation pin 0, pull-up with a dedicated 20-kΩ resistor¶ RESET AND INTERRUPTS RESET J20 I Device reset NMI K21 I Nonmaskable interrupt

• Edge-driven (rising edge) EXT_INT7 R16 EXT_INT6 P20 I External interrupts EXT_INT5 R15 I External interru ts
• Edge-driven (rising edge) EXT_INT4 R18 gg g IACK R11 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 T19 INUM2 T20 O Active interrupt identification number
• Valid during IACK for all active interrupts (not just external)INUM1 T14 O • Valid during IACK for all active interrupts (not just external)
• Encoding order follows the interrupt service fetchpacket ordering INUM0 T16
• Encoding order follows the interru t service fetch acket ordering LITTLE ENDIAN/BIG ENDIAN LENDIAN G20 I If high, selects little-endian byte/half-word addressing order within a word If low, selects big-endian addressing POWER DOWN STATUS PD D19 O Power-down mode 2 or 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect those pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION HOST PORT INTERFACE (HPI) HINT H2 O/Z Host interrupt (from DSP to host) HCNTL1 J6 I Host control – selects between control, address or data registers HCNTL0 H6 I Host control – selects between control, address or data registers HHWIL E4 I Host halfword select – first or second halfword (not necessarily high or low order) HBE1 G6 I Host byte select within word or half-word HBE0 F6 I Host byte select within word or half-word HR/W D4 I Host read or write select HD15 D11 HD14 B11 HD13 A11 HD12 G9 HD11 D10 HD10 A10 HD9 C10 HD8 B9 I/O/Z Host port data ( sed for transfer of data address and control)HD7 F9 I/O/Z Host port data (used for transfer of data, address and control) HD6 C9 HD5 A9 HD4 B8 HD3 D9 HD2 D8 HD1 B7 HD0 C7 HAS L6 I Host address strobe HCS C5 I Host chip select HDS1 C4 I Host data strobe 1 HDS2 K6 I Host data strobe 2 HRDY H3 O Host ready (from DSP to host) BOOT MODE BOOTMODE4 B16 BOOTMODE3 G14 BOOTMODE2 F15 I Boot mode BOOTMODE1 C18 I Boot mode BOOTMODE0 D17 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 Y5 O/Z CE2 V3 O/Z Memory space enables CE1 T6 O/Z • Enabled by bits 24 and 25 of the word address CE0 U2 O/Z • Only one asserted during any external data access BE3 R8 O/Z Byte enable control BE2 T3 O/Z • Decoded from the two lowest bits of the internal address BE1 T2 O/Z • Byte write enables for most types of memory BE0 R2 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF – ADDRESS EA21 L4 EA20 L3 EA19 J2 EA18 J1 EA17 K1 EA16 K2 EA15 L2 EA14 L1 EA13 M1 EA12 M2 O/Z E ternal address ( ord address)EA11 M6 O/Z External address (word address) EA10 N4 EA9 N1 EA8 N2 EA7 N6 EA6 P4 EA5 P3 EA4 P2 EA3 P1 EA2 P6 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION EMIF – DATA ED31 U18 ED30 U20 ED29 T15 ED28 V18 ED27 V17 ED26 V16 ED25 T12 ED24 W17 ED23 T13 ED22 Y17 ED21 T11 ED20 Y16 ED19 W15 ED18 V14 ED17 Y15 ED16 R9 I/O/Z E ternal dataED15 Y14 I/O/Z External data ED14 V13 ED13 AA13 ED12 T10 ED11 Y13 ED10 W12 ED9 Y12 ED8 Y11 ED7 V10 ED6 AA10 ED5 Y10 ED4 W10 ED3 Y9 ED2 AA9 ED1 Y8 ED0 W9 EMIF – ASYNCHRONOUS MEMORY CONTROL ARE R7 O/Z Asynchronous memory read enable AOE T7 O/Z Asynchronous memory output enable AWE V5 O/Z Asynchronous memory write enable ARDY R4 I Asynchronous memory ready input † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION EMIF – SYNCHRONOUS BURST SRAM CONTROL SSADS V8 O/Z SBSRAM address strobe SSOE W7 O/Z SBSRAM output enable SSWE Y7 O/Z SBSRAM write enable SSCLK AA8 O/Z SBSRAM clock EMIF – SYNCHRONOUS DRAM CONTROL SDA10 V7 O/Z SDRAM address 10 (separate for deactivate command) SDRAS V6 O/Z SDRAM row address strobe SDCAS W5 O/Z SDRAM column address strobe SDWE T8 O/Z SDRAM write enable SDCLK T9 O/Z SDRAM clock EMIF – BUS ARBITRATION HOLD R6 I Hold request from the host HOLDA B15 O Hold request acknowledge to the host TIMERS TOUT1 G2 O/Z Timer 1 or general-purpose output TINP1 K3 I Timer 1 or general-purpose input TOUT0 M18 O/Z Timer 0 or general-purpose output TINP0 J18 I Timer 0 or general-purpose input DMA ACTION COMPLETE DMAC3 E18 DMAC2 F19 O DMA action completeDMAC1 E20 O DMA action complete DMAC0 G16 MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 F4 I External clock source (as opposed to internal) CLKR1 H4 I/O/Z Receive clock CLKX1 J4 I/O/Z Transmit clock DR1 E2 I Receive data DX1 G4 O/Z Transmit data FSR1 F3 I/O/Z Receive frame sync FSX1 F2 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 K18 I External clock source (as opposed to internal) CLKR0 L21 I/O/Z Receive clock CLKX0 K20 I/O/Z Transmit clock DR0 J21 I Receive data DX0 M21 O/Z Transmit data FSR0 P16 I/O/Z Receive frame sync FSX0 N16 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 N21 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV1 K16 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV2 B13 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV3 B14 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV4 F13 I Reserved for testing, pull-down with a dedicated 20-kΩ resistor RSV5 C15 O Reserved (leave unconnected, do not connect to power or ground) RSV6 F7 I Reserved for testing, pull-up with a dedicated 20-k/C0087 resistor RSV7 D7 I Reserved for testing, pull-up with a dedicated 20-k/C0087 resistor RSV8 B5 I Reserved for testing, pull-up with a dedicated 20-k/C0087 resistor RSV9 F16 O Reserved (leave unconnected, do not connect to power or ground) SUPPLY VOLTAGE PINS C14 E19 H11 H13 J10 J12 J14 DV DD J19 S 3.3-V supply voltageDV DD S 3.3 V su ly voltage K11 K13 K15 L10 L12 L14 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) M11 M13 M15 N10 N12 N14 DV DD N19 S 3.3-V supply voltageDV DD S 3.3 V su ly voltage P11 P13 U19 W14 A12 A13 B10 B12 D15 D16 F10 F14 CV S 1 9 V s ppl oltageCV DD G13 S 1.9-V supply voltage A16 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) A18 AA4 AA6 AA15 AA17 AA19 B19 C20 D21 CV S 1 9 V s ppl oltageCV DD E10 S 1.9-V supply voltage E12 E14 E16 F17 F21 H17 K17 M17 P17 R21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) T17 U10 U12 U14 U16 U21 V20 W19 W21 Y18 Y20 CV DD AA11 S 1.9-V supply voltageCV DD AA12 S 1.9 V su ly voltage F20 G18 H16 H18 L18 L19 L20 N20 P18 P19 R10 R14 V11 V12 V15 W13 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS C11 C16 H10 H12 H14 J11 J13 VSS R3 GND Ground pinsVSS GND Ground ins A15 A17 A19 AA3 AA5 AA7 AA14 AA16 AA18 B18 B20 C19 C21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS (CONTINUED) D20 E11 E13 E15 E17 E21 G17 G21 J17 VSS L17 GND Ground pinsVSS GND Ground ins N17 P21 R17 T21 U11 U13 U15 U17 V21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS (CONTINUED) W20 Y19 F18 G19 H15 J15 J16 K10 K12 K14 L11 L13 L15 VSS M10 GND Ground pinsVSS M12 GND Ground ins M14 N11 N13 N15 P10 P12 P14 P15 R19 W11 W16 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION REMAINING UNCONNECTED PINS D13 D14 D18 F12 G12 G15 NC H19 UnconnectedpinsNC H20 Unconnected pins H21 L16 M16 M19 V19 W18 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

fully integrate and debug software and hardware modules. contact the Literature Response Center at 800/477-8924. availability, contact the nearest TI field sales office or authorized distributor. Table 2. SMJ320C6x Development-Support Tools † Contact IRVINE Compiler Corporation (949) 250-1366 to order. ‡ NT support estimated availability 1Q00. § Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included. ¶ Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable. XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Win32 and Windows NT are trademarks of Microsoft Corporation. SPARC is a trademark of SPARC International, Inc. Solaris is a trademark of Sun Microsystems, Inc.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

device and development-support tool nomenclature To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all SMJ320 devices and support tools. Each SMJ320 member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SMJ/TMDS). Device development evolutionary flow: SMX Experimental device that is not necessarily representative of the final device’s electrical specifications SM Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SMJ Fully qualified production device processed to MIL-PRF-38535 Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product SMX devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLP), the temperature range, and the device speed range in megahertz (for example, 16 is 167 MHz). Figure 4 provides a legend for reading the complete device name for any SMJ320 family member.

Figure 4. SMJ320 Device Nomenclature (Including SMJ320C6701) ’C6000 CPU architecture, instruction set, pipeline, and associated interrupts. power-down modes. This guide also includes information on internal data and program memories. assembly code for ’C6x devices and includes application program examples. debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.

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application programming interfaces, and technical reference material. and APIs to analyze embedded real-time DSP applications. development environment to build and debug embedded real-time DSP applications. development environment and software tools. devices, associated development tools, and third-party support. for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323. bypasses the PLL to become the internal CPU clock. Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. 20-30 MHz, maximum dB attenuation = 45-50 dB, and minimum dB attenuation above 30 MHz = 20 dB. Table 3. CLKOUT1 Frequency Ranges of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.

Table 4. ’C6701 PLL Component Selection Table typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. components other than the ones shown. C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD . Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode

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NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD . Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only supply is below the proper operating voltage. output buffers are powered up, thus, preventing bus contention with other chips on the board. between the core supply power up and the I/O supply power up can minimize the effects of this current draw. core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 27POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT CV DD Supply voltage 1.81 1.9 1.99 V DV DD Supply voltage 3.14 3.30 3.46 V VSS Supply ground 0 0 0 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IOH High-level output current –12 mA IOL Low-level output current 12 mA TC Case temperature S suffix device –40 90 /C0095CTC Case temperature W suffix device –55 115 /C0095C

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage DV DD = MIN, I OH = MAX 2.4 V VOL Low-level output voltage DV DD = MIN, I OL = MAX 0.6 V II Input current† VI = VSS to DVDD ±10 uA IOZ Off-state output current VO = DVDD or 0 V ±10 uA IDD2V Supply current, CPU + CPU memory access‡ CV DD = NOM, CPU clock = 150 MHz 470 mA IDD2V Supply current, peripherals§ CV DD = NOM, CPU clock = 150 MHz 250 mA IDD3V Supply current, I/O pins¶ DV DD = NOM, CPU clock = 150 MHz 85 mA C i Input capacitance *15 pF C o Output capacitance *15 pF * This parameter is not tested. † TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ‡ Measured with average CPU activity: 50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle 50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle § Measured with average peripheral activity: 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs ¶ Measured with average I/O activity (30-pF load, SDCLK on): 25% of time: Reads from external SDRAM 25% of time: Writes to external SDRAM 50% of time: No activity

† Typical distributed load circuit capacitance. All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements

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NO. CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 UNITNO. † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. *This parameter is not tested. Figure 8. CLKIN Timings ‡ P = 1/CPU clock frequency in nanoseconds (ns). § PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. *This parameter is not tested. Figure 9. CLKOUT1 Timings

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 12 and Figure 13) NO. ’C6701-14 ’C6701-16 UNITNO . MIN MAX UNIT 6 tsu(EDV-CKO1H) Setup time, read EDx valid before CLKOUT1 high 4.8 ns 7 th(CKO1H-EDV) Hold time, read EDx valid after CLKOUT1 high 1.5 ns 10 tsu(ARDY-CKO1H) Setup time, ARDY valid before CLKOUT1 high 3.5 ns 11 th(CKO1H-ARDY) Hold time, ARDY valid after CLKOUT1 high 1.5 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics for asynchronous memory cycles‡ (see Figure 12 and Figure 13) NO. PARAMETER ’C6701-14 ’C6701-16 UNITNO . PARAMETER MIN MAX UNIT 1 td(CKO1H-CEV) Delay time, CLKOUT1 high to CEx valid –1.0 4.5 ns 2 td(CKO1H-BEV) Delay time, CLKOUT1 high to BEx valid 4.5 ns 3 td(CKO1H-BEIV) Delay time, CLKOUT1 high to BEx invalid –1.0 ns 4 td(CKO1H-EAV) Delay time, CLKOUT1 high to EAx valid 4.5 ns 5 td(CKO1H-EAIV) Delay time, CLKOUT1 high to EAx invalid –1.0 ns 8 td(CKO1H-AOEV) Delay time, CLKOUT1 high to AOE valid –1.0 4.5 ns 9 td(CKO1H-AREV) Delay time, CLKOUT1 high to ARE valid –1.0 4.5 ns 12 td(CKO1H-EDV) Delay time, CLKOUT1 high to EDx valid 4.5 ns 13 td(CKO1H-EDIV) Delay time, CLKOUT1 high to EDx invalid –1.0 ns 14 td(CKO1H-AWEV) Delay time, CLKOUT1 high to AWE valid –1.0 4.5 ns ‡ The minimum delay is also the minimum output hold after CLKOUT1 high.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

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SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 14) NO ’C6701-14 ’C6701-16 UNITNO. MIN MAX MIN MAX UNIT 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 2.6 2.5 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 14 and Figure 15) NO PARAMETER ’C6701-14 ’C6701-16 UNITNO. PARAMETER MIN MAX MIN MAX UNIT 1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns 2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns 3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 0.5P – 1.6 0.5P – 1.6 ns 4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high0.5P – 1.7 0.5P – 1.7 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high0.5P – 2.5 0.5P – 2.5 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high0.5P – 1.5 0.5P – 1.3 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high0.5P – 1.5 0.5P – 1.3 ns 12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P – 2.5 0.5P – 2.5 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high0.5P – 1.5 0.5P – 1.3 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high0.5P – 2.5 0.5P – 2.5 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high0.5P – 1.5 0.5P – 1.3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16) NO ’C6701-14 ’C6701-16 UNITNO. MIN MAX MIN MAX UNIT 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 3.8 3.8 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 16 and Figure 17) NO PARAMETER ’C6701-14 ’C6701-16 UNITNO. PARAMETER MIN MAX MIN MAX UNIT 1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns 2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns 3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns 4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.3 0.5P – 2 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high1.5P – 5.5 1.5P – 4.5 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high0.5P – 2.3 0.5P – 2 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high1.5P – 5.5 1.5P – 4.5 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns 12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high1.5P – 5.5 1.5P – 4.5 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high0.5P – 2.3 0.5P – 2.2 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

timing requirements for synchronous DRAM cycles (see Figure 18) NO ’C6701-14 ’C6701-16 UNITNO. MIN MAX MIN MAX UNIT 7 tsu(EDV-SDCLKH) Setup time, read EDx valid before SDCLK high 2 2 ns 8 th(SDCLKH-EDV) Hold time, read EDx valid after SDCLK high 3 3 ns switching characteristics for synchronous DRAM cycles† (see Figure 18–Figure 23) NO PARAMETER ’C6701-14 ’C6701-16 UNITNO. PARAMETER MIN MAX MIN MAX UNIT 1 tosu(CEV-SDCLKH) Output setup time, CEx valid before SDCLK high 1.5P – 5 1.5P – 4 ns 2 toh(SDCLKH-CEV) Output hold time, CEx valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns 3 tosu(BEV-SDCLKH) Output setup time, BEx valid before SDCLK high 1.5P – 5 1.5P – 4 ns 4 toh(SDCLKH-BEIV) Output hold time, BEx invalid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 5 tosu(EAV-SDCLKH) Output setup time, EAx valid before SDCLK high1.5P – 5 1.5P – 4 ns 6 toh(SDCLKH-EAIV) Output hold time, EAx invalid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 9 tosu(SDCAS-SDCLKH) Output setup time, SDCAS valid before SDCLK high 1.5P – 5 1.5P – 4 ns 10 toh(SDCLKH-SDCAS) Output hold time, SDCAS valid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 11 tosu(EDV-SDCLKH) Output setup time, EDx valid before SDCLK high1.5P – 5 1.5P – 4 ns 12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 13 tosu(SDWE-SDCLKH) Output setup time, SDWE valid before SDCLK high 1.5P – 5 1.5P – 4 ns 14 toh(SDCLKH-SDWE) Output hold time, SDWE valid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 15 tosu(SDA10V-SDCLKH) Output setup time, SDA10 valid before SDCLK high 1.5P – 5 1.5P – 4 ns 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns 17 tosu(SDRAS-SDCLKH) Output setup time, SDRAS valid before SDCLK high 1.5P – 5 1.5P – 4 ns 18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.

40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Figure 20. SDRAM ACTV Command Figure 21. SDRAM DCAB Command

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

† HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. ¶ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE , SDA10, SDRAS, SDCAS, and SDWE. *This parameter is not tested. † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE , SDA10, SDRAS, SDCAS, and SDWE. Figure 24. HOLD/HOLDA Timing

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 RESET TIMING timing requirements for reset (see Figure 25) NO. ’C6701-14 ’C6701-16 UNITNO . MIN MAX UNIT 1 tw(RESET) Width of the RESET pulse (PLL stable)† *10 CLKOUT1 cycles1 tw(RESET) Width of the RESET pulse (PLL needs to sync up)‡ *250 µs † This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. *This parameter is not tested. ‡ This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. switching characteristics during reset§ (see Figure 25) NO. PARAMETER ’C6701-14 ’C6701-16 UNITNO . PARAMETER MIN MAX UNIT 2 tR(RESET) Response time to change of value in RESET signal *1 CLKOUT1 cycles 3 td(CKO1H-CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid *–1 ns 4 td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 valid *10 ns 5 td(CKO1H-SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid *–1 ns 6 td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK valid *10 ns 7 td(CKO1H-SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid *–1 ns 8 td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK valid *10 ns 9 td(CKO1H-LOWIV) Delay time, CLKOUT1 high to low group invalid *–1 ns 10 td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group valid *10 ns 11 td(CKO1H-HIGHIV) Delay time, CLKOUT1 high to high group invalid *–1 ns 12 td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group valid *10 ns 13 td(CKO1H-ZHZ) Delay time, CLKOUT1 high to Z group high impedance *–1 ns 14 td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group valid *10 ns § Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HRDY and HINT. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE , SDA10, SDRAS, SDCAS, SDWE , HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. *This parameter is not tested.

44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

† Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HRDY and HINT. SDWE , HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. Figure 25. Reset Timing

be connected to asynchronous inputs. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. *This parameter is not tested. § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. Figure 26. Interrupt Timing

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) NO. ’C6701-14 ’C6701-16 UNITNO . MIN MAX UNIT 1 tsu(SEL-HSTBL) Setup time, select signals§ valid before HSTROBE low 4 ns 2 th(HSTBL-SEL) Hold time, select signals§ valid after HSTROBE low 2 ns 3 tw(HSTBL) Pulse duration, HSTROBE low *2P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses *2P ns 10 tsu(SEL-HASL) Setup time, select signals§ valid before HAS low 4 ns 11 th(HASL-SEL) Hold time, select signals§ valid after HAS low 2 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 3 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. *1 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low *2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low *2 ns *This parameter is not tested. † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics during host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) NO. PARAMETER ’C6701-14 ’C6701-16 UNITNO . PARAMETER MIN MAX UNIT 5 td(HCS-HRDY) Delay time, HCS to HRDY¶ 1 12 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 1 12 ns 7 toh(HSTBL-HDLZ) Output hold time, HD low impedance after HSTROBE low for an HPI read *4 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low *P – 3 *P + 3 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance *3 *12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 12 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 1 12 ns *This parameter is not tested. † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. ||This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 29. HPI Write Timing (HAS Not Used, Tied High) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 30. HPI Write Timing (HAS Used)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 49POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 31) NO. ’C6701-14 ’C6701-16 UNITNO . MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext *2P ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext *P – 1 ns 5 t Set p time e ternal FSR high before CLKR lo CLKR int *13 ns5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 4 ns 6 t Hold time e ternal FSR high after CLKR lo CLKR int *7 ns6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 4 ns 7 t Set p time DR alid before CLKR lo CLKR int 10 ns7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 1 ns 8 t Hold time DR valid after CLKR low CLKR int 4 ns8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4 ns 10 t Set p time e ternal FSX high before CLKX lo CLKX int *13 ns10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 4 ns 11 t Hold time e ternal FSX high after CLKX lo CLKX int *7 ns11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. *This parameter is not tested.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP†‡§ (see Figure 31) NO. PARAMETER ’C6701-14 ’C6701-16 UNITNO . PARAMETER MIN MAX UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 3 15 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1¶ C + 1¶ ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –4 4 ns 9 t Dela time CLKX high to internal FSX alid CLKX int –4 5 ns9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext *3 *16 ns 12 t Disable time, DX high impedance following last data bit fromCLKX int *–3 *2 ns12 tdis(CKXH-DXHZ) Disable time, DX high im edance following last data bit from CLKX high CLKX ext *2 *9 ns 13 t Delay time CLKX high to DX valid CLKX int –2 4 ns13 td(CKXH-DXV) Delay time, CLKX high to DX valid. CLKX ext 3 16 ns 14 t Delay time, FSX high to DX valid. FSX int *–2 *4 ns14 td(FXH-DXV) Delay time, FSX high to DX valid. ONLY applies when in data delay 0 (XDATDLY = 00b) mode.FSX ext *2 *10 ns † CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero *This parameter is not tested.

Figure 31. McBSP Timings

52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

*This parameter is not tested. Figure 32. FSR Timing When GSYNC = 1

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) NO ’C6701-14 ’C6701-16 UNITNO. MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 – 3P ns 5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 5 + 6P ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) NO PARAMETER ’C6701-14 ’C6701-16 UNITNO. PARAMETER MASTER § SLAVE UNIT MIN MAX MIN MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ T – 4 T + 4 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# L – 4 L + 4 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid –4 4 3P + 1 5P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low *L – 2 *L + 3 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high *P + 4 *3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns *This parameter is not tested. † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

*This parameter is not tested. in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001

56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) NO ’C6701-14 ’C6701-16 UNITNO. MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 – 3P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 5 + 6P ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) NO PARAMETER ’C6701-14 ’C6701-16 UNITNO. PARAMETER MASTER § SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ T – 4 T + 4 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# H – 4 H + 4 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid –4 4 3P + 1 5P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high *H – 2 *H + 3 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high *P + 4 *3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns *This parameter is not tested. † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

*This parameter is not tested. in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

*This parameter is not tested. Figure 40. JTAG Test-Port Timing

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS030B – APRIL 2000 – REVISED MAY 2001 61POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 MECHANICAL DATA GLP (S-CBGA-N429) CERAMIC BALL GRID ARRAY 0,15 1,27 M∅ 0,10 25,40 TYP 1816 15 171311 10 12 14 Y V W AA U R T N M P K H J F E G C A B D L Seating Plane 4164732/A 08/98 SQ27,20 26,80 0,50 0,700,60 0,90 1,00 1,22 3,30 MAX 1,27 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-156 D. Flip chip application only thermal resistance characteristics (S-CBGA package) NO °C/W Air Flow 1 R Θ JC Junction-to-Case, measured to the bottom of solder ball 3.0 N/A 2 R Θ JC Junction-to-Case, measured to the top of the package lid 7.3 N/A 3 R Θ JA Junction-to-Ambient 14.5 0 4 11.8 150 fpm 5 R Θ JMA Junction-to-Moving-Air 11.1 250 fpm R Θ JMA Junction to Moving Air 10.2 500 fpm

7 R Θ JB

Junction-to-Board, measured by soldering a thermocouple to one of the middle traces on the board at the edge of the package 6.2 N/A

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9866101QXA ACTIVE FC/CSP GLP 429 1 TBD Call TI N / A for Pkg Type 5962-9866101VXA ACTIVE FC/CSP GLP 429 1 TBD Call TI N / A for Pkg Type 5962-9866102VXA ACTIVE FC/CSP GLP 429 1 TBD Call TI N / A for Pkg Type SM320C6701GLPS16 ACTIVE FC/CSP GLP 429 1 TBD Call TI N / A for Pkg Type SM320C6701GLPW14 ACTIVE FC/CSP GLP 429 1 TBD Call TI N / A for Pkg Type SMJ320C6701GLPW14 ACTIVE FC/CSP GLP 429 1 TBD Call TI N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2007 Addendum-Page 1

MCBG004A – SEPTEMBER 1998 – REVISED JANUARY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GLP (S-CBGA-N429) CERAMIC BALL GRID ARRAY 0,15 1,27 M∅ 0,10 25,40 TYP 1816 15 171311 10 12 14 Y V W AA U R T N M P K H J F E G C A B D L Seating Plane 4164732/B 11/01 SQ27,20 26,80 0,50 0,700,60 0,90 1,00 1,22 3,30 MAX 1,27 A1 Corner Bottom View NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-156 D. Flip chip application only

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