SMV512K32

SMV512K32-SP TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 26

Technical content

www.ti.com SLVSA21I – JUNE 2011– REVISED JANUARY 2014 16-MbRADIATION-HARDENEDSRAM Check for Samples: SMV512K32-SP 1FEATURES

• 20-ns Read, 13.8-ns Write Through Maximum • Radiation Performance (1) Access Time – Uses Both Substrate Engineering and
• Functionally Compatible With Commercial Radiation Hardened by Design (HBD) (2) 512K x 32 SRAM Devices – TID Immunity > 3e5 rad (Si)
• Built-In EDAC (Error Detection and Correction) – SER < 5e-17 Upsets/Bit-Day to Mitigate Soft Errors (Core Using EDAC and Scrub) (3)
• Built-In Scrub Engine for Autonomous – Latch up immunity > LET = 110 MeV Correction (T = 398K)
• CMOS Compatible Input and Output Level, • Available in a 76-Lead Ceramic Quad Flatpack Three State Bidirectional Data Bus • Engineering Evaluation (/EM) Samples are – 3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE Available (4) (1) Radiation tolerance is a typical value based upon initial device qualification. Radiation Data and Lot Acceptance Testing is available – contact factory for details. (2) HardSILTM technology and memory design under a license agreement with Silicon Space Technology (SST). (3) SER calculated using CREME96 for geosynchronous orbit, solar minimum. (4) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of -55°C to 125°C or operating life.

DESCRIPTION

The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can be initiated by a master device. Three read cycles and four write cycles (described below) are available depending on the user needs. xxx HardSILTM is a trademark of Silicon Space Technology (SST). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2011–2014, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Figure 1. SMV512K32 Block Diagram Figure 2. SMV512K32 Pin Out

2 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

www.ti.com SLVSA21I – JUNE 2011– REVISED JANUARY 2014 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TERMINAL FUNCTIONS PIN NAME TYPE ACTIVE DESCRIPTION A[18:0] Input N/A Address DQ[31:0] Bidirectional N/A Data input/output E1Z Input Low Chip enable - 1 E2 Input High Chip enable - 2 WZ Input Low Write enable GZ Input Low Output enable for bidirectional input/output VDD1 Power N/A Power supply (1.8 V) VDD2 Power N/A Power supply (3.3 V) VSS1 Power N/A Ground (core) VSS2 Power N/A Ground (I/O) Used for setting master/slave selection. MSS Input N/A Connect to VSS2 for master operation and VDD2 for slave operation. Multiple bit or single bit error indicator MBE Bidirectional High (output - user programmable) EDAC function select (input) Master SCRUBZ (output)SCRUBZ Bidirectional Low Slave SCRUBZ (input) Master BUSYZ (output)BUSYZ Output Low Slave (do not use) ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) VALUE UNIT VDD1 DC supply voltage(core) –0.3 to 2.0 V VDD2 DC supply voltage (I/O) –0.3 to 3.8 V VI/O Voltage on any pin –0.3 to 3.8 V TSTG Storage temperature –65 to 150 °C PD Maximum power dissipation 1.2 W TJ Maximum junction temperature 150 °C θJC Thermal resistance, junction-to-case 5 °C/W II DC input current ±5 mA (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SMV512K32-SP

← Continuous TJ of 95°C results in operating life of 15.03 years. (1) See datasheet for absolute maximum and minimum recommended operating conditions. (2) Mil-Prf 38535, appendix B, section B.3.4 targets a 15 year operating life at 65°C ≤ TJ ≤ 95°C. at 50 MHz and may not reflect actual usage. Figure 3. SMV512K32 Operating Life Derating Chart Over operating free-air temperature range (unless otherwise noted).

4 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

www.ti.com SLVSA21I – JUNE 2011– REVISED JANUARY 2014

ELECTRICAL CHARACTERISTICS

TC = -55°C to 125°C, VDD1 = 1.7 V to 1.9 V, VDD2 = 3 V to 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 0.7 xVIH HIgh-level input voltage VVDD2 0.3 xVIL Low-level input voltage VVDD2 0.2 xVOL Low-level output voltage IOL = 4 mA, VDD2 = VDD2(min) VVDD2 0.8 xVOH High-level output voltage IOH = -4 mA, VDD2 = VDD2(min) VVDD2 CIN (1) Input capacitance f = 1 MHz at 0 V 4.5 pF CIO (1) Bidirectional I/O capacitance f = 1 MHz at 0 V 4.5 pF IIN Input leakage current VIN=VDD2 and VSS –500 500 nA Tri-state output leakage VO= VDD2 and VSSIOZ –500 500 nAcurrent VDD2 = VDD2(max), GZ=VDD2(max) VDD2 = VDD2(max), VO = VDD2IOS (2) (3) Short-circuit output current –46 46 mAVDD = VDD2(max), VO = VSS –55°C to 25°C 18Input: VIL = VSS + 0.2 V, Write 125°C 31VDD1 supply operating current VIH = VDD2 - 0.2 V, IOUT = 0 A,IDD1(OP1) mAat 1 MHz VDD1 = VDD1(max), –55°C to 25°C 13 ReadVDD2 = VDD2(max) 125°C 27 –55°C to 25°C 635Input: VIL = VSS + 0.2 V, Write 125°C 460VDD1 supply operating current VIH = VDD2 - 0.2 V, IOUT = 0 A,IDD1(OP2) mAat 50 MHz VDD1 = VDD1(max), –55°C to 25°C 365 ReadVDD2 = VDD2(max) 125°C 315 –55°C to 25°C 255Input: VIL = VSS + 0.2 V, Write µA 125°C 255VDD2 supply operating current VIH = VDD2 - 0.2 V, IOUT = 0 A,IDD2(OP1) at 1 MHz VDD1 = VDD1(max), –55°C to 25°C 5.2 Read mAVDD2 = VDD2(max) 125°C 5.1 –55°C to 25°C 5.9Input: VIL = VSS + 0.2 V, Write 125°C 1.2VDD2 supply operating current VIH = VDD2 - 0.2 V, IOUT = 0 A,IDD2(OP2) mAat 50 MHz VDD1 = VDD1(max), –55°C to 25°C 275 ReadVDD2 = VDD2(max) 125°C 120 CMOS inputs, IOUT = 0 A –55°C to 25°C 0.375 Supply stand-by current E1Z = VDD2 - 0.2 V, E2 = GND,IDD1(SB)(4) mAat 0 MHz VDD1 = VDD1(max), 125°C 17 VDD2 = VDD2(max) CMOS inputs, IOUT = 0 A –55°C to 25°C 330 Supply stand-by current E1Z = VDD2 - 0.2 V, E2 = GND,IDD2(SB)(4) µAat 0 MHz VDD1 = VDD1(max), 125°C 330 VDD2 = VDD2(max) CMOS inputs, IOUT = 0 A –55°C to 25°C 4.4 Supply stand-by current E1Z = VDD2 - 0.2 V, E2 = GND,IDD1(SB)(4) mAA[16:0] at 50 MHz VDD1 = VDD1(max), 125°C 21 VDD2 = VDD2(max) CMOS inputs, IOUT = 0 A –55°C to 25°C 1.6 Supply stand-by current E1Z = VDD2 - 0.2 V, E2 = GND,IDD2(SB)(4) mAA[16:0] at 50 MHz VDD1 = VDD1(max), 125°C 0.8 VDD2 = VDD2(max) (1) Measured for initial qualification and after process or design changes that could affect input/output capacitance. (2) Provided as a design limit but not guaranteed or tested. (3) No more than one output may be shorted at a time for maximum duration of one second. (4) VIH = VDD2(max), VIL = 0 V Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SMV512K32-SP

device selection, active and stand-by modes (with and without scrub). WZ controls read and write operations. During read operation, GZ must be asserted to enable the outputs. Table 1. SRAM Device Control Operation Truth Table (1) During SCRUB mode, MBE is 3-state if GZ is high and indicates multiple or single bit error if GZ is low. detected and the memory drives MBE high (please refer to the next section). intervals when it is not actively driven HIGH by the memory or actively driven by the external memory control. high this will disable scrub during the interval that GZ is being set high after the memory is disabled. controlled output data valid time, tGLMV.

6 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 2. Example Control Settings for Resetting MBE

1 L H L H L DQ[31:0] Data out Normal read mode with EDAC enabled

3 H L L H H DQ[31:0] Data out Memory disabled

4 H L H H H → L DQ[31:0] Tri-state Outputs tri-stated and MBE pulled low by load R

5 L H H H L DQ[31:0] Tri-state Read at a last known error free address(1)

6 L H L H L DQ[31:0] Data out Output enable-controlled read(2)

(1) During this operation MBE drive circuitry in the memory is tri-stated but MBE is held low by the 1-kΩ resistor to ground. the original state corresponding to normal read mode with EDAC enabled. address to valid data output.

• SRAM read cycle 1 (Figure 4): Address controlled access is initiated by a change in address inputs while device is selected with WZ high and GZ low. Valid data appears on DQ[31:0] after a specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as the device enable and output enable are active, the minimum time between valid address changes is specified by the read cycle time tAVAV.
• SRAM read cycle 2 (Figure 5): Chip-enable controlled access is initiated by the latter of either E1Z or E2 going active while GZ is low, WZ is high, and address remains stable for the entire cycle. After the specified time tETQV, the 32-bit word addressed by A[18:0] is accessed and appears at DQ[31:0].
• SRAM read cycle 3 (Figure 6): Output-enable controlled access is initiated by GZ going active while E1Z and E2 are asserted, WZ is de-asserted, and address is stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. If EDAC is turned on during read operation:
• If MBE is low, data is valid.
• If MBE is high, data is corrupted (dependent on EDAC programming configuration on A[12], MBE can indicate a single bit or double bit error). Single bit error is correctable by EDAC.

Table 3. AC Characteristics Read Cycle (1)

Table 3. AC Characteristics Read Cycle (1) (continued) (3) Parameters ensured by design and/or characterization if not production tested. Figure 4. SRAM Read Cycle 1, Address-Controlled Access Figure 5. Read Cycle 2, Chip Enable-Controlled Access

8 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

will cause MBE to be asserted. Figure 6. Read Cycle 3, Output Enable-Controlled Access or WZ is low during standard read and write cycles.

• Write cycle 1 (Figure 7): Access and data write through controlled by WZ is initiated when WZ goes low and is terminated by WZ going high while E1Z and E2 remain active. The write pulse width is determined by tWLWH and tETWH. To avoid bus contention, tWLQZ must be satisfied before write data is applied to the DQ[31:0] pins. In addition, at the end of the write operation write data must be removed from the DQ[31:0] pins after tWHDX is met, but before tWHQX. The output access time is determined by tWHQV as long as GZ remains low.
• Write cycle 1a (Figure 8): WZ controlled write cycle with GZ high is similar to write cycle 1 but with GZ fixed high so data outputs remain in high impedance state.
• Write cycle 2 (Figure 9): WZ controlled write access with data write through controlled by GZ is similar to write cycle 1 with the difference being that the output data comes out when GZ goes low with WZ high. The output access time is determined by tGLQV. The GZ high pulse is used to keep the DQ[31:0] outputs in a high impedance state during the write operation to avoid bus contention.
• Write cycle 3 (Figure 10): Chip enable controlled write access with data write through controlled by WZ is initiated when E1Z or E2 goes active, and the data write operation is terminated by WZ going high. The write pulse width is defined by tETWHZ from the latter of E1Z or E2 going active to WZ high. The output access time is determined by tWHQV as long as GZ remains low. As with write cycle 1, the write data must be removed from the DQ[31:0] pins after the input data hold time, tWHDX, but before tWHQX.
• Write cycle 3a (Figure 11): chip enabled controlled write cycle with GZ high is similar to write cycle3, but with GZ fixed high so the data outputs remain in a high impedance state.
• Write cycle 4 (Figure 12): Chip enable controlled write access with data write through controlled by GZ is similar to Write cycle 3 with the difference that the data output is controlled by GZ going low. The output access time is determined by tGLQV. The GZ high pulse is used to keep the DQ[31:0] pins in a high impedance state during the write operation to avoid bus contention. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SMV512K32-SP

Table 4. AC Characteristics Write Cycle (1) (2) Write-only operations with GZ fixed high (no write-through). (3) Parameters ensured by design and/or characterization if not production tested.

10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Figure 8. SRAM Write Cycle 1a, WZ-Controlled Write Only With GZ Fixed High Figure 9. SRAM Write Cycle 2, WZ Controlled Write With Data Write Through Controlled by GZ

12 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Figure 12. SRAM Write Cycle 4, Enable Controlled Write With Data Write Through Controlled by GZ cycles for slave units by connecting their respective SCRUBZ pins to the SCRUBZ master output. The EDAC operation truth table is shown in Table 5.

14 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 5. EDAC Control Operation Mode Truth Table (1) MBE is only valid in EDAC operation modes (Read with EDAC enable or scrub). MBE indicates Multiple Bit Error if A[12] bit in the control register is ‘0’. MBE indicates Single Bit Error if A[12] bit in the control register is ‘1’. Data errors are detected and corrected not only during scrub cycles, but also during normal read cycles. detection. See Table 7 for more detail. characteristics for EDAC functions. The following EDAC control operations are defined by Table 6.

• Control register write (Figure 15): This mode is used to write configuration values to the EDAC control register.
• Control register read (Figure 16): This mode is used to read the contents of the EDAC control register.
• Scrub address counter read (Figure 17): This mode is to read out the address counter which is used as a pointer for scrub operations. The address counter is reset to all ‘1’when the configuration register is written. It is then automatically incremented for each scrub cycle. In the event of a single or multiple bit error detected during a scrub cycle, the address can be polled to determine the location of the data error. During the address counter read, the 19 bits of the counter are output on data bits DQ[18:0]. The value of the other data bits DQ[31:19] are ignored.

Table 6. EDAC Function Select Truth Table(1) (1) All other combinations of A7-A10 are reserved and should be avoided.

Table 7. EDAC Control Register Programming(1)(2) (1) A(10:9) must be '00' during control register programming according to Table 6.

1. Scrub enable bit is 0 (enabled).
2. SE/DE indication bit is 0 (multiple bit).

16 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 8. Scrub Rate Variation

0000 N/A

0001 N/A

0010 N/A

0011 N/A

Table 9. BUSYZ Low to SCRUBZ Low Delay Variation

Table 10. AC Characteristics for EDAC Function (1) (2) Parameters ensured by design and/or characterization if not production tested.

18 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Figure 15. Control Register Write Cycle Figure 16. Control Register Read Cycle

20 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Figure 17. Address Counter Read

SLVSA21I – JUNE 2011– REVISED JANUARY 2014 www.ti.com

REVISION HISTORY

Changes from Revision H (July 2013) to Revision I Page

22 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: SMV512K32-SP

www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 5962-1123701VXC Active Production CFP (HFG) | 76 1 | JEDEC TRAY (5+1) Yes AU N/A for Pkg Type -55 to 125 SMV512K32HFG 5962-1123701VXC 5962-1123701VXC.A Active Production CFP (HFG) | 76 1 | JEDEC TRAY (5+1) Yes AU N/A for Pkg Type -55 to 125 SMV512K32HFG 5962-1123701VXC SMV512K32HFG Active Production CFP (HFG) | 76 1 | JEDEC TRAY (5+1) Yes AU N/A for Pkg Type -55 to 125 SMV512K32HFG 5962-1123701VXC (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) 5962-1123701VXC HFG CFP 76 1 2 x 5 150 315 135.9 7620 57 43.5 39.45 5962-1123701VXC.A HFG CFP 76 1 2 x 5 150 315 135.9 7620 57 43.5 39.45 SMV512K32HFG HFG CFP 76 1 2 x 5 150 315 135.9 7620 57 43.5 39.45 Pack Materials-Page 1

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated