MUN5312DW1 ONSEMI | Alldatasheet
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Features
Simplifies Circuit Design Reduces Board Space Reduces Component Count S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (TA = 25C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted) Rating Symbol Max Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current − Continuous IC 100 mAdc Input Forward Voltage VIN(fwd) 40 Vdc Input Reverse Voltage VIN(rev) 10 Vdc Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Device Package Shipping† MUN5312DW1T1G, SMUN5312DW1T1G SOT−363 3,000/Tape & Reel MUN5312DW1T2G SOT−363 3,000/Tape & Reel NSBC124EPDXV6T1G SOT−563 4,000/Tape & Reel NSBC124EPDXV6T5G SOT−563 8,000/Tape & Reel NSBC124EPDP6T5G SOT−963 8,000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refe r to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com MARKING DIAGRAMS PIN CONNECTIONS
12 M /C0071
/C0071 /C0071 12/R = Specific Device Code M = Date Code* /C0071 = Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. SOT−363 CASE 419B SOT−563 CASE 463A (1)(2)(3) (6)(5)(4) R2R1 SOT−963 CASE 527AD M /C0071 /C00711 R
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6 http://onsemi.com THERMAL CHARACTERISTICS Characteristic Symbol Max Unit MUN5312DW1 (SOT−363) ONE JUNCTION HEATED Total Device Dissipation TA = 25C (Note 1) (Note 2) Derate above 25C (Note 1) (Note 2) PD 187 256 1.5 2.0 mW mW/C Thermal Resistance, (Note 1) Junction to Ambient (Note 2) R/C0113JA 670 490 C/W MUN5312DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3) Total Device Dissipation TA = 25C (Note 1) (Note 2) Derate above 25C (Note 1) (Note 2) PD 250 385 2.0 3.0 mW mW/C Thermal Resistance, Junction to Ambient (Note 1) (Note 2) R/C0113JA 493 325 C/W Thermal Resistance, Junction to Lead (Note 1) (Note 2) R/C0113JL 188 208 C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 C NSBC124EPDXV6 (SOT−563) ONE JUNCTION HEATED Total Device Dissipation TA = 25C (Note 1) Derate above 25C (Note 1) PD 357 2.9 mW mW/C Thermal Resistance, Junction to Ambient (Note 1) R/C0113JA 350 C/W NSBC124EPDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3) Total Device Dissipation TA = 25C (Note 1) Derate above 25C (Note 1) PD 500 4.0 mW mW/C Thermal Resistance, Junction to Ambient (Note 1) R/C0113JA 250 C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 C NSBC124EPDP6 (SOT−963) ONE JUNCTION HEATED Total Device Dissipation TA = 25C (Note 4) (Note 5) Derate above 25C (Note 4) (Note 5) PD 231 269 1.9 2.2 MW mW/C Thermal Resistance, Junction to Ambient (Note 4) (Note 5) R/C0113JA 540 464 C/W NSBC124EPDP6 (SOT−963) BOTH JUNCTION HEATED (Note 3) Total Device Dissipation TA = 25C (Note 4) (Note 5) Derate above 25C (Note 4) (Note 5) PD 339 408 2.7 3.3 MW mW/C Thermal Resistance, Junction to Ambient (Note 4) (Note 5) R/C0113JA 369 306 C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 C 1. FR −4 @ Minimum Pad. 2. FR −4 @ 1.0 1.0 Inch Pad. 3. Both junction heated values assume total power is sum of two equally powered channels. 4. FR −4 @ 100 mm2, 1 oz. copper traces, still air. 5. FR −4 @ 500 mm2, 1 oz. copper traces, still air.
- Pulsed Condition: Pulse Width = 300 ms, Duty Cycle 2%.
Figure 1. Derating Curve
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6 http://onsemi.com PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419B −01 OBSOLETE, NEW STANDARD 419B−02. E0.2 (0.008) MM 123 D e A C L 654 −E− b 6 PL DIM MIN NOM MAX MILLIMETERS A 0.80 0.95 1.10 A1 0.00 0.05 0.10 b 0.10 0.21 0.30 C 0.10 0.14 0.25 D 1.80 2.00 2.20 0.031 0.037 0.043 0.000 0.002 0.004 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 MIN NOM MAX INCHES 0.20 REF 0.008 REF HE HE E 1.15 1.25 1.35 e 0.65 BSC L 0.10 0.20 0.30 2.00 2.10 2.20 0.045 0.049 0.053
0.026 BSC
0.004 0.008 0.012 0.078 0.082 0.086 /C0466mm inches/C0467SCALE 20:1 0.65 0.025 0.65 0.025 0.50 0.0197 0.40 0.0157 1.9 0.0748 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* SC−88/SC70−6/SOT−363
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6 http://onsemi.com PACKAGE DIMENSIONS HE DIM MIN NOM MAX MILLIMETERS A 0.50 0.55 0.60 b 0.17 0.22 0.27 C D 1.50 1.60 1.70 E 1.10 1.20 1.30 e 0.5 BSC L 0.10 0.20 0.30 1.50 1.60 1.70 0.020 0.021 0.023 0.007 0.009 0.011 0.059 0.062 0.066 0.043 0.047 0.051
0.02 BSC
0.004 0.008 0.012 0.059 0.062 0.066 MIN NOM MAX INCHES SOT−563, 6 LEAD CASE 463A ISSUE F e M0.08 (0.003) X b 6 5 PL A C −X− −Y− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. D E Y 12 3 L 1.35 0.0531 0.5 0.0197 /C0466mm inches/C0467SCALE 20:1 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* HE
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6 http://onsemi.com PACKAGE DIMENSIONS SOT−963 CASE 527AD ISSUE E DIM MIN NOM MAX MILLIMETERS A 0.34 0.37 0.40 b 0.10 0.15 0.20 C 0.07 0.12 0.17 D 0.95 1.00 1.05 E 0.75 0.80 0.85 e 0.35 BSC 0.95 1.00 1.05HE E D C A HE 12 3 456 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. X Y TOP VIEW SIDE VIEW e b X0.08 Y BOTTOM VIEW 0.35 PITCH 1.20 0.20 DIMENSIONS: MILLIMETERS RECOMMENDED PACKAGE OUTLINE MOUNTING FOOTPRINT* L 0.19 REF L2 0.05 0.10 0.15 L6X L26X 0.35 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a numb er of patents, trademarks, reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 DTC124EP/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative