SMSNE555 SECOS | Alldatasheet

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High current driver capability (=200mA) Adjustable duty cycle timing form sec to hours turn off time less than 2 sec Precision timing Pulse generation Time delay generation or stable mode: frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The SMSNE555 is a highly stable timer IC that can be operated in astable mode and monostable mode. For monostable mode: time delay is controlled by one external and one capacitor. http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual Package Dimensions RoHS Compliant Product Block Diagram and Simplified Application & Pin Configuration 01-Jun-2006 Rev. A Page 1 of 5 M i n . M a x . M i n . M a x . A - 1 . 1 0 L 0 . 4 0 . 7 A 1 0 . 0 5 0 . 1 5 L 1 A 2 0 . 7 8 0 . 9 4 b 0 . 2 2 0 . 3 8 D 2 . 9 0 3 . 1 0 c 0 . 0 8 0 . 2 3 E 2 . 9 0 3 . 1 0 e H E 4 . 7 5 5 . 0 5 0 . 9 5 B S C . 0 . 6 5 B S C . R e f . R e f . m mm m

http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2006 Rev. A Page 2 of 5 Elektronische Bauelemente Single Timer Absolute Maximum Ratings (Ta = 25 °C) Parameter Sy mbol Value Units Supply Voltage VCC 16 V Differential Input Voltage IO 200 mA Input Voltage Tlead 300 °C Power Dissipation PD 440 mW Opearting, Storage Temperature TOPR, TSTG 0~70, -65~150 °C Electrical Characteristics (Ta = 25 °C, VCC = 5 ~ 15V) Parameter Symbol Test Conditions Min Typ Max Units Supply Voltage VCC 4.5 - 16 V VCC = 5V, RL = ∞ - 3 6 mA Supply Current (Note 1) ICC VCC = 15V, RL = ∞ - 10 15 mA Timing Error (monostable) Initial Accurary (Note 1) ACCUR RA = 1k ~ 100kΩ - 1.0 - % Drift with Temperature Δt/ΔT C = 0.1 μF - 50 - ppm/°C Drift with Supply Voltage Δt/ΔVCC - 0.1 - %/V Timing Error (astable) Initial Accurary (Note 1) ACCUR RA = 1k ~ 100kΩ - 2.25 - % Drift with Temperature Δt/ΔT C = 0.1 μF - 150 - ppm/°C Drift with Supply Voltage Δt/ΔVCC - 0.3 - %/V VCC = 15V 9.0 10.0 11.0 Control Voltage VC VCC = 5V 2.6 3.33 4.0 VCC = 15V 9.2 10.0 10.8 Threshold Voltage VTH VCC = 5V 3.1 3.33 3.55 V Threshold Current (Note 3) ITH - 0.1 0.25 μA VCC = 5V 1.1 1.67 2.2 Trigger Voltage Vtr VCC = 15V 4.5 5 5.6 V Trigger Current Itr Vtr = 0 - - 2.0 μA Reset Voltage Vrst 0.4 0.7 1.0 V Reset Current Irst - 0.1 0.4 μA VCC = 15V, Isink = 10mA - 0.06 0.25 VCC = 15V, Isink = 50mA - 0.3 0.75 Low Output Voltage VOL VCC = 5V, Isink = 5mA - 0.05 0.35 V VCC = 15V, Isink = 200mA - 12.5 - VCC = 15V, Isink = 100mA 12.75 13.3 15 High Output Voltage VOH VCC = 5V, Isink = 100mA 2.75 3.3 5 V Reset Time of Output tR - 100 - nSec Fall Time of Output tF - 100 - nSec Discharge leakage Current ILKG - 20 100 nA Note 1: Supply current when output is high typically 1 mA less at VCC = 5V Note 2: Tested at VCC = 5V and VCC = 15V. Note 3: This will determine the maximum value or RA+RB for 15V operation, the maximum total is R=20MΩ, and for 5V operation the maximum total is R=6.7MΩ. SMSNE555

01-Jun-2006 Rev. A Page 3of 5 http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual Elektronische Bauelemente Single Timer Characteristics Curve VCC = 15 V SMSNE555

http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2006 Rev. A Page 4 of 5 Elektronische Bauelemente Single Timer SMSNE555

01-Jun-2006 Rev. A Page 5of 5 http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual Elektronische Bauelemente Single Timer Application Circuit Application Notes The application circuit shows astable mode configuration. Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1 of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of GSCNE555, one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is connected to Pin 6. As soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop circuit is set output high. That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is 0.693RB*C1. In 3- VccVcc Vcc 2 =0.693 T1=0.693*(RA+RB)*C1 Thus the total period time T is given by T2=0.693*RB*C1 T=T1+T2=0.693(RA+2RB)*C1 Then the frequency of astable mode is given by f = = The duty cycle is given by D.C. = = FLIP-FLOP SPNE555 Vcc Vcc Vcc T (RA+2RB)*C1C1 1.44 1.44 T RB RA+2RB RA+2RB RB Vcc SMSNE555