SMS2916 ETC1 | Alldatasheet
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SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 1998 2028-02 4/24/98 Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc.
FEATURES
– Automatic VCC Supply Monitor - Complementary reset outputs for complex microcontroller systems - Integrated memory write lockout function - No external components required Watchdog Timer – Nominal 1.6 second Timeout Memory Internally Organized 2K X 8 – Two Wire Serial Interface (I2C™) High Reliability – Endurance: 1,000,000 erase/write cycles – Data retention: 100 years 8-Pin PDIP or SOIC Packages Precision Voltage Supervisory Circuit With Watchdog Timer and 16K I2C Memory SMS2916 OVERVIEW The SMS2916 is a power supervisory circuit that monitors VCC (either in a 5V system or 3V system) and will generate complementary reset outputs. The reset pins also act as I/Os and may be used for signal conditioning. The SMS2916 also has an on-board watchdog timer that has a nominal time out period of 1.6 seconds. The SMS2916 integrates a 16K-bit nonvolatile serial memory. It features the industry standard I2C serial interface allowing quick implementation in an end-users’ system. BLOCK DIAGRAM 3 and 5 Volt Systems Preliminary 5KHz Oscillator RESET PULSE GENERATOR RESET CONTROL 1.26V VCC RESET RESET VCC VTRIP SDA SCL GND MEMORY ARRAY EEPROM WATCHDOG TIMER WDI 2028 ILL2.1
FIGURE 1. TYPICAL APPLICATION USING DUAL RESET FUNCTION AND WATCHDOG TIMER
Description
low transition will clear the watchdog timer RESET Active Low RESET Input/Output NC No Connect, tie to ground or leave open GND Analog and Digital Ground SDA Serial Memory Input/ Output data line SCL Serial Memory clock input RESET Active High RESET Input/ Output VCC Supply Voltage 2028 PGM T1.1 RST SCL (P0.0) SDA (P0.1 Vcc RESET SCL SDA WDI RESET NC GND SCL SDA RESET VCC = 3.0 0r 5.0
8051 Type MCU
PB_RST ALE 2028 ILL3.1 WDI RESET NC GND VCC RESET SCL SDA 2028 ILL1.2
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. 2.7V to 4.5V 4.5V to 5.5V Symbol Parameter Conditions Min Max Min Max Units fSCL SCL Clock Frequency 100 400 KHz tLOW Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4.0 0.6 µs tBUF Bus Free Time Before New Transmission 4.7 1.3 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tSU:STO Stop Condition Setup Time 4.7 0.6 µs tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 3.5 0.2 0.9 µs tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 0.2 µs tR SCL and SDA Rise Time 1000 300 ns tF SCL and SDA Fall Time 300 300 ns tSU:DAT Data In Setup Time 250 100 ns tHD:DAT Data In Hold Time ns TI Noise Spike Width Noise Suppression Time Constant 100 100 ns @ SCL, SDA Inputs tWR Write Cycle Time ms AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) 2028 PGM T5.0 2028 PGM T4.0 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter Conditions Min Max Units SCL = CMOS Levels @ 100KHz VCC =5.5V mA ICC Supply Current (CMOS) SDA = Open All other inputs = GND or VCC VCC =3.3V mA ISB Standby Current (CMOS) SCL = SDA = VCC VCC =5.5V µA All other inputs = GND ILI Input Leakage VIN = 0 To VCC µA ILO Output Leakage VOUT = 0 To VCC µA VIL Input Low Voltage S0, S1, S2, SCL, SDA, RESET 0.3xVCC V VIH Input High Voltage S0, S1, S2, SCL, SDA, RESET 0.7xVCC V VOL Output Low Voltage IOL = 3mA SDA 0.4 V VCC =3.3V µA Temperature Min Max Commercial 0°C +70°C Industrial -40°C +85°C RECOMMENDED OPERATING CONDITIONS 2028 PGM T3.0
FIGURE 4. RESET OUTPUT TIMING
The RESET pins are I/Os; therefore, the SMS2916 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a reset conditioning circuit. WATCHDOG TIMER OPERATION The SMS2916 has a watchdog timer with a nominal timeout period of 1.6 seconds. Whenever the watchdog times out it will generate a reset output on both RESET and RESET. There are two methods of clearing the watchdog timer; the first is through the use of software, and the second is by strobing the WDI input pin. Software Method The watchdog timer will clear to t0 whenever the SMS2916 issues an ACKnowledge. Therefore, the host system will need to issue a start condition, followed by a valid address and command. It can be a normal com- mand as in the sequence of reading or writing to the memory, or it can be a dummy command issued solely for the purpose of resetting the watchdog timer. Refer to Figure 12 for detailed sequence of operations. The watchdog timer will be held in the cleared state during power-on while VCC is less than VTRIP. Once VCC ex- ceeds VTRIP the watchdog will continue to be held in a cleared state for the duration of tPURST. After tPURST, the timer will be released and begin counting. If either reset input is asserted the watchdog timer will be cleared and remain in the reset condition until either tPURST has expired or the reset input is released, which- ever is longer. If the watchdog times out and no action is taken by the host the SMS2916 will drive the reset outputs active for the duration of tPURST at which point it will release the outputs and clear the watchdog timer again and release it to begin a new count. Refer to Figure 13 for detailed sequence of operations. Hardware Method A high to low transition on WDI will clear the watchdog timer. If a transition is not detected within 1.6 seconds the watchdog will time out and force the reset outputs active. PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wire- ORed with any number of open-drain or open-collector outputs. RESET RESET RESET RESET RESET - RESET is an active low output. Whenever VCC is below VTRIP the SMS2916 will drive the RESET pin to ground. The RESET pin is an I/O and can be used as a reset input. Refer to Figure 1 as an example use of this pin as a push button switch debounce circuit. It should be noted this is an open drain output and an external pull-up resistor tied to VCC is needed for proper operation. RESET — RESET is an active high output. Whenever VCC is below VTRIP the SMS2916 will drive the RESET pin to the VCC rail. The RESET pin is an I/O and can be used as a reset input. It should be noted this is an open drain output and an external pull-down resistor tied to ground is needed for proper operation. WDI WDI WDI WDI WDI - The WDI input is used as a hardware method of clearing the watchdog timer. A high to low transition on this pin will clear the watchdog timer. If a transition is not detected within 1.6 seconds the watchdog will time out and force the reset outputs active. ENDURANCE AND DATA RETENTION The SMS2916 is designed for applications requiring 1,000,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 1,000,000 erase/write cycles. Reset Controller Description The SMS2916 provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. During power-up, the RESET outputs remain active until VCC reaches the VTRIP threshold and will continue driving the outputs for approximately 200ms after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when VCC falls below VTRIP.
FIGURE 10. RANDOM ADDRESS BYTE READ MODE WRITE) followed by the address of the word it is to read. SMS2916 to the desired address. the address, acknowledge and data transfer sequence.
ACKnowledge, and issues a STOP conditions. address, acknowledge and data transfer sequence. FIGURE 11. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
Frequently the supervisory circuit will be deployed on a PC board that provides a peripheral function to a system. Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. The system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. The I/O capability of the RESET pins can provide a solution. The system’s reset signal to the peripheral can be fed into the SMS2916 and it in turn can clean up the signal and provide a known entity to the peripheral’s circuits. The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than tPURST. The same reset output affect can be attained by using the active high reset input. If you happen to be using one of the more common supervisory circuits like a 1232, you might consider reducing your component count such as illustrated below. RESET Input RESET Output RESET Output 2028 ILL16.0 tPURST +5VDC PBRST TOL GND RST RST ST +5VDC ALE RST
8051 Family Part
2028 ILL18.1
.228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.
8 Places
.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00) .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
8 Pin PDIP (Type P) Package
.375 (9.525) PIN 1 INDICATOR .015 (.381) Min. .130 (3.302) .100 (2.54) TYP. .018 (.457) TYP. .060 ± .005 (1.524) ± .127 TYP. .130 (3.302) SEATING PLANE .070 (1.778) .0375 (0.952) .300 (7.620) 5°-7°TYP. (4 PLCS) .350 (8.89) .009 ± .002 (.229 ± .051) 0°-15° .250 (6.350) 8pn PDIP/P ILL.3
ORDERING INFORMATION
Blank = Bulk T = Tape & Reel Package P = 8 Lead PDIP S = 8 Lead 150mil SOIC Operating Temperature Range Blank = 0°C to +70°C I = -40°C to +85°C Operating Voltage Range A = 4.5V to 5.5V VTRIP Min. @ 4.25V B = 4.5V to 5.5V VTRIP Min. @ 4.50V P I -2.7 T 2028 ILL17.0
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