SMS256AF

SMSXXXAF NUMONYX | Alldatasheet

Document overview

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• PDF pages: 61

Technical content

Datasheet sections

• 1 Description
• 2 Memory array partitioning
• 3 Secure digital memory card interface
• 3.1 Secure digital memory card bus topology
• 3.2 SD bus protocol
• 3.3 SD Memory Card Functional Description
• 3.4 Operation Modes
• 3.4.1 Card Identification Mode
• 3.4.2 Data Transfer Mode
• 3.5 Commands
• 3.6 Responses
• 4 SD memory card hardware interface
• 4.1 SD memory card bus circuitry
• 4.2 Power-Up
• 4.3 Hot Insertion/Removal
• 4.4 Power Protection
• 4.5 Electrical Specifications
• 5 Card registers
• 5.1 OCR Register
• 5.2 CID Register
• 5.3 CSD Register
• 5.4 RCA Register
• 5.5 DSR Register (Optional)
• 5.6 SCR Register
• 6 Timings
• 6.1 Command and Response
• 6.1.1 Card Identification and Operating Conditions Timings
• 6.1.2 Card Relative Address Timings

Datasheet sections

• 7.6.2 Data Write Timings
• 8 Package mechanical data
• 9 Part numbering
• 10 Revision history

Features

■ SD Memory Card Specification Version 1.01- compliant ■ Up to 1 Gbyte of Formatted Data Storage ■ Bus Mode – SD Protocol (1 to 4 Data Lines) – SPI Protocol ■ Operating Voltage Range: – Basic Communication (CMD0, CMD15, CMD55 and ACMD41): 2.0V to 3.6V – O t h e r C o m m a n d s a n d M e m o r y A c c e s s : 2.7V to 3.6V ■ Variable Clock Rate: 0 to 25 MHz ■ Read Access (using 4 Data Lines) – Sustained Multiple Block: 6.3 Mb/s ■ Write Access (using 4 Data Lines) – Sustained Multiple Block: 3.0 Mb/s ■ Maximum Data Rate with up to 10 Cards ■ Aimed at Portable and Stationary Applications ■ Communication Channel Protocol Attributes: – Six-wire communication channel (clock, command, 4 data lines) – Error-proof data transfer – Single or Multiple block oriented data transfer ■ Memory Field Error Correction ■ Safe Card Removal during Read ■ Write Protect Feature using Mechanical Switch ■ Built-in Write Protection Features (Permanent and Temporary) ■ SD, MiniSD and MicroSD Packages – ECOPACK ® compliant – Halogen free – Antimony free SD miniSD SD Secure Digital MiniSD MicroSD Table 1. Device summary

SMSxxxAF, SMSxxxFF, SMSxxxBF Contents

1 Description

mobile phones, digital cameras, digital recorders, PDAs, organizers, electronic toys, etc. power consumption device that features high data throughput at the memory card interface. uses mutual authentication and a “cipher algorithm” that protects the card from illegal use. Unsecured access to the user's personal content is also available. MicroSD Memory Card has an 8-pin interface, and can also be fitted with a 9-pin adapter. The SD, MiniSD and MicroSD packages are also Halogen free and Antimony free.

• Secure Digital Memory Card Specifications: Part 1 Physical Layer Specification, Version 1.01
• MiniSd Memory Card Specifications: Addendum to SD Memory Card Specifications Part 1 Physical layer Specification, Version 1.02
• MicroSD Memory Card Specifications: Addendum to SD Memory Card Specifications Part 1, Physical Layer Specification, Version 1.00

Table 2. System performance

1. 43X, 20X, 12X and 5X Speed grade mark ings where 1X = 150 KBytes/s.

Table 3. Power consumption (1) Table 4. Environmental specifications (1)

1. NA = Not Applicable; RH = Relative Humidity; ESD = ElectroStatic Discharge

Table 5. Physical dimensions

Table 6. System reliability and maintenance

1. MTBF = Mean Time Between Failures.

2 Memory array partitioning

is divided into several structures as described below and summarized in Table 17. information about allowed block sizes and programmability is stored in the CSD Register. information about the sector size (in blocks) is stored in the CSD register. Protect Group size is stored in the CSD Register. Table 7. Memory array structures

64 MByte

128 MByte

256 MByte

512 MByte

1 GByte

Figure 1. Write Protection hierarchy

3 Secure digital memory card interface

card when used with an adapter. are still to be announced. Figure 3: MicroSD pin assignment shows the MicroSD pinout. Figure 2. Full size Secure Di gital Memory Card form factor Table 8. Full-size SD Memory Card pin assignment

1. S: power supply; I: input; O: output using push- pull drivers; PP: I/O using push-pull drivers.
2. The extended DAT lines (DAT1-DAT3) are input on power-up. T hey start to operate as DAT lines after SET_BUS_WIDTH
3. After power-up this line is input with 50kW pull-up (can be used for card detection or SPI mode selection). The pull-up

should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command.

2 CMD PP Command/Response DI I Data In

5 CLK I Clock SCLK I Clock

7 DAT0 I/O/PP Data Line [Bit 0] DO O/PP Data Out

Figure 3. MicroSD pin assignment Table 9. MicroSD Contact Pad Assignment

1. S: power supply; I: input; O: output using push- pull drivers; PP: I/O using push-pull drivers.

1 DAT2 I/O/PP Data Line [Bit 2] RSV Reserved

2 CD/DA

1. The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after

they are not used. It is defined so, in order to keep compatibility to MultiMediaCards.

1. After power up this line is input with 50KOhm pull-up (can be used for card detection or SPI mode

SET_CLR_CARD_DETECT (ACMD42) command.

3 CMD PP Command/Response DI I Data In

4 V DD S Supply voltage V DD S Supply voltage

8 DAT1 RSV Reserved

SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface

3.1 Secure digital me mory card bus topology

The Secure Digital Memory Card system defines two alternative communications protocols: SD and SPI that correspond to two operating modes. Either mode can be selected in the application, mode selection is transparent to the host. The host automatically detects the operating mode of the card by issuing the Reset command (refer to Section 7.2.1: Mode Selection) and will expect all further communications to use the same mode. Therefore, applications that use only one communication mode do not have to be aware of the other. The SD bus includes the following signals:

• CLK: Host to card clock signal
• CMD: Bi-directional Command/Response signal
• DAT0 - DAT3: 4 Bi-directional data signals.
• VDD, VSS1, VSS2: Power and ground signals. The SD Memory Card bus has a synchronous star topology (refer to Figure 4: Secure Digital Memory Card system bus topology) with a single master (the application) and multiple slaves (the cards). The Clock, power and ground signals are common to all cards. The command (CMD) and data (DAT0 - DAT3) signals are dedicated to the cards, they provide continuous point-to-point connection to all the cards. During the initialization process, commands are sent to each card individually, allowing the application to detect the cards and assign logical addresses to the physical slots. Data is always sent (received) to (from) each card individually. However, in order to simplify the handling of the card stack, after the initialization process, all commands may be sent concurrently to all cards. Addressing information is provided in the command packet. The SD bus allows dynamic configuration of the number of data lines. After power-up the SD Memory Card defaults to using only DAT0 for data transfer. After initialization the host can change the bus width (number of active data lines). This feature is an easy trade off between hardware cost and system performance.

Figure 4. Secure Digital Memory Card system bus topology

1. DAT1 and DAT2 not connected.

3.2 SD bus protocol

initiated by a start bit and terminated by a stop bit.

• Command: a command is a token which starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). Commands are transferred serially on the CMD line. See Figure 5: "No Response" and "No Data" operations. The Command token format is shown in Figure 8
• Response: a response is a token which is sent from an addressed card, or (simultaneously) from all connected cards, to the host, as an answer to a previously received command. Responses are transferred serially on the CMD line. A response is illustrated in Figure 5: "No Response" and "No Data" operations. The Response token format is shown in Figure 9
• Data: data can be transferred from the card to the host or from the host to the card. Data is transferred via the data lines. See Figure 6: (Multiple) Block Read operation for an illustration. The Data Packet format is shown in Figure 10 Card addressing is implemented using a session address assigned to the card during the initialization phase (See SD Memory Card Specification, Chapter 4). The basic transaction on the SD bus is the command/response transaction. In this type of bus transactions, the information is directly transferred within the command or response structure. In addition, some operations have a data token. Data transfers to/from the SD Memory Card are done in blocks. Data blocks are always followed by CRC bits. Single and Multiple Block operations are supported. Note that the Multiple Block operation mode improves the speed of write operations. A Multiple Block transmission is terminated by issuing a STOP_TRANSMISSION command on the CMD line (See Figure 6 and Figure 7). CLK VDD VSS DAT0-DAT3(A) CMD(A) CLK VDD VSS DAT0-DAT3 CMD SD Memory Card (A) CLK VDD VSS DAT0-DAT3 CMD SD Memory Card (B) DAT0-DAT3(B) CMD(B) CLK VDD VSS DAT0, CS, CMD(1)DAT0-DAT3(C) CMD(C) MultiMediaCard (C) ai10029 HOST

Figure 10. Data Packet format

3.3 SD Memory Card Functional Description

All communications between the host and the cards are controlled by the host (master).

• Broadcast commands which are intended for all cards. Some of these commands require a response.
• Addressed (point-to-point) commands that are sent to the addressed card and are followed by a response from the card.

3.4 Operation Modes

mode and the Data Transfer mode, respectively.

0 CONTENT CRC 1

0 CONTENT CRC 1DAT0

Table 10. Card States vs. Operation Modes

3.4.1 Card Identification Mode

finished searching for new cards on the bus. own CMD line. In this mode, all data communications use the command line (CMD) only. Memory Card has push-pull CMD line output drives. conditions (ACMD41 preceded by APP_CMD - CMD55 with RCA=0000h). are connected separately so each MultiMediaCard has to be initialized individually. Table 10. Card States vs. Operation Modes (continued)

Figure 11. SD Memory Card State Diagram (Card Identification Mode)

3.4.2 Data Transfer Mode

The host enters the Data Transfer mode after identifying all the cards on the bus. fOD because some cards may have operating frequency limitations.

Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF When CMD7 is issued with the reserved relative card address "0000h", all cards revert to the Standby State. This function may be used before identifying new cards, to avoid resetting already registered cards. When in Standby state the cards that already have an RCA do not respond to identification commands (CMD41, CMD2, CMD3). Note that a card is deselected when it receives a CMD7 with an RCA that does not match. Card deselection is automatic if another card in a system is selected and the cards share the same CMD lines. So, in an SD Memory Card system, the host may either have a common CMD line for all SD Memory Cards (in which case card deselection is automatic just like in a MultiMediaCard system) or the host may have separate CMD lines, in which case it must be aware of the necessity of deselecting cards. All data communications in the Data Transfer Mode are point-to point between the host and the selected card (using addressed commands). All addressed commands are acknowledged by a response on the CMD line. The relationships between the various states in the Data Transfer mode are summarized below (see Figure 12):

• All Data Read commands (CMD17, CMD18, CMD30, CMD56, ACMD51) can be aborted at any time using the Stop command (CMD12). The data transfer will terminate and the card will return to the Transfer State.
• All Data Write commands (CMD24,CMD25, CMD26, CMD27, CMD42, CMD56) can be aborted at any time using the Stop command (CMD12). The write commands must be stopped prior to deselecting the card using CMD7.
• As soon as the data transfer has completed, the card switches from the Data Write state to either the Programming state (if the transfer was successful) or the Transfer state (if the transfer failed).
• If a Block Write operation is stopped and the block length and CRC of the last block are valid, the data will be programmed.
• The card can provide buffering during Block Write. This means that the data to be programmed to the next block can be sent to the card while the previous block is being programmed. If all write buffers are full, the DAT0 line will remain Low (BUSY) as long as the card is in the Programming state (see Figure 12).
• There is no buffering option for Write CSD, Write CID, Write Protection and erase. This means that while the card is busy with any one of these commands, no other Data Transfer command will be accepted. The DAT0 line will remain Low as long as the card is busy and in the Programming state.
• Parameter Set commands (CMD16, CMD32, CMD33) are not allowed while the card is programming.
• Read commands are not allowed while the card is programming.
• Switching another card from the Standby to the Transfer state (using CMD7) will not terminate erase and programming operations. The card will switch to the Disconnect state and release the DAT line.
• A card in the Disconnect state can be reselected using CMD7. The card will then revert to the Programming state and reactivate the busy signaling.
• Resetting a card (using CMD0 or CMD15) will terminate any pending or ongoing programming operation. This may result in the loss of card contents. It is up to the host to prevent possible data loss.

Figure 12. SD Memory Card State Diagram (Data Transfer Mode)

3.5 Commands

1. Broadcast commands (bc), no response: The broadcast feature is available only if

interconnected then each individual card will accept the command in turn.

1. Broadcast commands with response (bcr): Since there is no Open Drain mode in

responses from all cards are sent simultaneously.

1. addressed (point-to-point) commands (ac): There is no data transfer on DAT.
2. addressed (point-to-point) data transfer commands (adtc): There is a data transfer

All commands have a fixed code length of 48 bits for a transmission time of 2.4µs at 20MHz. All commands and responses are sent over the CMD line of the SD Memory Card. arguments are specified in the SD Memory Card Specification.

Table 11. SD Card Command Format

3.6 Responses

direction of transmission (from card = '0'). are terminated by the end bit (always '1').

1. R1 (normal response command): the code length is 48 bits. Bits 45 to 40 indicate the

and 63). The status of the card is coded in 32 bits (see Table 12). after data block transmission.

1. R1b is identical to R1 with an optional busy signal transmitted on the data line. The

in prior to receiving the command. The Host has to check for busy in the response.

1. R2 (CID, CSD Register): the code length is 136 bits. The contents of the CID Register

bit of the response (see Table 13).

1. R3 (OCR register): the code length is 48 bits. The contents of the OCR register are

sent as a response to ACMD41 (see Section Table 14. on page 25).

1. R6 (Published RCA response): the code length is 48 bits. Bits 45 to 40 indicate the

field are used for the Published RCA number.

Table 12. Response R1 Table 13. Response R2 Table 14. Response R3 Table 15. Response R6

4 SD memory card hardware interface

4.1 SD memory card bus circuitry

Figure 13 shows the internal bus circuitry required for the Full Size SD Memory Card. disconnected and another resistor should be connected to Ground. against bus floating when no card is inserted or when all card drivers are high impedance. WP is used to protect the Write Protect/Card Detection switch. Figure 13. Full Size SD Memory Card Circuitry

4.2 Power-Up

ACMD41 is received (ACMD command type should always be preceded by CMD55). cleared (‘0’). The power-up sequence of an individual card should not exceed 1 second. After power-up the host starts the clock and sends the initializing sequence on the CMD line. Figure 14. Power-Up Diagram

1. Initialization delay = 1ms (max) + 74 clock cycles + supply ramp-up time.
2. Timeout value for initia lization process is 1s.

41 CMD2

responds with the busy bit set.

SD memory card hardware interface SMSxxxAF, SMSxxxFF, SMSxxxBF

4.3 Hot Insertion/Removal

To guarantee a reliable initialization during hot insertion, some measures must be taken on by the host. For example, a special hot-insertion capable card connector may be used to guarantee the sequence of the card pin connection. The card contacts are connected in three steps: 1. Ground V SS (pin 3) and supply voltage VDD (pin 4). 2. CLK, CMD, DAT0, DAT1, DAT2 and V SS (pin 6). 3. CD / DAT3 (pin 1). Pins 3 and 4 should be connected first on insertion, and be disconnected last on extraction. Another method is a switch which could ensure that the power is switched on only after all card pads are connected. Inserting a Card in or removing it from the SD Memory Card bus with the power on will not damage the card. Data transfer operations are protected by CRC codes, therefore any bit changes induced by card insertion and removal can be detected by the SD Memory Card bus master.

• The inserted card must be properly reset even when the clock frequency is fPP.
• Each card should be fitted with a protection from the power supply to prevent damage to the card (and host).
• Data transfer failures induced by removal/insertion are detected by the bus master. They must be corrected by the application, which may repeat the issued command.

4.4 Power Protection

Cards have to be inserted in or removed from the bus without being damaged. If one of the supply pins (V DD or VSS) is not connected properly, then the current is drawn through a data line. All the card outputs should also be able to withstand shortcuts to either supply. If the hot insertion feature is implemented in the host, then the host has to be able to withstand an instant shortcut between V DD and VSS without being damaged.

4.5 Electrical Specifications

Table 16 defines the Bus Operating Conditions for the SD Memory Card. The total capacitance CL of the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS and the capacitances CCARD of all the cards connected to this line. CL = CHOST + CBUS + N × CCARD, where:

• N is the number of cards connected to the line.
• CHOST + CBUS must be lower than 30pF for up to 10 cards and lower than 40pF for up to 30 cards.
• The values in Table 16 should not be exceeded. As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. See Figure 15: Bus Signal levels and Table 17: Bus Signal Condition - I/O Signal Voltages.

Figure 15. Bus Signal levels Table 16. Bus Operating Conditions

21 Cards

Table 17. Bus Signal Condition - I/O Signal Voltages

Figure 16. Data Input/Output Timings Referenced to Clock Table 18. Bus Timings (1) MultiMediaCard compatibility).

1. Clock CLK: All values are referred to min (V IL) and max (VIH).

5 Card registers

registers are configuration registers that store the actual configuration parameters. Table 19. SD Memory Card Registers

5.1 OCR Register

match the definition given in Figure 14: Power-Up Diagram. identification number. It is mandatory.

1. The RCA Register is not used (available) in SPI mode.

initialization. It is mandatory. operation conditions. It is mandatory. OCR 32 Operation Condition Register. It is mandatory. Table 20. OCR Register Definition

5.2 CID Register

identification number. The structure of the CID register is defined in Figure 16. Table 20. OCR Register Definition (continued) Table 21. CID Fields

5.3 CSD Register

The Card Specific Data Register provides information on how to access the card contents. Table 22. CSD Fields Compatible with CSD Structure V1 / MM Card Specification V2.11

5.4 RCA Register

5.5 DSR Register (Optional)

The 16-bit Driver Stage Register is not used in Numonyx Cards.

5.6 SCR Register

1. R = readable, W(1) = can be written onc e, W = can be written several times.

Table 23. SCR Fields SD Memory Card - Specification.

6 Timings

The symbols listed in Table 24 are used in all timing diagrams. CMD and RDAT. P-bits, which are actively driven High, are less sensitive to noise.

6.1 Command and Response

6.1.1 Card Identification and Operating Conditions Timings

Table 24. Timing Diagram Symbols

Figure 17. Identification Sequence

6.1.2 Card Relati ve Address Timings

The SD Memory Card timings for CMD3 (SEND_RELATIVE_ADDR) are given in Figure 18. The minimum delay between the host command and the card response is NCR clock cycles. Figure 18. SEND_RELATIVE_ADDRESS Command

6.1.3 Data Transfer Mode

Figure 19. Response (Data Transfer Mode)

6.1.4 Last Card Response, Ne xt Host Command Timings

applies to any host command. Figure 20. Response End To Next CMD Start (Data Transfer Mode)

6.1.5 Last Host Command, Next Host Command Timings

Figure 21. Command Sequence (All Modes)

6.2 Data Read

6.2.1 Single Block Read

check for transmission errors. Figure 22. Single Block Read Command

6.2.2 Multiple Block Read

end bit of the STOP_TRANSMISSION command.

Figure 23. Multiple Block Read Command Figure 24. STOP_TRANSMISSION Command (CMD12, Data Transfer Mode)

6.3 Data Write

6.3.1 Single Block Write

WR clock cycles after the card response is received. starts programming the data. start bit on the bus and the three CRC status bits will read ('111'). Note that the CRC response is always output two clock cycles after the data. information by issuing a CMD13 (SEND_STATUS) to the card.

Figure 25. Block Write Command

6.3.2 Multiple Block Write

result as a CRC status token on the DAT0 line. starts programming the data. start bit on the bus and the three CRC status bits will read ('111'). Figure 26 describes a Multiple Block data transmission with and without a card busy signal. Figure 26. Multiple Block Write Command

6.4 STOP_TRANSMISSION Command

The STOP_TRANSMISSION command works in the same way as in the read mode.

Figure 30. STOP_TRANSMISSION Received After Last Data Block with Card Idle

6.4.1 Erase, Set and Clear Write Protect Timings

erased. The Erase command (CMD38), once issued, will erase all the selected write blocks. Similarly, Set and Clear Write Protect commands start a programming operation as well. STOP_TRANSMISSION Command in Figure 30.

6.4.2 Re-selecting a busy card

for STOP_TRANSMISSION command illustrated in Figure 30.

6.5 Timing Values

Figure 25 gives all timings. Table 25. Timing Values

Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF

7 Serial peripheral interface (SPI) mode

The SPI mode is a secondary communication protocol, which is available in Flash memory- based SD Memory Cards. The SD Memory Card SPI implementation uses a subset of the SD Memory Card protocol and command set. The advantage of the SPI mode is the capability of using off-the-shelf host, hence reducing the design-in effort to a minimum. The disadvantage is the loss of performance (e.g., Single data line and hardware CS signal per card). The SPI mode is selected during the first Reset command after power-up (CMD0) and cannot be changed once the part is powered on.

7.1 SPI bus topology

The SPI compatible communication mode of the SD Memory Card is designed to communicate with an SPI channel, commonly found in various microcontrollers on the market. The SPI standard defines the physical link only, and not the complete data transfer protocol. The SD Memory Card SPI and SD modes use the same command set. Like all SPI devices, the SD Memory Card SPI channel uses the four following signals:

• CS: Host to card Chip Select signal.
• CLK: Host to card clock signal
• DataIn: Host to card data signal.
• DataOut: Card to host data signal. All data tokens are multiples of Bytes (8 bits) and always Byte-aligned to the CS signal. The card identification and addressing methods are replaced by a hardware Chip Select (CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by asserting (active Low) the CS signal (see Figure 31: SD Memory Card System SPI Mode Bus Topology).The CS signal must be continuously active for the duration of the SPI transaction. The only exception occurs during card programming, when the host can de- assert the CS signal without affecting the programming process. The SPI interface uses 7 out of the 9 SD signals (DAT1 and DAT2 are not used, DAT3 is the CS signal) of the SD bus.

Figure 31. SD Memory Card System SPI Mode Bus Topology

7.2 SPI Bus Protocol

multiple of 8 clock cycles).

• the selected card always responds to the command.
• two additional (8 & 16 bit) response structures are used
• when the card encounters a data retrieval problem, it sends an error response in place of the expected data block (in the SD mode the card does not respond but implements a timeout). In addition to returning a response for every command received, the card returns a special data response token for every data block received during write operations.

7.2.1 Mode Selection

is asserted (Low) when the Reset command (CMD0) is received. The only way to return to the SD mode is to start a new power-down/power-up sequence. In SPI mode, the SD Card protocol state machine does not apply.

7.2.2 Bus Transfer Protection

have the hardware and firmware necessary to implement CRC functions. can be turned on and off by the host through the CRC_ON_OFF command (CMD59).

7.2.3 Data Read

block, replaced by the response to a STOP_TRANSMISSION command. in a single physical card sector. Figure 32. Read Operation Mechanism Figure 33. Multiple Block Read Operation

Figure 34. Read Data Error

7.2.4 Data Write

Single and Multiple Block Write operations are supported in SPI mode. CRC, block length and start address. Figure 35. Write Operation

7.2.5 Erase & Write Protect Management

and holds the DataOut line Low. Figure 36. Erase & Write Protect Operations

Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF

7.2.6 Read CID/ CSD Registers

In SPI mode the CID and CSD Registers use a Block Read operation. When a Read command is issued, the card returns a response message followed by a 16 Byte data block with a 16-bit CRC. As T AAC, the Data Read Access Time, is stored in the CSD Register, it cannot be used as the read latency of the CSD Register. NCR (see Table 25: Timing Values) is used instead.

7.2.7 Reset Sequence

The SD Memory Card requires a defined reset sequence. After power-on reset or CMD0 (software reset) the card enters an idle state. When idle, the only host commands the card will accept are CMD1 (SEND_OP_COND), ACMD41 (SD_SEND_OP_COND) and CMD58 (READ_OCR). In SPI mode CMD1 and ACMD41 have the same function. The host must poll the card (by repeatedly sending CMD1 or ACMD41) until the 'in-idle-state' bit in the card response switches to Low, thus indicating that the card has completed its initialization process and is ready for the next command. In the SPI mode, as opposed to the SD mode, CMD1 (and ACMD41) has no operands and does not return the contents of the OCR register. Instead, the host may use CMD58 (available in SPI mode only) to read the OCR register. Also it is up to the host to pay attention not to gain access to cards that do not support its voltage range. The use of CMD58 is not restricted to the initializing phase, it can be issued at any time. 7.2.8 Memory Array Partitioning. It is the same as in the SD mode. 7.2.9 Card Lock/Unlock Commands. In the SPI mode, the Lock and Unlock commands are the same as in the SD mode. 7.2.10 Application Specific Commands. The only difference between the SD and SPI modes is the APP_CMD status bit, which is not available in the SPI mode.

7.3 SPI Mode Commands

All the SPI commands are 6 Bytes long. The command always starts with the MSB of the string, which corresponds to the command code. See Table 26 for details of the command format. Like in the SD mode, the commands in the SPI mode are divided into classes. However, the classes supported by the two modes are different. See Table 27 For details. The commands supported in the SPI mode are described in detail in Table 27 If no argument is required in the command, the value of the field should be set to '0'. Reserved commands are reserved in both the MultiMediaCard and SPI modes. The contents of the

Table 26. Command Format Table 27. Command Classes in SPI Mode

7.4 Responses

7.4.1 R1 Format

indicate errors, an error being indicated by a '1'.

7.4.2 R1b Format

busy. A non-zero value indicates that the card is ready for the next command.

7.4.3 R2 Format

7.4.4 R3 Format

response. The other four Bytes contain the OCR register. For more details about responses, please refer to the SD Memory Card Specification v.1.01.

7.5 Clearing Status Bits

token (the same bits may exist in several response types - e.g. Card ECC failed). state. For more details, please refer to the SD Memory Card Specification.

7.6 SPI Bus Timings

response format). For timings, refer to Table 25. Table 28. SPI Timing Symbols

Figure 39. Card Response to Host Command

7.6.1 Data Read Timings

CR). See Figure 40., for details. For timings, refer to Table 25. Figure 40. Single Block Read Operation Figure 41. STOP_TRANSMISSION between Blocks During Multiple Block Read

6 Byte Command

Figure 42. STOP_TRANSMISSION within a Block During Multiple Block Read Figure 43. CSD Register Read Operation

7.6.2 Data Write Timings

High). To check whether the card is still busy, the host must reselect it by driving CS Low. Figure 44 for details). The timing of Stop Tran prefixes is the same as that of data blocks. Figure 44. Single Block Write Operation

Figure 45. Multiple Block Write Operation

8 Package mechanical data

Figure 46. Full-Size Secure Digital Memory Card Dimensions Table 30. Full-Size Secure Digital Memory Card Mechanical Data

Figure 47. mini Secure Digital Card Dimensions Table 31. MiniSD package mechanical data

Table 31. MiniSD package mechanical data (continued)

Figure 48. MicroSD card mechanical dimensions Table 32. MicroSD package mechanical data

Table 32. MicroSD package mechanical data (continued)

9 Part numbering

Table 33. Ordering Information Scheme Note: Other digits may be added to the ordering code for preprogrammed parts or other options. Devices are shipped from the factory with the memory content bits erased to ’1’. A = Version depending on device mix.

the bus side corresponding to Figure 49. Figure 49. Power supply decoupling The host controller includes a central buffer capacitor for VDD. Its value is 1 µF/slot.

Table 34. Document Revision History Information on power dissipation removed from Features section. VDD updated in Note 1 below Table 3: Power consumption. Diagram (Card Identification Mode) updated. 10-Dec-2007 3 Applied Numonyx branding.