SMP08 AD | Alldatasheet

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REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Octal Sample-and-Hold with Multiplexed Input SMP08* FUNCTIONAL BLOCK DIAGRAM SW SW SW SW SW SW SW SW

1 OF 8 DECODER

(INTERNAL) SMP08 INPUT (LSB) A B (MSB) C INH

FEATURES

TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatible With CD4051 Pinout Low Cost

APPLICATIONS

Multiple Path Timing Deskew for ATE Memory Programmers Mass Flow/Process Control Systems Multichannel Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control GENERAL DESCRIPTION The SMP08 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP08 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to ± 1/2 LSB in less than 7 microseconds. The SMP08’s output swing includes the negative supply in both single and dual sup- ply operation. The SMP08 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP08 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters. *Protected by U.S. Patent No. 4,739,281. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 The SMP08 is also ideally suited for a wide variety of sample- and-hold applications including amplifier offset or VCA gain adjustments. One or more SMP08s can be used with single or multiple DACs to provide multiple set points within a system. The SMP08 offers significant cost and size reduction over dis- crete designs. It is available in a 16-pin plastic DIP, or surface- mount SOIC package.

–2– SMP08–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units Linearity Error –3 V ≤ VIN ≤ +3 V 0.01 % Buffer Offset Voltage V OS TA = +25°C, VIN = 0 V 2.5 10 mV –40°C ≤ TA ≤ +85°C, VIN = 0 V 3.5 20 mV Hold Step V HS VIN = 0 V, TA = +25°C to +85°C 2.5 4 mV VIN = 0 V, TA = –40°C5 m V Droop Rate ΔVCH/ΔtT A = +25°C, VIN = 0 V 2 20 mV/s Output Source Current I SOURCE VIN = 0 V1 1.2 mA Output Sink Current I SINK VIN = 0 V1 0.5 mA Output Voltage Range R L = 20 kΩ –3.0 +3.0 V LOGIC CHARACTERISTICS Logic Input High Voltage V INH 2.4 V Logic Input Low Voltage V INL 0.8 V Logic Input Current I IN VIN = 2.4 V 0.5 1 µA DYNAMIC PERFORMANCE 2 Acquisition Time 3 tAQ TA = +25°C, –3 V to +3 V to 0.1% 3.6 7 µs Hold Mode Settling Time t H To ± 1 mV of Final Value 1 µs Channel Select Time t CH 90 ns Channel Deselect Time t DCS 45 ns Inhibit Recovery Time t IR 90 ns Slew Rate SR 3 V/ µs Capacitive Load Stability <30% Overshoot 500 pF Analog Crosstalk –3 V to +3 V Step –72 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR V S = ± 5 V to ± 6 V 60 75 dB Supply Current I DD TA = +25°C 4 7.5 mA Parameter Symbol Conditions Min Typ Max Units Linearity Error 60 mV ≤ VIN ≤ 10 V 0.01 % Buffer Offset Voltage V OS TA = +25°C, VIN = 6 V 2.5 10 mV –40°C ≤ TA ≤ +85°C, VIN = 6 V 3.5 20 mV Hold Step V HS VIN = 6 V, TA = +25°C to +85°C 2.5 4 mV VIN = 6 V, TA = –40°C5 m V Droop Rate ΔVCH/ΔtT A = +25°C, VIN = 6 V 2 20 mV/s Output Source Current I SOURCE VIN = 6 V1 1.2 mA Output Sink Current I SINK VIN = 6 V1 0.5 mA Output Voltage Range R L = 20 kΩ 0.06 10.0 V RL = 10 kΩ 0.06 9.5 V LOGIC CHARACTERISTICS Logic Input High Voltage V INH 2.4 V Logic Input Low Voltage V INL 0.8 V Logic Input Current I IN VIN = 2.4 V 0.5 1 µA DYNAMIC PERFORMANCE 2 Acquisition Time 3 tAQ TA = +25°C, 0 V to 10 V to 0.1% 3.5 4.25 µs Hold Mode Settling Time t H To ± 1 mV of Final Value 1 µs Channel Select Time t CH 90 ns Channel Deselect Time t DCS 45 ns Inhibit Recovery Time t IR 90 ns Slew Rate SR R L = 20 kΩ 4 34 V / µs Capacitive Load Stability <30% Overshoot 500 pF Analog Crosstalk 0 V to 10 V Step –72 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR 10.8 V ≤ VDD ≤ 13.2 V 60 75 dB Supply Current I DD TA = +25°C 6.0 8.0 mA NOTES 1Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels. 2All input control signals are specified with t r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 3This parameter is guaranteed without test. 4Slew rate is measured in the sample mode with 0 V to 10 V step from 20% to 80%. Specifications subject to change without notice. (@ VDD = +5 V, VSS = –5 V, DGND = 0 V, R L = No Load, TA = –40 8C to +858C for SMP08F, unless otherwise noted) (@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –40 8C to +858C for SMP08F, unless otherwise noted) REV. D

–3–REV. D ABSOLUTE MAXIMUM RATINGS (Not Short-Circuit Protected) Operating Temperature Range Package Type uJA* uJC Units 16-Pin Plastic DIP (P) 76 33 °C/W 16-Pin SOIC (S) 92 27 °C/W *θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for plastic DIP package; θJA is specified for device soldered to printed circuit board for SO package. ORDERING GUIDE Temperature Package Package Model Range Description Option SMP08FP –40 °C to +85°C Plastic DIP N-16 SMP08FS –40 °C to +85°C SO-16 R-16A PIN CONNECTIONS TOP VIEW (Not to Scale) SMP08 CH 4OUT CH 0OUT CH 1OUT CH 2OUT VDD CH 6OUT INPUT CH 7OUT B CONTROL A CONTROL CH 3OUTCH 5OUT INH VSS DGND C CONTROL WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP08 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 10. Offset Voltage vs. Figure 11. Supply Current vs. V DD

10 REJECTION RATIO – dB

Figure 12. Sample Mode Power Figure 13. Gain, Phase Shift vs. Figure 15. Maximum Output Voltage Figure 14. Output Impedance vs. Figure 16. Hold Mode Power Supply

Figure 17. Burn-In Circuit The buffers are designed to drive loads connected to ground. tained by restricting the output range to 2 V from either supply. taken to avoid shorting any output to the supplies or ground. SMP08’s acquisition time characteristics are to be maintained. be used with a value ranging from 200 k Ω to 1 MΩ . CMOS compatibility is maintained over the full supply range. See Figure 18 for channel decode address information. noise will appear at the outputs. noise from entering the analog circuitry. but standard precautions should still be taken.

–8– REV. D C2192–2–10/96PRINTED IN U.S.A. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-Lead SOIC (Narrow Body) (SO-16) 16 9 0.3937 (10.00) 0.3859 (9.80) 0.2550 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (5.80) PIN 1 SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45°