SMP04ES

SMP04 AD | Alldatasheet

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REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a CMOS Quad Sample-and-Hold Amplifier FUNCTIONAL BLOCK DIAGRAM VSS VOUT1 VOUT2 VOUT3 VOUT4 VSS DGND VIN1 S/H1 VIN2 VIN3 VIN4 S/H2 S/H3 S/H4 VDD VSS VSS VSS SMP04

FEATURES

Four Independent Sample-and-Holds Internal Hold Capacitors High Accuracy: 12 Bit Very Low Droop Rate: 2 mV/s typ Output Buffers Stable for C L £ 500 pF TTL/CMOS Compatible Logic Inputs Single or Dual Supply Applications Monolithic Low Power CMOS Design

APPLICATIONS

Multichannel Data Acquisition Systems Automatic Test Equipment Medical and Analytical Instrumentation Event Analysis DAC Deglitching The SMP04 offers significant cost and size reduction over equivalent module or discrete designs. It is available in a 16-lead hermetic or plastic DIP and surface mount SOIC packages. It is specified over the extended industrial tem- perature range of –40 °C to +85 °C. GENERAL DESCRIPTION The SMP04 is a monolithic quad sample-and-hold; it has four internal precision buffer amplifiers and internal hold capacitors. It is manufactured in ADI’s advanced oxide isolated CMOS technology to obtain the high accuracy, low droop rate and fast acquisition time required by data acquisition and signal process- ing systems. The device can acquire an 8-bit input signal to – 1/2 LSB in less than four microseconds. The SMP04 can operate from single or dual power supplies with TTL/CMOS logic compatibility. Its output swing includes the negative supply. The SMP04 is ideally suited for a wide variety of sample-and- hold applications, including amplifier offset or VCA gain adjust- ments. One or more can be used with single or multiple DACs to provide multiple setpoints within a system. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 SMP04* *Protected by U.S. Patent No. 4,739,281.

SMP04–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units Linearity Error 0.01 % Buffer Offset Voltage V OS VIN = 6 V –10 – 2.5 +10 mV Hold Step V HS VIN = 6 V, TA = +25°C to +85°C2 . 5 4 m V VIN = 6 V, TA = –40°C5 m V Droop Rate D V/DtV IN = 6 V, TA = +25°C 2 25 mV/s Output Source Current 1 ISOURCE VIN = 6 V 1.2 mA Output Sink Current 1 ISINK VIN = 6 V 0.5 mA Output Voltage Range OVR R L = 20 kW 0.06 10.0 V RL = 10 kW 0.06 9.5 V LOGIC CHARACTERISTICS Logic Input High Voltage V INH 2.4 V Logic Input Low Voltage V INL 0.8 V Logic Input Current I IN 0.5 1 mA DYNAMIC PERFORMANCE 2 Acquisition Time 3 tAQ TA = +25°C, 0 V to 10 V Step to 0.1% 3.5 4.25 ms Acquisition Time 3 tAQ TA = +25°C, 0 V to 10 V Step to 0.01% 9 ms Hold Mode Settling Time t H To 1 mV 1 ms Slew Rate4 SR R L = 20 kW 34 V / ms Capacitive Load Stability C L <30% Overshoot 500 pF Analog Crosstalk 0 V to 10 V Step –80 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR 10.8 V £ VDD £ 13.2 V 60 75 dB Supply Current I DD 47 m A Power Dissipation P DIS 84 mW Parameter Symbol Conditions Min Typ Max Units Linearity Error 0.01 % Buffer Offset Voltage V OS VIN = 0 V –10 – 2.5 +10 mV Hold Step V HS VIN = 0 V, TA = +25°C to +85°C2 . 5 4 m V VIN = 0 V, TA = –40°C5 m V Droop Rate D V/DtV IN = 0 V, TA = +25°C 2 25 mV/s Output Resistance R OUT 1 W Output Source Current 1 ISOURCE VIN = 0 V 1.2 mA Output Sink Current 1 ISINK VIN = 0 V 0.5 mA Output Voltage Range OVR R L = 20 kW –3.0 +3.0 V LOGIC CHARACTERISTICS Logic Input High Voltage V INH 2.4 V Logic Input Low Voltage V INL 0.8 V Logic Input Current I IN 0.5 1 mA DYNAMIC PERFORMANCE 2 Acquisition Time 3 tAQ –3 V to +3 V Step to 0.1% 3.6 11 ms Acquisition Time 3 tAQ –3 V to +3 V Step to 0.01% 9 ms Hold Mode Settling Time t H To 1 mV 1 ms Slew Rate5 SR R L = 20 kW 3V / ms Capacitive Load Stability C L <30% Overshoot 500 pF SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR – 5 V £ VDD £ – 6 V 60 75 dB Supply Current I DD 3.5 5.5 mA Power Dissipation P DIS 55 mW NOTES 1Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels. 2All input control signals are specified with t R = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 3This parameter is guaranteed without test. 4Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%. 5Slew rate is measured in the sample mode with a –3 V to +3 V step from 20% to 80%. Specifications are subject to change without notice. REV. D–2– (@ VDD = +12.0 V, VSS = DGND = 0 V, RL = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.) (@ VDD = +5.0 V, VSS = –5.0 V, DGND = 0.0 V, R L = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.)

–3–REV. D ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted) (Not Short-Circuit Protected) Operating Temperature Range Package Type uJA* uJC Units 16-Lead Cerdip 94 12 °C/W 16-Lead Plastic DIP 76 33 °C/W 16-Lead SO 92 27 °C/W *uJA is specified for worst case mounting conditions, i.e., uJA is specified for device in socket for cerdip and plastic DIP packages; uJA is specified for device soldered to printed circuit board for SO package. CAUTION 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; function operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. Digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. 3. Remove power before inserting or removing units from their sockets. ORDERING GUIDE Temperature Package Package Model Range Description Options* SMP04EQ –40 °C to +85°C Cerdip-16 Q-16 SMP04EP –40 °C to +85°C PDIP-16 N-16 SMP04ES –40 °C to +85°C SO-16 R-16A *Q = Cerdip; N = Plastic DIP; R = Small Outline. PIN CONNECTIONS 16-Lead Cerdip 16-Lead Plastic DIP 16-Lead SO TOP VIEW (Not to Scale) SMP04 NC = NO CONNECT VOUT2 VSS VOUT4 VOUT3 VDD VOUT1 VIN1 NC S/H4 VIN3 VIN4VIN2 S/H1 S/H2 DGND S/H3 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

–4– SMP04 REV. D WAFER TEST LIMITS SMP04G Parameter Symbol Conditions Limits Units Buffer Offset Voltage V OS VIN = +6 V – 10 mV max Hold Step V HS VIN = +6 V – 4 mV max Droop Rate DV/DtV IN = +6 V 25 mV/s max Output Source Current I SOURCE VIN = +6 V 1.2 mA min Output Sink Current I SINK VIN = +6 V 0.5 mA min Output Voltage Range OVR R L = 20 kW 0.06/10.0 V min/max RL = 10 kW 0.06/9.5 V min/max LOGIC CHARACTERISTICS Logic Input High Voltage V INH 2.4 V min Logic Input Low Voltage V INL 0.8 V max Logic Input Current I IN 1 mA max SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR 10.8 V £ VDD £ 13.2 V 60 dB min Supply Current I DD 7 mA max Power Dissipation P DIS 84 mW max NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot asse mbly and testing. (@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +258C, unless otherwise noted.) VOUT3VOUT1 VOUT2 VOUT4 VIN1 VIN2 VIN3 VIN4 S/H1 S/H3 S/H4DGND VSS VDD S/H2 Dice Characteristics Die Size: 0.80 x 0.120 mil = 9,600 sq. mil (2.032 x 3.048mm = 6.193 sq. mm)

–7–REV. D GENERAL INFORMATION The SMP04 is a quad sample-and-hold with each track-and- hold having its own input, output, control, and on-chip hold capacitor. The combination of four high performance track-and- hold capacitors on a single chip greatly reduces board space and design time while increasing reliability. After the device selection, the primary considerations in using track-and-holds are the hold capacitor and layout. The SMP04 eliminates most of these problems by having the hold capacitors internal, eliminating the problems of leakage, feedthrough, guard ring layout and dielectric absorption. POWER SUPPLIES The SMP04 is capable of operating with either single or dual supplies over a voltage range of 7 to 15 volts. Based on the supply voltages chosen, V DD and VSS establish the output volt- age range, which is: VSS + 0.05 V £ VOUT £ VDD –2 V Note that several specifications, including acquisition time, offset and output voltage compliance will degrade for a total supply voltage of less than 7 V. Positive supply current is typi- cally 4 mA with the outputs unloaded. The SMP04 has an inter- nally regulated TTL supply so that TTL/CMOS compatibility will be maintained over the full supply range. Single Supply Operation Grounding Considerations In single supply applications, it is extremely important that the V SS (negative supply) pin be connected to a clean ground. This is because the hold capacitor is internally tied to V SS. Any noise or disturbance in the ground will directly couple to the output of the sample-and-hold, d egrading the signal-to-noise performance. It is advisable that the analog and digital ground traces on the circuit board be physically separated to reduce digital switching noise from entering the analog circuitry. Power Supply Bypassing For optimum performance, the V DD supply pin must also be bypassed with a good quality, high frequency ceramic capacitor. The recommended value is 0.1 mF. In the case where dual sup- plies are used, VSS (negative supply) bypassing is particularly important. Again this is because the internal hold capacitor is tied to VSS. Good bypassing prevents high frequency noise from entering the sample-and-hold amplifier. A 0.1 mF ceramic bypass capacitor is generally sufficient. For high noise environments, adding a 10 mF tantalum capacitor in parallel with the 0.1 mF provides additional protection. Power Supply Sequencing It may be advisable to have the VDD turn on prior to having logic levels on the inputs. The SMP04 has been designed to be resis- tant to latch-up, but standard precautions should still be taken. OUTPUT BUFFERS (Pins 1, 2, 14 and 15) The buffer offset specification is – 10 mV; this is less than 1/2 LSB of an 8-bit DAC with 10 V full scale. Change in offset over the output range is typically 3 mV. The hold step is the magnitude of the voltage step caused when switching from sample-to-hold mode. This error is sometimes referred to as the pedestal error or sample-to-hold offset, and is about 2 mV with little variation. The droop rate of a held channel is 2 mV/ms typical and – 25 mV/ ms maximum. The buffers are designed primarily to drive loads connected to ground. The outputs can source more than 1.2 mA each, over the full voltage range and maintain specified accuracy. In split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 V from either supply. On-chip SMP04 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capaci- tive loads up to 500 pF. However, since the SMP04’s buffer outputs are not short-circuit protected, care should be taken to avoid shorting any output to the supplies or ground. SIGNAL INPUT (Pins 3, 5, 11 and 12) The signal inputs should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP04’s fast acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails (V SS £ VIN £ VDD) to avoid the possibil- ity of setting up a latch-up condition. The internal hold capacitance is typically 60 pF and the internal switch ON resistance is 2 k W . If single supply operation is desired, op amps such as the OP183 or AD820, that have input and output voltage compliances including ground, can be used to drive the inputs. Split sup- plies, such as – 7.5 V, can be used with the SMP04 and the above mentioned op amps. APPLICATION TIPS All unused digital inputs should be connected to logic LOW and the analog inputs connected to analog ground. For connec- tors or driven analog inputs that may become temporarily dis- connected, a resistor to V SS or analog ground should be used with a value ranging from 0.2 M W to 1 MW . Do not apply signals to the SMP04 with power off unless the input current’s value is limited to less than 10 mA. Track-and-holds are sensitive to layout and physical connections. For the best performance, the SMP04 should not be socketed.

Figure 17. THD+N vs. Frequency

1.4 V p-p pure sine wave input of 20 kHz and 8 kHz respec-

improved S/N performance of –48 dB. this condition, the signal-to-noise measures 53 dB. Figure 19. SMP04 Spectral Response with an Input Carrier Figure 18. SMP04 Spectral Response with a 1.8 kHz Carrier Frequency. (a) Shows the Sampling Frequency at 14.4 kHz;

–10– SMP04 REV. D MULTIPLEXED QUAD DAC (Figure 20) The SMP04 can be used to demultiplex a single DAC converter’s output into four separate analog outputs. The circuit is greatly simplified by using a voltage output DAC such as the DAC8228. To minimize output voltage perturbation, 5 ms should be allowed to settle to its final voltage before a sample signal is asserted. Each sample-and-hold amplifier must be refreshed every second or less in order to assure the droop does not exceed 10 mV or 1/2 LSB. CHANNEL DECODE VSS VOUT1 VOUT2 VOUT3 VOUT4 DGND VSS VSS VSS SMP04 1mF +12V REF02+12V 0.1mF 1/2 DAC8228 VZ +5V GND VDD VREF VO DIGITAL INPUTS ADDRESS INPUTS S/H1 S/H2 S/H3 S/H4 +12V 5V TO 10V WR CS Figure 20. Multiplexed Quad DAC

–15–REV. D OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Cerdip (Q-16) 1 8 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.080 (2.03) MAX SEATING PLANE0.023 (0.58) 0.014 (0.36) 0.200 (5.08) MAX 0.840 (21.34) MAX 0.150 (3.81) MIN 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 15° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 16-Lead Plastic DIP (N-16) 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-Lead SO (R-16A) 16 9 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° PRINTED IN U.S.A. C3131–0–4/98