SMP-11B

SMP-10 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

FEATURES low droop rate with no penalty in acquisition time. The use of bi- SMP-10 polar transistors achieves a low change in droop rate over the © LOW Dr00p Rate wnnenssnnnemnnnrannannn 5.0HVIms —_ oPerating temperature range, Continued Linearity Ett Of .nneonnorinrninsrinneinnenennees 0.005% @ High Sample/Hold Current Ratlo wcsewnsnenne 2X09 PINCONNECTIONS SMP-11 @ Low Droop Rate Over Temperature .nrsinnnne 2400KV/MS. Bag @- High Sample/Hold Current Ratio w.ccnceevee 1.7108 xed Lane iggks BOTH SMP-10 AND SMP-11 wor Gl oe 4c © Fast Acquisition Time, 10V Step 100.1% wrwnnnnne 3.51 wu BI fle Bie © High Slew Rate o..sessescsesneestsesnetnnernenseenserene TOV/ES we palvic nut [a] oes © LOW Aperture TIM .sssccssseusseseneemssanseneesneinseneee SONS ae fens ne. fF] fil we. © Feedthrough Attenuation Ratlo —..nnrwnenennnnne 9608 net Fave PraMra @ Low Power Dissipation ..nnsnnunsmnnnnnnsene 16OMW esas #. DTL, TTL & CMOS Compatible Logic Input 46-PINSOL TER © HA-2420, HA-2425, SHM-IC-1, and ADS83 Socket (S-Suttix) Compatible . ‘SMP-11BRC/883 ¢ Avaliable in Die Form ‘SAMPLEMOLD CONTROL LCC PACKAGE (RC-Suttix) ORDERING INFORMATION ' one. Of baer Tase2eC input [2] fi) Mic oer PACKAGE openarine mu Fane 14-PIN DIP (Y-Suffix) Vis RATE IN 14-PIN DIP TEMPERATURE owe ET fc, 14-PIN EPOXY DIP (P-Sutfix) (mv) Vins: HERMETIC Lec RANGE GI HEIN. + pins 1 AND 8 ARE NOT INTERNALLY ee OE ne. fi}v. "CONNECTED, IUNTY GARTAPPLICA 15 2 SMPIOAY" = Mi comet Fjncs TIONS, SMP-10 AND SMP-11 CAN RE- 18 20 SMPIOEY : com ACE HA 2125, W240, SHI 30 50 ‘SMP10FY = COM 18 200 SMPIIAY" - ML 30 500 SMPIYBY" SMPIYBRC/663 (MIL 5 20 0 SMPIIEY - com

32 SMPY : CoM FUNCTIONAL DIAGRAM

70 00 = SMPIIGY - com 79 900 © SMPI1GS. - XIND ay 70 900 SMPIIGP. - XIND 5 9 waveaniron

7 Fordevicesprocessedin otal compliance toMiL-STD 689, add/883 alter part cd pt -

number. Consult factory for 883 data sheet. ang o4 cael

1 Burminis avaiable on commer and instil omperatre range pain wet >

CerDIP, plastic DIP, and TO-can packages. A+ @ cotta rR ‘008 GENERAL DESCRIPTION Le Ky ns 1 The SMP-10/11 are precision sample-and-hold amplifiers that nso} > Ye sv er provide the high accuracy, the low droop rate and the fast ac- Quisition time required in data acquisition and signal processing ‘) systems. Both devices are essentially noninverting unity gain circuits consisting of two very high input impedance buffer am- e plifiers connected together by a diode bridge switch, HIGH ACCURACY AND LOW DROOP RATE The high input impedance andthe low droop rates of the SMP-10 FF \\ andthe SMP-1 are achieved by using bipolar Darlington circuits Seat Yeesovron mu mur camry | and an ion implant process that creates "super beta” transistors. | The output buffer's input stage converts to a super beta Darling- a | ton configuration during the hold mode, which results in a very SS | Marafactored under he olowing patent 4 308,218 and 142,197 REV. C SAMPLE/TRACK-HOLD AMPLIFIERS 4-109

GENERAL DESCRIPTION Continued FAST ACQUISITION ‘Aunique super charger provides upto SOmAot charging current Operating Temperature Range , tothe hold capacitor, which results in smooth, fast charging with SMP-AOAY wren nsrinrnininennenen “ECHO 4 125°C minimum noise, Asthe hold capacitor voltage nears its final value, SMP-TOEY, FY secnvenrnnnennnanenmneanens O° 10 470°C the low current diode bridge controls the final settling time. This SMP-11AY, BY, BRC won srnnennennnne “BSPC10 +125°C unique combination of linear functions in a monolithic circuit pve aged GY vosrrnneientniennrnenens OC ® eG ‘les the system designer to achieve superior performance. GP enrmmetnnnectnnennnannee AOC 10 44 enables the system designer to uperior pa Junction Temperature (Tj) nn.nrnnneennese ~B5°C 10 +150°C ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE TYPE ©, (Note 2) & UNITS Supply Voltage (V+ MINUS V=) vevnenenninnemnnnnnnee SOV Wop HemeiO) Bs Input Voltage ..ns.n.nnsnnisnnnsenenene Equal to Supply Voltage teBeeen De) _ 2 —_8 $a Logic and Logic Reference Jepnsous) Voltage «.ersessietuenintanensneneenes Equal to Supply Voltage 2oComacteciAC) Hold Capacitor Short-Circuit Duration... 60sec" Abselut ratings apply to both DICE and packaged pars, uross cherie Storage Temperature Range vnrnnswennnnnn “65°C 10+150°C 2. @y is epaciied for worst case mounting conditions, i... is specified for Lead Temperature (Soldering, 60 $60) .rcmnninsemnee 300°C device in socket for CerDIP and LCC packages. ELECTRICAL CHARACTERISTICS at Vs = #15V, Cy = 0.005pF, Vic connected to ground, Ts = +25°C, unless otherwise noted. ELECTRICAL CHARACTERISTICS al V5 = 210y oa ee eee ‘SMP-10VE ‘SMP-10F ‘SMP-11A/E ‘SMP-11B/F ‘SMP-11G PARAMETER SYMBOL CONDITIONS Min TYP oOMAX)oMIN) TYP MAX MIN” TYP -MAX_UNITS PARAMETER SYMBoL_conomions OOOO ower Sao Zero-Scale Evor Vireo awed %25 yr, (Nowe2) - 04 15 - 060 30 - 18 70 ww (Droop) Current ton ‘SMP-11 - =__ 1.00 = = 2.50 = = 45 a Droop Fate eVewst sup-11 ee ee ca InputResisiance Ay (Nolo 1) 2 80 - tA = 20 ~SOGa Sample Mode or Vy = 5V, Ry = 2.5K. FOV Step to Within 10" To ‘Acquisition Time ‘ of Final Value (0.1%) 7 3s 7 - 35 7 7 35 7 as _ im bd 10V Step to Within 1.0mV of Final Value (0.01%) = 50 = - so - 7 so - Bs Aperture Time tap = a - so - s Hold Mode Senting wo mV SMP-10 = 7 - - rr re ‘Setting Time hia ‘ofFinal Value. SMP-11 - 15 - - 15 - - 18 - Charge Transfer Ot vee sy a - 5s - pC Sree trons Vemessy Slow Rate SR ped - 10 - - 10 - - 10 - vm Swen ee cront len Vin~Vout2#8V 30 50 - 20 50 - - 50 - mA _Gharging Gurren low NT Now Samplestiols SMP10 oxi0® 2xi® = BxTO” xt - CurentRaio __ler/lon SMP-11 = 170 ~_ 18x10" - = ssaoh = MAMA Feedthrough nput= 20Vpp The ‘Aeration Ratio ** R= 5x0, (Rove 1) se 8 - © mw - - * - * Full Power 210, Bandwidth fo {Dissipation Limited) - m= — me 4-110 SAMPLE/TRACK-HOLD AMPLIFIERS REV.C

ELECTRICAL CHARACTERISTICS at Vg = #15V, Cy = 0.005uF, Vic connected to ground, T, = +25°C, unless otherwise noted. Continued ‘SMP-0AE ‘SMP-10F ‘SMP-11A/E ‘SMP-11B/F ‘SMP-11G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN] TYP oMAX MIN TYP MAX UNTS Tnpui Voltage Range ‘andlor Output Ry =25k0 aoanS = HOS aS OS SV Voltage Swing OuiputResistance Ro = 0s = 015 ee) Power Supply ‘Sample Mode - - Fe hg PSA YATES rev 82 92 7 oe 7 92 fr) Power — om mpton(oc) PO Sample Mode Vy=0 - 160 180 - 17% 210 = 18 240 ow NoTes: 1. Guaranteed by design. 2. Measured S00ps after hold command, ELECTRICAL CHARACTERISTICS - SMP-10 ONLY at Vs = #15V, Cy = 0.005pF, Vic = OV, Ta = +25°C, device fully warmed vp, unless othorwise noted. 4 pr uniess otherwise te ‘SMP-10A/E SMP-10F PARAMETER ‘SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS: Hold Step Vas Vin=0 “0 45 140-30 1580 mv Linearity Error NL Vin = 210V, Ry = 5k ~ 0,005 - - 0.007 = — %of10V ‘Wideband Noise 100H2 (Ouput Noise Ewes) to 100kHz Sample Mode 7 40 7 7 50 ~ Wes ELECTRICAL CHARACTERISTICS at Vs = +15V, Cy = 0.005pF, Vic connected to ground, 0°C s Ta < +70°C, unless otherwise noted. ‘SMP-10E ‘SMP-10F ‘SMP-11E ‘SMP-11F ‘SMP-11G PARAMETER SYMBOL CONDITIONS MIN TYP MAX Mm TYP MAX win TYP MAX UNITS Zero-Seale Ever Vz5 Vin=0,Ven=3SV, (Noe) - 075 20 = 1040 = 270 input Bias Current Ia Vin oV = 9090 =o 140 = 120 250A Loakage ; SMP.10 = 005 025 = 0080 088 - = = Wn (Droop) Current OF ‘SMP-14 - os 18 = 06 28 - 07 5 SMP-10 - 10 50 = 130 - Droop Ree sVewat ‘SMP11 - 100 360 - 120 560 - 140 = 1000 wvims ‘Sample Mode or Viy = 35V, Ry = 2.540, Power Supply ‘Sample Mode Rejection Ratio PSRR Vg =49V to 318V 80 90 ~ 7s 80 ~ 70 90 7 8 Logic Contra! secon KE Vic=0¥ - 4 2 - 4 3 - - Sample Mode - 6 48 - 8 48 - 8 415 WA Logic Input i? Von =0.8¥ om Hold Mode vane sov - 020 = - 020 = - 02 = ma Differential Logie Meron NOO Vay os 13 20 os 1320 o8 13 200 NoTE: 1. Measured 500us afer hold command, REV. C SAMPLE/TRACK-HOLD AMPLIFIERS 4-111

ELECTRICAL CHARACTERISTICS at Vs = = 15V, Cry = 0.005yF, Vic connected to ground, -55°C < Tas +125°C, unless otherwise noted. piltlelaelliciee no ‘SMP-10A SMP-10 SMP-11A SMP-11B PARAMETER SYMBOL CONDITIONS MIN TYP MAK MIN” TYP MAX UNITS Zero-Scale Error Ves Vin= 0, Vgqu=8.5¥, «Note t = 13530 — e085 ov Input Blas Curent le Viy= OV = 90180 = 160 280 nA Tra 556 = 0050 080 =~ 0080 122 Leakage (Droop) Current Jor Tam + 125°C ‘SMP=10 - 12 20 - 16 25 nA Ta=Full Range _SMP-11 - 2 » - 6 8 Ta= 56 — 1 100 = 1% 250 Droop Rate Aey/dt — Ta = + 128°C SMP-10 — 2400 4000 — 3200 5000 wes Ta= Full Range SMP-11 — 2400 4000 — —— 52008000 “ Sample Mode Voltage Gain Ay Viu= 10M, Ry = 5KO 0.99950 0.90972 — «0.98840 0.96068 w oF Vig #5V, RL 25KO Power Supply Sample Mode _ _ Rejection Ratio PSRR Vs = +9V to > 18V - i 88 rR 90 bad Logie Control input Gurrent Ine We=v = 4 8 = 41s HA Sample Mode . _ . Logic Input I Nam= ony ~ a ss “ Hc Input sm Hold Mode ee ov = 0 = - 02 = oA Differential Logic sain Vow 06 1320 os 61320 v NOTES: 1. Measures 5004s after hold command. BURN-IN CIRCUIT 1 “ a | r As. me E | MV $1 - ] v v 1 (ONE DIODE SETPER BOARD) | 4-112, SAMPLE/TRACK-HOLD AMPLIFIERS REV. C

1. INpuT teers 3. NULL aa Bair oregon Ne Neat Sl] FT a a=.0 reer 4. NULL Caer Es 4. NULL b eka 5. NEGATIVE SUPPLY by oes 5. NEGATIVE SUPPLY ey (SUBSTRATE) Ae ae B (SUBSTRATE) Za UM gl ol 7. output nT TN at el nouwer (=e Ey 8. POSITIVE SUPPLY me Si 8. POSITIVE SUPPLY Fa Pe | ‘11. HOLD CAPACITOR (Cy) a es Pe erg 11. HOLD CAPACITOR (Cy) feat umrerreas 13. LOGIC THRESHOLD fees 0 reer 43, LOGIC THRESHOLD. lang Seat. CONTROL (Vic) jy ears CONTROL (Vic) er a 14, SAMPLEHOLD Fea and lies 14. SAMPLEHOLD pal = ty COMMAND Cr = Gs COMMAND Aare pl ett ais BEE oie size 0.0ee 0.089 inch, 720889. mits fF euM. (2.295 «2108 mim, 471159, 0) ‘SMP-10 ‘SMP-11 WAFER TEST LIMITS at Vs = +15V, Cy) = 0.005uF, Vic connected to ground, Ta = 25°C, unless otherwise noted. Pt tas cl tee in a aac cna ‘SMP-10N ‘SMP-10G 4 ‘SMP-11N SMP-11G PARAMETER SYMBOL __ CONDITIONS uit uit unis nor Vin=0. Vg 3.5 o Zero-Seale Ero Ves Varo Venn ay 7% 2 W MAX input Bias Current ie Vn ov © MAK MP0 a0 025 Leakage (Oro0p) Current lon Since ° 28 nA MAX ‘sme-10 20 30 Droop Rate aveyien SPIO oe 2 sims MAX Sample Mode Voltage Gain Ay Vu = 10 0.90968 0.90889 win orVy= 5 Hold Cepsciter “yee. 7 Input Volage Range and/or wn . vtput Voltage Swing eo sy os vin Power Supply Sample Mode Rejection Ratio PSAR Ve= £9V to #18 _ ® _ " ceMn Power Consumption Po Semple Mode Viy= 0 180 a ri MAX Topic Comtrotinput Gurrent hue “Ve= ov _ “3 DA MAX ‘Sample Mode 16 18 BAMAX Logic input Is Vena = 0.6V ” Hold Mode Differential Logic y Veuo 20 20 VMAX Threshold ™ ia o8 os vMIN NoTEs: 4. Measured S008 after hold command Erectical tests are performed at water probe to the limits shown. Due to variations in assembly methods and normal yield lass, yield after packaging isnot Guaranteed for standard procuctdiee. Conault factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. TYPICAL ELECTRICAL CHARACTERISTICS at Vs = + 15V, Cy = 0.005uF, Vic Connected to ground, Ta = 25°C, unless otherwise noted, a ‘SMP-10N SMP-106 ‘SMP-11N SMP-11G PARAMETER SYMBOL _ CONDITIONS TYPICAL TYPICAL unis ‘Acquisition Time 7 10V stop 100.1% o inal value 35 35 = Aperture Time ‘ep 50 30 8 ‘Charge Transfer a, Vin= 0, Vou=3.5V 5 3 pe Slow ate sR Vy=# 10, Ry = 25K 0 0 Was REV. C SAMPLE/TRACK-HOLD AMPLIFIERS 4-113

TYPICAL PERFORMANCE CHARACTERISTICS CHANGE IN HOLD STEP AMPLITUDE CHANGE IN ve s/n 2 HOLD STEP vs HOLD MODE dt INPUT VOLTAGE POWER SUPPLY REJECTION Sage cee) ¢ | Ae Milt aig caiie atten eR NR = EN | | _ 00 Pope TYPICAL D.C POSITIVE PONER SUPPLY! Paes ES NS s {i roi p four” = avai =r tt HE ° NOx 3 Ni |

8 Eon CoA on : BERNE & ht i

§ LUE ST, NO g ‘i ESA aave, ie z2 NN * Hit Ha feeder ‘eee (NN) em sae LO aria oLitiggrenmacersce! TA Tl sav ne arr suc avn re ae oven nn ‘SMP-10 ‘SMP-11 DROOP RATE DROOP RATE DROOP CURRENT ve TEMPERATURE vs TEMPERATURE vs TEMPERATURE sae ss ee [eres TTT | TY vonfecet] TT TTT J ————_—— =H HH Hitt ; LA i ie 2 eS Se ee ee ee ee ee ee sae PCO EO) ee Reef TTA? L| [YT | : eS SAE : HAH oe see TT TT I mettt titi | Et 4 a ae ee es oe INPUT BIAS CURRENT ACQUISITION TIME vs TEMPERATURE vs HOLD CAPACITOR LOGIC INPUT CURRENT “AT Nee) ee secrete SENET es BE eT NTL Pe poe PCPRET TTT) og. NI Pee pNP NET Oo-Rf - PONG i SH | La aa Lar | LETTS ET ewes \\ceeen femewnr TT) UT raenurne re) cn to coven vocage wou 4-114 SAMPLE/TRACK-HOLD AMPLIFIERS REV. C

TYPICAL PERFORMANCE CHARACTERISTICS POWER DISSIPATION vs MAXIMUM INPUT SIGNAL

8 GAIN ERROR olNPUT FREQUENCY = V, oT eT

i ExT TW | het) lyn Sst iirc ” x oS OH ae OI Pope can a SS CTI =A i. | | Pest ime is a A an OR OUTPUT RESISTANCE Sa BANDWIDTH (ele TO. CHARGING CURRENT va vs FREQUENCY FREQUENCY INDICATED) INPUT OUTPUT VOLTAGE CCMDCMETIT] 5 “Sse =eeera 2 | COTO) = § AEF tay tt es NAT a Hage y= Sau at a Bee castatat: 13 ‘cn EN A ctl Fe TOTAL HARMONIC SAMPLE MODE POWER SUPPLY CURRENT DISTORTION vs FREQUENCY POWER SUPPLY REJECTION vs POWER SUPPLY VOLTAGE 0 ee wo Aa] 7 SSlaae | Wal fe RT [ camera NS] Leer 5 Eee EO LIl IN 7? - Pe THITTITIN ibe titty aa, ec aout A | REV. C ‘SAMPLE/TRACK-HOLD AMPLIFIERS 4-115

‘SMP-10/SMP-11 ACQUISITION TIMES ACQUISITION TIME ACQUISITION TIME ACQUISITION TIME —10V to OV +10V to OV -1,0V to OV E TTT YT. | Pty TTT cca of aanann load 1 r ai i ACQUISITION TIME ACQUISITION TIME ACQUISITION TIME +1.0V to OV -100mV to OV +100mV to OV ston Tt Ht 44 e = a tt H+ {4 } | +r HX} t + ia | a See bol TT TT [oe | to i ftw | | pd 1D aa we FL, APPLICATIONS INFORMATION During the nuil adjustment, the amplifier should be switched As shown in the Figure, the sample/hold mode contro! is continuously between the “sample” and “hold” mode. The accomplished by steering the current (1;) through Q1 or Q2, error should be adjusted to read zero when the unit is in the thus providing high-speed switching and a predictable logic “hold” mode. In this way, both offset voltage errors and threshold. For TTL and DTL interface, simply ground Vic charge transfer errors are adjusted to zero. (Pin 13). For CMOS, HTL and HNIL interface, the appropriate ZERO-SCALE NULL ADJUSTMENT LOGIC CONTROL er 2 uF eho wo " “ ret ~ tre + le|, a Peo vic iweur 02 2 OOUTRUT Ta = on anor quar jocum <|" T aetna Ree Wk Trucowanatiry afte » w 4-116 SAMPLE/TRACK-HOLD AMPLIFIERS REV. C

threshold voltage, allowing for 2 diode drops for D1andVge GUARDING AND GROUNDING LAYOUT of Q3, should be applied to Vic. The use of a ground plane is strongly recommended to For proper operation, the Vic (logic control} must alwaysbe 'inimize ground path resistances. Separate analog and at least 3.5V below the positive supply and 2.0V above the _digital grounds should be used, and it is advisable to keep negative supply. these two ground systems isolated until they are tied back to the common system ground. Digital currents should not flow Sample-and-hold control voltage (S/H) must always be at back to the system ground through the analog ground path. least 2.8V above the negative supply. HOLD CAPACITOR RECOMMENDATIONS The hold capacitor (C}) acts as a memory element and also as a compensating capacitor for the sample-and-hold am sete BY amplifier. For stable operation, a minimum value of 2000p F is. tone {sas = SOx suaico] recommended, with no limit set for the maximum value. The contrat | Grouno SK&KS SS wor devices have been internally trimmed for C}=5000pF. Other UNO RESIN values of Cy will cause a zero-scale shift, which can be ict Lon HOSS» | S&S: calculated from the following equation: sine © KeSSe Ny SS YEE | yey. AVzs(mV) = Soe) x10? “1 fa VID? N Ws == eS Ss: The hold capacitor should have very high insulation G91 AG" | resistance and low dielectric absorption. For temperatures below 85°C, polystyrene capacitors are recommended, while teflon capacitors are recommended for higher temperature applications. REV. C ‘SAMPLE/TRACK-HOLD AMPLIFIERS 4-117