SMJ9914A

SMJ9914A TI | Alldatasheet

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JUNE 1996 — REVISED MARCH 1988 © Handles All IEEE-488 1975/78 Functions JD PACKAGE © Compatible with IEEE-488A 1980 (ror view) Supplement Recra C]1 Cho vec © Maximum Transfer Rate . . . Greater Than AccGRE 2 39f }7R

360 Kilobytes/Second SEL|s 38f }DI01

WE(]4 = 37[)pI02 © Talker and Listener Function (T, TE, L, LE) painE}s 36[-Jo103 © Automatic Source and Acceptor Rso[je 35] ] D104 Handshakes (SH, AH) Rsi{|7 34[ }DI08 RS2(]8 33°] DI06 © Controller with Pass Control IWtE]s 32F]0107 © System Controller Capabilities D7 [10 31f }o108 System Cap peC]i11 30f|TONT © Device Trigger and Device Clear Capabilities ps—12 29 ]sro (DT, DC) p4(13 28 ]ATN © Optional Automatically Cleared ‘Request o3(jr4 27, Jeo Service Bt o2C)15 26) DAV Dif}16 25, ]NRFD © Parallel and Serial Poll Facilities (PP) voC}17 24 Npac @ Remote/Local Function with Local Lockout ee (RL) RESET] 19 22/7) REN Vss(]20 210) TE © Single or Dual Primary Addressing e ities Secondary Address Capabilit FD PACKAGE © Direct interface to SN75160/161/162 Bus (TOP View) Transceivers with No Additional Logic x © Compatible with Most Microprocessors z B 4 <a . Buup se SeQ8e @ Direct-Memory-Access Facilities alsiol«icz2>F O02 e Mi 7 65 4321 44 43 424140 Memory-Mapped Microprocessor Interface sof? 20) bios @ Temperature Range... - 55°C to 110°C. Rs1)/8 38] DI04 (S Suffix) Rs2]}9 37 DI05 INTf}10 36] DIO6 description o7fn 38] D107 The SMJ9914A provides an interface between ee Hl ie ped bec a Microprocessor System and the General be p ne bss | CONT Purpose Interface Bus (GPIB) specified in the pee ot bee IEEE-488 1975/78 standards and the IEEE-488A ed 304 ary 1980 supplement. The device is controlled and i H he bs H for configured through 8-bit_ memory-mapped registers and enables all aspects of the standards to be implemented, including talker, listener and Sart gkzeges controller. The functional block diagram is shown iB > © os on page 3. eee PRODUCTION DATA documents contain information Copyright © 1986, Texas Instruments incorporated seuminciratsaa i eo Texas SSittcnipncus tetey oS peramere INSTRUMENTS POST OFFICE BOX 1483. ® HOUSTON, TEXAS 77001 14-308

The GPIB is designed to allow up to 15 instruments within a localized area to communicate with each other over a common bus. Each device has a unique address, read from external switches at power-on, to which it responds. information is transmitted by byte-serial bit-parallel format and may consist of either device-dependent data or interface messages, commonly referred to as data or command, respectively. A typical application is shown in Figure 1. Auxiliary commands are listed in Table 1- Device data may be sent by any one device (the talker) and received by a number of other devices (listeners). Instructions, such as select range, select function, or measurement data for processing or printout, may be sent in this way. The SMJ9914A performs the interface function between the microprocessor and GPIB bus and relieves the processor of the task of maintaining the IEEE protocol. By utilizing the interrupt capabilities of the device, the bus does not have to be continually polled, and fast responses to changes in the interface configuration can be achieved. The GPIB input/output pins are connected to the IEEE-488 bus via bus tranceivers. The direction of data flow is controlled by the TE and CONT outputs generated on the SMJ9914A. The SN75160, 75161 and 75162 bus transceivers are designed specifically for use with a GPIB interface. The TE and CONT signals are routed within the devices so that the buffers on particular lines are controlled as required by the SMJ9914A, Other buffers may be used, but they may require a small amount of external logic, particularly around the EOI line buffer. TEXAS ap INSTRUMENTS 14-310 POST OFFICE BOX 1443 @ HOUSTON, TEXAS 7700

FIGURE 1. TYPICAL SMJ9914A APPLICATION

[ ew 0 ("No WaME—) rye) osenenion | _1_[ AcenG [ot | Access Reavest_ This pin becomes active How to request a dest memory eccess—_—_—| [2 | rem || Site tmansne SCC mun wengrancrau scpang can cone KCCGR byte onto the data bus. ACCGR must be high when not participating in DMA transfer. ae ee impedance unless ACCGR is low. Write Enablo. When active Yow), indicates to the SMJBTAA that data is being writen to one a Bie Data Bus In. An active (ighi state Indicates to the SMISOT4A that Fead le about to be a @ [#80 S| Se Register Select Lines. Determine which register is addressed by the MPU during a read 7] or write operation [2 | mT | oF ntorupt. Sent to the MPU to cause a branch oa service routine. Sd [#8 [2 | 1 ciock input. 500 Kz to 5 Miz. Need not be synchronous to system clock, [19 | Resets [1 [ ieitisizes te SMu99148 at poweron. Cd [20 | Vas | [Ground revere wortage, a ee ICACS + TACS + EIO.ATN.(CIDS + CADS) SWRSTI. Remote Enable. Sent by system controller to select control either from the front panel or from ee [2 [re [ot cecnans Term naernen tenis nace | aviescent state. The aystem controller becomes the controller in charge. data from the I/O lines. | 25 | warp | vot | Not Reasy For Data. Handshake ine. Sent by acceptor to indicate readiness forthe next byte | ee to the bus. a true low), the controller is requesting © pale! pol Le [am [et eine nen tte na nae ayaa ee | over the DIO lines. When false (high), these lines carry data. | 20 [sna | wot | ‘Service Request. Set true low) by @ device to indicate @ need forsewice > for | o [eames ATN in pass control systems. Logicaily, it is (CIDS + CADS). the IEEE-488 bus via non-inverting transceivers, a re is given by the MPU. [0 [Wee [J Snoty vatage (5 Vnominals ‘Push-pull output Open-drain output with no internal pullup SThe hardware RESET pin has the following effect on the SMJ9914A: —Serial and Parallel Poll registers cleared All clear'set auxiliary commands cleared except ‘swrst’ ~"swrst’ auxilary command set. This holds the SMJ9914A in known states Open-drain output with internal pullup TEXAS % INSTRUMENTS 14-312 OST OFACE BOX 1643 @ HOUSTON. TEXAS 77001

Communication between the microprocessor and SMJ991 4A is carried out via memory-mapped registers. location loads the auxiliary-command register. Each device on the bus interface is given a 5-bit address enabling it to be addressed as a talker or listener. This address is set on an external DIP switch (usually at the rear of an instrument) before power-on. when this address is detected on the GPIB data tines. TABLE 1. AUXILIARY COMMANDS. TABLE 2. REGISTER ADDRESSES

4 DESCRIPTION NA oO 0 oO Interrupt Status 0 | Interrupt Mask 0

nbaf New byte available false 05 space of the device at these locations. rhdf Release RFD hoidoff 02 occurred.

INTERRUPT MASK/STATUS REGISTER 0. FIGURE 2. INTERNAL REGISTERS

—_— EE absolute maximum ratings over operating case temperature range (unless otherwise noted) t tStresses beyond those listed under ‘‘Absolute Maximum Ratings’” may cause permanent damage to the device. This is a stress rating only and furctional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device rekabily. Ali voltage values in this data sheet are with respect to Vgs. recommended operating conditions a [vss Svpiy voltage SSCS [Vin High-level input volage [Vi towlevel mputvotage TL VT [_Ailoutputs excent REN RC.INT | 800 | [Tren wcony OT t00 [Tigr —ewiever output cuenta =55 110 electrical characteristics over full range of recommended operating conditions [—aramerer TEST CONDITIONS min tye max | unit | ‘Al outputs except High tevel Ion = ~400 wa Vou out it ra acer [owt v pervenese [REN Cony | lon= —TOOWA TT [Wor towieveroutputvorage | ious ama | OV Vee = 5.25V. vi = Ves Vee [0a Voc =8.25V.Vo=24V [20 Ta] loz Off it eur oz _ OM state ouput covert [ice Vee supply curent ec 828V 200 mA | Cj Input capacitance (any input)! f= 1 MHz all omher ‘ pa yin pins at 0 V Parameter guaranteed via characterization data, —_—_ Eee TEXAS 4% INSTRUMENTS POST OFFICE BOX 1443 @ HOUSTON, TEXAS 77001 14-315

‘Parameter guaranteed via characterization data. FIGURE 3. TEST LOAD CIRCUITS

a twos —el wiry —ol | fete; read cycle timing Bn } \\ ‘talCE) fete) ef OE 7 | - | ' esac} 1 tacen-0z—f-—o4 t RSO-RS2 x VALID ADDRESS ee TEXAS 4% INSTRUMENTS 14-318 POST OFFICE BOX 1443 @ HOUSTON, TEXAS 77001

be—thicer—o| ferwwer| i} WE \\! i 1 fe toice a | a \\ if feeessuioam | feb osm paw \\ | \\ } bee} taut) fe tniani-t teuDAY trial 00.07 NOTE 2: thiap} and thio) are shown measured from the rising edge of WE. This is the correct reference point in this figure, since the measurements should be from the rising edge of WE or CE — whichever comes first. DMA read operation KCCrG \\ } fe taicat rane l 1 pa r\\ | / a a we 1 wey { \\ note 3 Io to DO-D7 1 1 }e—tatDeiny—>y pt cine 0z) memory and need not be suppressed at the SMJ8914A, am TEXAS 4% INSTRUMENTS POST OFFICE BOX 1443 @ HOUSTON. TEXAS 77001 14-319

WE \\! } H 1 KCCGR \\ t l } fe teutoein) > Fe nom) 9 084 pein rot I rel! fe su(08)' 44th) —of be—tsuiDa)' 1 Pr uar tesa" 0.07 ; DATA ‘teuiDA}end thiDa are only applicable to the first signal to become inactive, whether it is WE or ACCOR source handshake timing characteristics over full range of operating conditions (see Note 4) PARAMETER TEST CONDITIONS [mn wax | unre | Dalay of DAV true from end Normal Ty (see Note 5) Tei Tiel + 310] ns | ta1 of write operation to Short Ty (see Note 5) Beit sig + 310 | ns | dota out register [Wey short Ty ieee Nowe 5) | eit sie + S10 | ns_| Delay of valid GPIB t42 data lines from end of 140 '43__Delay of BO interrupt rom DAC wue [BO interrupt unmasked «0 | ns t4a___Delay of ACCRG DAC true [a0 rs] tg§ Delay of DAV Talse from OAC wwe [160 Ss] NOTES: 4. The timing of the source handshake is the same whether ATN is true o false: i-e., whether the device isin TACS, CACS, or SPAS. 5.A very short bus settling time (T) occurs on the second and subsequent data byte when ATN is false ifthe “vstd1” feature is set. A slightly longer bus settling time takes place it "std" is set unless there is @ very short bus settling time. In all other TEXAS 4p INSTRUMENTS 14-320 POST OFFICE BOX 1443 @ HOUSTON, TEXAS 77001

LL , acceptor handshake timing characteristics over full range of operating conditions PARAMETER TEST CONDITIONS [ww max | une | Bi interrupt unmasked. Jay of Bi interrupt wyo ERY ft tern ATN = false, apt 2g +418 " ue device in LACS Delay of ACCRO from ATN = false, 2)? 2p)! + 290 ‘7 OAV true device is in LACS io ial Delay of NDAC Tolse ATN = false,

1 Beit + aa

. Delay ot . ‘D false fror ATN © false, 220 ns ‘39 end of read operation device is in LACS of Data-n register BIN = tase, Delay of interface gerige Wot in CACS 5 message inter Dot ae + 418 ‘10 sage interupt message interrupts ° ° from DAV true {except UNC) UNC interrupt only ser sens ais | as _| ‘IN = woe, Delay of NDAC fa tat ley 0 false device not in CACS, Tet Tiey + 415 from DAV true no DAC holdott Delay of NDAC false ta12 trom end of write 230 | ns Delay of NAFD false RIN = woe, 13 180 from DAV false device not in CACS NOTE 6: The interrupts generated by interface messages are shown in Table 3-15 of the TMS9914A General Purpose interface Bus (GPIB) Controller Data Manual (MPO33A1. ATN, EOI, and IFC timing characteristics over full range of operating conditions PARAMETER TEST CONDITIONS [mm max | unit | Taia Delay of NDAG true from ATN te Device is not in CACS 8 | ta15 Delay of TE high from EOI troe Device is not in CACS | tg16 Delay of valid data from EOI true Device is not in CACS rf — 140 [as | 1gi7 Delay of TE low from EOI false Device 1s not in CACS [25 | ns | tdi8 Delay of NAFD true from ATN false Device is in LADSILACS [0 | ns] tara Response time 19 FC a 6 300) | ns TEXAS % INSTRUMENTS POST OFFICE BOX 1443 @ HOUSTON. TEXAS 7001 14-321

controller timing characteristics over full range of operating conditions PARAMETER TEST CONDITIONS [wn wax | uw Delay of ATN tue t420_ from end of tea Bicio) 101611 + 220 Delay of BO interrupt tg21 from end of tea T8tc(0) —-221@)1 + 415 Delay of ATN woe 80 unmasked, rom end of tower + 22 1622 _ from end of tes device is in ANRS Btcior Ore ° Delay of 80 inter 23 device is in ANRS 101 , Delay of EOI true Wom 26 'pp auxiliary command set t Delay of EO! false from 425 pp auxiliary command set Delay of BO interrupt from rpp BO unmasked Bie) T0W@NT + 415 ‘426 auxiliary command cleared 0 unmaske et) i Delay of ATN false from 1427 lay of ATN false fror Device is not in SDYS or STRS 210 ats auxiliary command ee TEXAS 4 INSTRUMENTS 14-322 POST OFFICE BOX 1443 @ HOUSTON. TEXAS 7007

SMJ9914A source and acceptor handshake timing(s) cE \\ / we YS! — ote pI08.0101 i s 1 ° tt 4 wo | __ ¢ | Letas-of (SEE NOTE 7) € ry Accra afi oy ! | ! tot toa AecGR \\ / I Dav i | roe | ape pet | Noac 1 Fr \\ 1 A I I c — r ened int \\ /\\ 5 fe-tus->] (SEE NOTE 8) 1 T ACCRO. 1 ' ° a a R a | ee er aACCGR / cE \\ 4 NOTES: 7. The interrupt jine is taker: low by @ BO interrupt. 8. The interrupt line is taken low by a BI interrupt. el TEXAS 2 INSTRUMENTS POST OFFICE BOX 1443 @ HOUSTON. TEXAS 77001 14-323

SMJ9914A acceptor handshake timing ‘‘ATN’’ true s DIOB-DIO1 x ° 108-0! u R c E pay \\ F fi le 13> NRED t \\ a b-— 1911 5} ot a2 a NDAC | Fee note 9)| 7 \\ c E | | P T int i) i o t ! R be ta10—4 I = I cE | we \\ FF READ INTERRUPT WRITE dacr TO STATUS AUXILIARY COMMAND REGISTER NOTE 9: The broken line shows the waveform if there is no DAC holdoff. The solid lines assume there is a DAC holdoff. TEXAS % INSTRUMENTS 14-324 POST OFFICE BOX 1443 @ HOUSTON, TEXAS 77007

SMJ9914A response to ‘ATN’ and ‘EOI’ | i Eo! | \\ f I \\ | | | pst 1 | | -—-*" a \\ ' 1 | ] | tate tse nore 10 NNRFD | 1 \\ J | \\ }

1 Hi-Z

| | Lewes I ; Hz NDAC \\ i / “™\\ Of erbtare | | av 1-7 —HZ 1 fh as jl ors9 ire (SEE NOTE 1) \\ | int \\ NOTES: 10. This assumes that an RFD holdoff occurs 11. IFC causos the SMJ9914A to be unaddressed and an IFC interrupt occurs. i TEXAS % INSTRUMENTS POST OFFICE BOX 1443 @ HOUSTON, TEXAS 77001 14-325

SMJ9914A controller timing ‘a2r-—| ATN \\ | } Rr ta20, 422 tas | £01 1 \\ wa (SEE td24 (SEE. int | \\ / t | \\ I pees 423 i] Bote | = f f | I 1 | we VF VWI VPS Write READ INT Ser CLEAR WRITE tes oF tea STATO pp pp gts NOTE 12: A BO interrupt accurs as the SMJ9914A enters CACS. TEXAS 4 INSTRUMENTS 14-326 POST OFFICE BOX 1443 @ HOUSTON. TEXAS 77001