SMJ626162

SMJ626162 TI | Alldatasheet

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524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SGMS737C – JULY 1997 – REVISED MARCH 1999 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization 512K × 16 Bits × 2 Banks /C00683.3-V Power Supply (±5% Tolerance) /C0068Two Banks for On-Chip Interleaving (Gapless Accesses) /C0068High Bandwidth – Up to 83-MHz Data Rates /C0068Read Latency Programmable to 2 or 3 Cycles From Column-Address Entry /C0068Burst Sequence Programmable to Serial or Interleave /C0068Burst Length Programmable to 1, 2, 4, 8, or 256 (Full Page) /C0068Chip Select and Clock Enable for Enhanced System Interfacing /C0068Cycle-by-Cycle DQ-Bus Mask Capability With Upper- and Lower-Byte Control /C0068Autorefresh Capability /C00684K Refresh (Total for Both Banks) /C0068High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface /C0068Power-Down Mode /C0068Pipeline Architecture /C0068Temperature Ranges: Operating, – 55°C to 125°C Storage, – 65°C to 150°C /C0068Performance Ranges: SYNCHRONOUS ACCESS TIME REFRESH CLOCK CYCLE CLOCK TO TIME TIME OUTPUT INTERVAL tCK tAC tREF (MIN)/C0123 (MIN)/C0123 (MAX) ’626162-12 12 ns 8ns 32ms ’626162-15 15 ns 9ns 32ms ’626162-20 20 ns 10ns 32ms † Read latency = 3

description

The SMJ626162 series of devices are 16777216-bit synchronous dynamic random- access memory (SDRAM) devices organized as two banks of 524288 words with 16 bits per word. All inputs and outputs of the SMJ626162 series are compatible with the LVTTL interface. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PIN NOMENCLATURE A[0:10] Address Inputs A0–A10 Row Addresses A0–A7 Column Addresses A10 Automatic-Precharge Select A11 Bank Select CAS Column-Address Strobe CKE Clock Enable CLK System Clock CS Chip Select DQ[0:15] SDRAM Data Input/Data Output DQML, DQMU Data-Input/Data-Output Mask Enable NC No Connect RAS Row-Address Strobe VCC Power Supply (3.3-V Typical) VCCQ Power Supply for Output Drivers (3.3-V Typical) VSS Ground VSSQ Ground for Output Drivers W Write Enable VSS DQ15 DQ14 VSSQ DQ13 DQ12 V CCQ DQ11 DQ10 VSSQ DQ9 DQ8 V CCQ NC DQMU CLK CKE NC V SS VCC DQ0 DQ1 VSSQ DQ2 DQ3 V CCQ DQ4 DQ5 VSSQ DQ6 DQ7 V CCQ DQML W CAS RAS CS A11 A10 V CC HKD PACKAGE (TOP VIEW) Copyright  1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

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description (continued) The SDRAM employs state-of-the-art technology for high performance, reliability, and low power requirements. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches. The SMJ626162 SDRAM is available in a 50-lead, 650-mil-wide ceramic dual flatpack (HKD suffix). functional block diagram CLK CKE CS DQMx RAS CAS W A0–A11 AND Control Mode Register Array Bank T Array Bank B DQ Buffer DQ0–DQ15 operation All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs, DQ0–DQ15, are also referenced to the rising edge of CLK. The ’626162 has two banks that are accessed independently; however, a bank must be activated before it can be accessed (read from or written to). Refresh cycles refresh both banks alternately. Five basic commands or functions control most operations of the ’626162: /C0068Bank-activate/row-address entry /C0068Column-address entry/write operation /C0068Column-address entry/read operation /C0068Bank-deactivate /C0068Autorefresh Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or gate) the CLK input. The device contains a mode register that must be programmed for proper operation. Table 1, Table 2, and Table 3 show the various operations that are available on the ’626162. These truth tables identify the command and/or operations and their respective mnemonics. Each truth table is followed by a legend that explains the abbreviated symbols. An access operation refers to any read or write command in progress at cycle n. Access operations include the cycle upon which the read or write command is entered and all subsequent cycles through the completion of the access burst.

Table 1. Basic Command Truth Table† – tCES and nCLE must be satisfied for clock-suspend exit. DQMx (n) is irrelevant. ‡ Autorefresh entry requires that all banks be deactivated or be in an idle state prior to the command entry.

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Table 2. Clock-Enable (CKE) Command Truth Table† † For execution of these commands, A0–A11 (n) and DQMx (n) are don’t care entries. ‡ On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode. either a DESL or a NOOP command must be applied before any other command.

Table 3. Data Mask (DQM) Command Truth Table† – tCES and nCLE must be satisfied for clock-suspend exit. (n), RAS(n), CAS(n), W(n), and A0–A11 are irrelevant.

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until the next read access is initiated. Table 4. 2-Bit Burst Sequences Table 5. 4-Bit Burst Sequences

Table 6. 8-Bit Burst Sequences the contents of the mode register. The ’626162 contains two independent banks that can be accessed individually or in an interleaved fashion. low, CAS high, W high, and A11 valid on the rising edge of CLK. Table 1 and the section on bank deactivation).

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two-bank row-access operation The two-bank feature allows access of information on random rows at a higher rate of operation than is possible with a standard DRAM. This is accomplished by activating one bank with a row address and, while the data stream is being accessed to/from that bank, activating the second bank with another row address. When the data stream to/from the first bank is complete, the data stream to/from the second bank can begin without interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next round of accesses. In this manner, operation can continue in an interleaved fashion. Figure 25 is an example of two-bank, row-interleaving, read bursts with automatic deactivate for a read latency of 3 and a burst length of 8. two-bank column-access operation The availability of two banks allows the access of data from random starting columns between banks at a higher rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate read or write commands between the banks to provide gapless accesses at the CLK frequency, provided all specified timing requirements are met. Figure 26 is an example of two-bank, column-interleaving, read bursts for a read latency of 3 and a burst length of 2. bank deactivation (precharge) Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB command except that A10 must be low and A11 is used to select the bank to be precharged as shown in Table 1. A bank can also be deactivated automatically by using A10 during a read or write command. If A10 is held high during the entry of a read or write command, the accessed bank (selected by A11) is deactivated automatically upon completion of the access burst. If A10 is held low during the entry of a read or write command, that bank remains active following the burst. The read and write commands with automatic deactivation are denoted as READ-P and WRT-P . chip select (CS) CS can be used to select or deselect the ’626162 for command entry, which might be required for multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not respond to RAS, CAS, or W until the device is selected again. Device select is accomplished by holding CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). The use of CS does not affect an access burst that is in progress; the DESL command can restrict only RAS, CAS, and W input to the ’626162. data mask The mask command, or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a cycle-by-cycle basis to gate any individual data cycle within a read burst or a write burst. DQML controls DQ0–DQ7, and DQMU controls DQ8–DQ15. The application of DQMx to a write burst has no latency DID = 0 cycle), but the application of DQMx to a read burst has a latency of nDOD = 2 cycles. During a write burst, if DQMx is held high on the rising edge of CLK, the data-input is ignored on that cycle. During a read burst, if DQMx is held high on the rising edge of CLK, then n DOD cycles after the rising edge of CLK, the data-output will be in the high-impedance state. Figure 16, Figure 29, Figure 30, Figure 31, and Figure 32 show examples of data-mask operations.

† All other combinations are reserved. ‡ See the timing requirements for minimum valid read latencies based on maximum frequency rating. Figure 1. Mode-Register Programming

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placed in suspension, beginning with the second rising edge of CLK after CKE returns high. If CKE is brought low when no read or write command is in progress, the device enters the power-down mode. WRT-P operation is not supported. Table 7. Read-Burst Interruption and new output cycles begin (see Figure 2). (nCCD +1), assuming that there is any output on these cycles (see Figure 3). occurs first (see Figure 4). NOTE A: For this example, assume read latency = 3 and burst length = 4. Figure 2. Read Burst Interrupted by Read Command

NOTES: A. For this example, assume read latency = 3 and burst length = 4. B. DQMx must be high to mask output of the read burst on cycles (nCCD – 1), nCCD , and (nCDD + 1). Figure 3. Read Burst Interrupted by Write Command NOTE A: For this example, assume read latency = 3 and burst length = 4. Figure 4. Read Burst Interrupted by DEAC Command Table 8. Write-Burst Interruption READ, READ-P Data that was input on the previous cycle is written; no further data inputs are accepted (see Figure 5).

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NOTE A: For this example, assume read latency = 3 and burst length = 4. Figure 5. Write Burst Interrupted by Read Command NOTE A: For this example, assume burst length = 4. Figure 6. Write Burst Interrupted by Write Command NOTE A: For this example, assume burst length = 4. Figure 7. Write Burst Interrupted by DEAC/DCAB Command

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SGMS737C – JULY 1997 – REVISED MARCH 1999 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 power up Device initialization should be performed after a power up to the full VCC level; however, after power is established, a 200-ms interval is required (with no inputs other than CLK). After this interval, both banks of the device must be deactivated. Eight REFR commands must be performed and the mode register must be set to complete the device initialization.

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absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 3.135 3.3 3.465 V VCCQ Supply voltage for output drivers‡ 3.135 3.3 3.465 V VSS Supply voltage 0 V VSSQ Supply voltage for output drivers 0 V VIH High-level input voltage 2 VCC + 0.3 V VIL Low-level input voltage – 0.3 0.8 V TA Ambient temperature –55 125 °C ‡ VCCQ /C0118 VCC + 0.3 V

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SGMS737C – JULY 1997 – REVISED MARCH 1999 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS ’626162-12 ’626162-15 ’626162-20 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = –2 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 0.4 V II Input current (leakage)

0 V ≤ VI ≤ VCC ,

All other pins = 0 V to VCC ±10 ±10 ±10 mA IO Output current (leakage) 0 V ≤ VO ≤ VCCQ , Output disabled ±10 ±10 ±10 mA ICC1 Average read or Burst length = 1, tRC ≥ tRC MIN, IOH /IOL =0m A Read latency = 2 85 75 70 mAICC1 g write current IOH /IOL = 0 mA , One bank activated (see Note 3) Read latency = 3 100 95 85 mA ICC2P Precharge standby CKE ≤ VIL MAX, t CK = MIN (see Note 4) 2 2 2 ICC2PS gy current in power-down mode CKE and CLK /C0118 VIL MAX, tCK = ∞ (see Note 5) 2 2 2 mA ICC2N Precharge standby current in CKE ≥ VIH MIN, t CK = MIN (see Note 4) 40 35 30 ICC2NS current in nonpower-down mode CKE ≥ VIH MIN, CLK ≤ VIL MAX, tCK = ∞ (see Note 5) 2 2 2 mA ICC3P Active standby current in CKE ≤ VIL MAX, t CK = MIN One bank activated (see Note 4) 10 10 10 mA ICC3PS current in power-down mode CKE and CLK ≤ VILMAX, t CK = ∞ One bank activated (see Note 5) 10 10 10 mA ICC3N Active standby current in CKE ≥ VIH MIN, t CK = MIN One bank activated (see Note 4) 55 45 40 mA ICC3NS nonpower-down mode CKE ≥ VIH MIN, CLK ≤ VIL MAX, tCK = ∞ , One bank activated (see Note 5) 15 15 15 mA ICC4 Burst current Continuous burst, IOH /IOL = 0 mA, All banks activated Read latency = 2 165 130 110 mAICC4 Burst current All banks activated, nCCD = one cycle (see Note 6) Read latency = 3 210 175 150 mA ICC5 Autorefresh tRC ≥ tRC MIN Read latency = 2 120 100 80 mAICC5 Autorefresh tRC ≥ tRC MIN Read latency = 3 120 100 80 mA NOTES: 2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 3. Control and address inputs change state twice during tRC . 4. Control and address inputs change state once every 2 × tCK . 5. Control and address inputs do not change state (stable). 6. Control and address inputs change state once every cycle.

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capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 7) PARAMETER MIN MAX UNIT C i(S) Input capacitance, CLK input 8 pF C i(AC) Input capacitance, address and control inputs: A0–A11, CS, DQMx, RAS, CAS, W 8 pF C i(E) Input capacitance, CKE input 8 pF C o Output capacitance 10 pF NOTE 7: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25°C with a 1-MHz signal applied to the pin under test. All other pins are open. ac timing requirements†‡ ’626162-12 ’626162-15 ’626162-20 UNIT MIN MAX MIN MAX MIN MAX UNIT tCK Cycle time CLK (system clock) Read latency = 2 15 20 30 nstCK C ycle time, CLK (system clock) Read latency = 3 12 15 20 ns tCKH Pulse duration, CLK (system clock) high 4 4 4 ns tCKL Pulse duration, CLK (system clock) low 4 4 4 ns tAC Access time, CLK ↑ to data out Read latency = 2 9 15 20 nstAC (see Note 8) Read latency = 3 8 9 10 ns tLZ Delay time, CLK to DQ in the low-impedance state (see Note 9)0 0 0 ns tHZ Delay time, CLK to DQ in the Read latency = 2 8 14 15 nstHZ high-impedance state (see Note 10) Read latency = 3 8 11 12 ns tDS Setup time, data input 3 4 4 ns tAS Setup time, address 3 4 4 ns tCS Setup time, control input (CS, RAS, CAS, W, DQMx) 3 4 4 ns tCES Setup time, CKE (suspend entry/exit, power-down entry) 3 4 4 ns tCESP Setup time, CKE (power-down/self-refresh exit) (see Note 11)10 10 10 ns tOH Hold time, CLK ↑ to data out 1.5 2 2 ns tDH Hold time, data input 2 2 2 ns tAH Hold time, address 2 2 2 ns tCH Hold time, control input (CS, RAS, CAS, W, DQMx) 2 2 2 ns tCEH Hold time, CKE 2 2 2 ns tRC REFR command to ACTV, MRS, or REFR command; ACTV command to ACTV, MRS, or REFR command 96 120 160 ns tRAS ACTV command to DEAC or DCAB command 60 100 000 75 100 000 100 100 000 ns tRCD ACTV command to READ or WRT command (see Note 12) 24 30 40 ns tRP DEAC or DCAB command to ACTV, MRS, or REFR command 36 45 60 ns † See Parameter Measurement Information for load circuits. ‡ All references are made to the rising transition of CLK unless otherwise noted. NOTES: 8. t AC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced from the rising transition of CLK that is one cycle before read latency for the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CLK that is one cycle before read latency for the READ command. 10. tHZ (MAX) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. See Figure 18. 12. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS .

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SGMS737C – JULY 1997 – REVISED MARCH 1999 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ac timing requirements†‡ (continued) ’626162-12 ’626162-15 ’626162-20 UNIT MIN MAX MIN MAX MIN MAX UNIT tAPR Final data out of READ-P operation to ACTV, MRS, or REFR command tRP + (nEP × tCK ) ns tAPW Final data in of WRT-P operation to ACTV, MRS, or REFR command tRP + tCK ns tRWL Final data in to DEAC or DCAB command 24 30 40 ns tRRD ACTV command for one bank to ACTV command for the other bank24 30 40 ns tT Transition time, all inputs (see Note 13) 1 5 1 5 1 5 ns tREF Refresh interval 32 32 32 ms † See Parameter Measurement Information for load circuits. ‡ All references are made to the rising transition of CLK unless otherwise noted. NOTE 13: Transition time (rise and fall) should be a minimum of 1 ns and a maximum of 5 ns measured between VIH MIN and VIL MAX. This is ensured by design but not tested. clock timing requirements‡§ ’626162-12 ’626162-15 ’626162-20 UNIT§ MIN MAX MIN MAX MIN MAX UNIT§ nEP Final data out to DEAC or Read latency = 2 –1 –1 –1 cyclesnEP DCAB command Read latency = 3 –2 –2 –2 cycles nHZP DEAC or DCAB interrupt of data out burst to DQ in the Read latency = 2 2 2 2 cyclesnHZP data-out burst to DQ in the high-impedance state Read latency = 3 3 3 3 cycles nCCD READ or WRT command to interrupting READ, WRT, DEAC, or DCAB command 1 1 1 cycles nCWL Final data in to READ or WRT command in either bank 1 1 1 cycles nWCD WRT command to first data in 0 0 0 0 0 0 cycles nDID ENBL or MASK command to data in 0 0 0 0 0 0 cycles nDOD ENBL or MASK command to data out 2 2 2 2 2 2 cycles nCLE HOLD command to suspended CLK edge; HOLD operation exit to entry of any command 1 1 1 1 1 1 cycles nRSA MRS command to ACTV, REFR, or MRS command 2 2 2 cycles nCDD DESL command to control input inhibit 0 0 0 0 0 0 cycles ‡ All references are made to the rising transition of CLK unless otherwise noted. § A CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CLK cycles occurring during the time when CKE is asserted low).

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specified as consecutive commands for the same bank unless otherwise noted. hardware for output impedance matching purposes. Figure 8. LVTTL-Load Circuit Figure 9. Input-Attribute Parameters

Figure 10. Output Parameters Figure 11. Command-to-Command Parameters

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NOTE A: For this example, assume read latency = 3 and burst length = 4. Figure 12. Read Followed by Deactivate NOTE A: For this example, assume read latency = 3 and burst length = 1. Figure 13. Read With Auto-Deactivate NOTE A: For this example, assume burst length = 1. Figure 14. Write Followed By Deactivate

Figure 15. Write With Auto-Deactivate NOTE A: For this example, assume read latency = 3 and burst length = 4. Figure 16. DQ Masking

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Figure 17. CLK-Suspend Operation

Figure 18. Power-Down Operation

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† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5). NOTE A: This example illustrates minimum tRCD and nEP for the ’626162-15 at 66 MHz. Figure 19. Read Burst (read latency = 3, burst length = 4)

† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6). NOTE A: This example illustrates minimum tRCD and tRWL for the ’626162-15 at 66 MHz. Figure 20. Write Burst (burst length = 8)

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† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4). NOTE A: This example illustrates minimum tRCD and nEP for the ’626162-15 at 66 MHz. Figure 21. Write-Read Burst (read latency = 3, burst length = 2)

† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz. Figure 22. Read-Write Burst With Automatic Deactivate (read latency = 3, burst length = 8)

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† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz. Figure 23. Read Burst – Single Write With Automatic Deactivate (read latency = 3, burst length = 8)

(D/Q) (B/T) ADDR a b c d e f g h i j k l m nopqr s . . † Column-address sequence depends on programmed burst type and starting column address C0. NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz. Figure 24. Read Burst – Full Page (read latency = 3, burst length = 256)

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(D/Q) (B/T) ADDR a b c d e f g h i j k l m nopqr s . . † Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6). NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz. Figure 25. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8)

† Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 4). Figure 26. Two-Bank Column-Interleaving Read Bursts (read latency = 3, burst length = 2)

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NOTE A: This example illustrates minimum tRCD , nEP, and tRWL for the ’626162-15 at 66 MHz. Figure 27. Read-Burst Bank B, Write-Burst Bank T (read latency = 3, burst length = 4)

† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum nCWL for the ’626162-15 at 66 MHz. Figure 28. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (read latency = 3, burst length = 4)

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† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz. Figure 29. Data Mask (read latency = 3, burst length = 4)

† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4). Figure 30. Data Mask With Byte Control (read latency = 3, burst length = 2)

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† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD and nEP read burst, and a minimum tRWL write burst for the ’626162-15 at 66 MHz. Figure 31. Data Mask With Byte Control (read latency = 3, burst length = 4)

† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD and tRWL for the ’626162-15 at 66 MHz. Figure 32. Data Mask With Cycle-by-Cycle Byte Control (read latency = 3, burst length = 4)

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† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5). NOTE A: This example illustrates minimuim tRC , tRCD , and nEP for the ’626162-15 at 66 MHz. Figure 33. Refresh Cycles (read latency = 3, burst length = 4)

† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5). NOTES: A. This example illustrates minimum tRP , nRSA , and tRCD for the ’626162-15 at 66 MHz. Figure 34. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)

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† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). Figure 35. CLK Suspend (HOLD) During Read Burst and Write Burst (read latency = 3, burst length = 4)

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SGMS737C – JULY 1997 – REVISED MARCH 1999 41POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA HKD (R-CDFP-F50) CERAMIC DUAL FLATPACK 0.250 (6,35) 0.370 (9,40) 0.012 (0,30) 0.020 (0,50) Lid 4081537/B 10/95 0.026 (0,66) MIN 0.843 (21,40) 0.811 (20,60) 0.015 (0,38) MIN (4 Places) 0.766 (19,45) 0.746 (18,95) 0.110 (2,80) 0.140 (3,55) 0.004 (0,10) 0.587 (14,90) 0.555 (14,10) 0.634 (16,10) 0.665 (16,90) 0.031 (0,80) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. The leads will be gold plated.

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