SMJ55161 TI | Alldatasheet
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Technical content
ta(R) (MAX) ta(SQ) (MAX) tc(W) (MIN) SMJ55161-75 80 ns 25 ns 150 nsSMJ55161-80 75 ns 23 ns 140 ns tc(P) (MIN) tc(SC) (MIN) ICC1 (MAX) ICC1A (MAX) 50 ns 30 ns 160 mA 195 mA 48 ns 24 ns 165 mA 210 mA ROW ENABLE SERIAL DATA CYCLE TIME PAGE MODE CYCLE TIME SERIAL PORT STAND- BY SERIAL PORT AC- TIVE ACCESS TIME ACCESS TIME DRAM DRAM SERIAL OPERATING CURRENT OPERATING CURRENT SMJ55161
262144 BY 16-BIT
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization: – DRAM: 262 144 by 16 Bits – SAM: 256 by 16 Bits /C0068Dual-Port Accessibility – Simultaneous and Asynchronous Access From the DRAM and SAM Ports /C0068Data-Transfer Function From the DRAM to the Serial-Data Register /C0068(4 × 4) × 4 Block-Write Feature for Fast Area-Fill Operations; as Many as Four Memory-Address Locations Written Per Cycle From the 16-Bit On-Chip Color Register /C0068Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design /C0068Byte-Write Control (CASL, CASU) Provides Flexibility /C0068Extended Data Output for Faster System Cycle Time /C0068Enhanced Page-Mode Operation for Faster Access /C0068CAS -Before-RAS (CBR) and Hidden-Refresh Modes /C0068Long Refresh Period Every 8 ms (Maximum) /C0068Up to 45-MHz Uninterrupted Serial-Data Streams /C0068256 Selectable Serial-Register Starting Locations /C0068SE -Controlled Register-Status QSF /C0068Split-Register-Transfer Read for Simplified Real-Time Register Load /C0068Performance Ranges: /C0068Programmable Split-Register Stop Point /C00683-State Serial Outputs Allow Easy Multiplexing of Video-Data Streams /C0068All Inputs/Outputs and Clocks TTL Compatible /C0068Compatible With JEDEC Standards /C0068Designed to Work With the Texas Instruments Graphics Family TRG SC SE VSS SQ15 DQ15 SQ14 DQ14 VCC SQ13 DQ13 SQ12 DQ12 VSS SQ11 DQ11 SQ10 DQ10 VCC SQ9 DQ9 SQ8 DQ8 DSF VSS NC / GND CASU QSF VSS VCC VSS SQ0 DQ0 SQ1 DQ1 VCC SQ2 DQ2 SQ3 DQ3 VSS SQ4 DQ4 SQ5 DQ5 VCC SQ6 DQ6 SQ7 DQ7 VSS CASL WE RAS VCC HKC PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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J H G F E D C B A GB PACKAGE (BOTTOM VIEW) PIN NOMENCLATURE A0–A8 Address Inputs CASL , CASU Column-Address Strobe/Byte Selects DQ0 –DQ15 DRAM Data I/O, Write Mask Data DSF Special-Function Select NC/GND No Connect/Ground (Important: Not connected internally to VSS ) QSF Special-Function Output RAS Row-Address Strobe SC Serial Clock SE Serial Enable SQ0–SQ15 Serial-Data Output TRG Output Enable, Transfer Select VCC 5-V Supply (TYP) VSS Ground WE DRAM Write-Enable Select
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PIN PIN PIN PIN PIN PIN PIN PIN PIN J1 DQ1 J2 SQ3 J3 DQ3 J4 DQ4 J5 DQ5 J6 DQ6 J7 SQ7 J8 CASL J9 A8 H1 DQ0 H2 SQ2 H3 DQ2 H4 SQ4 H5 SQ5 H6 SQ6 H7 DQ7 H8 WE H9 A7 G1 SQ0 G2 SQ1 G3 VDD2 G4 VSS2 G6 VDD2 G7 VSS2 G8 RAS G9 A6 F1 TRG F2 VSS1 F3 VDD1 F7 VDD1 F8 VDD1 F9 A5 E1 SC E2 VDD1 E8 VSS1 E9 A4 D1 SE D2 VSS1 D3 VDD1 D7 VSS1 D8 A3 D9 A2 C1 SQ15 C2 VSS1 C3 VDD2 C4 VSS2 C6 VDD2 C7 VSS2 C8 CASU C9 A1 B1 DQ15 B2 DQ14 B3 DQ13 B4 DQ12 B5 DQ11 B6 DQ10 B7 SQ8 B8 DSF B9 A0 A1 SQ14 A2 SQ13 A3 SQ12 A4 SQ11 A5 SQ10 A6 SQ9 A7 DQ9 A8 DQ8 A9 QSF PIN PIN PIN PIN PIN PIN A0 B9 DQ1 J1 DQ12 B4 SQ2 H2 SQ13 A2 VDD2 G6 A1 C9 DQ2 H3 DQ13 B3 SQ3 J2 SQ14 A1 VDD2 C6 A2 D9 DQ3 J3 DQ14 B2 SQ4 H4 SQ15 C1 VSS1 F2 A3 D8 DQ4 J4 DQ15 B1 SQ5 H5 TRG F1 VSS1 D2 A4 E9 DQ5 J5 DSF B8 SQ6 H6 VDD1 E2 VSS1 C2 A5 F9 DQ6 J6 QSF A9 SQ7 J7 VDD1 F3 VSS1 D7 A6 G9 DQ7 H7 RAS G8 SQ8 B7 VDD1 D3 VSS1 E8 A7 H9 DQ8 A8 SC E1 SQ9 A6 VDD1 F7 VSS2 G4 A8 J9 DQ9 A7 SE D1 SQ10 A5 VDD1 F8 VSS2 C4 CASL J8 DQ10 B6 SQ0 G1 SQ11 A4 VDD2 G3 VSS2 G7 CASU C8 DQ11 B5 SQ1 G2 SQ12 A3 VDD2 C3 VSS2 C7 DQ0 H1 WE H8
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description
The SMJ55161 multiport-video random-access memory (RAM) is a high-speed, dual-port memory device. It consists of a dynamic RAM (DRAM) module organized as 262 144 words of 16 bits each interfaced to a serial-data register (serial-access memory [SAM]) organized as 256 words of 16 bits each. The SMJ55161 supports three basic types of operation: random access to and from the DRAM, serial access from the serial register, and transfer of data from any row in the DRAM to the serial register. Except during transfer operations, the SMJ55161 can be accessed simultaneously and asynchronously from the DRAM and SAM ports. The SMJ55161 is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel-draw rates are achieved by the device’s (4 × 4) × 4 block-write feature. The block-write mode allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent column-address locations. As many as 64 bits of data can be written to memory during each CAS cycle time. Also, on the DRAM port, a write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles without reloading. The SMJ55161 also offers byte control which can be applied in read cycles, write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The SMJ55161 also offers extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and standard DRAM cycles. The SMJ55161 offers a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port) that enables real-time-register-load implementation for continuous serial-data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time register load (for example, loads done during CRT-retrace periods), the full-register mode of operation is retained to simplify system design. The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up to 45 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active. All inputs, outputs, and clock signals on the SMJ55161 are compatible with Series 74 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility. The SMJ55161 is offered in a 68-pin ceramic pin-grid-array package (GB suffix) and a 64-pin ceramic flatpack (HKC suffix). The SMJ55161 and other TI multiport-video RAMs are supported by a broad line of graphic processors and control devices from TI. See Table 2 and Table 4 for additional information.
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Split- Register Status Serial- Address Counter DRAM Output Buffer DRAM Input Buffer Input Buffer Row Buffer Column Buffer DQ0– DQ15 A0–A8 DSF 1 of 4 Subblocks (see next page) 1 of 4 Subblocks (see next page) 1 of 4 Subblocks (see next page) 1 of 4 Subblocks (see next page) QSF SERAS CASx WE TRG Special- Function Logic Refresh Counter Serial- Output Buffer Timing Generator SQ0– SQ15 SC SE
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functional block diagram (continued) SE 1 of 4 Subblocks Refresh Counter Row Decoder Split- Register Status Serial- Address Counter Color Register Address Mask W/B Latch W/B UnlatchMUX Write- Per-Bit Control Serial-Data Pointer Serial-Data Register 512 × 512 Memory Array Sense AMP Column DEC Special- Function Logic Input Buffer DQi DQi+1 DQi+2 DQi+3 RAS CASx TRG WE Column Buffer A0–A8 DSF Row Buffer QSF DRAM Output Buffer DRAM Input Buffer Timing Generator SQi SQi + 1 SQi +2 SQi + 3 Serial- Output Buffer SE SC
Table 1 lists the DRAM and SAM functions, summarizing Table 3 and Table 4. Table 1. DRAM and SAM Functions or the falling edge of WE, whichever occurs later. ‡ Logic L is selected when either or both CASL and CASU are low. § The column address and block address are latched on the first falling edge of CASx. ¶ CBRS cycle should be performed immediately after the powerup initialization cycle. ||CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. /C0107CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
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Table 2. Pin Description Versus Operational Mode † For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground. stable on or before the falling edge of RAS and the first falling edge of CASx. within the SAM. Locations 127 and 255 are not valid tap points. the chip to invoke DRAM and transfer-read functions of the SMJ55161.
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 column-address strobe (CASL, CASU) CASL and CASU are control inputs that latch the states of the column address and DSF to control DRAM and transfer functions of the SMJ55161. CASx also acts as output enable for the DRAM output pins DQ0–DQ15. In DRAM operation, CASL enables data to be written to or read from the lower byte (DQ0–DQ7), and CASU enables data to be written to or from the upper byte (DQ8–DQ15). In transfer operations, address bits A0–A8 are latched at the first falling edge of CASx as the start position (tap) for the serial-data output (SQ0–SQ15). output enable/transfer select (TRG) TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0–DQ15. For transfer operation, TRG must be brought low before RAS falls. write-mask select, write enable (WE) In DRAM operation, WE enables data to be written to the DRAM. WE is also used to select the DRAM write-per-bit mode. Holding WE low on the falling edge of RAS invokes the write-per-bit operation. The SMJ55161 supports both the nonpersistent write-per-bit mode and the persistent write-per-bit mode. special-function select (DSF) The DSF input is latched on the falling edge of RAS or the first falling edge of CASx, similar to an address. DSF determines which of the following functions are invoked on a particular cycle: /C0068CBR refresh with reset (CBR) /C0068CBR refresh with no reset (CBRN) /C0068CBR refresh with no reset and stop-point set (CBRS) /C0068Block write /C0068Loading write-mask register for the persistent write-per-bit mode (LMR) /C0068Loading color register for the block-write mode /C0068Split-register-transfer read DRAM data I/O, write mask data (DQ0–DQ15) DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG is brought low. Data appears at the outputs until TRG returns high, CASx returns high following RAS returning high, or RAS returns high following CASx returning high. The write mask is latched into the device through the random DQ pins by the falling edge of RAS and is used on all write-per-bit cycles. In a transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. serial-data outputs (SQ0 –SQ15) Serial data is read from the SQ pins. The SQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long as the serial-enable pin, SE , is high. The serial outputs are enabled when SE is brought low. serial clock (SC) Serial data is accessed out of the data register during the rising edge of SC. The SMJ55161 is designed to work with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC-clock operating frequency.
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serial enable (SE) During serial-access operations, SE is used as an enable/disable for the SQ outputs. SE low enables the serial-data output while SE high disables the serial-data output. SE is also used as an enable/disable for output pin QSF. IMPORTANT: While SE is held high, the serial clock is not disabled. External SC pulses increment the internal serial-address counter regardless of the state of SE. This ungated serial-clock scheme minimizes access time of serial output from SE low because the serial-clock input buffer and the serial-address counter are not disabled by SE. special-function output (QSF) QSF is an output pin that indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 128 bits of the serial register (SAM). When QSF is high, the pointer is accessing the higher (most significant) 128 bits of the SAM. During full-register-transfer operations, QSF can change state upon completing the cycle. This state is determined by the tap point loaded during the transfer cycle. QSF is enabled by SE ; therefore, if SE is high, the QSF output is in the high-impedance state. no connect / ground (NC/GND) NC/GND must be tied to system ground or left floating for proper device operation.
Table 3 lists the DRAM functions. Table 3. DRAM Functions or the falling edge of WE, whichever occurs later. ‡ Logic L is selected when either or both CASL and CASU are low. § The column address and block address are latched on the first falling edge of CASx. ¶ CBRS cycle should be performed immediately after the power-up initialization cycle. ||CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. /C0107CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
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Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row-address setup, row-address hold, and address multiplex. The maximum RAS low time and CAS page cycle time used determine the number of columns that can be accessed. Unlike conventional page-mode operations, the enhanced page mode allows the SMJ55161 to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx transitions low. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CASx. In this case, data is obtained after ta(C) MAX (access time from CASx low) if ta(CA) MAX (access time from column address) has been satisfied. refresh CAS -before-RAS (CBR) refresh CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode. The CBRN and CBRS refreshes (no reset) do not end the persistent write-per-bit mode or the stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh is completed within the required time period, t rf(MA). The output buffers remain in the high-impedance state during the CBR refresh cycles regardless of the state of TRG. hidden refresh A hidden refresh is accomplished by holding both CASL and CASU low in the DRAM read cycle and cycling RAS . The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh. RAS -only refresh A RAS -only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the output buffers remain in the high-impedance state to conserve power. Externally-generated addresses must be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be refreshed.
page-mode read, and read-modify-write cycles (see Figure 3). Figure 1. DRAM Read Cycle With RAS-Controlled Output Figure 2. DRAM Read Cycle With CASx-Controlled Output
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Figure 3. DRAM Page-Read Cycle With Extended Output
byte (DQ8–DQ15) (see Figure 4). Figure 4. Example of a Byte-Read Cycle
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Figure 5. Example of an Early-Write Cycle
is strobed in with data setup and hold times for DQ0 –DQ15 referenced to WE (see Figure 6). Figure 6. Example of a Late-Write Cycle
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nonpersistent write-per-bit and persistent write-per-bit. Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
of write cycles until another LMR cycle is performed or power is removed. is reset only by a CBR refresh (option-reset) cycle (see Figure 8). Figure 8. Example of a Persistent Write-Per-Bit Operation
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The block-write feature allows up to 64 bits of data to be written simultaneously to one row of the memory array. Figure 9. Block-Write Operation and 12 –15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 10).
Figure 10. Block Write With Masks
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block 1 comprises columns 4 –7, block 2 comprises columns 8 –11, etc., as shown in Figure 11. Figure 11. Block Columns Organization has the same block selected. write-mask capability, allowing additional performance options.
- DQ3 is not written and retains its previous data due to write-mask-register-bit 3 being 0.
column-mask-register-bit 8 being 0.
block-write operation shown in the previous example. Figure 12. Example of Fourth Quadrant After a Block-Write Operation data until power is lost or until another load-color-register cycle is performed (see Figure 13 and Figure 14).
- Block address (A2–A8) is latched on the first falling edge of CASx
- Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS.
- Column-mask data: DQi–DQi+3 (i = 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of WE, whichever
Figure 13. Example of Block Writes
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- Block address (A2–A8) is latched on the first falling edge of CASx
- Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS
- Column-mask data: DQi–DQi+3 (i = 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of WE, whichever
Figure 14. Example of a Persistent Block Write Table 4. SAM Function Table † Logic L is selected when either CASL or CASU are low.
is read out (see Figure 15). Figure 15. Full-Register-Transfer Read Figure 16. Example of Full-Register-Transfer Read Operations
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half can be loaded from the memory array. Figure 17. Split-Register-Transfer Read at the first falling edge of CASx. Column-address bit A8 selects which half of the row is to be transferred. bit A7 is ignored, and the split-register transfer is controlled internally to select the inactive register half.
0 A7 = 0 † 511
0 A7 = 1 † 511
0 A7 = 0† 511
† A7 shown as internally controlled. Figure 18. Example of a Split-Register-Transfer Read Operation immediately without any minimum SC-clock requirement.
QSF. QSF also changes state when a boundary between two register halves is reached. Figure 19. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read Figure 20. Example of Successive Split-Register-Transfer-Read Operations
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bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown in Figure 21. Figure 21. Serial-Pointer Direction for Serial Read split-register transfer (see Figure 22). Figure 22. Serial Pointer for Split-Register Read – Case I bit 128 or bit 0, respectively (see Figure 23). Figure 23. Serial Pointer for Split-Register Read – Case II can be used to improve two-dimensional drawing performance in a nonscanline data format. (CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 24). Figure 24. Example of the SAM With Partitions
A4–A7 which are used to define the SAM’s partition length. The other row-address inputs are don’t cares. Stop-point mode should be initiated after the initialization cycles are performed (see Table 5). Table 5. Programming Code for Stop-Point Mode
16 X L L L L X 16 15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175,
32 X L L L H X 8 31, 63, 95, 127, 159, 191, 223, 255
64 X L L H H X 4 63, 127, 191, 255
of the SAM and switches to the opposite half of the SAM (see Figure 25). Figure 25. Example of Split-Register Operation With Programmable Stop Points
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CBR cycles ensures that the SMJ55161 remains in normal mode. Figure 26. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point after the power-up initialization cycles are performed. SC cycles are required to initialize the SAM port. After initialization, the internal state of the SMJ55161 is as shown in Table 6. Table 6. Internal State of SMJ55161
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VSS Supply voltage 0 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) –1 0.8 V TA Operating free-air temperature – 55 125 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ SAM ’55161-75 ’55161-80 UNITPARAMETER TEST CONDITIONS ‡ PORT MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = –1 mA 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 5.8 V, All other pins at 0 V to VCC ± 10 ± 10 µA IO Output current (leakage) (see Note 3)VCC = 5.5 V, VO = 0 V to VCC ± 10 ± 10 µA ICC1 Operating current§ See Note 4 Standby 165 160 mA ICC1A Operating current§ tc(SC) = MIN Active 210 195 mA ICC2 Standby current All clocks = VCC Standby 12 12 mA ICC2A Standby current tc(SC) = MIN Active 70 65 mA ICC3 RAS -only refresh current See Note 4 Standby 165 160 mA ICC3A RAS -only refresh current tc(SC) = MIN, (See Note 5) Active 215 195 mA ICC4 Page-mode current§ tc(P) = MIN, (See Note 5) Standby 100 95 mA ICC4A Page-mode current§ tc(SC) = MIN, (See Note 5) Active 145 130 mA ICC5 CBR current See Note 4 Standby 165 160 mA ICC5A CBR current tc(SC) = MIN, (See Note 5) Active 210 195 mA ICC6 Data-transfer current See Note 4 Standby 180 170 mA ICC6A Data-transfer current tc(SC) = MIN Active 225 200 mA ‡ For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. § Measured with outputs open NOTES: 3. SE is disabled for SQ output leakage tests. 4. Measured with one address change while RAS = VIL; tc(rd), tc(W) , tc(TRD) = MIN 5. Measured with one address change while CASx = VIH
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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6) PARAMETER MIN TYP MAX UNIT C i(A) Input capacitance, address inputs 5 10 pF C i(RC) Input capacitance, address-strobe inputs 8 10 pF C i(W) Input capacitance, write-enable input 7 10 pF C i(SC) Input capacitance, serial clock 6 10 pF C i(SE) Input capacitance, serial enable 7 10 pF C i(DSF) Input capacitance, special function 7 10 pF C i(TRG) Input capacitance, transfer-register input 7 10 pF C o(O) Output capacitance, SQ and DQ 12 15 pF C o(QSF) Output capacitance, QSF 10 12 pF NOTE 6: V CC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7) PARAMETER TEST ALT. ’55161-75 ’55161-80 UNITPARAMETER CONDITIONS † SYMBOL MIN MAX MIN MAX UNIT ta(C) Access time from CASx td(RLCL) = MAX tCAC 20 20 ns ta(CA) Access time from column address td(RLCL) = MAX tAA 38 40 ns ta(CP) Access time from CASx high td(RLCL) = MAX tCPA 43 45 ns ta(R) Access time from RAS td(RLCL) = MAX tRAC 75 80 ns ta(G) Access time of DQ from TRG low tOEA 20 20 ns ta(SQ) Access time of SQ from SC high C L = 30 pF tSCA 23 25 ns ta(SE) Access time of SQ from SE low C L = 30 pF tSEA 18 20 ns tdis(CH) Disable time, random output from CASx high (see Note 8) C L = 50 pF tOFF 0 20 0 20 ns tdis(RH) Disable time, random output from RAS high (see Note 8) C L = 50 pF 0 20 0 20 ns tdis(G) Disable time, random output from TRG high (see Note 8) C L = 50 pF tOEZ 0 20 0 20 ns tdis(WL) Disable time, random output from WE low (see Note 8) C L = 50 pF tWEZ 0 25 0 25 ns tdis(SE) Disable time, serial output from SE high (see Note 8) C L = 30 pF tSEZ 0 18 0 20 ns † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to one TTL load and 50 pF. Data-out reference level: VOH / VOL = 2 V/0.8 V. Switching times for SAM-port output are measured with a load equivalent to one TTL load and 30 pF. Serial-data out reference level: VOH / VOL = 2 V/0.8 V. 8. tdis(CH), tdis(RH), tdis(G), tdis(WL), and tdis(SE) are specified when the output is no longer driven.
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 33POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature† ALT. ’55161-75 ’55161-80 UNITSYMBOL MIN MAX MIN MAX UNIT tc(rd) Cycle time, read tRC 140 150 ns tc(W) Cycle time, write tWC 140 150 ns tc(rdW) Cycle time, read-modify-write tRMW 188 200 ns tc(P) Cycle time, page-mode read, write tPC 48 50 ns tc(RDWP) Cycle time, page-mode read-modify-write tPRMW 88 90 ns tc(TRD) Cycle time, transfer read tRC 140 150 ns tc(SC) Cycle time, serial clock (see Note 9) tSCC 24 30 ns tw(CH) Pulse duration, CASx high tCPN 10 10 ns tw(CL) Pulse duration, CASx low (see Note 10) tCAS 20 10 000 20 10 000 ns tw(RH) Pulse duration, RAS high tRP 55 60 ns tw(RL) Pulse duration, RAS low (see Note 11) tRAS 75 10 000 80 10 000 ns tw(WL) Pulse duration, WE low tWP 13 15 ns tw(TRG) Pulse duration, TRG low 20 20 ns tw(SCH) Pulse duration, SC high tSC 9 10 ns tw(SCL) Pulse duration, SC low tSCP 9 10 ns tw(GH) Pulse duration, TRG high tTP 20 20 ns tw(RL)P Pulse duration, RAS low (page mode) tRASP 75 100 000 80 100 000 ns tsu(CA) Setup time, column address before CASx low tASC 0 0 ns tsu(SFC) Setup time, DSF before CASx low tFSC 0 0 ns tsu(RA) Setup time, row address before RAS low tASR 0 0 ns tsu(WMR) Setup time, WE before RAS low tWSR 0 0 ns tsu(DQR) Setup time, DQ before RAS low tMS 0 0 ns tsu(TRG) Setup time, TRG high before RAS low tTHS 0 0 ns tsu(SFR) Setup time, DSF low before RAS low tFSR 0 0 ns tsu(DCL) Setup time, data valid before CASx low tDSC 0 0 ns tsu(DWL) Setup time, data valid before WE low tDSW 0 0 ns tsu(rd) Setup time, read command, WE high before CASx low tRCS 0 0 ns tsu(WCL) Setup time, early-write command, WE low before CASx low tWCS 0 0 ns tsu(WCH) Setup time, WE low before CASx high, write tCWL 18 20 ns tsu(WRH) Setup time, WE low before RAS high, write tRWL 20 20 ns th(CLCA) Hold time, column address after CASx low tCAH 13 15 ns th(SFC) Hold time, DSF after CASx low tCFH 15 15 ns th(RA) Hold time, row address after RAS low tRAH 10 10 ns † Timing measurements are referenced to VIL MAX and VIH MIN. NOTES: 9. Cycle time assumes tt = 3 ns. 10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the transition times, this can require additional CASx low time [tw(CL)]. 11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the transition times, this can require additional RAS low time [tw(RL)].
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) † ALT. ’55161-75 ’55161-80 UNITSYMBOL MIN MAX MIN MAX UNIT th(TRG) Hold time, TRG after RAS low tTHH 15 15 ns th(RWM) Hold time, write mask after RAS low tRWH 15 15 ns th(RDQ) Hold time, DQ after RAS low (write-mask operation) tMH 15 15 ns th(SFR) Hold time, DSF after RAS low tRFH 10 10 ns th(RLCA) Hold time, column address valid after RAS low (see Note 12) tAR 33 35 ns th(CLD) Hold time, data valid after CASx low tDH 15 15 ns th(RLD) Hold time, data valid after RAS low (see Note 12) tDHR 35 35 ns th(WLD) Hold time, data valid after WE low tDH 15 15 ns th(CHrd) Hold time, read, WE high after CASx high (see Note 13) tRCH 0 0 ns th(RHrd) Hold time, read, WE high after RAS high (see Note 13) tRRH 0 0 ns th(CLW) Hold time, write, WE low after CASx low tWCH 15 15 ns th(RLW) Hold time, write, WE low after RAS low (see Note 12) tWCR 35 35 ns th(WLG) Hold time, TRG high after WE low (see Note 14) tOEH 10 10 ns th(SHSQ) Hold time, SQ valid after SC high tSOH 2 2 ns th(RSF) Hold time, DSF after RAS low tFHR 35 35 ns th(CLQ) Hold time, output valid after CASx low tDHC 0 0 ns td(RLCH) Dela time RAS lo to CAS high tCSH 75 80 nstd(RLCH) D elay time, RAS low to CAS x high (See Note 15) tCHR 13 15 ns td(CHRL) Delay time, CASx high to RAS low tCRP 0 0 ns td(CLRH) Delay time, CASx low to RAS high tRSH 20 20 ns td(CLWL) Delay time, CASx low to WE low (see Notes 16 and 17) tCWD 48 50 ns td(RLCL) Delay time, RAS low to CASx low (see Note 18) tRCD 20 50 20 60 ns td(CARH) Delay time, column address valid to RAS high tRAL 38 40 ns td(CACH) Delay time, column address valid to CASx high tCAL 38 40 ns td(RLWL) Delay time, RAS low to WE low (see Note 16) tRWD 100 105 ns td(CAWL) Delay time, column address valid to WE low (see Note 16) tAWD 63 65 ns td(CLRL) Delay time, CASx low to RAS low (see Note 15) tCSR 0 0 ns td(RHCL) Delay time, RAS high to CASx low (see Note 15) tRPC 0 0 ns td(CLGH) Delay time, CASx low to TRG high for DRAM read cycles 20 20 ns td(GHD) Delay time, TRG high before data applied at DQ tOED 15 15 ns † Timing measurements are referenced to VIL MAX and VIH MIN. NOTES: 12. The minimum value is measured when td(RLCL) is set to td(RLCL) MIN as a reference. 13. Either th(RHrd) or td(CHrd) must be satisfied for a read cycle. 14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 15. CBR refresh operation only 16. Read-modify-write operation only 17. TRG must disable the output buffers prior to applying data to the DQ pins. 18. The maximum value is specified only to assure RAS access time.
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)† ALT. ’55161-75 ’55161-80 UNITSYMBOL MIN MAX MIN MAX UNIT td(RLTH) Delay time, RAS low to TRG high (see Note 19) tRTH 58 60 ns td(RLSH) Delay time, RAS low to first SC high after TRG high (see Note 20) tRSD 75 80 ns td(RLCA) Delay time, RAS low to column address valid tRAD 15 35 15 40 ns td(GLRH) Delay time, TRG low to RAS high tROH 20 20 ns td(CLSH) Delay time, CASx low to first SC high after TRG high (see Note 20) tCSD 23 25 ns td(SCTR) Delay time, SC high to TRG high (see Notes 19 and 20) tTSL 5 5 ns td(THRH) Delay time, TRG high to RAS high (see Note 19) tTRD –10 –10 ns td(THRL) Delay time, TRG high to RAS low (see Note 21) tTRP 55 60 ns td(THSC) Delay time, TRG high to SC high (see Note 19) tTSD 18 20 ns td(RHMS) Delay time, RAS high to last (most significant) rising edge of SC before boundary switch during split-register-transfer read cycles 20 20 ns td(CLTH) Delay time, CASx low to TRG high in real-time-transfer read cyclestCTH 15 15 ns td(CASH) Delay time, column address to first SC in early-load-transfer read cyclestASD 28 30 ns td(CAGH) Delay time, column address to TRG high in real-time-transfer read cycles tATH 20 20 ns td(DCL) Delay time, data to CASx low tDZC 0 0 ns td(DGL) Delay time, data to TRG low tDZO 0 0 ns td(MSRL) Delay time, last (most significant) rising edge of SC to RAS low before boundary switch during split-register-transfer read cycles 20 20 ns td(SCQSF) Delay time, last (127 or 255) rising edge of SC to QSF switching at the boundary during split-register-transfer read cycles (see Note 22)tSQD 28 30 ns td(CLQSF) Delay time, CASx low to QSF switching in transfer-read cycles (see Note 22) tCQD 33 35 ns td(GHQSF) Delay time, TRG high to QSF switching in transfer-read cycles (see Note 22) tTQD 28 30 ns td(RLQSF) Delay time, RAS low to QSF switching in transfer-read cycles (see Note 22) tRQD 73 75 ns trf(MA) Refresh time interval, memory tREF 8 8 ms tt Transition time tT 3 50 3 50 ns † Timing measurements are referenced to VIL MAX and VIH MIN. NOTES: 19. Real-time-load transfer read or late-load-transfer read cycle only 20. Early-load-transfer read cycle only 21. Full-register-(read) transfer cycles only 22. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is VOH / VOL = 2 V/0.8 V.
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Figure 27. Read-Cycle Timing With CASx-Controlled Output
Figure 28. Read-Cycle Timing With RAS-Controlled Output
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Figure 29. Early-Write-Cycle Timing Table 7. Early-Write-Cycle State Table
Figure 30. Late-Write-Cycle Timing (Output-Enable-Controlled Write) Table 8. Late-Write-Cycle State Table
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† Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. Figure 31. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)
† Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. Figure 32. Load-Write-Mask-Register-Cycle Timing (Late-Write Load)
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Figure 33. Read-Write-/Read-Modify-Write-Cycle Timing Table 9. Read-Write-/Read-Modify-Write-Cycle State Table
NOTES: A. Access time is ta(CP) or ta(CA) dependent. B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. write mode (normal, block write, etc.). Figure 34. Enhanced-Page-Mode Read-Cycle Timing
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Figure 35. Enhanced-Page-Mode Write-Cycle Timing Table 10. Enhanced-Page-Mode Write-Cycle State Table
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 36. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing Table 11. Enhanced-Page-Mode Read-Modify-Write-Cycle State Table
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NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. write mode (normal, block write, etc.). Figure 37. Enhanced-Page-Mode Read-/Write-Cycle Timing
Figure 38. Load-Color-Register-Cycle Timing (Early-Write Load)
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Figure 39. Load-Color-Register-Cycle Timing (Late-Write Load)
Figure 40. Block-Write-Cycle Timing (Early Write) Table 12. Block-Write-Cycle State Table
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Figure 41. Block-Write-Cycle Timing (Late Write) Table 13. Block-Write-Cycle State Table
B. To ensure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late-write feature is used. If the early-write cycle timing is used, the state of TRG is a don’t care after the minimum period th(TRG) from the falling edge of RAS. Figure 42. Enhanced-Page-Mode Block-Write-Cycle Timing Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table
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Figure 43. RAS-Only Refresh-Cycle Timing
Figure 44. CBR-Refresh-Cycle Timing Table 15. CBR-Cycle State Table
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Figure 45. Hidden-Refresh-Cycle Timing Table 16. Hidden-Refresh-Cycle State Table
to from the 256 corresponding columns of the selected row. D. Early-load operation is defined as th(TRG) MIN < th(TRG) < td(RLTH) MIN. Figure 46. Full-Register Transfer-Read Timing, Early-Load Operations
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to from the 256 corresponding columns of the selected row. D. Late load operation is defined as td(THRH) < 0 ns. Figure 47. Full-Register Transfer Read-Timing, Real-Time Load Operation/Late-Load Operation
Figure 48. Split-Register-Transfer-Read Timing
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low. This is to avoid the initiation of a register-data transfer operation. into the read mode by performing a transfer-read cycle. Figure 49. Serial-Read-Cycle Timing (SE = VIL)
low. This is to avoid the initiation of a register-data transfer operation. the read mode by performing a transfer-read cycle. Figure 50. Serial-Read Timing (SE-Controlled Read)
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and the first split-register cycle. the inactive half and the rising edge of the serial clock of the last bit (bit 127 or 255). Figure 51. Split-Register Operating Sequence
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 61POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA GB (S-CPGA-P68) CERAMIC PIN GRID ARRAY PACKAGE 4040114-14/A 2/95
4 Places
0.800 (20,32) TYP 0.018 (0,46) DIA TYP 0.055 (1,39) J H G F E D C A B 123456789 0.100 (2,54) 0.166 (4,16) 0.194 (4,98) 0.072 (1,83) 0.088 (2,23) 0.950 (24,13) 0.970 (24,63) 0.524 (13,31) 0.536 (13,61) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark may appear on top or bottom depending on package vendor. D. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within 0.015 (0,38) radius relative to the center of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold plated or solder dipped. G. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
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HKC (R-CDFP-F64) CERAMIC DUAL FLATPACK WITH TIE BAR 4073160/B 10/94 0.445 (11,30) 0.420 (10,67) 0.185 (4,70) 0.145 (3,68) 0.0098 (0,250) 0.0060 (0,150) 0.070 (1,78) 0.055 (1,40) 0.150 (3,81) 0.100 (2,54) 0.026 (0,66) MIN 0.320 (8,13) 0.295 (7,49) 0.0079 (0,200) 0.0043 (0,110) 0.040 (1,02) 0.030 (0,76) 0.765 (19,43) 0.730 (18,54) 1.020 (25,91) 0.980 (24,89) 1.580 (40,13) 1.620 (41,14) 6433 32 1 0.0196 (0,500) SQ NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. All leads not shown for clarity purposes. device symbolization SMJ55161 HKC LLLXXXARF -SS Speed (-70, -80) Die Revision Code Assembly Site Code Wafer Fab Code Date Code Lot Traceability Code Package Code M Temperature Range
SGMS056D – MAY 1995 – REVISED OCTOBER 1997 63POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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