SMJ4C1024-12HL

SMJ4C1024 TI | Alldatasheet

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1048576 BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization...1 0 4 8 5 7 6 × 1-Bit /C0068Processed to MIL-STD-883, Class B /C0068Single 5-V Supply (10% Tolerance) /C0068Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR ta(R) ta(C) ta(CA) WRITE (tRAC )( t CAC ) (t AA ) CYCLE (MAX) (MAX) (MAX) (MIN) ’4C1024-80 80 ns 20 ns 40 ns 150 ns ’4C1024-10 100 ns 25 ns 45 ns 190 ns ’4C1024-12 120 ns 30 ns 55 ns 220 ns ’4C1024-15 150 ns 40 ns 70 ns 260 ns /C0068Enhanced Page-Mode Operation for Faster Memory Access – Higher Data Bandwidth Than Conventional Page Mode Parts – Random Single-Bit Access Within a Row With a Column Address /C0068One of TI’s CMOS Megabit Dynamic Random-Access Memory (DRAM) Family Including SMJ44C256 — 256K × 4 Enhanced Page Mode /C0068CAS -Before-RAS (CBR) Refresh /C0068Long Refresh Period 512-Cycle Refresh in 8 ms (Max) /C00683-State Unlatched Output /C0068Low Power Dissipation /C0068All Inputs/Outputs and Clocks Are TTL-Compatible /C0068Packaging Offered: – 20/26-Pin J-Leaded Ceramic Surface Mount Package (HJ Suffix) – 18-Pin 300-Mil Ceramic Dual-In-Line Package (JD Suffix) – 20-Pin Ceramic Flatpack (HK Suffix) – 20/26-Terminal Leadless Ceramic Surface Mount Package (FQ/HL Suffixes) – 20-Pin Ceramic Zig-Zag In-Line Package (SV Suffix) /C0068Operating Temperature Range – 55°C to 125°C Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VSS Q CAS NC D W RAS TF NC V CC VSS Q CAS NC HJ PACKAGE (TOP VIEW) D W RAS TF V CC VSS Q CAS JD PACKAGE (TOP VIEW) D W RAS TF NC V CC HK PACKAGE (TOP VIEW) Q D RAS NC VCC CAS VSS W TF NC SV PACKAGE (SIDE VIEW) FQ/HL PACKAGES (TOP VIEW) D W RAS TF NC V CC VSS Q CAS NC Copyright  1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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A0–A9 Address Inputs CAS Column Address Strobe D Data In NC No Internal Connection Q Data Out RAS Row Address Strobe TF Test Function VCC 5-V Supply VSS Ground W Write Enable

description

The SMJ4C1024 is a 1048576-bit DRAM organized as 1048576 words of one bit each. It employs technology for high performance, reliability, and low power at a low cost. This device features maximum RAS access times of 80 ns, 100 ns, 120 ns, and 150 ns. Maximum power dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices. IDD peaks are typIcally 140 mA and a –1 V input voltage undershoot can be tolerated, minimizing system noise. All inputs and outputs, including clocks, are compatible with series 54 TTL. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The SMJ4C1024 is offered in an 18-pin ceramic dual-in-line package (JD suffix), a 20/26-terminal leadless ceramic carrier package (FQ/HL suffixes), a 20/26-pin J-leaded carrier package (HJ suffix), a 20-pin flatpack (HK suffix), and a 20-pin ceramic zig-zag in-line package (SV suffix). They are characterized for operation from – 55°C to 125°C.

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 logic symbol† RAS CAS W D 20D10/21D0 20D19/21D9 C20 [ROW] G23 [REFRESH ROW] 24 [PWR DWN] C21 [COL] G24 23C22 23,21D 24 EN A, 22D A 0 1 048 575 RAM 1024K × 1 A ∇ Q17 A9 15 † This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. The pin numbers shown are for the 18-pin JD package.

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(10) Column Address Buffers (10) 256K Array Row Decode 256K Array Sense Amplifiers Sense Amplifiers 256K Array Row Decode 256K Array Column Decode I/O Buffers 1 of 8 Selection Data In Reg. Data Out Reg. D Q operation enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and for address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS page-cycle time used. With minimum CAS page-cycle time, all 1024 columns specified by column addresses A0 through A9 can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS latches the column addresses. This feature lets the SMJ4C1024 operate at a higher data bandwidth than conventional page-mode parts, since data retrieval begins as soon as the column address is valid rather than when CAS goes low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CAS . In this case, data is obtained after ta(C) maximum (access time from CAS low) if ta(CA) maximum (access time from column address) has been satisfied. If the column addresses for the next page cycle are valid at the same time CAS goes high, access time for the next cycle is determined by the later occurrence of ta(CA) or ta(CP) (access time from rising edge of CAS). address (A0–A9) Twenty address bits are required to decode one of 1048576 storage cell locations. Ten row-address bits are set up on inputs A0 through A9 and latched onto the chip by RAS. The ten column-address bits are set up on pins A0 through A9 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 address (A0–A9) (continued) of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select to activate the output buffer as well as to latch the address bits into the column-address buffer. write enable (W) The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic low selects the write mode. The write-enable pin can be driven from standard TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting common input/output operation. data in (D) Data-in is written during a write or a read-modify-write cycle. Depending on the mode of operation, the falling edge of CAS or W strobes data into the on-chip latch. In an early-write cycle, W is brought low prior to CAS, and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or a read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold times referenced to this signal. data out (Q) The 3-state output buffers provide direct TTL compatibility (no pullup resistor required) with a fanout of two series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle, the output becomes valid after the access time ta(C). The access time from CAS low (ta(C)) begins with the negative transition of CAS as long as ta(R) and ta(CA) are satisfied. The output becomes valid after the access time has elapsed and remains valid while CAS is low; when CAS goes high, the output returns to a high-impedance state. In a delayed-write or read-modify-write cycle, the output follows the sequence for the read cycle. refresh A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing each of the 512 rows (A0–A8). A normal read or write cycle refreshes all bits in each selected row. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. CAS -before-RAS (CBR) refresh CBR refresh is used by bringing CAS low earlier than RAS (see parameter td(CLRL)R) and holding it low after RAS falls (parameter td(RLCH)R ). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. The external address is also ignored during the hidden refresh cycles. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full V CC level is achieved. test function (TF) pin During normal device operation, TF must be disconnected or biased at a voltage ≤ VCC .

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) –1 0.8 V TA Minimum operating free-air temperature – 55 °C TC Maximum operating case temperature 125 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST ’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15 UNITPARAMETER CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltageIOH = – 5 mA 2.4 2.4 2.4 2.4 V VOL Low-level II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 10 ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current VCC = 5.5 V, Minimum cycle 75 70 60 55 mA ICC2 Standby current After one memory cycle, RAS and CAS high, VIH = 2.4 V 3 3 3 3 mA ICC3 Average refresh current (RAS only or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 70 65 55 50 mA ICC4 Average page current VCC = 5.5 V, tPC = minimum, RAS low, CAS cycling 50 45 35 30 mA capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER HL/JD/FQ HJ HK SV UNITPARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNIT C i(A) Input capacitance, address inputs 6 7 8 9 pF C i(D) Input capacitance, data input 5 5 6 7 pF C i(RC) Input capacitance, strobe inputs 7 7 8 8 pF C i(W) Input capacitance, write-enable input 7 7 7 7 pF C o Output capacitance 7 9 10 8 pF NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal applied to the pin under test. All other pins are open. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 1) PARAMETER ALT. ’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15 UNITPARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT ta(C) Access time from CAS low tCAC 20 25 30 40 ns ta(CA) Access time from column address tAA 40 45 55 70 ns ta(R) Access time from RAS low tRAC 80 100 120 150 ns ta(CP) Access time from column precharge tCPA 40 40 60 75 ns tdis(CH) Output disable time after CAS high (see Note 4) tOFF 20 25 30 35 ns NOTE 4: tdis(CH) is specified when the output is no longer driven. The output is disabled by bringing CAS high.

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 5) ALT. ’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15 UNITSYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT tc(rd) Cycle time, read (see Note 6) tRC 150 190 220 260 ns tc(W) Cycle time, write tWC 150 190 220 260 ns tc(rdW) Cycle time, read-write/read-modify-writetRWC 175 220 265 315 ns tc(P) Cycle time, page-mode read or write (see Note 7) tPC 50 55 65 80 ns tc(PM) Cycle time, page-mode read-modify-write tPRWC 75 85 110 135 ns tw(CH) Pulse duration, CAS high tCP 10 10 15 25 ns tw(CL) Pulse duration, CAS low (see Note 8) tCAS 20 10000 25 10000 30 10000 40 10000 ns tw(RH) Pulse duration, RAS high (precharge) tRP 60 80 90 100 ns tw(RL) Pulse duration, nonpage mode, RAS low (see Note 9) tRAS 80 10000 100 10000 120 10000 150 10000 ns tw(RL)P Pulse duration, page mode, RAS low (see Note 9) tRASP 80 100000 100 100000 120 100000 150 100000 ns tw(WL) Pulse duration, write tWP 15 15 20 25 ns tsu(CA) Setup time, column address before CAS low tASC 0 3 3 3 ns tsu(RA) Setup time, row address before RAS low tASR 0 0 0 0 ns tsu(D) Setup time, data (see Note 10) tDS 0 0 0 0 ns tsu(rd) Setup time, read before CAS low tRCS 0 0 0 0 ns tsu(WCL) Setup time, W low before CAS low (see Note 11) tWCS 0 0 0 0 ns tsu(WCH) Setup time, W low before CAS high tCWL 20 25 30 40 ns tsu(WRH) Setup time, W low before RAS high tRWL 20 25 30 40 ns th(CA) Hold time, column address after CAS low tCAH 15 20 20 25 ns th(RA) Hold time, row address after RAS low tRAH 12 15 15 20 ns NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min. 6. All cycle times assume tt = 5 ns. 7. To assure tc(P) min, tsu(CA) should be ≥ tw(CH). 8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. 9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. 10. Referenced to the later of CAS or W in write operations 11. Early write operation only

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 5) (continued) ALT. ’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15 UNITSYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT th(RLCA) Hold time, column address after RAS low (see Note 12) tAR 60 70 80 100 ns th(D) Hold time, data (see Note 10) tDH 15 20 25 30 ns th(RLD) Hold time, data after RAS low (see Note 12) tDHR 60 70 85 110 ns th(CHrd) Hold time, read after CAS high (see Note 13) tRCH 0 0 0 0 ns th(RHrd) Hold time, read after RAS high (see Note 13) tRRH 10 10 10 10 ns th(CLW) Hold time, write after CAS low (see Note 11) tWCH 15 20 25 30 ns th(RLW) Hold time, write after RAS low (see Note 12) tWCR 60 70 85 100 ns td(RLCH) Delay time, RAS low to CAS high tCSH 80 100 120 150 ns td(CHRL) Delay time, CAS high to RAS low tCRP 0 0 0 0 ns td(CLRH) Delay time, CAS low to RAS high tRSH 20 25 30 40 ns td(CLWL) Delay time, CAS low to W low (see Note 14) tCWD 20 25 40 50 ns td(RLCL) Delay time, RAS low to CAS low (see Note 15) tRCD 22 60 28 75 28 90 33 110 ns td(RLCA) Delay time, RAS low to column address (see Note 15) tRAD 17 40 20 55 20 65 25 80 ns td(CARH) Delay time, column address to RAS high tRAL 40 45 55 70 ns td(CACH) Delay time, column address to CAS high tCAL 40 45 55 70 ns td(RLWL) Delay time, RAS low to W low (see Note 14) tRWD 80 100 130 160 ns td(CAWL) Delay time, column address to W low (see Note 14) tAWD 40 45 65 80 ns td(RLCH)R Delay time, RAS low to CAS high (see Note 16) tCHR 20 25 25 30 ns td(CLRL)R Delay time, CAS low to RAS low (see Note 16) tCSR 10 10 10 15 ns td(RHCL)R Delay time, RAS high to CAS low tRPC 0 0 0 0 ns trf Refresh time interval tREF 8 8 8 8 ms tt Transition time (see Note 17) — — — — — ns NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min. 10. Referenced to the later of CAS or W in write operations. 11. Early-write operation only 12. The minimum value is measured when td(RLCL) is set td(RLCL) min as a reference. 13. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle. 14. Read-modify-write operation only 15. Maximum value specified only to assure access time. 16. CBR refresh only 17. Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and a maximum of 50 ns.

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NOTE A: C L includes probe and fixture capacitance. Figure 1. Load Circuits for Timing Parameters

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 2. Read-Cycle Timing

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Figure 3. Early-Write-Cycle Timing

Figure 4. Write-Cycle Timing

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NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 5. Read-Write-/Read-Modify-Write-Cycle Timing

NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. C. Access time is ta(CP) or ta(CA) dependent. Figure 6. Enhanced-Page-Mode Read-Cycle Timing

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specifications are not violated. B. Referenced to CAS or W, whichever occurs last. Figure 7. Enhanced-Page-Mode Write-Cycle Timing

NOTES: A. Output can go from high-impedance state to an invalid-data state prior to the specified access time. Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing

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Figure 9. RAS -Only Refresh-Cycle Timing

Figure 10. Hidden-Refresh-Cycle Timing

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Figure 11. Automatic-CBR-Refresh-Cycle Timing

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA HJ (R-CDCC-J20) J-LEADED CERAMIC CHIP CARRIER

4 Places

0.025 (0,64) 0.035 (0,89) 0.338 (8,59) 0.137 (3,48) 0.048 (1,22) 0.685 (17,40) 0.608 (15,44) Radius 0.080 (2,03) 0.012 (0,30) 0.044 (1,12) 0.665 (16,89) 0.264 (6,71) 0.006 (0,15) 0.114 (2,90) 0.322 (8,18) 4040144-2/B 10/94 0.050 (1,27) 11 0 20 11 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals will be gold plated.

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HK (R-CDFP-F20) CERAMIC DUAL FLATPACK 4040174/C 08/95 0.075 (1,91) 0.025 (0,64) 0.004 (0,10) 0.660 (16,76) 0.090 (2,29) 0.010 (0,25) 0.680 (17,27) 0.120 (3,05) 0.095 (2,41) 0.035 (0,89) 0.310 (7,87) 0.290 (7,37) 0.021 (0,53) 0.015 (0,38) Lid 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA FQ (R-CDCC-N20) LEADLESS CERAMIC CHIP CARRIER 4040143/B 10/94 0.090 (2,29) TYP 0.050 (1,27) TYP 0.685 (17,40) 0.357 (9,07) 0.092 (2,34) 0.030 (0,76) MIN 0.028 (0,71) 0.608 (15,44) 0.343 (8,71) 0.069 (1,75) 0.665 (16,89) 0.022 (0,56) 0.592 (15,04) 10 11 0.008 (0,20) RAD TYP 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

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HL (R-CDCC-N20/26) LEADLESS CERAMIC CHIP CARRIER 4040145/B 4/95 0.685 (17,40) 0.357 (9,07) 0.030 (0,76) MIN 0.080 (2,03) 0.022 (0,56) 0.592 (15,04) 0.090 (2,29) TYP 0.050 (1,27) TYP 0.665 (16,89) 0.028 (0,71) 0.608 (15,44) 10 11 0.008 (0,20) RAD TYP 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 25POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA SV (R-CZIP-T) CERAMIC ZIG-ZAG PACKAGE 4040002/C 08/95 282420PINS B DIM 0.015 (0,38) 0.050 (1,27) Seating Plane 0.115 (2,92) 0.085 (2,16) 0.015 (0,38) 0.008 (0,20) 0.100 (2,54) 0.130 (3,30) (36,45) 1.435 (37,21) 0.465 (11,18) 0.440 (33,27) 1.310 (11,81) 1.290 (32,77) 1.035 (26,29) (27,05) 0.355 (9,02) 0.380 (9,65) (23,11) 0.910 (22,61) 0.890 0.023 (0,58) 0.015 (0,38) 0.355 (9,02) 0.375 (9,53) A MIN A MAX B MIN B MAX C MIN C MAX (32,13) (31,37) 1.235 (11,18) 0.440 (11,81) 0.465 1.110 (28,19) 1.090 (27,69) 1.065 1.265 1.465 A C 0.060 (1,52) 0.040 (1,02) 20181614121086 0.040 (1,02) 0.070 (1,78) 2 4 0.125 (3,18) 0.200 (5,08)

20 PIN SHOWN

0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.

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JD (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 4040086/C 08/95 (27,94) 1.100 PINS ** 0.810 (20,57) (23,11) 0.910A MAX DIM 16 18 20 (25,65) 1.010 0.320 (8,13) 0.290 (7,37) 0.020 (0,51) MIN Seating Plane 0.012 (0,30) 0.008 (0,20) A 0.045 (1,14) 0.065 (1,65) 0.075 (1,91) MAX 4 Places 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.175 (4,45) 0.140 (3,56) 0.290 (7,37) TYP 0°–15° 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

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