SMJ44C251

SMJ44C251 TI | Alldatasheet

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A0–A8 Address Inputs CAS Column Enable DQ0–DQ3 DRAM Data In-Out/Write-Mask Bit SE Serial Enable RAS Row Enable SC Serial Data Clock SDQ0–SDQ3 Serial Data In-Out TRG Transfer Register/Q Output Enable W Write-Mask Select/Write Enable DSF Special Function Select QSF Split-Register Activity Status VCC 5-V Supply VSS Ground GND Ground (Important: Not connected to internal VSS ) PIN NOMENCLATURE SMJ44C251B

262144 BY 4-BIT

SGMS058A – MARCH 1995 – REVISED JUNE 1995 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Military Operating Temperature Range –5 5°C to 125°C /C0068Performance Ranges: ACCESS ACCESS ACCESS ACCESS TIME TIME TIME TIME ROW COLUMN SERIAL SERIAL ADDRESS ENABLE DATA ENABLE (MAX) (MAX) (MAX) (MAX) ta(R) ta(C) t a(SQ) ta(SE) ’44C251B-10 100 ns 25 ns 30 ns 20 ns ’44C251B-12 120 ns 30 ns 35 ns 25 ns /C0068Class B High-Reliability Processing /C0068DRAM: 262144 Words × 4 Bits SAM: 512 Words × 4 Bits /C0068Single 5-V Power Supply (±10% Tolerance) /C0068Dual Port Accessibility–Simultaneous and Asynchronous Access From the DRAM and SAM Ports /C0068Bidirectional-Data-Transfer Function Between the DRAM and the Serial-Data Register /C00684 × 4 Block-Write Feature for Fast Area Fill Operations; As Many as Four Memory Address Locations Written per Cycle From an On-Chip Color Register /C0068Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design /C0068Enhanced Page-Mode Operation for Faster Access /C0068CAS -Before-RAS (CBR) and Hidden Refresh Modes /C0068All Inputs/Outputs and Clocks Are TTL Compatible /C0068Long Refresh Period Every 8 ms (Max) /C0068Up to 33-MHz Uninterrupted Serial-Data Streams /C00683-State Serial I/Os Allow Easy Multiplexing of Video-Data Streams /C0068512 Selectable Serial-Register Starting Locations /C0068Packaging: – 28-Pin J-Leaded Ceramic Chip Carrier Package (HJ Suffix) – 28-Pin Leadless Ceramic Chip Carrier Package (HM Suffix) – 28-Pin Ceramic Sidebrazed DIP (JD Suffix) – 28-Pin Zig-Zag In-Line (ZIP), Ceramic Package (SV Suffix) /C0068Split Serial-Data Register for Simplified Real-Time Register Reload

description

The SMJ44C251B multiport video RAM is a high-speed, dual-ported memory device. It consists of a dynamic random-access memory (DRAM) organized as 262144 words of 4 bits each interfaced to a serial-data register or serial-access memory (SAM) organized as 512 words of 4 bits each. The SMJ44C251B supports three types of operation: random access to and from the DRAM, serial access to and from the serial register, and bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer operations, the SMJ44C251B can be accessed simultaneously and asynchronously from the DRAM and SAM ports. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1995, Texas Instruments Incorporated

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(TOP VIEW) RAS W TRG CAS SE VCC VSS DSF DQ3 SDQ2 VSS SDQ0 TRG GND DQ1 DQ2 SE SDQ3 SC SDQ1 DQ0 W RAS SV PACKAGE (TOP VIEW) SC SDQ0 SDQ1 TRG DQ0 DQ1 W GND RAS V CC VSS SDQ3 SDQ2 SE DQ3 DQ2 DSF CAS QSF HM PACKAGE (TOP VIEW) QSF VCC A7 CAS SC SDQ0 SDQ1 DQ0 DQ1 GND SDQ3 SDQ2 DQ3 DQ2 DSF QSF HJ PACKAGE (TOP VIEW) RAS W TRG CAS SE VCC VSS description (continued) During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial data register. The 512 × 4-bit serial-data register can be loaded from the memory row (transfer read), or the contents of the 512 × 4-bit serial-data register can be written to the memory row (transfer write). The SMJ44C251B is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can be achieved by the device’s 4 × 4 block-write mode. The block-write mode allows four bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent column-address locations. As many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a write mask or a write-per-bit feature allows masking any combination of the four input/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles. The mask register eliminates having to provide mask data on every mask-write cycle. The SMJ44C251B offers a split-register transfer read (DRAM to SAM) feature for the serial tester (SAM port). This feature enables real-time register reload implementation for truly continuous serial data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time register reload (for example, reloads done during CRT retrace periods), the single-register mode of operation is retained to simplify design. The SAM can also be configured in input mode, accepting serial data from an external device. Once the serial register within the SAM is loaded, its contents can be transferred to the corresponding column positions in any row in memory in a single memory cycle. The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial rates up to 33 MHz. During the split-register mode of operation, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active at any given time in the split-register mode. All inputs, outputs, and clock signals on the SMJ44C251B are compatible with Series 54 TTL devices. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility.

SGMS058A – MARCH 1995 – REVISED JUNE 1995 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup, row-address hold, and address multiplex is eliminated, and a memory cycle time reduction of up to 3× can be achieved, compared to minimum RAS cycle times. The maximum number of columns that can be accessed is determined by the maximum RAS low time and page-mode cycle time used. The SMJ44C251B allows a full page (512 cycles) of information to be accessed in read, write, or read-modify-write mode during a single RAS-low period using relatively conservative page-mode cycle times. The SMJ44C251B employs state-of-the-art technology for very high performance combined with improved reliability. For surface mount technology, the SMJ44C251B is offered in a 28-pin J-leaded chip carrier package (HJ suffix) or a 28-pin leadless ceramic chip carrier package (HM suffix). The SMJ44C251B is offered in a 28-pin 400-mil dual-in-line ceramic sidebrazed package (JD suffix) or a 28-pin ZIP ceramic package (SV suffix) for through-hole insertion. The L suffix device is rated for operation from 0°C to 70°C. The M suffix device is rated for operation from – 55°C to 125°C. The SMJ44C251B and other multiport video RAMs are supported by a broad line of video/graphic processors from Texas Instruments, including the SMJ34010 and the SMJ34020 graphics processors. functional block diagram Column Decoder Sense Amplifier Split Register ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ Data Transfer Gate Serial Data Register Serial Data Pointer W/B Unlatch W/B Latch Address Mask Write- Per-Bit Control MUX QSF DQ0 DQ1 DQ2 DQ3 DSF SDQ0 SDQ1 SDQ2 SDQ3 VCC RAS CAS TRG W SC SE VSS O u t p u t B u f f e r I n p u t B u f f e r I n p u t B u f f e r S p e c i a l F u n c t i o n L o g i c S e r i a l O u t p u t B u f f e r C o l o r R e g i s t e r S e r i a l I n p u t B u f f e r R o w D e c o d e r C o l u m n B u f f e r R o w B u f f e r R e f r e s h C o u n t e r T i m i n g G e n e r a t o r S e r i a l A d d r e s s C o u n t e r

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FALL ADDRESS DQ0–DQ3 TYPE †FUNCTION CAS TRG W ‡ DSF SE DSF RAS CAS RAS CAS § W TYPE † CBR refresh L X X X X X X X X X R Register-to-memory transfer (transfer write) H L L X L X Row Addr Tap Point X X T Alternate transfer write (independent of SE ) H L L H X X Row Addr Tap Point X X T Serial-write-mode enable (pseudo-transfer write) H L L L H X Refresh Addr Tap Point X X T Memory-to-register transfer (transfer read) H L H L X X Row Addr Tap Point X X T Split-register-transfer read (must reload tap) H L H H X X Row Addr Tap Point X X T Load and use write mask, Write data to DRAM H H L L X L Row Addr Col Addr DQ Mask Valid Data R Load and use write mask, Block write to DRAM H H L L X H Row Addr Blk Addr A2–A8 DQ Mask Col Mask R Persistent write-per-bit, Write data to DRAM H H L H X L Row Addr Col Addr X Valid Data R Persistent write-per-bit, Block write to DRAM H H L H X H Row Addr Blk Addr A2–A8 X Col Mask R Normal DRAM read/write (nonmasked) H H H L X L Row Addr Col Addr X Valid Data R Block write to DRAM (nonmasked) H H H L X H Row Addr Blk Addr A2–A8 X Col Mask R Load write mask H H H H X L Refresh Addr X X DQ Mask R Load color register H H H H X H Refresh Addr X X Color Data R Legend: H = High L = Low X = Don’t care † R = random access operation; T = transfer operation ‡ In persistent write-per-bit function, W must be high during the refresh cycle. § DQ0–DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled DQ Mask = H: Write to I/O enabled

Depending on the type of operation chosen, the signals of the SMJ44C251B perform different functions. Table 1 summarizes the signal descriptions and the operational modes they control. Table 1. Detailed Signal Description Versus Operational Mode NC/GND Make no external connection or tie to system VSS . used to control these operations are described here, followed by discussions of the operations themselves. must be stable on or before the falling edges of RAS and CAS. to invoke DRAM and transfer functions. CAS is a control input that latches the states of column address and DSF to control DRAM and transfer functions. When CAS is brought low during a transfer cycle, it latches the new tap point for the serial-data input or output. CAS also acts as an output enable for the DRAM outputs DQ0–DQ3.

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output enable/transfer select (TRG) TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM outputs DQ0–DQ3. For transfer operation, TRG must be brought low before RAS falls. write-mask select, write enable (W) In DRAM operation, W enables data to be written to the DRAM. W is also used to select the DRAM write-per-bit mode. Holding W low on the falling edge of RAS invokes the write-per-bit operation. The SMJ44C251B supports both the normal write-per-bit mode and the persistent write-per-bit mode. For transfer operation, W selects either a read-transfer operation (DRAM to SAM) or a write-transfer operation (SAM to DRAM). During a transfer cycle, if W is high when RAS falls, a read transfer occurs; if W is low, a write transfer occurs. special function select (DSF) DSF is latched on the falling edge of RAS or CAS, similar to an address. DSF determines which of the following functions are invoked on a particular cycle: /C0068Persistent write-per-bit /C0068Block write /C0068Split-register transfer read /C0068Mask-register load for the persistent write-per-bit mode /C0068Color-register load for the block-write mode DRAM data I/O, write-mask data (DQ0–DQ3) DRAM data is written via DQ terminals during a write or read-modify-write cycle. In an early-write cycle, W is brought low prior to CAS and the data is strobed in by CAS with data setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, W is brought low after CAS and the data is strobed in by W with data setup and hold times referenced to this signal. The 3-state DQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state as long as CAS and TRG are held high. Data does not appear at the outputs until both CAS and TRG are brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS or TRG going high returns the outputs to the high-impedance state. In a register-transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. The write-per-bit mask is latched into the device via the random DQ terminals by the falling edge of RAS . This mask selects which of the four random I/Os are written. serial data I/O (SDQ0–SDQ3) Serial inputs and serial outputs share common I/O terminals. Serial-input or serial-output mode is determined by the previous transfer cycle. If the previous transfer cycle was a read transfer, the data register is in serial-output mode. While in serial-output mode, data in SAM is accessed from the least significant bit to the most significant bit. The data registers operate modulo 512; so after bit 511 is accessed, the next bits to be accessed are 00, 01, 02, etc. If the previous transfer cycle was either a write transfer or a pseudo transfer, the data register is in serial-input mode and signal data can be input to the register. serial clock (SC) Serial data is accessed in or out of the data register on the rising edge of SC. The SMJ44C251B is designed to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency.

SGMS058A – MARCH 1995 – REVISED JUNE 1995 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 serial enable (SE) During serial-access operations SE is used as an enable/disable for SDQ in both the input and output modes. If SE is held as RAS falls during a write-transfer cycle, a pseudo-transfer write occurs. There is no actual transfer, but the data register switches from the output mode to the input mode. no connect/ground (NC/GND) NC/GND is reserved for the manufacturer’s test operation. It is an input and should be tied to system ground or left floating for proper device operation. special function output (QSF) During split-register operation the QSF output indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of SAM. When QSF is high, the serial-address pointer is accessing the higher (most significant) 256 bits of SAM. QSF changes state upon crossing the boundary between the two SAM halves in the split-register mode. During normal transfer operations QSF changes state upon completing a transfer cycle. This state is determined by the tap point being loaded during the transfer cycle. power up To achieve proper device operation, an initial pause of 200 µs is required after power-up, followed by a minimum of eight RAS cycles or eight CBR cycles, a memory-to-register transfer cycle, and two SC cycles.

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The random-access operation functions are summarized in Table 2 and described in the following sections. Table 2. Random-Access-Operation Functions must be high during the refresh cycle. ‡ DQ0–DQ3 are latched on the later of W or CAS falling edge. columns that can be accessed. (access time from CAS low), if ta(CA) max (access time from column address) has been satisfied.

SGMS058A – MARCH 1995 – REVISED JUNE 1995 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 RAS -only refresh A refresh operation must be performed to each row at least once every 8 ms to retain data. Unless CAS is applied, the output buffers are in the high-impedance state, so the RAS-only refresh sequence avoids any output during refresh. Externally generated addresses must be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power. CAS -before-RAS (CBR) refresh CBR refresh is accomplished by bringing CAS low earlier than RAS. The external row address is ignored and the refresh row address is generated internally when using CBR refresh. Other cycles can be performed in between CBR cycles without disturbing the internal address generation. hidden refresh A hidden refresh is accomplished by holding CAS low in the DRAM-read cycle and cycling RAS. The output data of the DRAM-read cycle remains valid while the refresh is being carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh. write-per-bit The write-per-bit feature allows masking of any combination of the four DQs on any write cycle (see Figure 1). The write-per-bit operation is invoked only when W is held low on the falling edge of RAS. If W is held high on the falling edge of RAS, write-per-bit is not enabled and the write operation is performed to all four DQs. The SMJ44C251B offers two write-per-bit modes: the nonpersistent write-per-bit mode and the persistent write-per-bit mode. nonpersistent write-per-bit When DSF is low on the falling edge of RAS, the write mask is reloaded. A 4-bit code (the write-per-bit mask) is input to the device via the random DQ terminals and latched on the falling edge of RAS. The write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS has latched the on-chip write-per-bit mask, input data is driven onto the DQ terminals and is latched on the later falling edge of CAS or W . When a data low is strobed into a particular I/O on the falling edge of RAS, data is not written to that I/O. When a data high is strobed into a particular I/O on the falling edge of RAS, data is written to that I/O. persistent write-per-bit When DSF is high on the falling edge of RAS, the write-per-bit mask is not reloaded: it retains the value stored during the last write-per-bit mask reload. This mode of operation is known as persistent write-per-bit because the write-per-bit mask is persistent over an arbitrary number of write cycles. The write-per-bit mask reload can be done during the nonpersistent write-per-bit cycle or by the mask-register-load cycle.

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Figure 1. Example of Write-Per-Bit Operations is lost or until another load-color-register cycle is executed. cycle in the block-write mode.

† W must be low during the block-write cycle. NOTE: DQ0–DQ3 are latched on the later of W or CAS falling edge except in block 6 (see legend).

1. DQ-mask data. DQ0–DQ3 are latched on the falling edge of RAS

Figure 2. Example Block-Write Diagram Operations Figure 3. Block-Write Circuit Block Diagram

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Figure 4. Example of Block Write Operation With DQ Mask and Address Mask Figure 5. Block Diagram Showing One Random and One Serial-I/O Interface

mode. No actual data transfer takes place between the DRAM and the SAM. Table 3. Transfer-Operation Functions write-transfer operations: normal-write transfer, alternate-write transfer, and pseudo-write transfer. All write-transfer cycles switch the serial port to the serial-in mode. A normal-write transfer cycle loads the contents of the serial-data register to a selected row in the memory array. tap points in SAM that are available for the next serial input.

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Figure 6. Normal-Write-Transfer-Cycle Timing alternate-write transfer occurs. port from the serial-out (read) mode to the serial-in (write) mode. , selects one of the 512 tap points in the SAM that are available for the next serial input. read-transfer operations: normal-read transfer and split-register-read transfer. to select one of the SAM’s 512 available tap points where the serial data is read out. the read-transfer cycle (see Figure 7).

Figure 7. Normal-Read-Transfer Timings be loaded from the memory array. logic high, the high half is transferred. SAM locations 255 and 511 cannot be used as tap points. normal-read-transfer cycle. The tap point loaded during the current transfer cycle determines the state of QSF. reached (see Figure 8 and Figure 9).

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Figure 8. Example of a Split-Register Read-Transfer Cycle After a Normal Read-Transfer Cycle Figure 9. A Split-Register Read-Transfer Cycle After a Split-Register Read-Transfer Cycle

pseudo-write-transfer operation, the SAM port is in the input mode. significant bit (bit 0) (see Figure 10). Figure 10. Serial Pointer Direction for Serial Read/Write points next to bit 256 or bit 0, respectively (see Figure 11, Case II). Figure 11. Serial Pointer for Split-Register Read

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VSS Supply voltage 0 V VIH High-level input voltage 2.9 6.5 V VIL Low-level input voltage (see Note Note 2) –1 0.6 V TA O perating free air temperature L suffix 0 70 °CTA Operating free-air temperature M suffix – 55 125 TC O perating case temperature L suffix 70 °CTC Operating case temperature M suffix 125 NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

SGMS058A – MARCH 1995 – REVISED JUNE 1995 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage IOH = –5 mA 2.4 V VOL Low-level output voltage (see Note 3) IOL = 4.2 mA 0.4 V II Input leakage current VCC = 5 V, V I = 0 V to 5.8 V, All others open ± 10 µA IO Output leakage current (see Note 4) VCC = 5.5 V, VO = 0 V to VCC ± 10 µA NOTES: 3. The SMJ44C251B may exhibit simultaneous switching noise as described in the Texas Instruments Advanced CMOS Logic Designer’s Handbook. This phenomenon is exhibited on the DQ terminals when the SDQ terminals are switched and on the SDQ terminals when the DQ terminals are switched. This may cause VOL and VOH to exceed the data-book limit for a short period of time, depending upon output loading and temperature. Care should be taken to provide proper termination, decoupling, and layout of the device to minimize simultaneous switching effects. 4. SE is disabled for SDQ output leakage tests. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER (SEE NOTE 5) TEST CONDITIONS † SAM ’44C251B-10 ’44C251B-12 UNITPARAMETER (SEE NOTE 5) TEST CONDITIONS † PORT MIN MAX MIN MAX UNIT ICC1 Operating current tc(rd) and tc(W) = MIN Standby 100 90 ICC1A Operating current tc(SC) = MIN Active 110 100 ICC2 Standby current All clocks = VCC Standby 15 15 ICC2A Standby current tc(SC) = MIN Active 35 35 ICC3 RAS -only refresh current tc(rd) and tc(W) = MIN Standby 100 90 ICC3A RAS -only refresh current tc(SC) = MIN Active 110 100 mA ICC4 Page-mode current tc(P) = MIN Standby 65 60 mA ICC4A Page-mode current tc(SC) = MIN Active 70 65 ICC5 CAS -before-RAS current tc(rd) and tc(W) = MIN Standby 90 80 ICC5A CAS -before-RAS current tc(SC) = MIN Active 110 100 ICC6 Data-transfer current tc(rd) and tc(W) = MIN Standby 100 90 ICC6A Data-transfer current tc(SC) = MIN Active 110 100 † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. NOTE 5: ICC (standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for ICC2 ). ICCA (active) denotes that the SAM port is active and the DRAM port is active (except for ICC2 ). ICC is measured with no load on DQ or SDQ.

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A8 7 pF C i(RC) Input capacitance, CAS and RAS 7 pF C o(O) Output capacitance, SDQs and DQs 9 pF C o(QSF) Output capacitance, QSF 9 pF NOTE 6: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal applied to the terminal under test. All other terminals are open. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7) PARAMETER TEST ALT. ’44C251B-10 ’44C251B-12 UNITPARAMETER CONDITIONS † SYMBOL MIN MAX MIN MAX UNIT ta(C) Access time from CAS td(RLCL) = MAX tCAC 25 30 ns ta(CA) Access time from column address td(RLCL) = MAX tAA 50 60 ns ta(CP) Access time from CAS high td(RLCL) = MAX tCPA 55 65 ns ta(R) Access time from RAS td(RLCL) = MAX tRAC 100 120 ns ta(G) Access time of DQ0–DQ3 from TRG low tOEA 25 30 ns ta(SQ) Access time of SDQ0–SDQ3 from SC high C L = 30 pF tSCA 30 35 ns ta(SE) Access time of SDQ0–SDQ3 from SE low C L = 30 pF tSEA 20 25 ns tdis(CH) Disable time, random output from CAS high (see Note 8) C L = 100 pF tOFF 0 20 0 20 ns tdis(G) Disable time, random output from TRG high (see Note 8) C L = 100 pF tOEZ 0 20 0 20 ns tdis(SE) Disable time, serial output from SE high (see Note 8) C L = 30 pF tSEZ 0 20 0 20 ns † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. NOTES: 7. Switching times assume CL = 100 pF unless otherwise noted (see Figure 12). 8. tdis(CH), tdis(G), and tdis(SE) are specified when the output is no longer driven.

SGMS058A – MARCH 1995 – REVISED JUNE 1995 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature† ALT. ’44C251B-10 ’44C251B-12 UNITSYMBOL MIN MAX MIN MAX UNIT tc(rd) Cycle time, read (see Note 9) tRC 190 220 ns tc(W) Cycle time, write (see Note 9) tWC 190 220 ns tc(rdW) Cycle time, read-modify-write (see Note 9) tRMW 250 290 ns tc(P) Cycle time, page-mode read or write (see Note 9) tPC 60 70 ns tc(rdWP) Cycle time, page-mode read-modify-write (see Note 9) tPRMW 105 125 ns tc(TRD) Cycle time, read transfer (see Note 9) tRC 190 220 ns tc(TW) Cycle time, write transfer (see Note 9) tWC 190 220 ns tc(SC) Cycle time, serial clock (see Notes 9 and 10) tSCC 30 35 ns tw(CH) Pulse duration, CAS high tCPN 20 30 ns tw(CL) Pulse duration, CAS low (see Note 11) tCAS 25 75000 30 75000 ns tw(RH) Pulse duration, RAS high tRP 80 90 ns tw(RL) Pulse duration, RAS low (see Note 12) tRAS 100 75000 120 75000 ns tw(WL) Pulse duration, W low tWP 25 25 ns tw(TRG) Pulse duration, TRG low 25 30 ns tw(SCH) Pulse duration, SC high tSC 10 12 ns tw(SCL) Pulse duration, SC low tSCP 10 12 ns tw(SEL) Pulse duration, SE low tSE 35 40 ns tw(SEH) Pulse duration, SE high tSEP 35 40 ns tw(GH) Pulse duration, TRG high tTP 30 30 ns tw(RL)P Pulse duration, RAS low (page mode) 100 75000 120 75000 ns tsu(CA) Setup time, column address tASC 0 0 ns tsu(SFC) Setup time, DSF before CAS low tFSC 0 0 ns tsu(RA) Setup time, row address tASR 0 0 ns tsu(WMR) Setup time, W before RAS low tWSR 0 0 ns tsu(DQR) Setup time, DQ before RAS low tMS 0 0 ns tsu(TRG) Setup time, TRG before RAS low tTHS 0 0 ns tsu(SE) Setup time, SE before RAS low (see Note 13) tESR 0 0 ns tsu(SESC) Setup time, serial write disable tSWIS 10 15 ns tsu(SFR) Setup time, DSF before RAS low tFSR 0 0 ns tsu(DCL) Setup time, data before CAS low tDSC 0 0 ns tsu(DWL) Setup time, data before W low tDSW 0 0 ns tsu(rd) Setup time, read command tRCS 0 0 ns tsu(WCL) Setup time, early write command before CAS low tWCS 0 0 ns † Timing measurements are referenced to VIL max and VIH min. NOTES: 9. All cycle times assume tt = 5 ns. 10. When the odd tap is used (tap address can be 0–511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first serial data out cycle needs to be 70 ns minimum. 11. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this may require additional CAS low time [tw(CL)]. 12. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this may require additional RAS low time [tw(RL)]. 13. Register-to-memory (write) transfer cycles only

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)† ALT. ’44C251B-10 ’44C251B-12 UNITSYMBOL MIN MAX MIN MAX UNIT tsu(WCH) Setup time, write before CAS high tCWL 25 30 ns tsu(WRH) Setup time, write before RAS high with TRG = W = low tRWL 25 30 ns tsu(SDS) Setup time, SDQ before SC high tSDS 0 0 ns th(CLCA) Hold time, column address after CAS low tCAH 20 20 ns th(SFC) Hold time, DSF after CAS low tCFH 20 20 ns th(RA) Hold time, row address after RAS low tRAH 15 15 ns th(TRG) Hold time, TRG after RAS low tTLH 15 15 ns th(SE) Hold time, SE after RAS low with TRG = W = low (see Note 13) tREH 15 15 ns th(RWM) Hold time, write mask, transfer enable after RAS low tRWH 15 15 ns th(RDQ) Hold time, DQ after RAS low (write-mask operation) tMH 15 15 ns th(SFR) Hold time, DSF after RAS low tRFH 15 15 ns th(RLCA) Hold time, column address after RAS low (see Note 14) tAR 45 45 ns th(CLD) Hold time, data after CAS low tDH 20 25 ns th(RLD) Hold time, data after RAS low (see Note 14) tDHR 45 50 ns th(WLD) Hold time, data after W low tDH 20 25 ns th(CHrd) Hold time, read after CAS high (see Note 15) tRCH 0 0 ns th(RHrd) Hold time, read after RAS high (see Note 15) tRRH 10 10 ns th(CLW) Hold time, write after CAS low tWCH 30 35 ns th(RLW) Hold time, write after RAS low (see Note 14) tWCR 50 55 ns th(WLG) Hold time, TRG after W low (see Note 16) tOEH 25 30 ns th(SDS) Hold time, SDQ after SC high tSDH 5 5 ns th(SHSQ) Hold time, SDQ after SC high tSOH 5 5 ns th(RSF) Hold time, DSF after RAS low tFHR 45 45 ns th(SCSE) Hold time, serial-write disable tSWIH 20 20 ns td(RLCH) Delay time, RAS low to CAS high tCSH 100 120 ns td(CHRL) Delay time, CAS high to RAS low tCRP 0 0 ns td(CLRH) Delay time, CAS low to RAS high tRSH 25 30 ns td(CLWL) Delay time, CAS low to W low (see Notes 17 and 18) tCWD 55 65 ns td(RLCL) Delay time, RAS low to CAS low (see Note 19) tRCD 25 75 25 90 ns td(CARH) Delay time, column address to RAS high tRAL 50 60 ns td(RLWL) Delay time, RAS low to W low (see Note 17) tRWD 130 155 ns td(CAWL) Delay time, column address to W low (see Note 17) tAWD 85 100 ns † Timing measurements are referenced to VIL max and VIH min. NOTES: 13. Register-to-memory (write) transfer cycles only 14. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference. 15. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle. 16. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 17. Read-modify-write operation only 18. TRG must disable the output buffers prior to applying data to the DQ terminals. 19. The maximum value is specified only to assure RAS access time.

SGMS058A – MARCH 1995 – REVISED JUNE 1995 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)† ALT. ’44C251B-10 ’44C251B-12 UNITSYMBOL MIN MAX MIN MAX UNIT td(RLCH)RF Delay time, RAS low to CAS high (see Note 20) tCHR 25 25 ns td(CLRL)RF Delay time, CAS low to RAS low (see Note 20) tCSR 10 10 ns td(RHCL)RF Delay time, RAS high to CAS low (see Note 20) tRPC 10 10 ns td(CLGH) Delay time, CAS low to TRG high for DRAM read cycles 25 30 ns td(GHD) Delay time, TRG high before data applied at DQ tOED 25 30 ns td(RLTH) Delay time, RAS low to TRG high (real-time-reload read-transfer cycle only) tRTH 90 95 ns td(RLSH) Delay time, RAS low to first SC high after TRG high (see Note 21) tRSD 130 140 ns td(CLSH) Delay time, CAS low to first SC high after TRG high (see Note 21) tCSD 40 45 ns td(SCTR) Delay time, SC high to TRG high (see Notes 21, 22, and 23) tTSL 15 20 ns td(THRH) Delay time, TRG high to RAS high (see Notes 22 and 23) tTRD –10 –10 ns td(SCRL) Delay time, SC high to RAS low with TRG = W = low (see Notes 13, 24, and 25) tSRS 10 20 ns td(SCSE) Delay time, SC high to SE high in serial-input mode 20 20 ns td(RHSC) Delay time, RAS high to SC high (see Note 13) tSRD 25 30 ns td(THRL) Delay time, TRG high to RAS low (see Note 26) tTRP tw(RH) tw(RH) ns td(THSC) Delay time, TRG high to SC high (see Notes 22 and 23) tTSD 35 40 ns td(SESC) Delay time, SE low to SC high (see Note 27) tSWS 10 15 ns td(RHMS) Delay time, RAS high to last (most significant) rising edge of SC before boundary switch during split-register read-transfer cycles 15 20 ns td(CLGH) Delay time, CAS low to TRG high in real-time read-transfer cyclestCTH 5 5 ns td(CASH) Delay time, column address to first SC in early-load read-transfer cyclestASD 45 50 ns td(CAGH) Delay time, column address to TRG high in real-time read-transfer cycles tATH 10 10 ns td(RLCA) Delay time, RAS low to column address (see Note 19) tRAD 15 50 15 60 ns td(DCL) Delay time, data to CAS low tDZC 0 0 ns td(DGL) Delay time, data to TRG low tDZO 0 0 ns td(RLSD) Delay time, RAS low to serial-input data tSDD 50 50 ns td(GLRH) Delay time, TRG low to RAS high tROH 25 30 ns † Timing measurements are referenced to VIL max and VIH min. NOTES: 13. Register-to-memory (write) transfer cycles only 19. The maximum value is specified only to assure RAS access time. 20. CAS -before-RAS refresh operation only 21. Early-load read-transfer cycle only 22. Real-time-reload read-transfer cycle only 23. Late-load read-transfer cycle only 24. In a read-transfer cycle, the state of SC when RAS falls is a don’t care condition. However, to assure proper sequencing of the internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS goes low. 25. In a memory-to-register (read) transfer cycle, td(SCRL) applies only when the SAM was previously in serial-input mode. 26. Memory-to-register (read) and register-to-memory (write) transfer cycles only 27. Serial data-in cycles only

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† Timing measurements are referenced to VIL max and VIH min. NOTE 7: Switching times assume CL = 100 pF unless otherwise noted (see Figure 12). Figure 12. Load Circuit

Figure 13. Read-Cycle Timing

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Figure 14. Early-Write-Cycle Timing Table 4. Write-Cycle State Table

Figure 15. Delayed-Write-Cycle Timing (Output-Enable-Controlled Write) Table 5. Write-Cycle State Table

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12 Don’t Care

4 Valid

Figure 16. Read-Write/Read-Modify-Write-Cycle Timing Table 6. Write-Cycle State Table

† Access time is ta(CP) or ta(CA) dependent. ‡ Output can go from the high-impedance state to an invalid data state prior to the specified access time. Figure 17. Enhanced-Page-Mode Read-Cycle Timing

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Figure 18. Enhanced-Page-Mode Write-Cycle Timing Table 7. Write-Cycle State Table

45 Valid

† Output can go from the high-impedance state to an invalid data state prior to the specified access time. NOTE A: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated. Figure 19. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing Table 8. Write-Cycle State Table

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Figure 20. Load-Color-Register-Cycle Timing (Early-Write Load)

Figure 21. Load-Color-Register-Cycle Timing (Delayed-Write Load)

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Figure 22. Block-Write-Cycle Timing (Early Write) Table 9. Block-Write-Cycle State Table

Figure 23. Block-Write-Cycle Timing (Delayed-Write) Table 10. Block-Write-Cycle State Table

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the early-write-cycle timing is used, the state of TRG is a don’t care after the minimum period th(TRG) from the falling edge of RAS. Figure 24. Enhanced-Page-Mode Block-Write-Cycle Timing Table 11. Enhanced-Page-Mode Block-Write-Cycle Table

NOTE A: In persistent write-per-bit function, W must be high at the falling edge of RAS during the refresh cycle. Figure 25. RAS-Only Refresh-Cycle Timing

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NOTE A: In persistent write-per-bit operation, W must be high at the falling edge of RAS during the refresh cycle. Figure 26. CBR-Refresh-Cycle Timing

Figure 27. Hidden-Refresh-Cycle Timing

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into the data register. This figure assumes that the device was originally in the serial-read mode. Figure 28. Write-Mode-Control Pseudo-Transfer Timing

Figure 29. Data-Register-to-Memory Transfer Timing, Serial Input Enabled

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Figure 30. Alternate Data-Register-to-Memory Transfer-Cycle Timing

NOTES: A. Early-load operation is defined as th(TRG) min < th(TRG) < td(RLTH) min. out or transferred back into another row. Figure 31. Memory-to-Data-Register Transfer-Cycle Timing, Early-Load Operation

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NOTES: A. Late-load operation is defined as td(THRH) < 0 ns. out or transferred back into another row. Figure 32. Memory-to-Data-Register Transfer-Cycle Timing,

NOTES: A. Late-load operation is defined as td(THRH) < 0 ns. out or transferred back into another row. Figure 33. Memory-to-Data-Register Transfer-Cycle Timing, SDQ Ports Previously in Serial-Input Mode

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Figure 34. Split-Register-Mode Read-Transfer-Cycle Timing

(CASE III). There is no minimum requirement of SC clock between the normal read-transfer cycle and the first split-register cycle. Figure 35. Split-Register-Transfer Operating Sequence

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to prevent data transfers between memory and data registers. Figure 36. Serial-Write-Cycle Timing (SE = VIL)

to prevent data transfers between memory and data registers. Figure 37. Serial-Write-Cycle Timing (SE-Controlled Write)

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low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation. subsequent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data. Figure 38. Serial-Read-Cycle Timing (SE = VIL)

low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation. subsequent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data. Figure 39. Serial-Read-Cycle Timing (SE-Controlled Read)

SGMS058A – MARCH 1995 – REVISED JUNE 1995

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