SMJ416160

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SMJ416160, SMJ418160

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORIES SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization...1 0 4 8 5 7 6 b y 1 6 Bits /C0068Single 5-V Power Supply (±10% Tolerance) /C0068Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tCAC tAA CYCLE MAX MAX MAX MIN ’41x160-70 70 ns 18 ns 35 ns 130 ns ’41x160-80 80 ns 20 ns 40 ns 150 ns /C0068Enhanced Page-Mode Operation for Faster Memory Access /C0068CAS -Before-RAS (CBR) Refresh /C0068Long Refresh Period – ’416160 – 4096-Cycle Refresh in 32 ms (Maximum) – ’418160 – 1024-Cycle Refresh in 8 ms (Maximum) /C00683-State Unlatched Output /C0068Low Power Dissipation /C0068All Inputs/Outputs Are TTL Compatible /C0068Packaging 50-Lead, 650-Mil-Wide Ceramic Flatpack /C0068Operating Free-Air Temperature Range –55°C to 125°C

description

The SMJ41x160 series is a set of 16777216-bit dynamic random-access memories (DRAMs) organized as 1048576 words of 16 bits each. They employ state-of-the-art technology for high performance, reliability, and low power at low cost. These devices feature maximum RAS access times of 70 ns and 80 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The SMJ41x160 series is offered in a 50-lead, 650-mil-wide ceramic flatpack and is character- ized for operation from –55°C to 125°C. PIN NOMENCLATURE A0–A11 Address Inputs DQ0–DQ15 Data In/Data Out LCAS Lower Column-Address Strobe UCAS Upper Column-Address Strobe NC No Internal Connection OE Output Enable RAS Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable VSS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 NC NC NC NC NC LCAS UCAS OE V SS VCC DQ0 DQ1 DQ2 DQ3 V CC DQ4 DQ5 DQ6 DQ7 NC NC NC NC NC NC W RAS A11† A10† V CC HKD PACKAGE (TOP VIEW) † A10 and A11 are NC for SMJ418160. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SMJ416160, SMJ418160 DYNAMIC RANDOM-ACCESS MEMORIES SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997

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logic symbol† DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 RAS LCAS UCAS W RAM 1M × 16 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21 G24 23C22 A,22D A8 31 C21 G34 Z31 24,25EN27 34,25EN37 23C32 23,21D ∇ 26,27 A, Z26 A,32D ∇ 36,37 A, Z36 OE A 0 1 048 575 A9 32 20D15/21D7 20D16 20D17 20D8/21D0 A10 ‡ 20 A11‡ 19 20D18 20D19 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. ‡ A10 and A11 are NC for SMJ418160.

SMJ416160, SMJ418160 DYNAMIC RANDOM-ACCESS MEMORIES SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ’416160 functional block diagram Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array DQ0–DQ15 RAS UCAS W OELCAS 16 of 32 Selection32 A8– A11 ’418160 functional block diagram Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array DQ0–DQ15 RAS UCAS W OELCAS 16 of 32 Selection32

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Two CAS pins (LCAS and UCAS ) are provided to give independent control of the 16 data-I/O pins (DQ0–DQ15), with LCAS corresponding to DQ0–DQ7 and UCAS corresponding to DQ8–DQ15. For read or write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge. All address-setup and -hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out (see parameter tCAC ) is measured from each individual xCAS to its corresponding DQx pin. In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see parameter tCP ) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH . During tCLCH , at least one xCAS must be brought low before the other xCAS is taken high. For early-write cycles, the data is latched on the first xCAS falling edge. Only the DQs that have the corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet tCP . enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the first xCAS latches the column addresses. This feature allows the device to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when xCAS goes low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after row-address hold time (tRAH ) has been satisfied, usually well in advance of the falling edge of xCAS. In this case, data is obtained after access time from xCAS low (tCAC ) maximum if access time from column address (tAA ) maximum has been satisfied. In the event that column addresses for the next page cycle are valid at the time xCAS goes high, minimum-access time for the next cycle is determined by access time from rising edge of the last xCAS (tCPA ). address: A0–A11 (’416160) and A0–A9 (’418160) Twenty address bits are required to decode one of the 1048576 storage-cell locations. For the SMJ416160, 12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits are set up on A0 through A7 and latched onto the chip by the first xCAS. For the SMJ418160, ten row-address bits are set up on A0–A9 and latched onto the chip by RAS. Ten column-address bits are set up on A0–A9 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS . RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the column-address buffers. write enable (W) The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded.

SMJ416160, SMJ418160 DYNAMIC RANDOM-ACCESS MEMORIES SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 data in (DQ0–DQ15) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS and the data is strobed in by the first xCAS occurrence with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, xCAS is low already and the data is strobed in by W with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. data out (DQ0–DQ15) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access-time interval tCAC . tCAC begins with the negative transition of xCAS as long as tRAC and tAA are satisfied. output enable (OE) OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the low-impedance state, and they remain in the low-impedance state until either OE or xCAS is brought high. RAS -only refresh ’416160 A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing each of the 4096 rows (A0–A11). A normal-read or -write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. RAS -only refresh ’418160 A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing each of the 1024 rows (A0–A9). A normal-read or -write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally. xCAS -before-RAS (xCBR) refresh xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR ) and holding it low after RAS falls (see parameter tCHR ). For successive xCBR refresh cycles, xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh (RAS -only or xCBR) cycle.

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VSS Supply voltage 0 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) –1 0.8 V TA Operating free-air temperature – 55 125 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

SMJ416160, SMJ418160 DYNAMIC RANDOM-ACCESS MEMORIES SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SMJ416160 PARAMETER TEST CONDITIONS † ’416160-70 ’416160-80 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , xCAS high ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VCC = 5.5 V, Minimum cycle 80 70 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and xCAS high 2 2 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and xCAS high 1 1 mA ICC3 § Average refresh current (RAS only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, xCAS high (RAS only), RAS low after xCAS low (CBR) 80 70 mA ICC4 ‡¶ Average page current VCC = 5.5 V, t PC = MIN, RAS low, xCAS cycling 80 70 mA ICC7 ‡¶ Standby current, outputs enabled RAS = VIH, xCAS = VIL, Data out = enabled 5 5 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while xCAS = VIH

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) SMJ418160 PARAMETER TEST CONDITIONS † ’418160-70 ’418160-80 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , xCAS high ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VCC = 5.5 V, Minimum cycle 180 170 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and xCAS high 2 2 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and xCAS high 1 1 mA ICC3 § Average refresh current (RAS only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, xCAS high (RAS only), RAS low after xCAS low (CBR) 180 170 mA ICC4 ‡¶ Average page current VCC = 5.5 V, t PC = MIN, RAS low, xCAS cycling 180 170 mA ICC7 ‡¶ Standby current, outputs enabled RAS = VIH, xCAS = VIL, Data out = enabled 5 5 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while xCAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A11# 8 pF C i(OE) Input capacitance, OE 8 pF C i(RC) Input capacitance, xCAS and RAS 8 pF C i(W) Input capacitance, W 8 pF C o Output capacitance 10 pF # A10 and A11 are NC for SMJ418160. NOTE 3: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25°C with a 1-MHz signal applied to the pin under test. All other pins are open.

SMJ416160, SMJ418160 DYNAMIC RANDOM-ACCESS MEMORIES SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 4) PARAMETER ’41x160-70 ’41x160-80 UNITPARAMETER MIN MAX MIN MAX UNIT tAA Access time from column address 35 40 ns tCAC Access time from xCAS low 18 20 ns tCPA Access time from column precharge 40 45 ns tRAC Access time from RAS low 70 80 ns tOEA Access time from OE low 18 20 ns tOFF Output disable time after xCAS high (see Note 5) 0 18 0 20 ns tOEZ Output disable time after OE high (see Note 5) 0 18 0 20 ns NOTES: 4. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access time as the outputs are driven when xCAS and OE are low. 5. tOFF and tOEZ are specified when the output is no longer driven. The outputs are disabled by bringing either OE or xCAS high. timing requirements ’41x160-70 ’41x160-80 UNIT MIN MAX MIN MAX UNIT tRC Cycle time, read (see Note 6) 130 150 ns tWC Cycle time, write (see Note 6) 130 150 ns tRWC Cycle time, read-write (see Note 6) 181 205 ns tPC Cycle time, page-mode read or write (see Notes 6 and 7) 45 50 ns tPRWC Cycle time, page-mode read-write (see Note 6) 96 105 ns tRASP Pulse duration, RAS low, page mode (see Note 8) 70 100 000 80 100 000 ns tRAS Pulse duration, RAS low, nonpage mode (see Note 8) 70 10 000 80 10 000 ns tCAS Pulse duration, xCAS low (see Note 9) 18 10 000 20 10 000 ns tRP Pulse duration, RAS high (precharge) 50 60 ns tWP Pulse duration, W low 10 10 ns tASC Setup time, column address before xCAS going low 0 0 ns tASR Setup time, row address before RAS going low 0 0 ns tDS Setup time, data (see Note 10) 0 0 ns tRCS Setup time, W high before xCAS going low 0 0 ns tCWL Setup time, W low before xCAS going high 18 20 ns tRWL Setup time, W low before RAS going high 18 20 ns tWCS Setup time, W low before xCAS going low (early-write operation only) 0 0 ns tCAH Hold time, column address after xCAS low 15 15 ns tDH Hold time, data (see Note 10) 15 15 ns tRAH Hold time, row address after RAS low 10 10 ns tRCH Hold time, W high after xCAS high (see Note 11) 0 0 ns tRRH Hold time, W high after RAS high (see Note 11) 0 0 ns tWCH Hold time, W low after xCAS low (early-write operation only) 15 15 ns NOTES: 6. All cycle times assume tT = 5 ns, referenced to VIH(MIN) and VIL(MAX). 7. To assure tPC min, tASC should be ≥ to tCP . 8. In a read-write cycle, tRWD and tRWL must be observed. 9. In a read-write cycle, tCWD and tCWL must be observed. 10. Referenced to the later of xCAS or W in write operations 11. Either tRRH or tRCH must be satisfied for a read cycle.

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timing requirements (continued) ’41x160-70 ’41x160-80 UNIT MIN MAX MIN MAX UNIT tCLCH Hold time, xCAS low to xCAS going high 5 5 ns tRHCP Hold time, RAS low after xCAS precharge 40 45 ns tOEH Hold time, OE command 18 20 ns tROH Hold time, RAS referenced to OE 10 10 ns tCP Delay time, xCAS high (precharge) 10 10 ns tAWD Delay time, column address to W going low (read-write operation only) 63 70 ns tCHR Delay time, RAS low to xCAS going high (CBR refresh only) 10 10 ns tCRP Delay time, xCAS high to RAS going low 5 5 ns tCSH Delay time, RAS low to xCAS going high 70 80 ns tCSR Delay time, xCAS low to RAS going low (CBR refresh only) 5 5 ns tCWD Delay time, xCAS low to W going low (read-write operation only) 46 50 ns tOED Delay time, OE to data 18 20 ns tRAD Delay time, RAS low to column address (see Note 12) 15 35 15 40 ns tRAL Delay time, column address to RAS going high 35 40 ns tCAL Delay time, column address to xCAS going high 35 40 ns tRCD Delay time, RAS low to xCAS low (see Note 12) 20 52 20 60 ns tRPC Delay time, RAS high to xCAS going low 0 0 ns tRSH Delay time, xCAS low to RAS going high 18 20 ns tRWD Delay time, RAS low to W going low (read-write operation only) 98 110 ns tCPW Delay time, W going low after xCAS precharge (read-write operation only) 68 75 ns tREF Refresh time interval ’416160 32 32 mstREF Refresh time interval ’418160 8 8 ms tT Transition time (see Note 13) 3 30 3 30 ns NOTES: 12. The maximum value is specified only to ensure access time. 13. Transition times (rise and fall) should be a minimum of 3 ns and a maximum of 30 ns. This is ensured by design but not tested.

NOTES: A. C L includes probe and fixture capacitance. for inputs; 2.4 V and 0.4 V for outputs with the given load circuit. Figure 1. Load Circuits and Voltage Waveforms

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NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. tCAC is measured from xCAS to its corresponding DQx. C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 2. Read-Cycle Timing

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Figure 3. Write-Cycle Timing

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NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Figure 4. Early-Write-Cycle Timing

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. C. tCAC is measured from xCAS to its corresponding DQx. Figure 5. Read-Modify-Write-Cycle Timing

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NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. tCAC is measured from xCAS to its corresponding DQx. C. Access time is tCPA - or tAA -dependent. D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. specifications are not violated. Figure 6. Enhanced-Page-Mode Read-Cycle Timing

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. specifications are not violated. Figure 7. Enhanced-Page-Mode Write-Cycle Timing

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NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Access time is tCPA - or tAA -dependent. C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. F. tCAC is measured from xCAS to its corresponding DQx. Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing

NOTE A: All xCAS must be high. Figure 9. RAS-Only Refresh-Cycle Timing

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Figure 10. Hidden-Refresh-Cycle Timing

NOTE A: Any xCAS can be used. Figure 11. Automatic-xCBR-Refresh-Cycle Timing

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HKD (R-CDFP-F50) CERAMIC DUAL FLATPACK 0.250 (6,35) 0.370 (9,40) 0.012 (0,30) 0.020 (0,50) Lid 4081537/B 10/95 0.026 (0,66) MIN 0.843 (21,40) 0.811 (20,60) 0.015 (0,38) MIN (4 Places) 0.766 (19,45) 0.746 (18,95) 0.110 (2,80) 0.140 (3,55) 0.004 (0,10) 0.587 (14,90) 0.555 (14,10) 0.634 (16,10) 0.665 (16,90) 0.031 (0,80) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. The leads will be gold plated.

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