SMJ320C40GFM40

SMJ320C40_08 TI | Alldatasheet

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Technical content

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068SMJ: QML Processing to MIL−PRF−38535 /C0068SM: Standard Processing /C0068TMP: Commercial Level Processing TAB /C0068Operating Temperature Ranges: − Military (M) −55°C to 125°C − Special (S) −55°C to 100°C − Commercial (C) −25°C to 85°C − Commercial (L) 0°C to 70°C /C0068Highest Performance Floating-Point Digital Signal Processor (DSP) − C40-60: 33-ns Instruction Cycle Time:

60 MFLOPS, 30 MIPS, 330 MOPS,

384 MBps

− C40-50: 40-ns Instruction Cycle Time:

50 MFLOPS, 25 MIPS, 275 MOPS,

320 MBps

− C40-40: 50-ns Instruction Cycle Time:

40 MFLOPS, 20 MIPS, 220 MOPS,

256 MBps

/C0068Six Communications Ports /C00686-Channel Direct Memory Access (DMA) Coprocessor /C0068Single-Cycle Conversion to and From IEEE-745 Floating-Point Format /C0068Single Cycle 1/x, 1/ /C0068Source-Code Compatible With SMJ320C30 /C0068Validated Ada Compiler /C0068Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers /C006812 40-Bit Registers, 8 Auxiliary Registers,

14 Control Registers, and 2 Timers

/C0068IEEE Standard 1149.1† Test-Access Port (JTAG) /C0068Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers: − High Port-Data Rate of 100 MBytes/s (Each Bus) − 16G-Byte Continuous Program/Data/Peripheral Address Space − Memory-Access Request for Fast, Intelligent Bus Arbitration − Separate Address-, Data-, and Control-Enable Pins − Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware /C0068Packaging: − 325-Pin Ceramic Grid Array (GF Suffix) − 352-Lead Ceramic Quad Flatpack (HFH Suffix) − 324-Pad JEDEC-Standard TAB Frame /C0068Fabricated Using Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments (TI) /C0068Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance /C0068On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance − 512-Byte Instruction Cache − 8K Bytes of Single-Cycle Dual-Access Program or Data RAM − ROM-Based Bootloader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories Over Any One of the Communications Ports Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright  2001, Texas Instruments Incorporated x/C0504 †IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture. EPIC and TI are trademarks of Texas Instruments Incorporated. /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

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352-LEAD HFH QUAD FLATPACK PACKAGE (TOP VIEW)† 352 265 264 177 17689 11 13 14 16 26 28 29 31 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR Pin A1 325-PIN GF GRID ARRAY PACKAGE (BOTTOM VIEW) † TAB 325-LEAD OLB/ILB TAPE AUTOMATED BONDING (TAB) PACKAGE (TOP VIEW)† † See the pin assignments tables and the signal description table for location and description of all pins.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

description

The C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-µm, double-level metal CMOS technology. The 320C40 is a part of the fourth-generation DSPs from Texas Instruments and is designed primarily for parallel processing. For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001. operation The 320C40 has six on-chip communication ports for processor-to-processor communication with no external hardware and simple communication software. This allows connectivity to other C4x processors with no external-glue logic. The communication ports remove input/output bottlenecks, and the independent smart DMA coprocessor is able to handle the CPU input/output burden. central processing unit The 320C40 CPU is configured for high-speed internal parallelism for the highest sustained performance. The key features of the CPU are: /C0068Eight operations/cycle: − 40/32-bit floating-point/integer multiply − 40/32-bit floating-point/integer arithmetic logic unit (ALU) operation − Two data accesses − Two address-register updates /C0068IEEE floating-point conversion /C0068Divide and square-root support /C0068C3x assembly language compatibility /C0068Byte and halfword accessibility DMA coprocessor The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance. The key features of the DMA processor are: /C0068Link pointers that allow DMA channels to autoinitialize without CPU intervention /C0068Parallel CPU operation and DMA transfers /C0068Six DMA channels that support memory-to-memory data transfers /C0068Split-mode operation doubles the available DMA channels to 12 when data transfers to and from a communication port are required. communication ports The C40 is the first DSP with on-chip communication ports for processor-to-processor communication with no external hardware and simple communication software. The features of the communication ports are: /C0068Direct interprocessor communication and processor I/O /C0068Six communication ports for direct interprocessor communication and processor I/O /C006820M-byte/s bidirectional interface on each communication port for high-speed multiprocessor interface

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communication-port-software reset. Table 1. Communication-Port Software-Reset Address Figure 1. Example of Communication-Port-Software Reset

with the communication-port software-reset feature. −IIOF0 pins configured as an external interrupt instead of a general-purpose I/O. /C0068The CPU, peripherals, and internal memory retain their previous state. the high-impedance state, and the output-control signals are inactive. Figure 2. Example of Software Subroutine Using IDLE2 can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped. However, the H1 and H3 clocks remain 180° out of phase with each other. interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode. instruction is not executed until after execution of a return opcode. When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction. The clocks continue to run for correct operation of the emulator.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

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The C40 is supported by a host of parallel-processing development tools for developing and simulating code easily and for debugging parallel-processing systems. The code generation tools include: /C0068An ANSI C compiler optimized with a runtime support library that supports use of communication ports and DMA. /C0068Third-party support for C, C++, and Ada compilers /C0068Several operating systems available for parallel-processing support, as well as DMA and communication port drivers /C0068An assembler and linker with support for mapping program and data to parallel processors The simulation tools include: /C0068Parallel DSP system-level simulation with LAI hardware verification (HV) model and full function (FF) model /C0068TI software simulator with high-level language debugger interface for simulating a single processor The hardware development and verification tools include: /C0068Parallel processor in-circuit emulator and high-level language debugger: XDS510 /C0068Parallel processor development system (PPDS) with four 320C40s, local and global memory, and communication port connections XDS510 is a trademark of Texas Instruments Incorporated.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 block diagram Cache (512 Bytes) 32 32 PDATA Bus DDATA Bus DADDR 1 Bus DADDR 2 Bus DMADATA Bus RAM Block 0 (4K Bytes) 32 32 RAM Block 1 (4K Bytes) 32 32 ROM Block (Reserved) 32 32 PADDR Bus DMAADDR Bus M U X D31−D0 A30−A0 DE AE STAT3−STAT0 LOCK STRB0 ,STRB1 R/W 0,RW 1 PAGE0,PAGE1 RDY0 ,RDY1 CE0 ,CE1 IR PC X2/CLKIN ROMEN RESET RESETLOC0, RESETLOC1 NMI IIOF3−IIOF0 IACK CV SS DV DD DV SS IVSS LADV DD LDDV DD VDDL VSSL SUBS C o n t r o l l e r 3232 32 40 40 32-Bit Barrel Shifter ALU Extended Precision Registers (R0−R11) 32 40 DISP , IR0, IR1 ARAU0 ARAU1 BK Auxiliary Registers (AR0−AR7) Other Registers (14) CPU1 CPU2 REG1 MUX C P U R E G Multiplier Continued on next page REG2R E G REG 1 R E G

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

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block diagram (continued) LD31−LD0 LA30−LA0 LDE LAE LSTAT3−LSTAT0 LLOCK LSTRB0 −LSTRB1 LR/W 0−LR/W 1 LPAGE0−LPAGE1 LRDY0 −LRDY1 LCE0 , LCE1 DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 DMA Coprocessor Six DMA Channels 3232 Global Local Port Control Global Control Register Time Period Register Timer 1 Timer Counter Register TCLK1 Global Control Register Time Period Register Timer 0 Timer Counter Register TCLK0 Port Control Registers Output FIFO Input FIFO PAU COM Port 0 CREQ0 CACK0 CSTRB0 CRDY0 C0D7−C0D0 P e r i p h e r a l D a t a B u s P e r i p h e r a l A d d r e s s B u s Continued from previous page Port Control Registers Output FIFO Input FIFO PAU COM Port 5 CREQ5 CACK5 CSTRB5 CRDY5 C5D7−C5D0 MUX DDATA Bus DADDR 1 Bus DADDR 2 Bus DMADATA Bus PADDR Bus DMAADDR Bus PDATA Bus M U X Six Communication Ports

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

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This section gives signal descriptions for the SMJ320C40 device. The SMJ320C40 signal descriptions table lists each signal, the number of pins, operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively), and function. All pins labeled NC are not to be connected by the user. A line over a signal name (for example, RESET ) indicates that the signal is active low (true at a logic-0 level). The signals are grouped according to functions. SMJ320C40 Signal Descriptions SIGNAL NAME NO. OF PINS TYPE † DESCRIPTION GLOBAL BUS EXTERNAL INTERFACE (80 PINS) D31−D0 32 I/O/Z 32-bit data port of the global bus external interface DE 1 I Data-bus-enable signal for the global bus external interface A30−A0 31 O/Z 31-bit address port of the global bus external interface AE 1 I Address-bus-enable signal for the global bus external interface STAT3−STAT0 4 O Status signals for the global bus external interface LOCK 1 O Lock signal for the global bus external interface STRB0 ‡ 1 O/Z Access strobe 0 for the global bus external interface R/W 0‡ 1 O/Z Read/write signal for STRB0 accesses PAGE0 ‡ 1 O/Z Page signal for STRB0 accesses RDY0 ‡ 1 I Ready signal for STRB0 accesses CE0 ‡ 1 I Control enable for the STRB0, PAGE0, and R/W0 signals STRB1 ‡ 1 O/Z Access strobe 1 for the global bus external interface R/W 1‡ 1 O/Z Read/write signal for STRB1 accesses PAGE1 ‡ 1 O/Z Page signal for STRB1 accesses RDY1 ‡ 1 I Ready signal for STRB1 accesses CE1 ‡ 1 I Control enable for the STRB1, PAGE1, and R/W1 signals LOCAL BUS EXTERNAL INTERFACE (80 PINS) LD31−LD0 32 I/O/Z 32-bit data port of the local bus external interface LDE 1 I Data-bus-enable signal for the local bus external interface LA30−LA0 31 O/Z 31-bit address port of the local bus external interface LAE 1 I Address-bus-enable signal for the local bus external interface LSTAT3−LSTAT0 4 O Status signals for the local bus external interface LLOCK 1 O Lock signal for the local bus external interface LSTRB0 ‡ 1 O/Z Access strobe 0 for the local bus external interface LR/W 0 1 O/Z Read/write signal for LSTRB0 accesses LPAGE0 1 O/Z Page signal for LSTRB0 accesses LRDY0 1 I Ready signal for LSTRB0 accesses LCE0 1 I Control enable for the LSTRB0, LPAGE0, and LR/W0 signals LSTRB1 ‡ 1 O/Z Access strobe 1 for the local bus external interface LR/W 1 1 O/Z Read/write signal for LSTRB1 accesses † I = input, O = output, Z = high impedance ‡ STRB0 , STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the STRB ACTIVE bits. § HFH package has additional power and ground pins to reduce noise problems.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMJ320C40 Signal Descriptions (Continued) SIGNAL DESCRIPTIONTYPE † NAME DESCRIPTIONTYPE †NO. OF PINS LOCAL BUS EXTERNAL INTERFACE (80 PINS) (CONTINUED) LPAGE1 1 O/Z Page signal for LSTRB1 accesses LRDY1 1 I Ready signal for LSTRB1 accesses LCE1 1 I Control enable for the LSTRB1, LPAGE1, and LR/W1 signals COMMUNICATION PORT 0 INTERFACE (12 PINS) C0D7−C0D0 8 I/O Communication port 0 data bus CREQ0 1 I/O Communication port 0 token-request signal CACK0 1 I/O Communication port 0 token-request-acknowledge signal CSTRB0 1 I/O Communication port 0 data-strobe signal CRDY0 1 I/O Communication port 0 data-ready signal COMMUNICATION PORT 1 INTERFACE (12 PINS) C1D7−C1D0 8 I/O Communication port 1 data bus CREQ1 1 I/O Communication port 1 token-request signal CACK1 1 I/O Communication port 1 token-request-acknowledge signal CSTRB1 1 I/O Communication port 1 data-strobe signal CRDY1 1 I/O Communication port 1 data-ready signal COMMUNICATION PORT 2 INTERFACE (12 PINS) C2D7−C2D0 8 I/O Communication port 2 data bus CREQ2 1 I/O Communication port 2 token-request signal CACK2 1 I/O Communication port 2 token-request-acknowledge signal CSTRB2 1 I/O Communication port 2 data-strobe signal CRDY2 1 I/O Communication port 2 data-ready signal COMMUNICATION PORT 3 INTERFACE (12 PINS) C3D7−C3D0 8 I/O Communication port 3 data bus CREQ3 1 I/O Communication port 3 token-request signal CACK3 1 I/O Communication port 3 token-request-acknowledge signal CSTRB3 1 I/O Communication port 3 data-strobe signal CRDY3 1 I/O Communication port 3 data-ready signal COMMUNICATION PORT 4 INTERFACE (12 PINS) C4D7−C4D0 8 I/O Communication port 4 data bus CREQ4 1 I/O Communication port 4 token-request signal CACK4 1 I/O Communication port 4 token-request-acknowledge signal CSTRB4 1 I/O Communication port 4 data-strobe signal CRDY4 1 I/O Communication port 4 data-ready signal † I = input, O = output, Z = high impedance ‡ STRB0 , STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the STRB ACTIVE bits. § HFH package has additional power and ground pins to reduce noise problems. signal descriptions (continued)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

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SMJ320C40 Signal Descriptions (Continued) SIGNAL DESCRIPTIONTYPE † NAME DESCRIPTIONTYPE †NO. OF PINS COMMUNICATION PORT 5 INTERFACE (12 PINS) C5D7−C5D0 8 I/O Communication port 5 data bus CREQ5 1 I/O Communication port 5 token-request signal CACK5 1 I/O Communication port 5 token-request-acknowledge signal CSTRB5 1 I/O Communication port 5 data-strobe signal CRDY5 1 I/O Communication port 5 data-ready signal INTERRUPTS, I/O FLAGS, RESET, TIMER (12 PINS) IIOF3−IIOF0 4 I/O Interrupt and I/O flags NMI 1 I Nonmaskable interrupt. NMI is sensitive to a low-going edge. IACK 1 O Interrupt acknowledge RESET 1 I Reset signal RESETLOC1− RESETLOC0

2 I Reset-vector location pins

ROMEN 1 I On-chip ROM enable (0 = disable, 1 = enable) TCLK0 1 I/O Timer 0 pin TCLK1 1 I/O Timer 1 pin CLOCK (4 PINS) X1 1 O Crystal pin X2/CLKIN 1 I Crystal/oscillator pin H1 1 O H1 clock H3 1 O H3 clock POWER AND GROUND (70 PINS) § CV SS 15§ I Ground pins DV SS 15§ I Ground pins IVSS 6§ I Ground pins DV DD 13 I 5-VDC supply pins GADV DD 3§ I 5-VDC supply pins GDDV DD 3§ I 5-VDC supply pins LADV DD 3§ I 5-VDC supply pins LDDV DD 3§ I 5-VDC supply pins SUBS 1 I Substrate pin (tie to ground) VDDL 4 I 5-VDC supply pins VSSL 4 I Ground pins † I = input, O = output, Z = high impedance ‡ STRB0 , STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the STRB ACTIVE bits. § HFH package has additional power and ground pins to reduce noise problems. signal descriptions (continued)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMJ320C40 Signal Descriptions (Continued) SIGNAL DESCRIPTIONTYPE † NAME DESCRIPTIONTYPE †NO. OF PINS EMULATION (7 PINS) TCK 1 I IEEE 1149.1 test port clock TDO 1 O/Z IEEE 1149.1 test port data out TDI 1 I IEEE 1149.1 test port data in TMS 1 I IEEE 1149.1 test port mode select TRST 1 I IEEE 1149.1 test port reset EMU0 1 I/O Emulation pin 0 EMU1 1 I/O Emulation pin 1 † I = input, O = output, Z = high impedance ‡ STRB0 , STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the STRB ACTIVE bits. § HFH package has additional power and ground pins to reduce noise problems. signal descriptions (continued)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

GF package pin assignments — alphabetical listing A0 D32 C0D6 AN7 C5D4 AM30 CV SS E35 D31 F32 A1 B32 C0D7 AK8 C5D5 AP32 CV SS AR25 DE AA31 A2 D30 C1D0 AL7 C5D6 AM32 CV SS AE1 DV DD AR11 A3 C29 C1D1 AP8 C5D7 AL31 CV SS AR13 DV DD AR29 A4 B30 C1D2 AM8 CACK0 AN11 CV SS A19 DV DD A13 A5 F28 C1D3 AK12 CACK1 AN13 CV SS R35 DV DD A7 A6 F24 C1D4 AK10 CACK2 AM14 CV SS AL1 DV DD A17 A7 E29 C1D5 AN9 CACK3 AM16 D0 U33 DV DD L35 A8 C27 C1D6 AL9 CACK4 AK32 D1 V32 DV DD AR23 A9 D28 C1D7 AP10 CACK5 AJ31 D2 T34 DV DD A29 A10 B28 C2D0 AM18 CE0 AA33 D3 U31 DV DD L1 A11 F26 C2D1 AN19 CE1 V34 D4 R33 DV DD AC1 A12 C25 C2D2 AL19 CRDY0 AP12 D5 P34 DV DD AR17 A13 E27 C2D3 AP20 CRDY1 AP14 D6 T32 DV DD A23 A14 B26 C2D4 AM20 CRDY2 AL15 D7 N33 DV DD AJ1 A15 D26 C2D5 AN21 CRDY3 AL17 D8 R31 DV SS AJ35 A16 C23 C2D6 AL21 CRDY4 AH30 D9 M34 DV SS A21 A17 B24 C2D7 AP22 CRDY5 AH32 D10 P32 DV SS A25 A18 E25 C3D0 AM22 CREQ0 AM10 D11 L33 DV SS G35 A19 C21 C3D1 AN23 CREQ1 AM12 D12 N31 DV SS A11 A20 D24 C3D2 AL23 CREQ2 AN15 D13 K34 DV SS AG1 A21 B22 C3D3 AP24 CREQ3 AN17 D14 M32 DV SS AM2 A22 E23 C3D4 AM24 CREQ4 AN33 D15 J33 DV SS R1 A23 C19 C3D5 AN25 CREQ5 AL33 D16 L31 DV SS AR21 A24 D22 C3D6 AL25 CSTRB0 AL11 D17 M30 DV SS AR15 A25 B20 C3D7 AP26 CSTRB1 AL13 D18 K32 DV SS A15 A26 E21 C4D0 AN27 CSTRB2 AP16 D19 H34 DV SS AR27 A27 B18 C4D1 AM26 CSTRB3 AP18 D20 J31 DV SS G1 A28 C17 C4D2 AK24 CSTRB4 AM34 D21 G33 DV SS N35 A29 D20 C4D3 AL27 CSTRB5 AK34 D22 K30 DV SS AR9 A30 B16 C4D4 AP28 CV SS AR19 D23 F34 EMU0 AA35 AE AG31 C4D5 AK26 CV SS AR7 D24 H32 EMU1 AD34 C0D0 AP4 C4D6 AN29 CV SS N1 D25 E33 GADV DD B2 C0D1 AL5 C4D7 AM28 CV SS AL35 D26 D34 GADV DD AR1 C0D2 AN5 C5D0 AL29 CV SS A27 D27 G31 GADV DD U35 C0D3 AM4 C5D1 AP30 CV SS A9 D28 C33 GDDV DD V2 C0D4 AP6 C5D2 AK28 CV SS E1 D29 H30 GDDV DD A35 C0D5 AM6 C5D3 AN31 CV SS J35 D30 E31 GDDV DD A1

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 GF package pin assignments — alphabetical listing (continued) NAME NO. NAME NO. NAME NO. NAME NO. H1 AC3 LA25 R5 LD26 B4 STAT0 AD32 H3 AC5 LA26 T2 LD27 F8 STAT1 AE33 IACK W3 LA27 U3 LD28 D6 STAT2 AF34 IIOF0 AN3 LA28 T4 LD29 C3 STAT3 AE31 IIOF1 AL3 LA29 V4 LD30 E5 STRB0 AD30 IIOF2 AH6 LA30 U5 LD31 F6 STRB1 AC33 IIOF3 AK2 LADV DD B34 LDDV DD AR35 SUBS C31 IVSS AR5 LADV DD AB2 LDDV DD AP2 TCK Y34 IVSS AR31 LADV DD AP34 LDDV DD U1 TCLK0 AE3 IVSS AG35 LAE AB4 LDE AD4 TCLK1 AD2 IVSS A31 LCE0 AG5 LLOCK AA5 TDO AB34 IVSS J1 LCE1 AF2 LOCK W33 TDI AC35 IVSS A5 LD0 E19 LPAGE0 AH2 TMS W35 LA0 D2 LD1 C15 LPAGE1 AG3 TRST AE35 LA1 D4 LD2 D18 LRDY0 AF6 VDDL AN1 LA2 E3 LD3 B14 LRDY1 AE5 VDDL AN35 LA3 F4 LD4 E17 LR/W 0 AH4 VDDL C35 LA4 H6 LD5 D16 LR/W 1 AF4 VDDL C1 LA5 F2 LD6 C13 LSTAT0 AA3 VSSL A3 LA6 G5 LD7 E15 LSTAT1 Y4 VSSL AR3 LA7 G3 LD8 B12 LSTAT2 Y2 VSSL AR33 LA8 H4 LD9 D14 LSTAT3 W5 VSSL A33 LA9 H2 LD10 C11 LSTRB0 AJ3 X1 W1 LA10 K6 LD11 E13 LSTRB1 AD6 X2/CLKIN AA1 LA11 M6 LD12 B10 NMI AJ5 LA12 J5 LD13 D12 PAGE0 AG33 LA13 J3 LD14 C9 PAGE1 AB32 LA14 K4 LD15 E11 RDY0 Y32 LA15 K2 LD16 F12 RDY1 W31 LA16 L3 LD17 D10 RESETLOC0 AF30 LA17 L5 LD18 B8 RESETLOC1 AH34 LA18 M2 LD19 E9 RESET AJ33 LA19 M4 LD20 C7 ROMEN AK4 LA20 N3 LD21 F10 R/W 0 AF32 LA21 N5 LD22 B6 R/W 1 AC31 LA22 P2 LD23 D8 LA23 P4 LD24 C5 LA24 R3 LD25 E7

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

GF package pin assignments — numerical listing NO. NAME NO. NAME NO. NAME NO. NAME A1 GDDV DD AD30 STRB0 AK24 C4D2 AM30 C5D4 A3 VSSL AD32 STAT0 AK26 C4D5 AM32 C5D6 A5 IVSS AD34 EMU1 AK28 C5D2 AM34 CSTRB4 A7 DV DD AE1 CV SS AK32 CACK4 AN1 VDDL A9 CV SS AE3 TCLK0 AK34 CSTRB5 AN3 IIOF0 A11 DV SS AE5 LRDY1 AL1 CV SS AN5 C0D2 A13 DV DD AE31 STAT3 AL3 IIOF1 AN7 C0D6 A15 DV SS AE33 STAT1 AL5 C0D1 AN9 C1D5 A17 DV DD AE35 TRST AL7 C1D0 AN11 CACK0 A19 CV SS AF2 LCE1 AL9 C1D6 AN13 CACK1 A21 DV SS AF4 LR/W 1 AL11 CSTRB0 AN15 CREQ2 A23 DV DD AF6 LRDY0 AL13 CSTRB1 AN17 CREQ3 A25 DV SS AF30 RESETLOC0 AL15 CRDY2 AN19 C2D1 A27 CV SS AF32 R/W 0 AL17 CRDY3 AN21 C2D5 A29 DV DD AF34 STAT2 AL19 C2D2 AN23 C3D1 A31 IVSS AG1 DV SS AL21 C2D6 AN25 C3D5 A33 VSSL AG3 LPAGE1 AL23 C3D2 AN27 C4D0 A35 GDDV DD AG5 LCE0 AL25 C3D6 AN29 C4D6 AA1 X2/CLKIN AG31 AE AL27 C4D3 AN31 C5D3 AA3 LSTAT0 AG33 PAGE0 AL29 C5D0 AN33 CREQ4 AA5 LLOCK AG35 IVSS AL31 C5D7 AN35 VDDL AA31 DE AH2 LPAGE0 AL33 CREQ5 AP2 LDDV DD AA33 CE0 AH4 LR/W 0 AL35 CV SS AP4 C0D0 AA35 EMU0 AH6 IIOF2 AM2 DV SS AP6 C0D4 AB2 LADV DD AH30 CRDY4 AM4 C0D3 AP8 C1D1 AB4 LAE AH32 CRDY5 AM6 C0D5 AP10 C1D7 AB32 PAGE1 AH34 RESETLOC1 AM8 C1D2 AP12 CRDY0 AB34 TDO AJ1 DV DD AM10 CREQ0 AP14 CRDY1 AC1 DV DD AJ3 LSTRB0 AM12 CREQ1 AP16 CSTRB2 AC3 H1 AJ5 NMI AM14 CACK2 AP18 CSTRB3 AC5 H3 AJ31 CACK5 AM16 CACK3 AP20 C2D3 AC31 R/W 1 AJ33 RESET AM18 C2D0 AP22 C2D7 AC33 STRB1 AJ35 DV SS AM20 C2D4 AP24 C3D3 AC35 TDI AK2 IIOF3 AM22 C3D0 AP26 C3D7 AD2 TCLK1 AK4 ROMEN AM24 C3D4 AP28 C4D4 AD4 LDE AK8 C0D7 AM26 C4D1 AP30 C5D1 AD6 LSTRB1 AK10 C1D4 AM28 C4D7 AP32 C5D5 AK12 C1D3 AP34 LADV DD

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 GF package pin assignments — numerical listing (continued) AR1 GADV DD C1 VDDL E1 CV SS H2 LA9 P2 LA22 AR3 VSSL C3 LD29 E3 LA2 H4 LA8 P4 LA23 AR5 IVSS C5 LD24 E5 LD30 H6 LA4 P32 D10 AR7 CV SS C7 LD20 E7 LD25 H30 D29 P34 D5 AR9 DV SS C9 LD14 E9 LD19 H32 D24 R1 DV SS AR11 DV DD C11 LD10 E11 LD15 H34 D19 R3 LA24 AR13 CV SS C13 LD6 E13 LD11 J1 IVSS R5 LA25 AR15 DV SS C15 LD1 E15 LD7 J3 LA13 R31 D8 AR17 DV DD C17 A28 E17 LD4 J5 LA12 R33 D4 AR19 CV SS C19 A23 E19 LD0 J31 D20 R35 CV SS AR21 DV SS C21 A19 E21 A26 J33 D15 T2 LA26 AR23 DV DD C23 A16 E23 A22 J35 CV SS T4 LA28 AR25 CV SS C25 A12 E25 A18 K2 LA15 T32 D6 AR27 DV SS C27 A8 E27 A13 K4 LA14 T34 D2 AR29 DV DD C29 A3 E29 A7 K6 LA10 U1 LDDV DD AR31 IVSS C31 SUBS E31 D30 K30 D22 U3 LA27 AR33 VSSL C33 D28 E33 D25 K32 D18 U5 LA30 AR35 LDDV DD C35 VDDL E35 CV SS K34 D13 U31 D3 B2 GADV DD D2 LA0 F2 LA5 L1 DV DD U33 D0 B4 LD26 D4 LA1 F4 LA3 L3 LA16 U35 GADV DD B6 LD22 D6 LD28 F6 LD31 L5 LA17 V2 GDDV DD B8 LD18 D8 LD23 F8 LD27 L31 D16 V4 LA29 B10 LD12 D10 LD17 F10 LD21 L33 D11 V32 D1 B12 LD8 D12 LD13 F12 LD16 L35 DV DD V34 CE1 B14 LD3 D14 LD9 F24 A6 M2 LA18 W1 X1 B16 A30 D16 LD5 F26 A11 M4 LA19 W3 IACK B18 A27 D18 LD2 F28 A5 M6 LA11 W5 LSTAT3 B20 A25 D20 A29 F32 D31 M30 D17 W31 RDY1 B22 A21 D22 A24 F34 D23 M32 D14 W33 LOCK B24 A17 D24 A20 G1 DV SS M34 D9 W35 TMS B26 A14 D26 A15 G3 LA7 N1 CV SS Y2 LSTAT2 B28 A10 D28 A9 G5 LA6 N3 LA20 Y4 LSTAT1 B30 A4 D30 A2 G31 D27 N5 LA21 Y32 RDY0 B32 A1 D32 A0 G33 D21 N31 D12 Y34 TCK B34 LADV DD D34 D26 G35 DV SS N33 D7 N35 DV SS

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

HFH package pin assignments — alphabetical listing A0 348 C1D0 168 CACK0 153 CV SS † 241 DE 53 A1 347 C1D1 167 CACK1 149 CV SS † 263 DV DD ‡ 63 A2 346 C1D2 166 CACK2 144 CV SS † 282 DV DD ‡ 77 A3 345 C1D3 165 CACK3 138 CV SS † 306 DV DD ‡ 91 A4 343 C1D4 164 CACK4 86 CV SS † 307 DV DD ‡ 100 A5 342 C1D5 163 CACK5 82 CV SS † 327 DV DD ‡ 112 A6 341 C1D6 162 CE0 51 CV SS † 328 DV DD ‡ 121 A7 340 C1D7 161 CE1 42 CV SS † 349 DV DD ‡ 135 A8 339 C2D0 131 CRDY0 151 D0 41 DV DD ‡ 146 A9 338 C2D1 130 CRDY1 147 D1 40 DV DD ‡ 160 A10 337 C2D2 129 CRDY2 142 D2 39 DV DD ‡ 169 A11 336 C2D3 128 CRDY3 136 D3 38 DV DD ‡ 179 A12 335 C2D4 127 CRDY4 84 D4 37 DV DD ‡ 195 A13 334 C2D5 126 CRDY5 80 D5 35 DV DD ‡ 219 A14 333 C2D6 125 CREQ0 154 D6 34 DV SS § 23 A15 332 C2D7 124 CREQ1 150 D7 33 DV SS § 24 A16 331 C3D0 120 CREQ2 145 D8 32 DV SS § 44 A17 324 C3D1 119 CREQ3 139 D9 31 DV SS § 45 A18 323 C3D2 118 CREQ4 87 D10 30 DV SS § 61 A19 322 C3D3 117 CREQ5 83 D11 29 DV SS § 62 A20 321 C3D4 116 CSTRB0 152 D12 28 DV SS § 89 A21 320 C3D5 115 CSTRB1 148 D13 27 DV SS § 90 A22 319 C3D6 114 CSTRB2 143 D14 26 DV SS § 110 A23 318 C3D7 113 CSTRB3 137 D15 25 DV SS § 111 A24 317 C4D0 108 CSTRB4 85 D16 17 DV SS § 133 A25 316 C4D1 107 CSTRB5 81 D17 16 DV SS § 134 A26 315 C4D2 106 CV SS † 18 D18 15 DV SS § 157 A27 314 C4D3 105 CV SS † 19 D19 14 DV SS § 158 A28 312 C4D4 104 CV SS † 46 D20 13 DV SS § 182 A29 311 C4D5 103 CV SS † 47 D21 12 DV SS § 183 A30 310 C4D6 102 CV SS † 88 D22 11 DV SS § 220 AE 75 C4D7 101 CV SS † 109 D23 10 DV SS § 221 C0D0 177 C5D0 99 CV SS † 132 D24 9 DV SS § 242 C0D1 176 C5D1 98 CV SS † 155 D25 8 DV SS § 243 C0D2 175 C5D2 97 CV SS † 156 D26 6 DV SS § 261 C0D3 174 C5D3 96 CV SS † 178 D27 5 DV SS § 262 C0D4 173 C5D4 95 CV SS † 196 D28 4 DV SS § 283 C0D5 172 C5D5 94 CV SS † 217 D29 3 DV SS § 284 C0D6 171 C5D6 93 CV SS † 218 D30 2 DV SS § 308 C0D7 170 C5D7 92 CV SS † 240 D31 1 DV SS § 309 † CV SS and IVSS pins are connected internally. ‡ DV DD , LADVDD , LDDVDD , GDDVDD , and GADVDD pins are connected internally. § DV SS pins are connected internally. ¶ VDDL pins are connected internally. # VSSL pins are connected internally.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HFH package pin assignments — alphabetical listing (continued) NAME NO. NAME NO. NAME NO. NAME NO. DV SS § 329 LA12 247 LD14 288 RDY0 52 DV SS § 330 LA13 246 LD15 287 RDY1 43 DV SS § 350 LA14 245 LD16 286 RESET 79 DV SS § 351 LA15 244 LD17 279 RESETLOC0 78 EMU0 59 LA16 237 LD18 278 RESETLOC1 76 EMU1 60 LA17 236 LD19 277 ROMEN 180 GADV DD ‡ 313 LA18 235 LD20 276 R/W 0 73 GADV DD ‡ 325 LA19 234 LD21 275 R/W 1 65 GADV DD ‡ 326 LA20 233 LD22 274 STAT0 67 GADV DD ‡ 344 LA21 232 LD23 273 STAT1 68 GDDV DD ‡ 7 LA22 231 LD24 272 STAT2 70 GDDV DD ‡ 21 LA23 230 LD25 271 STAT3 71 GDDV DD ‡ 22 LA24 229 LD26 270 STRB0 74 GDDV DD ‡ 36 LA25 228 LD27 269 STRB1 66 H1 204 LA26 227 LD28 267 SUBS 352 H3 203 LA27 225 LD29 266 TCK 54 IACK 212 LA28 224 LD30 265 TCLK0 201 IIOF0 181 LA29 223 LD31 264 TCLK1 202 IIOF1 184 LA30 222 LDDV DD ‡ 268 TDO 55 IIOF2 185 LADV DD ‡ 226 LDDV DD ‡ 280 TDI 56 IIOF3 186 LADV DD ‡ 238 LDDV DD ‡ 281 TMS 57 IVSS † 20 LADV DD ‡ 239 LDDV DD ‡ 298 TRST 58 IVSS † 69 LADV DD ‡ 256 LDE 200 VDDL ¶ 49 IVSS † 122 LAE 205 LLOCK 207 VDDL ¶ 140 IVSS † 123 LCE0 192 LOCK 48 VDDL ¶ 213 IVSS † 159 LCE1 199 LPAGE0 190 VDDL ¶ 304 IVSS † 206 LD0 303 LPAGE1 197 VSSL # 50 IVSS † 285 LD1 302 LRDY0 191 VSSL # 141 LA0 260 LD2 301 LRDY1 198 VSSL # 214 LA1 259 LD3 300 LR/W 0 189 VSSL # 305 LA2 258 LD4 299 LR/W 1 194 X1 215 LA3 257 LD5 297 LSTAT0 208 X2/CLKIN 216 LA4 255 LD6 296 LSTAT1 209 LA5 254 LD7 295 LSTAT2 210 LA6 253 LD8 294 LSTAT3 211 LA7 252 LD9 293 LSTRB0 188 LA8 251 LD10 292 LSTRB1 193 LA9 250 LD11 291 NMI 187 LA10 249 LD12 290 PAGE0 72 LA11 248 LD13 289 PAGE1 64 † CV SS and IVSS pins are connected internally. ‡ DV DD , LADVDD , LDDVDD , GDDVDD , and GADVDD pins are connected internally. § DV SS pins are connected internally. ¶ VDDL pins are connected internally. # VSSL pins are connected internally.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

HFH package pin assignments — numerical listing

1 D31 41 D0 81 CSTRB5 121 DV DD ‡ 161 C1D7

2 D30 42 CE1 82 CACK5 122 IVSS † 162 C1D6

3 D29 43 RDY1 83 CREQ5 123 IVSS † 163 C1D5

4 D28 44 DV SS § 84 CRDY4 124 C2D7 164 C1D4

5 D27 45 DV SS § 85 CSTRB4 125 C2D6 165 C1D3

6 D26 46 CV SS † 86 CACK4 126 C2D5 166 C1D2

7 GDDV DD ‡ 47 CV SS † 87 CREQ4 127 C2D4 167 C1D1

8 D25 48 LOCK 88 CV SS † 128 C2D3 168 C1D0

9 D24 49 VDDL ¶ 89 DV SS § 129 C2D2 169 DV DD ‡

10 D23 50 VSSL # 90 DV SS § 130 C2D1 170 C0D7

11 D22 51 CE0 91 DV DD ‡ 131 C2D0 171 C0D6

12 D21 52 RDY0 92 C5D7 132 CV SS † 172 C0D5

13 D20 53 DE 93 C5D6 133 DV SS § 173 C0D4

14 D19 54 TCK 94 C5D5 134 DV SS § 174 C0D3

15 D18 55 TDO 95 C5D4 135 DV DD ‡ 175 C0D2

16 D17 56 TDI 96 C5D3 136 CRDY3 176 C0D1

17 D16 57 TMS 97 C5D2 137 CSTRB3 177 C0D0

18 CV SS † 58 TRST 98 C5D1 138 CACK3 178 CV SS †

19 CV SS † 59 EMU0 99 C5D0 139 CREQ3 179 DV DD ‡

20 IVSS † 60 EMU1 100 DV DD ‡ 140 VDDL ¶ 180 ROMEN

21 GDDV DD ‡ 61 DV SS § 101 C4D7 141 VSSL # 181 IIOF0

22 GDDV DD ‡ 62 DV SS § 102 C4D6 142 CRDY2 182 DV SS §

23 DV SS § 63 DV DD ‡ 103 C4D5 143 CSTRB2 183 DV SS §

24 DV SS § 64 PAGE1 104 C4D4 144 CACK2 184 IIOF1

25 D15 65 R/W 1 105 C4D3 145 CREQ2 185 IIOF2

26 D14 66 STRB1 106 C4D2 146 DV DD ‡ 186 IIOF3

27 D13 67 STAT0 107 C4D1 147 CRDY1 187 NMI

28 D12 68 STAT1 108 C4D0 148 CSTRB1 188 LSTRB0

29 D11 69 IVSS † 109 CV SS † 149 CACK1 189 LR/W 0

30 D10 70 STAT2 110 DV SS § 150 CREQ1 190 LPAGE0

31 D9 71 STAT3 111 DV SS § 151 CRDY0 191 LRDY0

32 D8 72 PAGE0 112 DV DD ‡ 152 CSTRB0 192 LCE0

33 D7 73 R/W 0 113 C3D7 153 CACK0 193 LSTRB1

34 D6 74 STRB0 114 C3D6 154 CREQ0 194 LR/W 1

35 D5 75 AE 115 C3D5 155 CV SS † 195 DV DD ‡

36 GDDV DD ‡ 76 RESETLOC1 116 C3D4 156 CV SS † 196 CV SS †

37 D4 77 DV DD ‡ 117 C3D3 157 DV SS § 197 LPAGE1

38 D3 78 RESETLOC0 118 C3D2 158 DV SS § 198 LRDY1

39 D2 79 RESET 119 C3D1 159 IVSS † 199 LCE1

40 D1 80 CRDY5 120 C3D0 160 DV DD ‡ 200 LDE

† CV SS and IVSS pins are connected internally. ‡ DV DD , LADVDD , LDDVDD , GDDVDD , and GADVDD pins are connected internally. § DV SS pins are connected internally. ¶ VDDL pins are connected internally. # VSSL pins are connected internally.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HFH package pin assignments — numerical listing (continued) NO. NAME NO. NAME NO. NAME NO. NAME

201 TCLK0 241 CV SS † 281 LDDV DD ‡ 321 A20

202 TCLK1 242 DV SS § 282 CV SS † 322 A19

203 H3 243 DV SS § 283 DV SS § 323 A18

204 H1 244 LA15 284 DV SS § 324 A17

205 LAE 245 LA14 285 IVSS † 325 GADV DD ‡

206 IVSS † 246 LA13 286 LD16 326 GADV DD ‡

207 LLOCK 247 LA12 287 LD15 327 CV SS †

208 LSTAT0 248 LA11 288 LD14 328 CV SS †

209 LSTAT1 249 LA10 289 LD13 329 DV SS §

210 LSTAT2 250 LA9 290 LD12 330 DV SS §

211 LSTAT3 251 LA8 291 LD11 331 A16

212 IACK 252 LA7 292 LD10 332 A15

213 VDDL ¶ 253 LA6 293 LD9 333 A14

214 VSSL # 254 LA5 294 LD8 334 A13

215 X1 255 LA4 295 LD7 335 A12

216 X2/CLKIN 256 LADV DD ‡ 296 LD6 336 A11

217 CV SS † 257 LA3 297 LD5 337 A10

218 CV SS † 258 LA2 298 LDDV DD ‡ 338 A9

219 DV DD ‡ 259 LA1 299 LD4 339 A8

220 DV SS § 260 LA0 300 LD3 340 A7

221 DV SS § 261 DV SS § 301 LD2 341 A6

222 LA30 262 DV SS § 302 LD1 342 A5

223 LA29 263 CV SS † 303 LD0 343 A4

224 LA28 264 LD31 304 VDDL ¶ 344 GADV DD ‡

225 LA27 265 LD30 305 VSSL # 345 A3

226 LADV DD ‡ 266 LD29 306 CV SS † 346 A2

227 LA26 267 LD28 307 CV SS † 347 A1

228 LA25 268 LDDV DD ‡ 308 DV SS § 348 A0

229 LA24 269 LD27 309 DV SS § 349 CV SS †

230 LA23 270 LD26 310 A30 350 DV SS §

231 LA22 271 LD25 311 A29 351 DV SS §

232 LA21 272 LD24 312 A28 352 SUBS

233 LA20 273 LD23 313 GADV DD ‡

234 LA19 274 LD22 314 A27

235 LA18 275 LD21 315 A26

236 LA17 276 LD20 316 A25

237 LA16 277 LD19 317 A24

238 LADV DD ‡ 278 LD18 318 A23

239 LADV DD ‡ 279 LD17 319 A22

240 CV SS † 280 LDDV DD ‡ 320 A21

† CV SS and IVSS pins are connected internally. ‡ DV DD , LADVDD , LDDVDD , GDDVDD , and GADVDD pins are connected internally. § DV SS pins are connected internally. ¶ VDDL pins are connected internally. # VSSL pins are connected internally.

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 4. SMJ320C40 Die Numbering Format A. The TAB lead numbers. The TAB lead numbers are the same as the die bond pad numbers. C. There are 325 bond pad locations, 325 TAB leads, and 324 test pad locations. E. The inner lead bond pitch (ILB) is the same as the die bond pitch. F. The outer lead pitch is 0.25 ± 0.01 mm. G. The test pad pitch is 0.40 ± 0.01 mm. I. Outer lead bond (OLB) 18, 19 connect to test pad 18. J. X,Y coordinate data is in microns. K. Average pitch is 126 µm (4.96 mils). L. Smallest pitch value is 126 µm (4.96 mils). O. Distance from diced silicon to polyimide support ring is 889 µm (35.0 mils). Q. Center of bond pad to edge of die minimum (without scribe) = 107.80 µm (4.24 mils). R. The nominal die thickness is 381 ± 50.8 µm (15 ± 2 mils). S. The polyimide encapsulant thickness is approximately 304.8 µm (12 mils).

Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 µm)

22 D15

24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 µm) (Continued)

63 IVSS

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184 LPAGE1

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225 DV SS

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/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMJ320C40 device nomenclature SMJ 320 C 40 HFH M 40 PREFIX: SMJ = MIL-PRF-38535 SM = Standard Processing DEVICE FAMILY: 320 = SMJ320 DSP Family TECHNOLOGY: C = CMOS PACKAGE TYPE: GF = 325-Pin Ceramic Staggered PGA HFH = 352-Lead Ceramic Quad Flat Pack (nonconductive tie-bar) SPEED RANGE: 40 = 40 MHz 50 = 50 MHz 60 = 60 MHz TEMPERATURE RANGE: M = −55°C to 125°C S = −55°C to 100°C DEVICE: 40 = 320C40 SMJ 320 C 40 TAB M 40 /10 PREFIX: SMJ = MIL-PRF-38535 SM = Standard Processing TMP = Commercial Level DEVICE FAMILY: 320 = SMJ320 DSP Family TECHNOLOGY: C = CMOS PACKAGE TYPE: TAB = 324-Pad JEDEC Standard TAB Tape With Polyimide Overcoat SPEED RANGE: 40 = 40 MHz 50 = 50 MHz 60 = 60 MHz TEMPERATURE RANGE: M = −55°C to 125°C S = −55°C to 100°C L = 0°C to 70°C DEVICE: 40 = 320C40 SOLDER DIP LEAD FINISH

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions (see Note 2) MIN NOM ‡ MAX UNIT SMJ320C40-40 4.75 5 5.25 VDD Supply voltages (DVDD , etc.) SMJ320C40-50 4.75 5 5.25 VVDD Supply voltages (DVDD , etc.) SMJ320C40-60 4.75 5 5.25 V VSS Supply voltages (CVSS , etc.) 0 V X2/CLKIN 2.6 VDD + 0.3* VIH High-level input voltage CSTRBx , CRDYx§, CREQx, CACKx 2.2 VDD + 0.3* VVIH High-level input voltage All other pins 2 VDD + 0.3* V VIL Low-level input voltage − 0.3* 0.8 V IOH High-level output current − 300 µA IOL Low-level output current 2 mA M version −55 125 TC Operating case temperature (see Note 3) S version −55 100 °CTC Operating case temperature (see Note 3) C version −25 85 L version 0 70 ‡ All nominal values are at VDD = 5 V, TA (ambient-air temperature)= 25°C. § CRDYx is 2.6 V minimum for TAB package only. * On products compliant to MIL-PRF-38535, this parameter is not production tested. NOTES: 2. All input and output voltage levels are TTL-compatible. 3. TC MAX at maximum rated operating conditions at any point on case. TC MIN at initial (time zero) power-up.

† All nominal values are at VDD = 5 V, TA = 25°C.

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

NOTES: 2. All input and output voltage levels are TTL-compatible.

1. Pins with internal pullup devices: TDI, TCK, TMS. Pin with internal pulldown device: TRST
2. fx is the input clock frequency. The maximum value (MAX) for the 320C40-40, 320C40-50, and 320C40-60 is 40, 50, and 60 MHz,

C T = 80 pF typical load circuit capacitance. Figure 5. Test Load Circuit

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. at which the output is said to be no longer low is 1 V, and the level at which the output is said to be high is 2 V. Figure 6. TTL-Level Outputs CLKIN VIH = 3.12 V and CSTRBx, CRDYx, CREQx and CACKx VIH = 2.64 V. Figure 7. TTL-Level Inputs be increased to reduce the RC time constant during TPHZ and TPLZ testing.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A.To shorten the symbols, pin names that have both global and local applications generally are represented with (L) immediately preceding the basic signal name [for example, (L)RDY represents both the global term RDY and the local term LRDY]. Other pin names and related terminology have been abbreviated as follows, unless otherwise noted: A (L)A30−(L)A0 or (L)Ax H H1/H3 AE LAE , AE, or (L)AE IACK IACK ASYNCH asynchronous reset signals IIOF IIOF(3−0) or IIOFx BYTE byte transfer LOCK LLOCK , LOCK, or (L)LOCK CA CACK(0−5) or CACKx (L)RDY (L)RDY0 , (L)RDY1, or (L)RDYx CD C(0−5)D7−C(0−5)D0 or CxDx P t c(H) CE (L)CE0 , (L)CE1, or (L)CEx PAGE (L)PAGE0, (L)PAGE1, or (L)PAGEx CI X2/CLKIN RESET RESET COMM asynchronous reset signals RW (L)R/W 0, (L)R/W1, or (L)R/Wx CONTROL control signals S (L)STRB0 , (L)STRB1, or (L)STRBx CRDY CRDY(0 − 5) or CRDYx ST (L)STAT3−(L)STAT0 or (L)STATx CRQ CREQ(0−5) or CREQx TCK TCK CS CSTRB(0−5) or CSTRBx TDO TDO D (L)D31−(L)D0 or (L)Dx TMS TMS/TDI DE LDE , DE, or (L)DE WORD word transfer

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

Figure 8. X2/CLKIN Timing Figure 9. H1/H3 Timings

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

x stays high and (L)STRBx stays low. Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 11. Memory-Write-Cycle Timing [(L)STRBx = 0]

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

Figure 12. (L)DE, (L)AE, and (L)CEx Enable Timings

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Figure 13. Timing for (L)LOCK When Executing LDFI or LDII

Figure 14. Timing for (L)LOCK When Executing STFI or STII

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Figure 15. Timing for (L)LOCK When Executing SIGI

Figure 16. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page

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Figure 17. Timing for Loading IIF Register (IIOFx Pins) When Configured as an Output Pin

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

Figure 18. Change of IIOFx From Output to Input Mode

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Figure 19. Change of IIOFx From Input to Output Mode

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

NOTES: A. In this figure, (L)Dx includes D31−D0, LD31−D0, and CxD7−CxD0. B. (L)Ax includes A30−A0 and LA30−LA0. C. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3−(L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low. otherwise, an additional delay of one clock cycle can occur. Figure 20. RESET Timing

48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

sequence shown occurs; otherwise, an additional delay of one clock cycle can occur.

1. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists.
2. Level-triggered interrupts require interrupt pulse duration of at least 1P wide (P = one H1 period) to ensure that the interrupt is seen.

It must be less than 2P wide to ensure that it is responded to only once. Recommended pulse duration is 1.5P. NOTE A: The ’C40 can accept an interrupt from the same source every two H1 clock cycles. Figure 21. IIOF3−IIOF0 Interrupt Response Timing [P=tc(H)]

NOTE 10: The IACK output is active for the entire duration of the bus cycle and, therefore, is extended if the bus cycle utilizes wait states. Figure 22. IACK Timing

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† For these timing values, it is assumed that the SMJ320C40 that is to receive data is ready to receive data. 10 ns). This timing assumes that two ’C40s are connected.

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

width restriction in Section 8.9.1 of the TMS320C4x User’s Guide (literature number SPRU063). of 2 of each other (in other words, at most, one of the SMJ320C40s can be twice as fast as the other). Figure 23. Communication-Port Word-Transfer-Cycle Timing [P=tc(H)]

/C0008 means the value under max for parameter 6 in the table — a value of 10 ns). This assumes that two ’C40s are connected.

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

NOTE 12: Communication port timing does not include line length delay. Figure 24. Communication-Port Byte Timing (Write and Read)

52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

maximum delay occurs when the input condition occurs just after H1 falling.

• On products compliant to MIL-PRF-38535, this parameter is not production tested.

CREQx and CRDYx become inputs. Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P=tc(H)]

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 timing parameters for communication-token transfer sequence, output to an input port [P = tc(H)]† (see Figure 26) NO. ’320C40-40* UNITNO. MIN MAX MIN MAX UNIT 1† td(CRQL-CAL)T Delay time, CREQx low to start of CACKx going low for token-request acknowledge P+5 2P+26 P+5 2P+22 ns 2† td(CRDYL-CAL)T Delay time, start of CRDYx low at end of word transfer out to start of CACKx going low P+6 2P+27 P+6 2P+27 ns 3 td(CAL-CD)I Delay time, start of CACKx going low to CxD7−CxD0 change from outputs to inputs 0.5P−8 0.5P+8 0.5P−8 0.5P+8 ns 4 td(CAL-CRDY)T Delay time, start of CACKx going low to CRDYx change from an input to output, high level 0.5P−8 0.5P+8 0.5P−8 0.5P+8 ns 5† td(CRQH-CRQ)T Delay time, CREQx high to CREQx change from an input to output, high level 4 22 4 22 ns 6† td(CRQH-CA)T Delay time, start of CREQx high to CACKx change from output to an input 4 22 4 22 ns 7† td(CRQH-CS)T Delay time, start of CREQx high to CSTRBx change from output to an input 4 22 4 22 ns 8† td(CRQH-CRQL)T Delay time, CREQx high to CREQx low for the next token request P−4 2P+8 P−4 2P+8 ns † These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the maximum delay occurs when the input condition occurs just after H1 falling. * On products compliant to MIL-PRF-38535, this parameter is not production tested.

54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

and CRDYx become outputs, and CSTRBx, CACKx, and CxD7−CxD0 become inputs. Figure 26. Communication-Token Transfer Sequence, Output to an Input Port [P=tc(H)]

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

PRODUCT ORDERING INFORMATION SMJ320C40 standard package ordering information DEVICE TEMPERATURE RANGE OPERATING FREQUENCY PACKAGE TYPE PROCESSING LEVEL SMJ320C40GFM40 − 55°C to 125°C 40 MHz Ceramic 325-pin staggered PGA (GF) QML SM320C40GFM40 − 55°C to 125°C 40 MHz Ceramic 325-pin staggered PGA (GF) Standard SMJ320C40GFM50 − 55°C to 125°C 50 MHz Ceramic 325-pin staggered PGA QML SM320C40GFM50 − 55°C to 125°C 50 MHz Ceramic 325-pin staggered PGA Standard SMJ320C40HFHM40 − 55°C to 125°C 40 MHz Ceramic 352-pin quad flatpack (HFH) QML SM320C40HFHM40 − 55°C to 125°C 40 MHz Ceramic 352-pin quad flatpack (HFH) Standard SMJ320C40HFHM50 − 55°C to 125°C 50 MHz Ceramic 352-pin quad flatpack QML SM320C40HFHM50 − 55°C to 125°C 50 MHz Ceramic 352-pin quad flatpack Standard SMJ320C40GFS60 − 55°C to 100°C 60 MHz Ceramic 325-pin staggered PGA QML SM320C40GFS60 − 55°C to 100°C 60 MHz Ceramic 325-pin staggered PGA Standard SMJ320C40HFHS60 − 55°C to 100°C 60 MHz Ceramic 352-pin quad flatpack QML SM320C40HFHS60 − 55°C to 100°C 60 MHz Ceramic 352-pin quad flatpack Standard SMJ320C40 TAB ordering information† DEVICE TEMPERATURE RANGE OPERATING FREQUENCY PACKAGE TYPE PROCESSING LEVEL SMJ320C40TABM40/10 − 55°C to 125°C 40 MHz 325 ILB/OLB TAB tape (encapsulated) QML SM320C40TABM40/10 − 55°C to 125°C 40 MHz 325 ILB/OLB TAB tape (encapsulated) Standard SMJ320C40TABM50/10 − 55°C to 125°C 50 MHz 325 ILB/OLB TAB tape (encapsulated) QML SM320C40TABM50/10 − 55°C to 125°C 50 MHz 325 ILB/OLB TAB tape (encapsulated) Standard SM320C40TABS50/10 − 55°C to 100°C 50 MHz 325 ILB/OLB TAB tape (encapsulated) Standard TMP320C40TABL50/10 0°C to 70°C 50 MHz 325 ILB/OLB TAB tape (encapsulated) Commercial (No Burn-In) SM320C40TABC50/10 − 25°C to 85°C 50 MHz 325 ILB/OLB TAB tape (encapsulated) Commercial (No Burn-In) SMJ320C40TABS60/10 − 55°C to 100°C 60 MHz 325 ILB/OLB TAB tape (encapsulated) QML SM320C40TABS60/10 − 55°C to 100°C 60 MHz 325 ILB/OLB TAB tape (encapsulated) Standard TMP320C40TABL60/10 0°C to 70°C 60 MHz 325 ILB/OLB TAB tape (encapsulated) Commercial (No Burn-In) † /10 indicates solder-dip TAB lead frame.

1.879 (47,73) 1.841 (46,76)SQ TYP 0.050 (1,27) TYP 0.080 (2,03) TYP 0.150 (3,81) 0.145 (3,68) 0.200 (5,08) DETAIL A 1.717 (43,61) TYP 3533312925 2719 211715131197 23 1.683 (42,75) AR AN AJ AG AE AA AC AL W R U N L G E A C J 0.120 (3,05) 0.165 (4,19) 0.016 (0,41) 0.020 (0,51) 0.040 (1,02) 0.006 (0,152) 0.060 (1,52) 0.026 (0,660) 0.170 (4,32) 0.190 (4,83) 0.048 (1,22) DIA 4 Places0.050 (1,27) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark can appear on top or bottom, depending on package vendor. D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edge of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold-plated or solder-dipped. G. Package thickness of 0.165 (4,19) / 0.120 (3,05) includes package body and lid. H. Falls within JEDEC MO-128AK /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 57POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA GF (S-CPGA-P325) CERAMIC PIN GRID ARRAY Thermal Resistance Characteristics Parameter °C/W Air Flow LFPM R ΘJC 1.7 N/A R ΘJA 10.9 0 R ΘJA 9.8 200 R ΘJA 7.0 400 R ΘJA 6.4 600 R ΘJA 5.6 800 R ΘJA 5.5 1000

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001

58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

HFH (R-CQFP-F352) CERAMIC QUAD FLATPACK WITH NCTB 5,50 4,50 265 176 177 264 70,00 BSC Tie Bar Width DETAIL ”C”

2 Places

0,75 DETAIL ”C” 1,05 Dia2,60 2,50 3,34 MAX 0,35 0,05 2,79 MAX 4040232-5/F 12/98 0,50 MAX DETAIL ”B” 76,40 74,85 SQ 74,60 55,60 57,00 75,40 48,48 BSC 43,50 47,52 352 Dia1,45

4 Places

1,55 3,60 3,50 0,10 0,20 0,18 0,25 352 X 2,50 2,60 DETAIL ”A” DETAIL ”B” DETAIL ”A” 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. This package is hermetically sealed with a metal lid. D. The terminals are gold-plated. E. Leads not shown for clarity purposes F. Falls within JEDEC MO-134AE THERMAL RESISTANCE CHARACTERISTICS Parameter ° C/W R ΘJC 1.28 R ΘJA 28.70

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0052/C0048/C0044 /C0084/C0077/C0080/C0051/C0050/C0048/C0067/C0052/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 59POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA TAB (48 mm WITH PROTECTIVE FILM) SMJ320C40 324-PIN TAB FRAME SOCKET (PG 5.x) 325 OLB/ILB 0.25 mm OLB PITCH 4073433 2,25 (4 Places) 24,00 (2 Places) 0,26 0,24 × 80 =20,025 19,075 0,26 0,24 20,025 19,07580 =× 243 244 163 162 325 Die Face Up Tab Leads Up 0,26 0,24 × 81 =20,025 19,075 0,26 0,24 20,025 19,07580 =× NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. The OLB lead width is 0,10 ± 0,02 mm. D. The ILB lead width is 0,05 ± 0,01 mm. E. The tape width is 48 mm. F. The TAB is encapsulated die with polyimide overcoat.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9466902QXA ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type 5962-9466902QXC ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type 5962-9466902QYC ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type 5962-9466903QXA ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type 5962-9466903QXC ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type 5962-9466903QYC ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type 5962-9466904QXA ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type 5962-9466904QYC ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type SM320C40GFM40 ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type SM320C40GFM50 ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type SM320C40GFS60 ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type SM320C40HFHM40 ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type SM320C40HFHM50 ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type SM320C40HFHS60 ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type SM320C40KGDS50D ACTIVE XCEPT KGD 0 1 TBD Call TI N / A for Pkg Type SMJ320C40GFM40 ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type SMJ320C40GFM50 ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type SMJ320C40GFS60 ACTIVE CPGA GF 325 1 TBD Call TI N / A for Pkg Type SMJ320C40HFHM40 ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type SMJ320C40HFHM50 ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type SMJ320C40HFHS60 ACTIVE CFP HFH 352 1 TBD Call TI N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 2

MCFP029B – JANUARY 1995 – REVISED JUNE 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HFH (R-CQFP-F352) CERAMIC QUAD FLATPACK WITH NCTB 5,50 4,50 265 176 177 264 70,00 BSC Tie Bar Width DETAIL ”C” 0,75 DETAIL ”C” 1,05 Dia2,60 2,50 3,34 MAX 0,35 0,05 2,79 MAX 4040232-5/F 12/98 0,50 MAX DETAIL ”B” 76,40 74,85 SQ 74,60 55,60 57,00 75,40 48,48 BSC 43,50 47,52 352 Dia1,45 1,55 3,60 3,50 0,10 0,20 0,18 0,25 352 X 2,50 2,60 DETAIL ”A” DETAIL ”B” DETAIL ”A” 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. This package is hermetically sealed with a metal lid. D. The terminals are gold-plated. E. Leads not shown for clarity purposes F. Falls within JEDEC MO-134AE

MCPG013F – JANUARY 1995 – REVISED DECEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GF (S-CPGA-P325) CERAMIC PIN GRID ARRAY 4040035-2/F 11/01 1.879 (47,73) 1.841 (46,76)SQ TYP 0.050 (1,27) TYP 0.080 (2,03) TYP 0.150 (3,81) 0.145 (3,68) 0.200 (5,08) DETAIL A 1.717 (43,61) TYP 3533312925 2719 211715131197 23 1.683 (42,75) AR AN AJ AG AE AA AC AL W R U N L G E A C J 0.120 (3,05) 0.165 (4,19) 0.016 (0,41) 0.020 (0,51) 0.040 (1,02) 0.006 (0,152) 0.060 (1,52) 0.026 (0,660) 0.170 (4,32) 0.190 (4,83) 0.048 (1,22) DIA 4 Places0.050 (1,27) 0.100 (2,54) A1 Corner Bottom View NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark can appear on top or bottom, depending on package vendor. D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edge of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold-plated or solder-dipped. G. Package thickness of 0.165 (4,19) / 0.120 (3,05) includes package body and lid. H. Falls within JEDEC MO-128AK

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