SMJ320C30-50

SMJ320C30 TI | Alldatasheet

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Technical content

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068−55°C to 125°C Operating Temperature Range, QML Processing /C0068Processed to MIL-PRF-38535 (QML) /C0068Performance − SMJ320C30-40 (50-ns Cycle)

40 MFLOPS

20 MIPS

− SMJ320C30-50 (40-ns Cycle)

50 MFLOPS

25 MIPS

/C0068Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks /C0068Validated Ada Compiler /C006864-Word × 32-Bit Instruction Cache /C006832-Bit Instruction and Data Words, 24-Bit Addresses /C006840 / 32-Bit Floating-Point /Integer Multiplier and Arithmetic Logic Unit (ALU) /C0068Parallel ALU and Multiplier Execution in a Single Cycle /C0068On-Chip Direct Memory Access (DMA) Controller for Concurrent I/O and CPU Operation /C0068Integer, Floating-Point, and Logical Operations /C0068One 4K-Word × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block /C0068Two 32-Bit External Ports (24- and 13-Bit Address) /C0068Two Serial Ports With Support for 8- / 16- /24- /32-Bit Transfers /C0068Packaging − 181-Pin Grid Array Ceramic Package (GB Suffix) − 196-Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) /C0068SMD Approval for 40- and 50-MHz Versions /C0068Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) /C0068Zero-Overhead Loops With Single-Cycle Branches /C0068Interlocked Instructions for Multiprocessing Support /C006832-Bit Barrel Shifter /C0068Eight Extended-Precision Registers (Accumulators) /C0068Two- and Three-Operand Instructions /C0068Conditional Calls and Returns /C0068Block Repeat Capability /C0068Fabricated Using Enhanced Performance Implanted CMOS (EPIC/C0116) by Texas Instruments /C0068Two 32-Bit Timers

description

The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted in a less expensive processor that can be designed into systems currently using costly bit-slice processors. /C0068SMJ320C30-40: 50-ns single-cycle execution time, 5% supply /C0068SMJ320C30-50: 40-ns single-cycle execution time, 5% supply Copyright  2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 EPIC is a trademark of Texas Instruments Incorporated. /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

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description (continued) ABCDEFGHJKLMNPR 181-Pin GB Grid Array Package (BOTTOM VIEW) 196-Pin HFG Quad Flatpack (TOP VIEW) ÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉÉ /C0068/C0086/C0068/C0068 /C0068/C0086/C0083/C0083 /C0086/C0068/C0068 /C0068/C0086/C0083/C0083 /C0068/C0086/C0068/C0068 /C0086/C0083/C0083 /C0086/C0083/C0083/C0086/C0068/C0068 148 1471 196 9949 The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features. General-purpose applications are enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processor to dedicated coprocessor. High-level language support is implemented easily through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic. For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram ÉÉÉ ÉÉÉ ÉÉÉ ROM Block (4K × 32) Cache (64 × 32) RAM Block 0 (1K × 32) RAM Block 1 (1K × 32) RDY HOLD HOLDA STRB R/W D31− D0 A23 − A0 RESET IR PC CPU1 REG1 REG2 XRDY MSTRB IOSTRB ÉÉÉ XR / W XD31−XD 0 XA12 −XA 0 MUX BKARAU0 ARAU1 DISP0, IR0, IR1 Extended- Precision Registers (R7−R0) Auxiliary Registers (AR0 − AR7) Other Registers (12) Multiplier 32-Bit Barrel Shifter ALU DMA Controller Global-Control Register Source-Address Register Destination- Address Register Serial Port 0 Serial-Port-Control Register Receive/Transmit (R/X) Timer Register Data-Transmit Register Data-Receive Register FSX0 DX0 CLKX0 FSR0 DR0 CLKR0Serial Port 1 ÉÉÉÉ Data-Transmit Register Data-Receive Register FSX1 DX1 CLKX1 FSR1 DR1 CLKR1 Timer 0 Global-Control Register Timer-Period Register Timer-Counter Register TCLK0 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register TCLK1 Port Control Primary-Control Register Expansion-Control Register Transfer- Counter Register PDATA Bus PADDR Bus DDATA Bus DADDR1 Bus DADDR2 Bus DMADATA Bus DMAADDR Bus 32 32 24 24 32 24 INT(3 − 0) IACK MC / MP XF(1,0) VDD IODV DD ADV DD PDV DD DDV DD MDV DD VSS DV SS CV SS IVSS VBBP VSUBS X2 / CLKIN EMU(6 − 0) RSV(10 − 0) 32 24 24 24 24 32 32 32 CPU2 32 32 40 40 Serial-Port-Control Register MUX Controller Peripheral Data Bus Peripheral Address Bus CPU1 REG1 REG2 MUX Receive/Transmit (R/X) Timer Register

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vector/branches memory-map locations. Figure 3 shows the peripheral bus memory-mapped registers. Figure 1. Memory Map

Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations

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Figure 3. Peripheral Bus Memory-Mapped Registers†

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions This section gives signal descriptions for the SMJ320C30 devices in the microprocessor mode. The following tables list each signal, the number of pins, type of operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively), and a brief function description. All pins labeled NC have special functions and should not be connected by the user. A line over a signal name (for example, RESET ) indicates that the signal is active low (true at logic-0 level). The signals are grouped according to functions. Pin Functions PIN TYPE † DESCRIPTION CONDITIONS WHEN NAME QTY ‡ TYPE † DESCRIPTION WHEN SIGNAL IS Z TYPE§ PRIMARY BUS INTERFACE D31−D0 32 I/O/Z 32-bit data port of the primary bus interface S H A23−A0 24 O/Z 24-bit address port of the primary bus interface S H R R/W 1 O/Z Read/write for primary bus interface. R/ W is high when a read is performed and low when a write is performed over the parallel interface. S H R STRB 1 O/Z External access strobe for the primary bus interface S H RDY 1 I Ready. RDY indicates that the external device is prepared for a primary bus interface transaction to complete. HOLD 1 I Hold for primary bus interface. When HOLD is a logic low, any ongoing transaction is completed. A23−A0, D31−D0, STRB, and R/W are in the high-impedance state and all transactions over the primary bus interface are held until HOLD becomes a logic high or the NOHOLD bit of the primary bus control register is set. HOLDA 1 O/Z Hold acknowledge for primary bus interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23−A0, D31−D0, STRB, and R/W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the primary bus control register is set. S EXPANSION BUS INTERFACE XD31−XD0 32 I/O/Z 32-bit data port of the expansion bus interface S R XA12−XA0 13 O/Z 13-bit address port of the expansion bus interface S R XR/W 1 O/Z Read/write signal for expansion bus interface. When a read is performed, XR/W is held high; when a write is performed, XR/W is low. S R MSTRB 1 O/Z External memory access strobe for the expansion bus interface S IOSTRB 1 O/Z External I/O access strobe for the expansion bus interface S XRDY 1 I Ready signal. XRDY indicates that the external device is prepared for an expansion bus interface transaction to complete. CONTROL SIGNALS RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. INT3−INT0 4 I External interrupts IACK 1 O/Z Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. IACK can be used to indicate the beginning or end of an interrupt-service routine.S MC/MP 1 I Microcomputer/microprocessor mode XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support interlocked processor instructions. S R † I = input, O = output, Z = high-impedance state, NC = no connect ‡ For GB package § S = SHZ active, H = HOLD active, R = RESET active

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

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Pin Functions (Continued) PIN TYPE † DESCRIPTION CONDITIONS WHEN NAME QTY ‡ TYPE † DESCRIPTION WHEN SIGNAL IS Z TYPE§ SERIAL PORT 0 SIGNALS CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial-shift clock for the serial port 0 transmitter. S R DX0 1 I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0. S R FSX0 1 I/O/Z Frame synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data process over DX0. S R CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial-shift clock for the serial port 0 receiver.S R DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R FSR0 1 I/O/Z Frame synchronization pulse for receive. The FSR0 pulse initiates the receive-data process over DR0. S R SERIAL PORT 1 SIGNALS CLKX1 1 I/O/Z Serial port 1 transmit clock. CLKX1 is the serial-shift clock for the serial port 1 transmitter. S R DX1 1 I/O/Z Data transmit output. Serial port 1 transmits serial data on DX1. S R FSX1 1 I/O/Z Frame synchronization pulse for transmit. The FSX1 pulse initiates the transmit-data process over DX1. S R CLKR1 1 I/O/Z Serial port 1 receive clock. CLKR1 is the serial-shift clock for the serial port 1 receiver.S R DR1 1 I/O/Z Data receive. Serial port 1 receives serial data on DR1. S R FSR1 1 I/O/Z Frame synchronization pulse for receive. The FSR1 pulse initiates the receive-data process over DR1. S R TIMER 0 SIGNALS TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S R TIMER 1 SIGNALS TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. S R SUPPLY AND OSCILLATOR SIGNALS (see Note 1) VDD 4 I 5-V supply¶ IODV DD 2 I 5-V supply¶ ADV DD 2 I 5-V supply¶ PDV DD 1 I 5-V supply¶ DDV DD 2 I 5-V supply¶ MDV DD 1 I 5-V supply¶ VSS 4 I Ground DV SS 4 I Ground CV SS 2 I Ground † I = input, O = output, Z = high-impedance state, NC = no connect ‡ For GB package § S = SHZ active, H = HOLD active, R = RESET active ¶ Recommended decoupling capacitor is 0.1 µF. NOTE 1: CV SS , VSS , and IVSS are on the same plane.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Functions (Continued) PIN TYPE † DESCRIPTION CONDITIONS WHEN NAME QTY ‡ TYPE † DESCRIPTION WHEN SIGNAL IS Z TYPE§ SUPPLY AND OSCILLATOR SIGNALS (see Note 1) (CONTINUED) IVSS 1 I Ground VBBP 1 NC VBB pump oscillator output VSUBS 1 I Substrate pin. Tie to ground X1 1 O Output from the internal oscillator for the crystal. If a crystal is not used, X1 must be left unconnected. X2/CLKIN 1 I Input to the internal oscillator from the crystal or a clock H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S RESERVED (see Note 2) EMU0−EMU2 3 I Reserved. Use pullup resistors to 5 V EMU3 1 O/Z Reserved S EMU4/SHZ 1 I Shutdown high impedance. When active, EMU4/ SHZ shuts down the SMJ320C30 and places all pins in the high-impedance state. EMU4/ SHZ is used for board-level testing to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts SMJ320C30 memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. EMU5, EMU6 2 NC Reserved RSV0−RSV4 5 I Reserved. Tie pins directly to 5 V RSV5−RSV10 6 I/O Reserved. Use pullups on each pin to 5 V Locator 1 NC Reserved † I = input, O = output, Z = high-impedance state, NC=No Connect ‡ For GB package § S = SHZ active, H = HOLD active, R = RESET active NOTES: 1. CV SS , VSS , IVSS are on the same plane. 2. The connections specified for the reserved pins must be followed. For best results, 18-kΩ−22-kΩ pullup resistors are recommended. All 5-V supply pins must be connected to a common supply plane, and all ground pins must be connected to a common ground plane.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

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NUMBER NUMBER NUMBER NUMBER NUMBER GB PKG HFG PKG NAME GB PKG HFG PKG NAME GB PKG HFG PKG NAME GB PKG HFG PKG NAME GB PKG HFG PKG NAME F15 G12 G13 G14 G15 H15 H14 J15 J14 J13 K15 J12 K14 L15 K13 L14 M15 K12 L13 M14 N15 M13 L12 N14 D15 170 171 176 177 178 157 164 167 166 165 158 144 143 142 141 140 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 LOCATOR/NC IACK INT0 INT1 INT2 INT3 MC /MP MSTRB RDY RESET R/W STRB IOSTRB A10 B10 A11 C10 B11 A12 D10 C11 B12 139 138 137 136 135 134 133 132 131 130 129 128 127 122 121 120 119 118 117 116 115 113 112 111 110 109 108 161 160 156 159 191 194 192 193 190 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 HOLD HOLDA XRDY XR /W FSR0 FSX0 CLKR0 CLKX0 DR0 DX0 FSR1 FSX1 CLKR1 CLKX1 DR1 F14 E15 F13 E14 F12 H12 A13 A14 D11 C12 B13 A15 B15 C14 E12 D13 C15 D14 E13 195 155 145 146 152 151 169 168 154 153 123 124 107 106 105 104 103 102 179 180 181 182 183 184 DX1 EMU0 EMU1 EMU2 EMU3 EMU4 /SHZ EMU5 EMU6 X2 /CLKIN TCLK0 TCLK1 XF0 XF1 V BBP VSUBS VDD /C0125 VDD /C0125 VDD /C0125 VDD /C0125 VSS /C0119 XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 RSV0 RSV1 RSV2 RSV3 RSV4 RSV5 D12 H11 M12 P14 H13 185 186 187 188 189 100 114 147 162 163 172 173 125 126 149 150 174 175 RSV6 RSV7 RSV8 RSV9 RSV10 ADV DD /C0123 ADV DD /C0123 DDV DD /C0123 DDV DD /C0123 IODV DD /C0123 IODV DD /C0123 IODV DD /C0123 MDV DD /C0123 MDV DD /C0123 PDV DD /C0123 CV SS /C0119 CV SS /C0119 VDD /C0125 VDD /C0125 VDD /C0125 VDD /C0125 VSS /C0119 VSS /C0119 VSS /C0119 VSS /C0119 VSS /C0119 VSS /C0119 VSS /C0119 VSS /C0119 VSS /C0119 VSUBS XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 R10 P10 R11 N10 P11 R12 M10 N11 P12 R13 R14 M11 N12 P13 R15 P15 C13 N13 B14 101 148 196 XD11 XD12 XD13 XD14 XD15 XD16 XD17 XD18 XD19 XD20 XD21 XD22 XD23 XD24 XD25 XD26 XD27 XD28 XD29 XD30 XD31 DV DD DV DD DV SS /C0087 DV SS /C0087 DV SS /C0087 DV SS /C0087 IVSS /C0119 IVSS /C0119 † ADV DD , DDVDD , IODVDD , MDVDD , and PDVDD are on a common plane internal to the device. ‡ VDD is on a common plane internal to the device. § VSS , CVSS , and IVSS are on a common plane internal to the device. ¶ DV SS is on a common plane internal to the device.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 3. All voltage values are with respect to VSS . 4. Actual operating power is less. This value was obtained under specially produced worst-case test conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary and extension buses at the maximum rate possible. See normal (ICC ) current specification in the electrical characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020). recommended operating conditions (see Note 5) MIN NOM ‡ MAX UNIT VSS Supply voltage (CVSS , etc.) 0 V VIH High-level input voltage 2.1 VDD + 0.3* V VTH High-level input voltage for CLKIN 3 VDD + 0.3* V VIL Low-level input voltage − 0.3* 0.8 V IOH High-level output current − 300 µA IOL Low-level output current 2 mA TC Operating case temperature (see Note 6) − 55 125 °C ‡ All nominal values are at VDD = 5 V, TA (ambient-air temperature)= 25°C. * This parameter is not production tested. NOTE 5: All input and output voltage levels are TTL compatible. NOTE 6: T C MAX at maximum rated operating conditions at any point on the case, TC MIN at initial (time zero) power up

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† For conditions shown as MIN/MAX, use the appropriate value specified in recommended operating conditions. ‡ All typical values are at VDD = 5 V, TA = 25°C.

• This parameter is not production tested.

NOTES: 5. All input and output voltage levels are TTL compatible.

1. Pins with internal pullup devices: INT0−INT3, MC/MP , RSV0−RSV10. Although RSV0−RSV10 have internal pullup devices,

external pullups should be used on each pin as identified in the pin function tables.

1. Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test

Dissipation Application Report (literature number SPRA020). VLOAD = Selected to emulate 50 Ω termination (typical value = 1.54 V). Figure 4. Test Load Circuit

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the terminal names and other related terminology have been abbreviated as follows, unless otherwise noted: A A23−A0 IACK IACK ASYNCH Asynchronous reset signals include XF0, XF1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, and TCLK1 INT INT3 −INT0 CH CLKX includes CLKX0 and CLKX1 IOS IOSTRB CI CLKIN (M)S (M)STRB includes MSTRB and STRB CONTROL Control signals include STRB , MSTRB , and IOSTRB RDY RDY D D31−D0 RESET RESET DR Includes DR0, DR1 RW R/W DX Includes DX0, DX1 S STRB FS FSX/R includes FSX0, FSX1, FSR0, and FSR1 SCK CLKX/R includes CLKX0, CLKX1, CLKR0, and CLKR1 FSR Includes FSR0, FSR1 TCLK TCLK0, TCLK1 FSX Includes FSX0, FSX1 (X)A Includes A23−A0 and XA12−XA0 GPIO General-purpose input/output; peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1 (X)D Includes D31−D0 and XD31−XD0 H Includes H1, H3 XF XFx includes XF0 and XF1 H1 H1 XF0 XF0 H3 H3 XF1 XF1 HOLD HOLD (X)RDY Includes RDY and XRDY HOLDA HOLDA (X)RW (X)R/W includes R/W and XR/W

RESET timing in Figure 20 for CLKIN to H1 and H3 delay specification. † Numbers in this column match those used in Figure 7, Figure 8, and Figure 9.

• This parameter is not production tested.

NOTES: 5. All input and output voltage levels are TTL compatible.

1. Rise and fall times, assuming a 35 − 65% duty cycle, are incorporated within this specification (see Figure 6).

Figure 7. X2/CLKIN Timing

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 8. H1/H3 Timings

4.5 V Band

5.5 V Band

Figure 9. CLKIN to H1/H3 as a Function of Temperature

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 memory read/write timing The following table defines memory read/write timing parameters for (M)STRB. timing parameters for a memory [(M)STRB = 0] read/write (see Figure 10 and Figure 11) NO.† 320C30-40 320C30-50 UNITNO.† MIN MAX MIN MAX UNIT 11 td[H1L-(M)SL] Delay time, H1 low to (M)STRB low 0* 10 0* 4 ns 12 td[H1L-(M)SH] Delay time, H1 low to (M)STRB high 0* 6 0* 4 ns 13.1 td(H1H-RWL) Delay time, H1 high to R/W low 0* 9 0* 7 ns 13.2 td[H1H-(X)RWL] Delay time, H1 high to (X)R/W low 0* 13 0* 11 ns 14.1 td(H1L-A) Delay time, H1 low to A valid 0* 11 0* 9 ns 14.2 td[H1L-(X)A] Delay time, H1 low to (X)A valid 0* 9 0* 8 ns 15.1 tsu(D-H1L)R Setup time, D valid before H1 low (read) 14 10 ns 15.2 tsu[(X)DR-H1L]R Setup time, (X)D before H1 low (read) 16 14 ns 16 th[H1L-(X)D]R Hold time, (X)D after H1 low (read) 0* 0* ns 17.1 tsu(RDY-H1H) Setup time, RDY before H1 high 8 6 ns 17.2 tsu[(X)RDY-H1H] Setup time, (X)RDY before H1 high 9 8 ns 18 th[H1H-(X)RDY] Hold time, (X)RDY after H1 high 0 0 ns 19 td[H1H-(X)RWH]W Delay time, H1 high to (X)R/W high (write) 9 7 ns 20 tv[H1L(X)D]W Valid time, (X)D after H1 low (write) 17 14 ns 21 th[H1H-(X)D]W Hold time, (X)D after H1 high (write) 0* 0* ns 22.1 td(H1H-A) Delay time, H1 high to A valid on back-to-back write cycles (write)15 12 ns 22.2 td[H1H-(X)A] Delay time, H1 high to (X)A valid on back-to-back write cycles (write)21 18 ns 26 td[A-(X)RDY] Delay time, (X)RDY from A valid 7* 6* ns † Numbers in this column match those used in Figure 10 and Figure 11. * This parameter is not production tested.

18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

NOTE A: (M)STRB remains low during back-to-back read operations. Figure 10. Timing for Memory [(M)STRB = 0] Read

Figure 11. Timing for Memory [(M)STRB = 0] Write

20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The following table defines memory read timing parameters for IOSTRB. † Numbers in this column match those used in Figure 12.

• This parameter is not production tested.

Figure 12. Timing for Memory (IOSTRB = 0) Read

The following table defines memory write timing parameters for IOSTRB. † Numbers in this column match those used in Figure 13.

• This parameter is not production tested.

Figure 13. Timing for Memory (IOSTRB = 0) Write

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII. † Numbers in this column match those used in Figure 14. Figure 14. Timing for XF0 and XF1 When Executing LDFI or LDII

The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. † The number in this column matches that used in Figure 15. Figure 15. Timing for XF0 When Executing an STFI or STII

24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI. † Numbers in this column match those used in Figure 16. Figure 16. Timing for XF0 and XF1 When Executing SIGI

† The number in this column matches that used in Figure 17. NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register. Figure 17. Timing for Loading XFx Register When Configured as an Output Pin

26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin. † Numbers in this column match those used in Figure 18.

• This parameter is not production tested.

whether XF0 or XF1, respectively, is being affected. Figure 18. Timing for Change of XFx From Output to Input Mode

The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin. † The number in this column matches that used in Figure 19. whether XF0 or XF1, respectively, is being affected. Figure 19. Timing for Change of XFx From Input to Output Mode

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 20 occurs; otherwise, an additional delay of one clock cycle can occur. R/W and XR/W are in the high-impedance state during reset and can be provided with a resistive pullup, nominally 18 kΩ to 22 kΩ, to prevent spurious writes from occurring. The asynchronous reset signals include XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. HOLD is an asynchronous input and can be asserted during reset. Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states and, therefore, results in slow external accesses until these registers are initialized. timing parameters for RESET [P = tc(CI)] (see Figure 9 and Figure 20) NO. 320C30-40 320C30-50 UNITNO. MIN MAX MIN MAX UNIT 50 tsu(RESET) Setup time, RESET before CLKIN low 10 P* 10 P* ns 51 td(CLKINH-H1H) Delay time, CLKIN high to H1 high† 2 14 2 10 ns 52 td(CLKINH-H1L) Delay time, CLKIN high to H1 low† 2 14 2 10 ns 53 tsu(RESETH-H1L) Setup time, RESET high beforeH1 low after ten H1 clock cycles 9 7 ns 54 td(CLKINH-H3L) Delay time, CLKIN high to H3 low† 2 14 2 10 ns 55 td(CLKINH-H3H) Delay time, CLKIN high to H3 high† 2 14 2 10 ns 56 tdis(H1H-XD) Disable time, H1 high to (X)D high-impedance state 15* 12* ns 57 tdis(H3H-XA) Disable time, H3 high to (X)A high-impedance state 9* 8* ns 58 td(H3H-CONTROLH) Delay time, H3 high to control signals high 9* 8* ns 59 td(H1H-IACKH) Delay time, H1 high to IACK high 9* 8* ns 60 tdis(RESETL-ASYNCH) Disable time, RESET low to asynchronous reset signals in the high-impedance state 21* 17* ns † See Figure 9 for temperature dependence for the 40-MHz SMJ320C30. * This parameter is not production tested.

NOTES: A. In this diagram X(D) includes D31−D0 and XD31−XD0. B. In this diagram, (X)A includes A23−A0 and XA12−XA0. C. Control signals include STRB, MSTRB , and IOSTRB. vector is fetched twice, with no software wait states. Figure 20. Timing for Reset [P=tc(Cl)]

30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The following table defines the timing parameters for the INT signals.

• This parameter is not production tested.

SMJ320C30 interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1. respond to detected interrupts on instruction-fetch boundaries only. The SMJ320C30 can accept an interrupt from the same source every two H1 clock cycles. of one clock cycle is possible. Figure 21. Timing for INT3−INT0 Response [Q=tc(H)]

goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction. The following table defines the timing parameters for the IACK signal. † Numbers in this column match those used in Figure 22. Figure 22. Timing for Interrupt-Acknowledge (IACK)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

serial-port timing parameters (see Figure 23 and Figure 24) NO. CLOCK 320C30-40 320C30-50 UNITNO. CLOCK SOURCE MIN MAX MIN MAX UNIT 65 td(H1-SCK) Delay time, H1 high to internal CLKX/R 13 10 ns 66 tc(SCK) Cycle time, CLKX/R ext tc(H)× 2.5* tc(H)× 2.6* ns66 tc(SCK) Cycle time, CLKX/R CLKX/R int tc(H)× 2 tc(H)× 232* tc(H)× 2 tc(H)× 232* ns 67 tw(SCK) Pulse duration, CLKX/R ext tc(H)+12* tc(H)+10* ns67 tw(SCK) duration, CLKX /R high/low CLKX/R int [tc(SCK)/2]−15 [tc(SCK) / 2]+5 [tc(SCK)/2]−5 [tc(SCK) / 2]+5 ns 68 tr(SCK) Rise time, CLKX/R 7* 6* ns 69 tf(SCK) Fall time, CLKX/R 7* 6* ns 70 td(DX) Delay time, CLKX to DX CLKX ext 30 24 ns70 td(DX) CLKX to DX valid CLKX int 17 16 ns 71 tsu(DR) Setup time, DR before CLKR ext 9 9 ns71 tsu(DR) DR before CLKR low CLKR int 21 17 ns 72 th(DR) Hold time, DR from CLKR ext 9 7 ns72 th(DR) DR from CLKR low CLKR int 0 0 ns 73 td(FSX) Delay time, CLKX to CLKX ext 27 22 ns73 td(FSX) CLKX to internal FSX high/low CLKX int 15 15 ns 74 tsu(FSR) Setup time, FSR before CLKR ext 9 7 ns74 tsu(FSR) FSR before CLKR low CLKR int 9 7 ns 75 th(FS) Hold time, FSX/R input CLKX/R ext 9 7 ns75 th(FS) FSX/R input from CLKX/R low CLKX/R int 0 0 ns 76 tsu(FSX) Setup time, external FSX CLKX ext −[tc(H)−8 ] [tc(SCK) / 2]−10* −[tc(H)−8 ] [tc(SCK) / 2]−10* ns76 tsu(FSX) external FSX before CLKX high CLKX int −[tc(H)−21] tc(SCK)/2* −[tc(H)−21] tc(SCK)/2* ns 77 td(CH-DX)V Delay time, CLKX to first DX bit, FSX CLKX ext 30 24 ns77 td(CH-DX)V DX bit, FSX precedes CLKX high CLKX int 18 14 ns 78 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 30 24 ns 79 tdDXZ Delay time, CLKX high to DX high impedance following last data bit 17* 14* ns * This parameter is not production tested.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 25 occurs; otherwise, an additional delay of one clock cycle is possible. The “timing parameters for HOLD /HOLDA ” table defines the timing parameters for the HOLD and HOLDA signals. The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents future hold cycles. Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, allowing the processor to continue until a second write is encountered. HOLD /HOLDA timing (see Figure 25) NO.† 320C30-40 320C30-50 UNITNO.† MIN MAX MIN MAX UNIT 80 tsu(HOLD) Setup time, HOLD before H1 low 13 10 ns 81 tv(HOLDA) Valid time, HOLDA after H1 low 0* 9 0* 7 ns 82 tw(HOLD) Pulse duration, HOLD low 2tc(H) 2tc(H) ns 83 tw(HOLDA) Pulse duration, HOLDA low tc(H)−5* tc(H)−5* ns 84 td(H1L-SH)H Delay time, H1 low to STRB high for a HOLD 0* 9* 0* 7* ns 85 tdis(H1L-S) Disable time, H1 low to STRB high impedance 0* 9* 0* 8* ns 86 ten(H1L-S) Enable time, H1 low to STRB active 0* 9* 0* 7* ns 87 tdis(H1L-RW) Disable time, H1 low to R/W high impedance 0* 9* 0* 8* ns 88 ten(H1L-RW) Enable time, H1 low to R/W active 0* 9* 0* 7* ns 89 tdis(H1L-A) Disable time, H1 low to address high impedance 0* 9* 0* 8* ns 90 ten(H1L-A) Enable time, H1 low to address valid 0* 13* 0* 12* ns 91 tdis(H1H-D) Disable time, H1 high to data high impedance 0* 12* 0* 8* ns † Numbers in this column are used in Figure 25. * This parameter is not production tested.

NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low through one H1 cycle after HOLD returns to high. Figure 25. Timing for HOLD/HOLDA

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

internal-control registers associated with each peripheral define the modes for these pins. The following table defines peripheral pin general-purpose I/O timing parameters. † Numbers in this column are used in Figure 26.

• This parameter is not production tested.

Figure 26. Timing for Peripheral Pin General-Purpose I/O

pin to a general-purpose input pin and the reverse. † Numbers in this column are used in Figure 27. by the contents of internal control registers associated with each peripheral. Figure 27. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 28. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode

Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following table defines the timing parameters for the timer pin. † Numbers in this column are used in Figure 29.

• This parameter is not production tested.

NOTE A: Period and polarity of valid logic level are specified by contents of internal control registers. Figure 29. Timing for Timer Pin

40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The following table defines the timing parameter for the SHZ pin. † Numbers in this column are used in Figure 30.

• This parameter is not production tested.

Figure 30. Timing for SHZ

Figure 31. SMJ320C30 Device Nomenclature

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

HFG (S-CQFP-F196) CERAMIC QUAD FLATPACK WITH TIE BAR 4040231-6/F 04/96 2.505 (63,63) 2.485 (63,12) “C” “B” 0.004 (0,10) 0.105 (2,67) MAX DETAIL “C” 0.008 (0,20) 0.002 (0,05) 0.130 (3,30) MAX 0.014 (0,36) 0.018 (0,46) MAX 1.365 (34,67) 1.325 (33,66) 196 148 “A” DETAIL “B” Braze

8 Places

1.150 (29,21) 0.010 (0,25) 0.006 (0,15) DIA 4 Places DETAIL “A” 196 /C0002 0.061 (1,55) 0.059 (1,50) 99 147 1.200 (30,48) TYP 0.225 (5,72) 1.710 (43,43) 1.690 (42,93) 0.600 (15,20) TYP 0.030 (0,76) 0.040 (1,02) 0.020 (0,51) MAX 0.175 (4,45) 0.025 (0,64) 1.3 PARAMETER Thermal Resistance Characteristics °C/W 28.9 R θJC R θJA Tie Bar Width NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Ceramic quad flatpack with flat leads brazed to nonconductive tie-bar carrier D. This package can be hermetically sealed with a metal lid. E. The terminals will be gold plated. F. Falls within JEDEC MO-113 AB The above data applies to the SMJ320C30 196-pin QFP.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA (CONTINUED) GA-GB (S-CPGA-P15 X 15) CERAMIC PIN GRID ARRAY PACKAGE 4040114-8/C 04/96 Down Cavity Up Cavity Down Cavity Cavity Up Outline Small Outline Large MAXIMUM PINS WITHIN MATRIX − 225 1.590 (40,38) DIM MIN MAX Notes 1.540 (39,12)A A or A1 SQ

4 Places

1.400 (35,56) TYP 0.016 (0,41) 0.022 (0,55) 0.140 (3,56) B or B1 C or C1 J H G F E D C A B 123456789 K L 11 12 M N P 0.100 (2,54) R NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark may appear on top or bottom depending on package vendor. D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edges of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold plated or solder dipped. G. Falls within MIL-STD-1835 CMGA7-PN and CMGA19-PN and JEDEC MO-067AG and MO-066AG, respectively 1.1 PARAMETER Thermal Resistance Characteristics °C/W 26.6 R θJC R θJA The above data applies to the SMJ320C30 181-pin PGA.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9052604MUA ACTIVE CFP HFG 196 1 TBD Call TI Level-NC-NC-NC 5962-9052604MXA ACTIVE CPGA GB 181 1 TBD Call TI Level-NC-NC-NC 5962-9052604Q9A OBSOLETE XCEPT KGD 0 TBD Call TI Call TI 5962-9052605MUA ACTIVE CFP HFG 196 4 TBD Call TI Level-NC-NC-NC 5962-9052605MXA ACTIVE CPGA GB 181 1 TBD Call TI Level-NC-NC-NC 5962-9052605QXC ACTIVE CPGA GB 181 1 TBD Call TI Level-NC-NC-NC SM320C30GBM40 ACTIVE CPGA GB 181 1 TBD Call TI Level-NC-NC-NC SM320C30GBM50 ACTIVE CPGA GB 181 1 TBD Call TI Level-NC-NC-NC SM320C30HFGM40 ACTIVE CFP HFG 196 1 TBD Call TI Level-NC-NC-NC SM320C30HFGM50 ACTIVE CFP HFG 196 1 TBD Call TI Level-NC-NC-NC SMJ320C30GBM40 ACTIVE CPGA GB 181 1 TBD Call TI Level-NC-NC-NC SMJ320C30GBM50 ACTIVE CPGA GB 181 1 TBD Call TI Level-NC-NC-NC SMJ320C30HFGM40 ACTIVE CFP HFG 196 1 TBD Call TI Level-NC-NC-NC SMJ320C30HFGM50 ACTIVE CFP HFG 196 4 TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 2-May-2005 Addendum-Page 1

MCFP023C – JANUARY 1995 – REVISED JUNE 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HFG (S-CQFP-F196) CERAMIC QUAD FLATPACK WITH NCTB ”C” Á Á Á Á Á Á Á Á Tie Bar Width 2.505 (63,63) 2.485 (63,12) ”B” 0.014 (0,36) 0.002 (0,05) 0.105 (2,67) MAX DETAIL ”C” 0.009 (0,23) 0.004 (0,10) 4040231-6/J 01/99 0.130 (3,30) MAX 0.018 (0,46) MAX 1.365 (34,67) 196 148 147 BSC49 1.200 (30,48) 1.150 (29,21) 1.335 (33,91)SQ ”A” 0.020 (0,51) MAX DETAIL ”B” Braze 0.013 (0,33) 0.007 (0,18) BSC 8 Places DIA 4 Places DETAIL ”A” 0.061 (1,55) 0.059 (1,50) 196 X 0.225 (5,72) 1.710 (43,43) 1.690 (42,93) 0.030 (0,76) 0.040 (1,02) 0.175 (4,45) 0.025 (0,64) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier D. This package is hermetically sealed with a metal lid. E. The leads are gold-plated and can be solder-dipped. F. Leads not shown for clarity purposes G. Falls within JEDEC MO-113AB

MCPG014A – FEBRUARY 1996 – REVISED JANUARY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GB (S-CPGA-P181) CERAMIC PIN GRID ARRAY 4073426/C 11/01 15141311 128967 10 P R N L M K J 5423 G F D C E A B H 0.100 (2,54) TYP 1.560 (39,62)SQ 0.120 (3,05) 0.140 (3,56) 0.045 (1,14) DIA TYP 0.050 (1,27) DIA 0.016 (0,41) 0.022 (0,55) 0.140 (3,55) A1 Corner Bottom View NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark can appear on top or bottom, depending on package vendor. D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edge of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold-plated or solder-dipped. G. Falls within MIL-STD-1835 CMGA7-PN

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