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P-Channel Enhancement MOSFET Elektronische Bauelemente 12-Nov-2010 Rev. A Page 1 of 2 http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. SC-59 Top View A L C B D G H JF K E 1 2 RoHS Compliant Product A suffix of “-C” specifies halogen & lead-free

DESCRIPTION

The miniature surface mount MOSFETs utilize a high cell density trench process To provide low RDS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC conv erters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones.

FEATURES

 Low R DS(on) provides higher efficiency and extends battery life.  Low thermal impedance copper leadframe SC-59 saves board space.  Fast switching speed.  High performance trench technology. PRODUCT SUMMARY PRODUCT SUMMARY VDS(V) RDS(on) ( I D(A)

PACKAGE INFORMATION

SC-59 3K 7’ inch ABSOLUTE MAXIMUM RATINGS AND THERMAL DATA(TA = 25°C unless otherwise specified) PARAMETER SYMBOL RATING UNIT Drain-Source Voltage VDS -30 V Gate-Source Voltage V GS ±20 V Continuous Drain Current A TA=25°C ID -2.5 A TA=70°C -1.7 Pulsed Drain Current B I DM ±12 A Continuous Source Current (Diode Conduction) A I S -1.25 A Power Dissipation A TA=25°C PD -1.3 W TA=70°C -0.8 Operating Junction and Storage Temperature Range TJ, TSTG -55 ~ 150 °C THERMAL RESISTANCE DATA Maximum Junction to Ambient A t≦5 sec RθJA 100 °C/W Steady-State 166 Notes a. Surface Mounted on 1” x 1” FR4 Board. b. Pulse width limited by maximum junction temperature. REF. Millimeter REF. Millimeter Min. Max. Min. Max. A 2.70 3.10 G 0.10 REF. B 2.25 3.00 H 0.40 REF. C 1.30 1.70 J 0.10 0.20 D 1.00 1.40 K 0.45 0.55 E 1.70 2.30 L 0.85 1.15 F 0.35 0.50

P-Channel Enhancement MOSFET Elektronische Bauelemente 12-Nov-2010 Rev. A Page 2 of 2 http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. ELECTRICAL CHARACTERISTICS (T A=25°C unless otherwise specified) PARAMETER SYMBO MIN TYP MAX UNIT TEST CONDITIONS Static Gate-Threshold Voltage V GS(th) -1 - - V V DS = VGS, ID = -250μA Gate-Body Leakage I GSS - - ±100 nA V DS = 0V, VGS= ±20V Zero Gate Voltage Drain Current I DSS - - -1 μA VDS = -24V, VGS= 0V - - -50 V DS = -24V, VGS= 0V, TJ=55°C On-State Drain Current A I D(ON) 10 - - A V DS = -5V, VGS= -10V Drain-Source On-Resistance A R DS(ON) - - 112 mΩ VGS= -10V, ID = -2.5A Forward Transconductance A g FS - 5 - S V DS= -4.5V,,ID = -2.5A Diode Forward Voltage V SD - - -1.2 V I S= -0.75A, VGS=0V Dynamic b Total Gate Charge Q g - 4.5 - nC ID= -2.5A VDS= -30V VGS= -5V Gate-Source Charge Q gs - 1.4 - Gate-Drain Charge Q gd - 2.4 - Turn-On Delay Time T d(on) - 9 - nS ID= -1A, VDD= -30V VGEN= -10V RL= 30Ω Rise Time T r - 12 - Turn-Off Delay Time T d(off) - 25 - Fall Time T f - 14 - Notes a. Pulse test ：PW ≦ 300 us duty cycle ≦ 2%. b. Guaranteed by design, not subject to production testing.