SMD99C DATADELAY | Alldatasheet

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Doc #97018 DATA DELAY DEVICES, INC. 1/30/97 3 Mt. Prospect Ave. Clifton, NJ 07013 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES SMD99C)

FEATURES

Five equally spaced outputs Designed for surface mounting Low profile (0.175 maximum height) Input & outputs fully CMOS interfaced & buffered

10 T2L fan-out capability

The SMD99C-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). The total delay of the line is measured from IN to T5. The nominal tap-to-tap delay increment is given by one-fifth of the total delay. SERIES SPECIFICATIONS Minimum input pulse width: 40% of total delay Output rise time: 8ns typical Supply voltage: 5VDC ± 5% Supply current: ICCL = 40µa typical ICCH = 10ma typical Operating temperature: 0° to 70° C Temp. coefficient of total delay: 300 PPM/°C 20% 20% 20% 20% 20% VDD GND IN DDU8C Functional diagram 1997 Data Delay Devices data delay devices, inc. IN N/C N/C N/C GND VCC N/C N/C N/C IN GND VDD Commercial SMD99C-xx Military SMD99C-xxMC2 PIN DESCRIPTIONS IN Signal Input T1-T5 Tap Outputs VDD +5 Volts GND Ground DASH NUMBER SPECIFICATIONS Part Number Total Delay (ns) Delay Per Tap (ns) SMD99C-5050 50 ± 2.5 10.0 ± 3.0 SMD99C-5060 60 ± 3.0 12.0 ± 3.0 SMD99C-5075 75 ± 4.0 15.0 ± 3.0 SMD99C-5100 100 ± 5.0 20.0 ± 3.0 SMD99C-5125 125 ± 6.5 25.0 ± 3.0 SMD99C-5150 150 ± 7.5 30.0 ± 3.0 SMD99C-5175 175 ± 8.0 35.0 ± 4.0 SMD99C-5200 200 ± 10.0 40.0 ± 4.0 SMD99C-5250 250 ± 12.5 50.0 ± 5.0 NOTE: Any dash number between 5004 and 5250 not shown is also available.

Doc #97018 DATA DELAY DEVICES, INC. 1/30/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com APPLICATION NOTES HIGH FREQUENCY RESPONSE The SMD99C tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition. POWER SUPPLY BYPASSING The SMD99C relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage VDD -0.3 7.0 V Input Pin Voltage VIN -0.3 VDD+0.3 V Storage Temperature TSTRG -55 150 C Lead Temperature TLEAD 300 C 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES High Level Output Voltage VOH 3.98 4.4 V VDD = 5.0, IOH = MAX VIH = MIN, VIL = MAX Low Level Output Voltage VOL 0.15 0.26 V VDD = 5.0, IOL = MAX VIH = MIN, VIL = MAX High Level Output Current IOH -4.0 mA Low Level Output Current IOL 4.0 mA High Level Input Voltage VIH 3.15 V Low Level Input Voltage VIL 1.35 V Input Current IIH 0.10 µA VDD = 5.0

Doc #97018 DATA DELAY DEVICES, INC. 1/30/97 3 Mt. Prospect Ave. Clifton, NJ 07013 PACKAGE DIMENSIONS .350 TYP. SMD99C-xx (Commercial) .510 MAX. .020 .510 MAX. .480 MAX. .150 .100 .150 .050 .150 CL .175 MAX. .015 .050 MIN. .001 MIN. .780±.020 .882 ±.005 .020 TYP. .040 TYP. .100 .090 .600 .280 MAX. .590 MAX. .010±.002 .050 ±.010 .710 ±.005 .007 ±.005 SMD99C-xxMC2 (Military)

Doc #97018 DATA DELAY DEVICES, INC. 1/30/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25oC ± 3oC Load:

1 FAST-TTL Gate

Supply Voltage (VDD): 5.0V ± 0.1V Cload: 5pf ± 10% Input Pulse: High = 5.0V ± 0.1V Threshold: 2.5V (Rising & Falling) Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 5.0 ns Max. (measured between 0.5V and 4.5V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. OUT TRIG IN REF TRIG Test Setup DEVICE UNDER TEST (DUT) TIME INTERVAL COUNTER PULSE GENERATOR COMPUTER SYSTEM PRINTER IN 0.5V 0.5V Timing Diagram For Testing TRISE TFALL PERIN PWIN TRISE TFALL 2.5V 2.5V 4.5V 4.5V 2.5V 2.5V VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL