SMC83C795

83C795 SMSC | Alldatasheet

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Technical content

• 83C795 Data Book

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1.0 GENERAL DESCRIPTION

T he S MC 83C795 E thernet S ys tem Controller im p le m e n t s t h e IEEE 8 02. 3 p ro t o c o l f o r n e t w o rk s s uch as E ther net, Cheaper net, and 10B as eT . I t is a hi ghly i ntegr ated devi ce that s hr i nks the es s ence of a LAN a d a p ter c a rd onto a sing le p ie c e of silic on. It i ncl udes the 8 02 .3 Medi a Acces s Contr ol (MAC) functions , the P hys ical L ayer Interface (P L I) for 1 0 B AS E -T medi a, and a hos t i nter face des i gned for s imple connection to the I ndus try S tandard Architecture (IS A) P C/AT bus . T o cr eate a L AN adapter onl y the 83C79 5 , a s i ngl e buffer R AM, an E E R OM chi p, and an opti onal R OM for B I OS or I P L code s tor age ar e r equir ed. T r ans for mer s and s uppor ti ng anal og components c o m p le t e a n a d a p t e r d e sig n . A ll n e c e ssa ry c o n t ro l l ogi c i s pr ovi ded by the 83C795. T he r es ul ti ng L AN adapter appear s to the hos t as a bl ock of I /O r egi s ter s wi th a bl ock of s har ed memor y, unl es s the I /O pi pe i s us ed. T he bas e addr es s for I /O regis ters is programmable as i s the bas e addr es s and s i z e of the buffer memor y. Th i s d e v i c e i s si m i l a r t o t h e SM C 8 3 C 7 9 0 LA N c o ntro lle r w ith thre e m a jo r d iffe re nc e s:

• A small memory cache has been added for host accesses to shared memory.
• An I/O pipe mode has been added to access the buffer memory.
• Auto-configurability logic has been added in order to comply with the new ISA Plug and Play specification. As with the 83C790 chip, there are two bas i c modes of oper ati on: nor mal and AL T E GO. I n the nor mal m od e, the LAN c ontroller op e ra tes m uc h like the 83C690 L AN Controller with received frames being buffered in a ring of contiguous , fixed-s iz e buffers . When the ALT E GO featur e i s enabl ed, the devi ce s witches to a ver y different mode of oper ation. T he differences ar e s ummari z ed here and expl ai ned in detail throughout the s pecification: 1. Linked-list style of buffering instead of ring buffers. 2. Different register map for LAN controller, ex- posing new registers for the linked-list buff- ering. Figure 1-1 depic ts the 83C795’s func tionality.

2.0 FEATURES

T he bas i c featur es of the 83C795 chip ar e sum m a rized here:

• Memory caching with time-shared access to buffer RAM.
• Compliant with the ISA Plug And Play specification
• Software compatible with 83C790 drivers
• Direct interface with ISA bus without TTL buffers
• I/O-mapped pipe access to buffer RAM
• Extended length option for the twisted-pair port
• Underrun detection in early receive mode
• Staggered address transfers supported
• Ring-empty bit supplied to host
• Automatic ring-wrapping
• PC-98 bus support through addition of a jumper
• Buffered 20 MHz clock output available through addition of a jumper
• Support for diskless workstations via Initial Program Load ROM
• Programmable base address and window size for buffer memory and IPL ROM
• Support for paging of buffer memory and IPL ROM
• Programmable I/O base address
• Programmable bus width of either 8 or 16 bits
• Zero wait state operation
• Automatic loading of host interface configuration and LAN address from external serial EEPROM
• Separate address and data busses to memory with no external address latches
• 7 programmable interrupt levels
• Clock oscillator
• Full 802.3 MAC layer protocol implementation with extended features
• Support for transmission and reception of frames up to 32K bytes long
• Transmit frame start at any location - no word alignment required
• Two modes of frame buffering: 83C690 mode and descriptor table mode
• Loopback modes - internal and external
• Full-duplex DMA capability in loopback mode
• Built-in AUI serial interface including drivers and receivers GENERAL DESCRIPTION 83C795

• Built-in 10BASE-T serial interface for Ethernet on Twisted-Pair including drivers and receivers
• Manchester Encoder/Decoder with clock recovery circuitry
• Multicast addressing using 64-bit hashing algorithm
• I/O pin mapping enables rapid board test development
• 160-pin PQFP package for surface mounting. FIGURE 1-1. 83C795 BLOCK DIAGRAM 83C795 FEATURES

3.0 FUNCTIONAL DESCRIPTION

T he pr i nci pl e s ecti ons of the devi ce ar e the:

• Host interface which mediates host access to internal registers and buffer memory.
• LAN Controller which performs 802.3 MAC layer protocol and does supporting DMA transfers to and from local buffer memory.
• Serial line interface which supplies drivers and receivers for AUI and TP interfaces and port control logic for the 10BASE-T interface. In addition, it provides Manchester encoding and decoding.

3.1 DESCRIPTION OF DATA PATH

Figure 3-1 illustrates the data path for a 83C79 5 -bas ed boar d. Al l i nter nal byte s wappi ng i s handl ed by the memor y cache. T he data bus dri ver s ar e des igned to drive the I S A bus dir ectl y.

3.2 CONVENTIONS

A number of conventi ons ar e us ed i n thi s databook . 1. A bit may be described as "low" or "logical 0" when its value is set to 0. A bit is described as "high" or "logical 1" when its value is set to 1. 2. The location of a bit is frequently described in this manner: <register>.<bit> For example, since the bit MENB is located in the CR Register, it might be described in this book as CR.MENB. Or, alternatively, since MENB is the sixth bit in the CR Regis- ter, it might also be described in this manner: CR.6 FUNCTIONAL DESCRIPTION 83C795

FIGURE 3-1. 83C790 DATA PATH FLOW 83C795 FUNCTIONAL DESCRIPTION

T he S MC 83C795 E thernet S ys tem Controller im p le m e n t s t h e IEEE 8 02. 3 p ro t o c o l f o r n e t w o rk s s uch as E ther net, Cheaper net, and 10B as eT . I t is a hi ghly i ntegr ated devi ce that s hr i nks the es s ence of a LAN a d a p ter c a rd onto a sing le p ie c e of silic on. It i ncl udes the 8 02 .3 Medi a Acces s Contr ol (MAC) functions , the P hys ical L ayer Interface (P L I) for 1 0 B AS E -T medi a, and a hos t i nter face des i gned for s imple connection to the I ndus try S tandard Architecture (IS A) P C/AT bus . T o cr eate a L AN adapter onl y the 83C79 5 , a s i ngl e buffer R AM, an E E R OM chi p, and an opti onal R OM for B I OS or I P L code s tor age ar e r equir ed. T r ans for mer s and s uppor ti ng anal og components c o m p le t e a n a d a p t e r d e sig n . A ll n e c e ssa ry c o n t ro l l ogi c i s pr ovi ded by the 83C795. T he r es ul ti ng L AN adapter appear s to the hos t as a bl ock of I /O r egi s ter s wi th a bl ock of s har ed memor y, unl es s the I /O pi pe i s us ed. T he bas e addr es s for I /O regis ters is programmable as i s the bas e addr es s and s i z e of the buffer memor y. Th i s d e v i c e i s si m i l a r t o t h e SM C 8 3 C 7 9 0 LA N c o ntro lle r w ith thre e m a jo r d iffe re nc e s:

• A small memory cache has been added for host accesses to shared memory.
• An I/O pipe mode has been added to access the buffer memory.
• Auto-configurability logic has been added in order to comply with the new ISA Plug and Play specification. As with the 83C790 chip, there are two bas i c modes of oper ati on: nor mal and AL T E GO. I n the nor mal m od e, the LAN c ontroller op e ra tes m uc h like the 83C690 L AN Controller with received frames being buffered in a ring of contiguous , fixed-s iz e buffers . When the ALT E GO featur e i s enabl ed, the devi ce s witches to a ver y different mode of oper ation. T he differences ar e s ummari z ed here and expl ai ned in detail throughout the s pecification: 1. Linked-list style of buffering instead of ring buffers. 2. Different register map for LAN controller, ex- posing new registers for the linked-list buff- ering. Figure 1-1 depic ts the 83C795’s func tionality.

T he bas i c featur es of the 83C795 chip ar e sum m a rized here:

• Memory caching with time-shared access to buffer RAM.
• Compliant with the ISA Plug And Play specification
• Software compatible with 83C790 drivers
• Direct interface with ISA bus without TTL buffers
• I/O-mapped pipe access to buffer RAM
• Extended length option for the twisted-pair port
• Underrun detection in early receive mode
• Staggered address transfers supported
• Ring-empty bit supplied to host
• Automatic ring-wrapping
• PC-98 bus support through addition of a jumper
• Buffered 20 MHz clock output available through addition of a jumper
• Support for diskless workstations via Initial Program Load ROM
• Programmable base address and window size for buffer memory and IPL ROM
• Support for paging of buffer memory and IPL ROM
• Programmable I/O base address
• Programmable bus width of either 8 or 16 bits
• Zero wait state operation
• Automatic loading of host interface configuration and LAN address from external serial EEPROM
• Separate address and data busses to memory with no external address latches
• 7 programmable interrupt levels
• Clock oscillator
• Full 802.3 MAC layer protocol implementation with extended features
• Support for transmission and reception of frames up to 32K bytes long
• Transmit frame start at any location - no word alignment required
• Two modes of frame buffering: 83C690 mode and descriptor table mode
• Loopback modes - internal and external
• Full-duplex DMA capability in loopback mode
• Built-in AUI serial interface including drivers and receivers GENERAL DESCRIPTION 83C795

• Built-in 10BASE-T serial interface for Ethernet on Twisted-Pair including drivers and receivers
• Manchester Encoder/Decoder with clock recovery circuitry
• Multicast addressing using 64-bit hashing algorithm
• I/O pin mapping enables rapid board test development
• 160-pin PQFP package for surface mounting. FIGURE 1-1. 83C795 BLOCK DIAGRAM 83C795 FEATURES

T he pr i nci pl e s ecti ons of the devi ce ar e the:

• Host interface which mediates host access to internal registers and buffer memory.
• LAN Controller which performs 802.3 MAC layer protocol and does supporting DMA transfers to and from local buffer memory.
• Serial line interface which supplies drivers and receivers for AUI and TP interfaces and port control logic for the 10BASE-T interface. In addition, it provides Manchester encoding and decoding.

Figure 3-1 illustrates the data path for a 83C79 5 -bas ed boar d. Al l i nter nal byte s wappi ng i s handl ed by the memor y cache. T he data bus dri ver s ar e des igned to drive the I S A bus dir ectl y. A number of conventi ons ar e us ed i n thi s databook . 1. A bit may be described as "low" or "logical 0" when its value is set to 0. A bit is described as "high" or "logical 1" when its value is set to 1. 2. The location of a bit is frequently described in this manner: <register>.<bit> For example, since the bit MENB is located in the CR Register, it might be described in this book as CR.MENB. Or, alternatively, since MENB is the sixth bit in the CR Regis- ter, it might also be described in this manner: CR.6 FUNCTIONAL DESCRIPTION 83C795

FIGURE 3-1. 83C790 DATA PATH FLOW 83C795 FUNCTIONAL DESCRIPTION

4.0 PIN LIST

This section provides the pin list and pin/signal descriptions for the 83C795. Section 4.1 describes the input-to-output pin mapping feature. FIGURE 4-1. 83C790 PIN OUT DIAGRAM (160 PINS) PIN LIST 83C795

Mnemonic Pin Number I/O Description AE N 93 I P C ADDR E S S E NAB L E . Active low. When Addres s E nable is active the 83C795 res ponds to any hos t s trobe (IO R, IO W, ME MR , ME MW, SM EM R, SM EM W ) . BA LE 29 I PC ADDRE S S LA T CH E NABLE . Used to latc h valid add resses f ro m t h e LA b u s. Pa sse s LA sig n a ls t h ro u g h in t e rn a l la t c h e s w h ile hi gh and l atches them on fal l i ng edge. BSR 1 15 I BIAS RE S IS T OR. A resistor from BS R to VDD sets the internal b ia s le vels. Nom ina l va lue is 10KΩ . CAP 113 I P L L F I L T E R CAP. A capaci tor (nomi nal val ue . 0 1µF ) fr om CAP to gr ound is us ed as part of the fi lter for the i nter nal phas e lock loop. CD+ CD- 126 125 I AU I COL L I S I ON. CD+ / CD- are us ed by the external tr ans ceiver t o sig n a l a c o llisio n b y se n d in g a 10M Hz sig n a l. EEC S 132 O EEROM Chip S elec t. An external 9356 serial EEROM is used to s tor e up to 2048 bits of configurati on data. T hes e s ignals (along wi th LLED a n d R L E D) i nter f ace wi th that chi p. EED O 137 I/O EERO M D A TA O UTPUT. GP OU T 110 O G EN ERA L PURPO SE O UTPUT. In so m e sy st e m s, t h is b it is w ire d to a s hutdown contr ol input of the DC/DC is olated power s upply u se d in 10Ba se 2 a p p lic a t io n s. In o t h e r sy st e m s, t h is su p p lie s a c o n t ro l sig n a l f o r sw it c h in g p o w e r su p p lie s. ( Th e D C sig n a l’ s p ola rity on the 83C795 is the opp osite of the 83C790.) HO S T CLK 71 I/O P er s onal Computer B U S CL OCK . IO 16C S 28 O 16 B I T I/O S E L E CT E D. Active low. I ndicates to the P C/AT bus that the I/ O response will be 16 bits wide. Only used for the I/ O pipe. IO R 72 I/O P C I/O R E AD. Active low. R eads an I/O regis ter onto the P C data bus . IO RDY 90 O I/O IOR DY. R es pons e to hos t acces s which can be us ed directly as ’I /O Channel R eady’ when r es pondi ng to a per s onal computer b us. It is pulled low (not ready) to lengthen I/ O or memory c yc les. When the 8 3 C795 i s r eady to r es pond, the s i gnal i s dr i ven hi gh until the hos t acces s is completed, then becomes tris tated. T his s i gnal i s dr i ven by a tr i - s tate buffer capabl e of s i nk i ng 24 mA. IO W 73 I/O PC I/ O WRIT E. Ac tive lo w . Write s a n I/ O re g iste r fro m the PC d a ta bus . IRQ1 108 I/O PC INT E RRUPT RE QUE S T LINE S . Ac tive high. T rista ted when not active. IR Q2-9 on the P C/AT bus . IR Q1 is the s ame as the XTXD p in in so m e te st m o d e s. IRQ 2 95 I/O IRQ 3 o n PC / A T b u s. Sa m e a s XLO O P in so m e t e st m o d e s. IRQ3 106 I/O IRQ 5 o n PC / A T b u s. Sa m e a s XC RS in so m e t e st m o d e s. IRQ4 107 I/O IRQ 7 o n PC / A T b u s. Sa m e a s XRXC in so m e t e st m o d e s. IRQ 5 25 I/O IRQ10 on PC/ A T bus. S ame as XRXD in some test modes. IRQ 6 24 I/O IRQ11 on PC/ A T b us. S ame as XCOL in some test modes. IRQ 7 23 I/O IRQ15 on PC/ A T bus. S ame as XT XC in some test modes. TABLE 4-1. 83C795 PIN ASSIGNMENTS 83C795 PIN LIST

Mnemonic Pin Number I/O Description LA17-LA23 13-19 I/O PC LA A D D RESS BUS. A d v a n c e d t im i n g v e rsi o n o f sy st e m a d d re ss lin e s A 23 -A 17 f ro m PC / A T b u s. Th e se a re n o t a ssu m e d t o be s table during the entire hos t cycle and are latched internally by the B AL E s i gnal (fal l i ng edge). T hes e s i gnal s ar e acti ve hi gh. LLED 131 I/O T WPR LINK S TA T US . If valid data or Link Test pulses are rec eived o n TPR+ / TPR-, LLE D is low (link status OK). When no d ata or L i nk T es t pul s es ar e r ecei ved, LLED is h ig h . Th e LLED p in c a n s ink 4mA to drive an external L E D. T his pin als o functions as the EERO M c lo c k p in ( f o rm e rly EESK) a n d f u n c t io n s a s t h e sh if t c o ntro l p in (fo rm e rly SHIFTIN) in sc a n m o d e . M16CS 26 O ME MOR Y 16 S E L E CT E D. Active low. Indicates to the P C/AT bus t h a t RA M a c c e ss re sp o n se is 16 b it s w id e . MA15-MA10 139-144 O ME MOR Y ADDR E S S L I NE S . T hes e pins br ing out the DMA addr es s to memor y or feed-thr ough the hos t addr es s as modi fi ed for paging. When dumping R OM contents , thes e pi ns pr es ent RO M d a t a b it s: MA15 R OM30 then R OM31 MA14 R OM28 then R OM29 . . . MA00 R OM00 then R OM01 MA09/JMP 9 MA08/JMP 8 MA07/JMP 7 MA06/JMP 6 MA05/JMP 5 MA04/JMP 4 MA03/JMP 3 MA02/JMP 2 MA01/JMP 1 MA00/JMP 0 145 146 148 149 150 151 152 153 154 155 I/O S ame as other MA lines except that dur ing R E S E T , the drivers ar e di s abled and the I NI T jumper s ar e read through thes e pins and latc hed at the trailing edge of RE S E T. T hey are a c tive high and a re p ulle d up w e a kly b y inte rna l re sisto rs (35kΩ –150kΩ ). To set a zero va lue on the se p ins, use a n externa l p ull-d o w n res is tor of 3.6KΩ . MD7 MD6-MD0 158 3-9 I/O ME MOR Y DAT A L I NE S . T hes e pins connect to the data pins of the buffer R AM and the I P L or boot R OM. ME MR 12 I/O P C ME MOR Y R E AD for addres s es exceeding 1 M. Active low. ME MW 10 I/O P C ME MOR Y WR I T E for addr es s es exceeding 1 M. Active low. OS R 112 I VCO B I AS R E S I S T OR . A res is tor from OS R to VCC bias es the interna l VCO c urrent. Nom ina l va lue is 24.9KΩ .. RAMOE 156 O R AM OU T P U T E NAB L E . Active low. RAMWR 157 O R AM WR I T E E NAB L E . Active low. RESET 95 I/O SYSTEM RESET. A c t iv e h i g h . TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.) PIN LIST 83C795

Mnemonic Pin Number I/O Description RLED 130 I/O RE CV LE D DRIVE R. When on, RLE D drives low to turn on an external LE D. If no data is rec eived, RLE D is off. If data is rec e ived , R L E D goes acti ve for appr oximately 50ms longer than the rec eived pac ket length. T his pin also serves as the E E ROM d ata in p in (E E DI) and is used as the sc an data input (formerly SC A N IN ) i n sc a n m o d e . ROMCS 138 O BIOS ROM OUT PUT E NABLE . Ac tive low . Chip S elec t for ROM BIOS . Used for XT XE in some test modes. RX+ RX- 124 123 I AU I R E CE I VE . T he Manches ter encoded data fr om the external tra nsc eiver is rec eive d on RX+ / RX-. S A19 - 14 S A13 - 11 S A10 - 09 S A08 - 06 S A05 - 00 88 - 83 78 - 76 44 - 43 38 - 37 35 - 30 I/O PC A D D RESS BUS. N o rm a l t i m i n g v e r si o n o f sy st e m a d d re ss lines . T hes e s ignals ar e acti ve high. SBH E 2 0 I P C B U S H I GH E NAB L E . Acti ve l ow. I ndi cates a tr ans fer of data on the upper byte of the data bus , S D8 through S D15. S D15 - 14 S D13 - 12 SD 1 1 - 1 0 S D09 - 08 SD 0 7 S D06 - 04 S D03 - 02 S D01 - 00 45 - 46 48 - 49 51 - 52 54 - 55 65 - 63 61 - 60 58 - 57 I/O SYSTEM D A TA BUS. D a t a i n p u t a n d o u t p u t t o h o st a n d sh a r e d memor y. T hes e s i gnal s ar e acti ve hi gh. SM EM R 7 4 I/O LO W M EM O RY REA D STRO BE. Re a d s b u f f e r m e m o ry o n t o t h e PC da ta b us. It is ac tive only when the memory ad dress is within the fir s t 1Mb of memor y s pace. Acti ve l ow. SM EM W 7 5 I/O LOW ME MORY WRIT E S T ROBE . Writes buffer memory from the PC d a ta b us. S ME MW i s acti ve only when the memory addr es s i s within the firs t 1Mb of memory s pace. Active low. TESTA TESTB 117 118 I I/O-MAPPING CONTROL PINS. All signal pins on the 83C795 (except for the analog pins) have been divided into two groups, GROUPA and GROUPB. The functionality of these pins is controlled by the two test pins, as follows: TESTA TESTB GROUPA GROUPB 1 1 NORMAL NORMAL 1 0 1 0 0 1 0 1 0 0 TRISTATE TRISTATE TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.) 83C795 PIN LIST

Mnemonic Pin Number I/O Description T LED 129 O T R ANS MIT LE D DR IVE R . When on, T L E D drives low to turn on an ex ter nal L E D. When ther e i s no tr ans mi s s i on (T X E i nacti ve), TLED is o ff. Whe n d a ta is tra nsm itte d , TLED g o e s a c t iv e f o r approximately 50ms longer than the trans mitted packet length. T L E D does not go acti ve for L i nk T es t pul s es . T hi s pi n al s o s er ves as the s can data output (former ly S CANOU T ) i n s can mode, or as a 20 MH z buffer ed cl ock output i f J U MP E R 8 i s i ns tal l ed. TPR+ TPR- 128 127 I TW PR REC EIV E. In 1 0 Ba se T o p e ra t i o n , M a n c h e st e r e n c o d e d - d a t a a r e r e c e i v e d v i a TPR+ / TPR- . Th e y a r e c o n n e c t e d t o t h e twi s ted pai r medi um thr ough a tr ans for mer and fi l ter. TPX1 + TPX1 - 103 102 O TW PR TRA N SM I T. TPX1 + a n d TPX1 - a r e u se d f o r 1 0 Ba se T o n l y . T hey are the high cur rent pos itive and negative output pi ns . TPX2 + TPX2 - 104 101 O TW PR TRA N SM I T. TPX2 + a n d TPX2 - a r e u se d f o r 1 0 Ba se T o n l y . T hey are the low curr ent pos itive and negati ve output pins . TX+ TX- O AUI T RANS MIT. T X+ and T X- transmit differentia l, Manc hester encoded data to the tr ans ceiver. T hes e ar e cur rent-dr iving outputs that furnis h E CL level s ignals when connected to requi red exter nal p u llu p re sist o rs o f 150Ω . VDD (14 pins ) 22, 41, 42, 47, 53, 59, 67, 68, 81, 82, 105, 111, 116, 119, 120, 134, 135, 159, 160 + 5 V O L T SO URC ES. So m e a re f o r lo g i c , so m e p o w e r t h e p i n dr i ver s , and other s pr ovi de power to the anal og por ti ons of the ci r cui t. VS S (24 pins ) 1, 2, 11, 21, 27, 39, 40, 50, 56, 62, 66, 70, 79, 80, 89, 92, 94, 100, 114, 121, 122, 133, 136, 147 GR OU ND. S ome are for logic, s ome power the pin dri ver s , and other s pr ovi de power to the anal og por ti ons of the cir cui t. I O CR Y S T AL OS CI L L AT OR . T he crys tal i s attached acr os s thes e two p ins. Must b e 20.000 MHz ± 50 ppm. T his c loc k operates the chi p’s l ogi c and i s di vi ded by 2 i nter nal l y to become the tr ans mi t cl ock . ZW S 91 O PC Z E RO WAIT S TA T E . Ac tive low . Zero Wa it S tate signal tells the microproces s or that it can complete the pres ent bus cycle wi thout ins er ting any addi ti onal wai t cycl es . ZW S is d riv e n b y a tri-sta te d rive r c a p a b le o f sinking 24 m A. TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.) PIN LIST 83C795

4.1 SPECIAL INPUT-TO-OUTPUT PIN MAPPING

The 83C795 provides a special pin mapping feature which can be used for testing. The pins are divided into two groups, GROUPA and GROUPB, for the new I/O pin mapping scheme. GROUPA PINS GROUPB PINS PIN NAME PIN NAME 3M D 0 6 4 M D 0 5 5M D 0 4 6 M D 0 3 7M D 0 2 8 M D 0 1 9M D 0 0 1 0 ME MW

12 ME MR 13 L A17

14 LA18 15 LA19

16 LA20 17 LA21

18 LA22 19 LA23

24 IRQ6 25 IRQ15

29 BALE 30 S A00

31 S A01 32 S A02

33 S A03 34 S A04

35 S A05 36 S A07

37 S A06 38 S A08

43 S A09 44 S A10

45 S D15 46 S D14

48 S D13 49 S D12

51 S D11 52 S D10

54 S D09 55 S D08

57 S D00 58 S D01

60 S D02 61 S D03

63 S D04 64 S D05

65 S D06 69 S D07

71 BS CK 72

73 IO W 74 SM EM R

75 SM EM W 7 6 SA 1 1

77 S A12 78 S A13

83 S A14 84 S A15

85 S A16 86 S A17

87 S A18 88 S A19

TABLE 4-2. I/O PIN MAPPING SCHEME 83C795 PIN LIST

The I/O pin mapping test for this chip requires only two static vectors. The inputs you must set along with the desired output values are listed in Table 4-3. VECTOR PIN DRIVEN HIGH PINS DRIVEN LOW PINS OUTPUTTING 1’s PINS OUTPUTTING 0’s

1 TESTA , RXP ,

TPRP , C D P TESTB, RXM , TPRM , C D M GR OU PA pins GR OU P B pi ns

2 TESTB, RXM ,

TPRM , C D M TESTA , RXP , TPRP , C D P GR OU P B pins GR OU PA pins TABLE 4-3. I/O PIN OUTPUT VALUES Note This arrangement does not test the 83C795’s analog outputs. GROUPA PINS GROUPB PINS PIN NAME PIN NAM,E

90 IORDY 91 ZW S

93 AEN 95 IRQ2

106 IRQ3 107 IRQ4

108 IRQ1 109 RES ET

110 GPOUT 129 RXM

132 EECS 137 EEDO

140 MA14 141 MA13

142 MA12 143 MA11

144 MA10 145 MA09

146 MA08 148 MA07

149 MA06 150 MA05

151 MA04 152 MA03

153 MA02 154 MA01

155 MA00 156

157 RAMWR 158 MD07

TABLE 4-2. I/O PIN MAPPING SCHEME (CONT.) PIN LIST 83C795

5.0 ETHERNET SYSTEM CONTROLLER

T he regis ter s tructure of the 83C795 i s di vi ded into two regis ter groups : the Hos t Interface regis ters and the L AN Contr ol ler regis ters . T he followi ng s ections des cribe the contents of each of thes e r egis ter s , detai l the way they ar e acces s ed, and how they ar e us ed. T abl es 5 -1 thr ough 5 -3 pr ovi de a bri ef over vi ew of thes e r egi s ter s . R efer to the R egi s ter S ummar y tabl es at the end of this se c tio n fo r a q uic k refere nc e g uid e to a ll re le va nt re g iste r b it va lue s. OFFSET SWH = 0 SWH = 1

00 CR CR

01 EER EER

02 IOPL IOPL

03 IOPH IOPH

04 HWR HWR

05 BPR BPR

06 ICR ICR

07 REV/IOPA REV/IOPA

08 LAN0 GCR2

09 LAN1 —

TABLE 5-1. HOST INTERFACE REGISTERS SUMMARY 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

10 CMD CMD CMD CMD CMD CMD CMD CMD

11 INCRL RSTART STA0 STA0 RSTART INCRL TEST TEST

12 INCRH RSTOP STA1 STA1 RSTOP INCRH RTEST RTEST

13 BOUND BOUND STA2 STA2 TCNTL void TTEST TTEST

14 TSTAT TSTARTH STA3 STA3 TSTARTH void TEST2 TEST2

15 COLCNT TCNTL STA4 STA4 NEXT NEXT TSTARTL TSTARTL

16 {0} TCNTH STA5 STA5 TCNTH void {0} void

17 INTSTAT INTSTAT CURR CURR ENH ENH — —

18 ERWCNT ERWCNT GROUP0 GROUP0 RADDL RADDL — —

19 RENH RENH GROUP1 GROUP1 RADDH RADDH — —

1A RCNTL void GROUP2 GROUP2 TADDL TADDL — — 1B RCNTH void GROUP3 GROUP3 TADDH TADDH — — 1C RSTAT RCON GROUP4 GROUP4 RCON void — — 1D ALICNT TCON GROUP5 GROUP5 TCON void — void 1E CRCCNT DCON GROUP6 GROUP6 DCON void — void 1F MPCNT INTMASK GROUP7 GROUP7 INTMASK void MANCH MANCH TABLE 5-2. LAN CONTROLLER REGISTERS - NORMAL MODE OFFSET PAGE 0 READ PAGE 0 WRITE PAGE 1 READ PAGE 1 WRITE PAGE 2 READ PAGE 2 WRITE PAGE 3 READ PAGE 3 WRITE 11 — RBEGIN STA0 STA0 RBEGIN — — — 12 — REND STA1 STA1 REND — — —

13 CURRL CURRL STA2 STA2 TBEGIN void — —

14 TSTAT TEND STA3 STA3 TEND void — —

15 COLCNT TBEGIN STA4 STA4 — void TSTARTL TSTARTL

16 ERWCNT ERWCNT STA5 STA5 — void {0} void

17 INTSTAT INTSTAT CURRH CURRH ENH ENH — —

18 RTABL RTABL GROUP0 GROUP0 RDOWNL RDOWNL — —

19 RTABH RTABH GROUP1 GROUP1 RDOWNH RDOWNH — —

1A TTABL TTABL GROUP2 GROUP2 TDOWNL TDOWNL — — 1B TTABH TTABH GROUP3 GROUP3 TDOWNH TDOWNH — — 1C RSTAT RCON GROUP4 GROUP4 RCON void — — 1D ALICNT TCON GROUP5 GROUP5 TCON void — void 1E CRCCNT — GROUP6 GROUP6 DCON void — void 1F MPCNT INTMASK GROUP7 GROUP7 INTMASK void MANCH MANCH TABLE 5-3. LAN CONTROLLER REGISTERS - LINKED-LIST MODE ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.1 HOST INTERFACE INTERNAL

Th e f o llo w in g se c t io n d e sc rib e s t h e c o n t e n t s o f t h e Hos t I nterface I nternal r egis ter s . T his r egis ter s et cons is ts of 24 regis ters ar ranged i n three gr oups of eight. T hes e three groups are the L AN Addr es s re g isters, the Ha rd w a re Co nfig ura tio n re g iste rs (which write to and read from the E E R OM), and the Hardware Control r egi s ter s . T he S wi tch R egis ter bit (HWR .S WH) determines whether the L AN Addres s R egis ters (S WH = 0) or the Hardware Confi gur ati on R egi s ter s (S WH = 1) ar e vi s i bl e at any one ti me. (S ee H WR - H ar dwar e S uppor t R egi s ter on page 16 for mor e infor mati on on thi s b it.) T he Ha rd w a re Contro l reg isters (inc lud ing the C R, EER, HWR, BPR, IC R, a n d REV re g ist e rs) a re al ways vi s i bl e. Bit s w it h in re g ist e rs m a y a lso h a v e d if f e re n t functions depending on whether they ar e read from or written to. T hroughout this s ection, certain terms are us ed to des cr i be each r egi s ter and ar e defi ned bel ow: Term Definition RESET Value During RESET Time INIT If the INIT3, 2, 1, 0 jumpers = 1001, this value is loaded into the register immediately after RESET TIME. Some of these values are forced by hardware and others are recalled from EEROM. Recall time is on the order of 2 msec. While the initial recall is ongoing, register may have either the RESET or INIT values RECALL This value is loaded when a recall is performed other than after a RESET. REGISTER VALUES Possible register values are: 1 = logical 1 0 = logical 0 PIN = value unknown or wired to external pin. EE = value loaded from EEROM. — = not used. TABLE 5-4. REGISTER TERM DEFINITIONS

5.1.1 CR - Control Register

Re a d / Write Po rt = 00 T his re g iste r ha s c o ntro l o ve r b uffe r m e m o ry e n a b lin g a n d so f t re se t o f t h e LA N c o n t ro lle r . BIT CR RESET

7 RNIC 1

6 MENB 0

5— 0

4 CR4 0

3 CR3 0

2 RP15 0

1 RP14 0

0 RP13 0

Bit 7: RNIC, Reset Network Interface Controller S et R NIC to 1 then back to 0 to force a hardware re se t to the LAN C o ntro lle r. Bit 6: MENB, Memory Enable S et ME NB to 1 to enable hos t acces s to s hared memor y. Bit 4-3: CR4-CR3, Reserved For Increase In RP Field Bit 2-0: RP15-RP13, RAM Offset A buffer addr es s i s cr eated by addi ng the contents of thi s field to the differ ence between the buffer bas e addr es s and the addr es s s uppl i ed by the SA 1 9 - SA 0 0 l i n e s. Th i s su m i s t r e a t e d a s a m o v a b l e page offs et which i s then ins er ted into the buffer window. T hi s offs et val ue s hould only be us ed when the memor y pr ovi ded is larger than the window se le c t e d .

5.1.2 EER - EEROM Register

Re a d / Write Po rt = 01 T hi s r egi s ter contr ol s the s tor es to and r ecal l s fr om E E R OM. I n addition, four input pins are vis ible thro ug h this re g ister. Som e b its ha ve d iffe re nt functions when read than when written. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

5 EA4 0

4 UNLOCK 0

3 JMP3 PIN

2 JMP2 PIN

1 JMP1 PIN

0 JMP0 PIN

3 EA3 0

2 EA2 1

1 EA1 1

0 EA0 0

Bit 7: STO, Store Into Non-Volatile EEROM S et this bit to 1 to s tore the 8 L AN addres s regis ters into the E E R OM. T he bit automatically res ets when the store is c om p lete. T his func tion w ill not b e p e rf o rm e d u n le ss t h e st o ra g e c irc u it h a s b e e n a rm e d b y a se rie s o f a c c e sse s t o t h e EER Re g ist e r. (S e e S ec tion 6.5.2.3 for d e ta ils.) Bit 6: RC, Recall EEROM S et this bit to 1 to recall the 8 L AN addres s regis ters fr om E E R OM. T he bi t wi l l be automati cal l y r es et when the r ecal l i s compl ete. Bit 4: UNLOCK, Unlock Store T his bit is us ed to unlock the E E P R OM for s torage Bits 3-0: JMP3-JMP0, Initialization Jumpers T hes e bits are wired to the JMP input pins of the chip. T he JMP fi el d value is us ed by the r ecall l ogic to determine which bank of E E R OM to load the hos t i nter face confi gur ati on r egi s ter s fr om. Bits 5, 3-0: EA4-EA0, EEROM Address Field T hi s fi el d deter mi nes whi ch bank of E E R OM the LA N a d d re ss re g ist e rs a re st o re d in t o o r re c a lle d from. T his field does not change when a recall op e ra tion ta ke s p la c e. EA4 = 1 ind ic a te s a n a c c ess t o th e Plu g a nd Pla y re so u rc e string .

5.1.3 IOPL - I/O Pipe Data Location Low

Re a d / Write Po rt = 02 T his regis ter and I OP H determi ne the locations data is read from or written to. BIT IOPL RESET

7 IOP7 0

6 IOP6 0

5 IOP5 0

4 IOP4 0

3 IOP3 0

2 IOP2 0

1 IOP1 0

0 IOP0 0

Bits 7-0: IOP7-0, I/O Pipe Data Location Low When I OP E N (I CR .4) is s et, thes e ar e the locations t ha t d a t a is re a d fro m o r w rit te n t o in t he I/ O p ip e oper ation. Al l 8-bit oper ati ons mus t take place thro ug h IO PL o nly .

5.1.4 IOPH - I/O Pipe Data Location High

Re a d / Write Po rt = 03 T his regis ter and IOP L determine the locations data is read from or written to. BIT IOPH RESET

7 IOP15 0

6 IOP14 0

5 IOP13 0

4 IOP12 0

3 IOP11 0

2 IOP10 0

1 IOP9 0

0 IOP8 0

Bits 15-8: IOP15-8, I/O Pipe Data Location High When I OP E N (I CR .4) is s et, thes e ar e the locations t ha t d a t a is re a d fro m o r w rit te n t o in t he I/ O p ip e oper ation. Al l 8-bit oper ati ons mus t take place through the IOP L regis ter. ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.1.5 HWR - Hardware Support Register

Re a d / Write Po rt = 04 T his re g iste r is use d to c o ntro l g e ne ra l p urp o se outputs and to s wi tch between confi gur ati on and L AN Addres s regis ters . BIT HWR READ RESET 7S W H 0 6— 0

5 ETHR 1

4 HOST16 0

3— 0

2 ISTAT 0

1 PNPJMP JMP6

6— 0 5— 1 4— 0

3 NUKE 0

2— 0 1— 0 0G P O E 0 Bit 7: SWH, Switch Register Set Th is b it se le c t s b e t w e e n t h e LA N A d d re ss re g ist e rs and the B oard Configuration regis ters in the regis ter map where: SWH = 0 - LAN Address Registers are visible SWH = 1 - Configuration Registers are visible Bit 5: ETHER, MAC Protocol Type When E T HE R = 1, the 802.3 pr otocol is provided by this d evic e. T he 83C795 sup ports o nly 802.3. Bit 4: HOST16 T his b it rep orts whether the 83C795 b elieves it is connected to an 8-bit or 16-bit hos t. T he chip deter- mines this by looking at the ME MR pin for acti vi ty. Where: HOST16 = 0 - 8-bit host HOST16 = 1 - 16-bit host Bit 3: NUKE, Restart T his bit i s ’OR ’ed together with the R E S E T pin s ignal to form the internal R E S E T for the chip. S etting this bit has the s ame effect on the 83C795 as cycl i ng power on the hos t machi ne. T he chi p wi l l re se t to its initia l c o nd itio n a nd re lo a d fro m the E E R OM. T his bit is cleared when the res et be- comes effective. T he NU K E r es et executes for 256 chi p-cl ock cycl es to al l ow the MA bus to fl oat and the i ni tializ ation jumper s to achieve thei r true val - ues . Note Do not try to access this chip during reset. Bit 2: ISTAT, Interrupt Status IS T AT returns to 1 when Network Interface Control- ler has an interrupt active. Bit 1: PNPJMP , Plug and Play Jumper Installed A rea d -only b it tha t returns a 1 if jum p er 6 is in- st a lle d . If PNPJM P = 1 a n d t he PNPEN b it (ER- F AL .0) is s et, then P lug and P lay hardware is enabled. Bit 0: GPOE, GPX Pin Output Enable T he output i s enabl ed when GP OE = 1 . 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

5.1.6 BPR - BIOS Page Register

Re a d / Write Po rt = 05 T hi s r egi s ter contr ol s mapping of R OM window to R OM addr es s and other mi s cel l aneous contr ol s . BIT BPR RESET

7 M16EN 0

6 BP15 0

5 BP14 0

4 BP13 0

3— 0 2— 0

1 SOFT1 0

0 SOFT0 0

Bit 7: M16EN, Memory 16-bit Enable S et M16E N to 1 to enable 16-bit memory acces s by the hos t. T his s hould be only s et when all interrupts have been di s abled. S ee page 17 for details . Bits 6-4: BP15-13, ROM Offset R OM addr es s i s cr eated by addi ng the contents of this field to the di ffer ence between R OM bas e ad- dr es s and the addr es s s uppl i ed on the S A19 - S A00 l i nes . T hi s s um s er ves as a movabl e page offs et into the R OM window. It is intended that the offs et be us ed only when the R OM pr ovi ded is l ar ger than the window s el ected. Bits 1-0: SOFT1-SOFT0 T hese bits are written a nd read by software. T hey may be used as ’c laim’ b its for alloc a tion of drivers to m ultip le LAN c o nnec tions w ithin a c om mo n b a c k- pl ane.

5.1.7 ICR - Interrupt Control Register

Re a d / Write Po rt = 06 Th is re g ist e r e n a b le s a n d m a sk s in t e rru p t s. It is n o t us ed to s elect IR Q lines . T hat function is performed through the GCR R egis ter. BIT ICR RESET

7 MCTEST 0

5 IOPAV 0

4 IOPEN 0

3 SINT 0

2 MASK2 0

1 MASK1 0

0 EIL 0

Bit 7: MCTEST, Memory Cache Test Bit T he memor y cache counter s ar e accel er ated when MCT E S T =1. U s e this bit only for tes t purpos es . Bit 6: STAG, Staggered Address Enable When S T AG = 1, the l owes t bit in the buffer counter is for ced to 1 on memor y cache mis s es . Bit 5: IOPAV, I/O Pipe Address Visible When I OPAV = 1, it allows the I /O pi pe’s temporary addres s regis ter to be read out of the R E V R egis ter. Bit 4: IOPEN, I/O Pipe Enable When I OP E N = 1, the I /O pi pe i s enabl ed. R egul ar m e m o ry a c c e sse s sh o u ld b e d isa b le d w h e n t h is b it is set. Bit 3: SINT, Software Interrupt S et S INT = 1 to c reate an interrupt und er s oftware control. S et to zero to remove interrupt. F or more d eta ils, refer to p a g e 52. Bit 2: MASK2, Mask Interrupt Sources S et MAS K 2 to 1 to mas k out interrupt from the NIC. Bit 1: MASK1, Not used Bit 0: EIL, Enable Interrupts S et to 1 to enable interrupts from this device. T his enable controls S INT and interrupts from the L AN c o ntro lle r. Fo r m o re d e ta ils, re fe r to p a g e 52. ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.1.8 REV/IOPA - Revision/I/O Pipe Address

Re a d / Write Po rt = 07 T his regis ter s er ves two functions : 1. It provides the host with revision information about the chip (CHIP3-0 and REV3-0). 2. It provides a port for loading the I/O pipe address into the buffer counter. For more on this, see Section 6.2. T he revision info rm a tion is rea d -only a nd w ill b e returned on reads to this location when the I OPAV b it (ICR.5) is ze ro. T his informa tion is d e ta iled a s follows : BIT REV READ RESET

7 CHIP3 0

6 CHIP2 1

5 CHIP1 0

4 CHIP0 0

3 REV3 0

2 REV2 0

1 REV1 0

0 REV0 0

Bits 7-4: CHIP3-CHIP0, Chip Type Depending on the condition of Jumper 9, this field yield s either 0100 or 0010. A value of 0100 ind i- cates to the hos t that this is an 83C795 device; a val ue of 001 0 i ndi cates an 8 3 C790 devi ce. Bits 3-0: REV3-REV0, Revision Number T hes e bi ts ini ti ali z e to the r evi s ion number of this chi p. When the I /O pipe i s enabled – that is , when I OP E N is s et (I CR .4) – the I /O pi pe addres s is loaded into the buffer counter through this regis ter. S ince the buffer counter i s 1 6 -bi ts wi de, two cons ecuti ve writes are required to accomplis h this us ing this method.

• The first write, which contains the lower byte of the address, is stored in a temporary register.
• The second write, which contains the upper byte of the address, is then transferred, along with the contents of the temporary register, into the buffer counter. Any hos t acces s to the chip between the firs t and sec ond writes w ill a utom a tic a lly rese t the p roc e ss. When IOPAV is s et, the contents of the temporary register c a n be read from this loc ation. BIT IOPA RESET 7I O P A 7 0 6I O P A 6 0 5I O P A 5 1 4I O P A 4 0 3I O P A 3 0 2I O P A 2 0 1I O P A 1 1 0I O P A 0 0 Bits 7-0: IOPA7-IOPA0, I/O Pipe Address T his regis ter pr ovi des the locati on of the I /O P i pe addr es s .

5.1.9 LAN0 - LAN5 - LAN Address Registers

Re a d / Write Po rts = 08 - 0D SWH = 0 Th e se six LA N a d d re ss re g ist e rs ( a lo n g w it h t h e BD ID a n d C HKSUM re g ist e rs) re c a ll o r st o re gener al -pur pos e data fr om the E E R OM and, dur i ng norm a l use, rec a ll the p erm a nently-a ssig ne d LAN addr es s for the adapter. REG LN RESET INIT RECALL LAN0 LN07-LN00 0 EE EE LAN1 LN15-LN08 0 EE EE LAN2 LN23-LN16 0 EE EE LAN3 LN31-LN24 0 EE EE LAN4 LN39-LN32 0 EE EE LAN5 LNMSB, LN46-LN40 0E E E E Bits 0-7: LN07-LN00 I n normal us e, thes e are the leas t s ignifi cant bits of t h e g lo b a lly -a ssig n e d LA N a d d re ss b lo c k . Bits 8-15: LN08-LN15 In n o rm a l u se , LN8-LN15 a re p a rt o f t h e g lo b a lly as s i gned L AN addr es s bl ock. Bits 16-23: LN16-LN23 I n nor mal us e, L N16-L N23 are par t of the gl obally as s i gned L AN addr es s bl ock. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

Bits 24-31: LN24-LN31 I n normal us e, L N24-L N31 is par t of the unique L AN addr es s for each adapter (L N4 7 -L N24) and may be as s i gned at the ti me of manufactur e for the end pr oduct. Bits 32-39: LN32-LN39 I n normal us e, L N32-L N39 is par t of the unique L AN addr es s for each adapter (L N4 7 -L N24) and may be as s i gned at the ti me of manufactur e for the end pr oduct. Bits 40-46: LN40-LN46 LN40-LN46 forms part of the unique LAN address for each adapter (L N47- L N24) and may be as s i gned at the time of manufacture for the end pr oduct. Bit 47: LNMSB LN M SB is t h e m o st sig n if ic a n t d ig it o f t h e u n iq u e LA N address bloc k whic h c omprises LN24 through LN47.

5.1.10 BDID - Board ID Register

Re a d Po rt = O E SW H=0 T his reg ister is sim ila r to the LAN reg isters exc ep t that i t contai ns an 8- bi t code i denti fyi ng the boar d typ e fo r so ftw a re p urp o se s. The a d m inistra tio n o f thi s I D byte i s beyond the s cope of thi s s peci fi cati on. T hi s r egi s ter i s s tor ed and r ecal l ed al ong wi th the LA N re g ist e rs. BIT BDID RESET INIT RECALL

7 BDID7 0 EE EE

6 BDID6 0 EE EE

5 BDID5 0 EE EE

4 BDID4 0 EE EE

3 BDID3 0 EE EE

2 BDID2 0 EE EE

1 BDID1 0 EE EE

0 BDID0 0 EE EE

5.1.11 CKSM - Checksum Register

Re a d / Write Po rt = O F SWH=0 Be f o re st o rin g a LA N a d d re ss, C KSM sh o u ld b e pr ogr ammed with an 8-bit checks um which caus es t h e 2’ s c o m p le m e n t su m o f a ll e ig h t se c o n d -g ro u p r egis ter contents to be F F H . T he s um mus t include this r egis ter. T hi s regi s ter i s s tor ed and r ecall ed along wi th the L AN r egi s ter s . I t i s r ecommended that on r ecall of the L AN addr es s , the regi s ter ’s integr i ty s houl d be confi r med by computi ng (i n s oftwar e) the checks um of the s econd group of r egi s ter s . BIT CKSM RESET INIT RECALL

7 CHK7 1 EE EE

6 CHK6 1 EE EE

5 CHK5 1 EE EE

4 CHK4 1 EE EE

3 CHK3 1 EE EE

2 CHK2 1 EE EE

1 CHK1 1 EE EE

0 CHK0 1 EE EE

Bits 7-0: CHK7-CHK0, Checksum Register T he 83C795 s tor es the checks um amount i n thi s re g iste r fo r re fe re nc e a nd c o m p a riso n w ith the LAN re g iste rs’ a m o unts.

5.1.12 GCR2 - General Control Register 2

Re a d / Write Po rts = 08 SWH=1 T his re g iste r is use d to ho ld g e ne ra l c o ntro l informa tion. BIT GCR2 RESET INIT 7— 0 0 6— 0 0 5— 0 0 4— 0 0 3— 0 0 2— 0 0 1— 0 0

0 PNPIOP 0 0

Bit 0: PNPIOP, PNP and I/O Mapped Pipe T his bit is us ed to communicate to the P lug and P lay logic that the adapter us es the I/O-mapped mode. Whe n PNPIO P = 1, t he Plug a nd Pla y RA M C o n tro l r egi s ter s ar e di s abl ed and the R OM Contr ol r egi s - ters a re moved from 48h–4Ch to 40h–44h.

5.1.13 IAR - I/O Address Register

Re a d / Write Po rt = 0A SWH=1 Th is re g ist e r p ro g ra m s t h e b a se I/ O a d d re ss f o r t h e chi p. ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

7 IA15 0 0

6 IA14 0 0

5 IA13 0 0

0 PNPBOOT 0 0

Bits 7-5: IA15-IA13, I/O Address Lines T hes e bits are compared agai ns t the A15-A13 l ines fr om the hos t when I OR or I OW ar e active and AE N is n o t . To a c c e ss t h e c h ip , t h e lin e s m u st m a t c h . Bits 4-1: IA8-IA5, I/O Address Lines T hes e bi ts ar e compar ed agai ns t the A8- 5 l i nes fr om the hos t when I OR or I OW ar e active and AE N is n o t . To a c c e ss t h e c h ip , t h e lin e s m u st m a t c h . Bit 0: PNPBOOT, Plug and Play Boot Bit PNPBO O T = 1 t o in d ic a t e t o th e Plug a nd Pla y hardware that the adapter is a boot card. T his allows the 83C795 addres s decoders to be active wi thout wai ting for the P lug and P l ay har dwar e activate command.

5.1.14 RAR - RAM Address Register

Re a d / Write Po rt = O B SWH=1 T hi s r egi s ter contr ol s the bas e addr es s and wi ndow s ize for the buffer R AM. BIT RAR RESET INIT

7 HRAM 0 0

6 RA17 0 0

5 RAMSZ1 0 0

4 RAMSZ0 0 0

3 RA16 0 0

2 RA15 1 1

1 RA14 0 0

0 RA13 0 0

Bit 7: HRAM, High RAM Address T hi s bi t pr ovi des a means of l ocati ng the buffer memor y above the 1MB DOS l imit. When HR AM = 0 , the buffer addr es s decoder matches L A23- L A20 agains t z ero. When HR AM = 1, the L A23-L A20 l i nes ar e matched agai ns t the val ue F . T hi s fi el d i s not s upported by the P lug and P lay hardware. Bits 5-4: RAMSZ1-RAMSZ0, Buffer Window Size Field T hi s encoded fi el d deter mi nes the appar ent s i z e of the buffer R AM. I t i s decoded i n the fol l owi ng man- ner: SZ1 SZ0 Window Size 0 0 8K Bytes 0 1 16K Bytes 1 0 32K Bytes 1 1 64K Bytes TABLE 5-5. BUFFER WINDOW SIZE FIELD Bits 6, 3-0: RA17, RA16-RA13, RAM Base Address Field T hes e bi ts for m par t of the bas e addr es s for the buffer R AM decoder along with the fixed value of ’ 11’ for RA19-RA18. When S A19-S A13 ha s a va lue between this bas e addres s and the bas e plus the window s iz e, the reques t for memor y is r ecogni z ed. Once the S A19-S A13 value is no longer i n this r ange, the hos t ends the acces s . Note The 64K window size is not supported by Plug and Play.

5.1.15 BIO - ROM Control Register

Re a d / Write Po rt = 0C SWH = 1 Th is re g ist e r p ro g ra m s t h e b a se a d d re ss a n d window s ize for the external R OM. BIT BIO RESET INIT RECALL

7 FINE16 0 0 EE

6 BA17 0 0 EE

5 BIOSZ1 1 1 EE

4 BIOSZ0 1 1 EE

3 BA16 0 0 EE

2 BA15 0 0 EE

1 BA14 0 0 EE

0 BA13 0 0 EE

83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

Bit 7: FINE16, Fine Decode W h e n FIN E16 = 1 , M EM 1 6C S’ s re sp o n se is g e n - er ated onl y when the actual R AM wi ndow i s bei ng addr es s ed. I t includes S A16-S A13 in the addr es s decodi ng pr oces s . S ee page 5 1 for mor e detai l s . Bits 5-4: BIOSZ1-BIOSZ0, ROM Window Size Field T hes e two bits determine the R OM window s ize and ar e decoded i n thi s manner : SZ1 SZ0 ROM Window Size 00 8 K 0 1 16K 1 0 32K 1 1 Disabled TABLE 5-6. ROM WINDOW SIZE FIELD Bits 6, 3-0: BA17, BA16-BA13, Base Address Field T hes e bi ts for m par t of the bas e addr es s for the R OM decoder al ong wi th the fi x ed val ue of ’11’ for BA19-BA18. When S A19-S A13 ha s a va lue b e- tween thi s bas e addr es s and the bas e pl us the window s iz e and S ME MR ar e acti ve, a r eques t for the R OM i s r ecogniz ed. A chi p s el ect wi l l be gener - ated to the R OM if not dis abled. Memory acces s at the s ame addr es s i s bl ock ed i f R OM i s enabl ed.

5.1.16 GCR - General Control Register

Re a d / Write Po rt = O D SWH = 1 T his re g iste r c o ntro ls inte rrup t le ve l se le c tio n, ze ro w a it st a t e re sp o n se , a n d se v e ra l o t h e r f u n c t io n s. BIT GCR RESET INIT RECALL

7 XLENGTH 0 0 EE

6 IR2 0 0 EE

5 ZWSEN 0 0 EE

3 IR1 0 0 EE

2 IR0 0 0 EE

Bit 7: XLENGTH, Extended Length Bit Enable When X L E NGT H = 1, the extended length option is enabled as s pecified by the 802.3 s pecifi cati on (refer to page 69). Bit 5: ZWSEN, Zero Wait State Enable T his bit is s et to 1 to enable the chip to generate a Z WS r es pons e when the R AM is acces s ed and avai l abl e to the hos t. Bit 4: RIPL, Software Flag Bits 6, 3-2: IR2-IR0, Interrupt Request Field T hes e bits form an encoded field to s elect through which IR Q pin the interrupt output is channeled. Be c a use o f Plug a nd Pla y lo g ic , it is ne c e ssa ry to connect the interrupt pins to s pecific lines on the I S A bus , as s hown bel ow. T he i nter r upt r eques t pi ns and their corr es pondi ng I S A lines are decoded in this fas hion: IRQ2 IRQ1 IRQ0 IRQ Pin Selected ISA Bus Line 0 0 0 None None 0 0 1 IRQ1 IRQ2/9 0 1 0 IRQ2 IRQ3 0 1 1 IRQ3 IRQ5 1 0 0 IRQ4 IRQ7 1 0 1 IRQ5 IRQ10 1 1 0 IRQ6 IRQ11 1 1 1 IRQ7 IRQ15 TABLE 5-7. INTERRUPT REQUEST FIELD Bit 1: GPOUT, General Purpose Output T his bit c ontrols the GPOUT pin of the c hip. When GP OU T = 1, i t caus es the GP OU T pi n to dr i ve l ow. In so m e sy st e m s, t h is b it is w ire d t o a sh u t d o w n contr ol i nput for DC/DC i s ol ated power s uppl y us ed in 10Ba se 2 a p p lic a tio ns. Fo r m o re info rm a tio n o n this feature, refer to S ection 6.7. Bit 0: LIT, Link Integrity Test T his b it c o ntrols the Link Inte g rity Test. In S TAR- LAN-10 netwo rks, the Link Integrity Test should b e di s abl ed. LIT = 0 - Link Test is Disabled LIT = 1 - Link Test is Enabled. ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

Dis abling the L ink Integrity Tes t (L IT ) forces the 83C795 to s elect the twis ted-pair interface. When LIT is e na b le d , the tw iste d -p a ir inte rfa c e w ill b e automatically s elected when link activity is found and the AU I i nter face wi ll be s elected when the twis ted-pair link enters the 10BAS E -T link fail s tate.

5.1.17 ERFAL - Early Receive Fail Address

Re a d / Write Po rt = O E SWH = 1 T his regis ter contai ns the lower eight bits for the addr es s at which the ear ly-r eceive logi c detected an under r un. T hi s r egi s ter al s o contai ns a contr ol b it fo r th e Plu g a nd Pla y lo g ic . BIT ERFAL RESET RECALL

7 ERFA7 — —

6 ERFA6 — —

5 ERFA5 — —

4 ERFA4 — —

3 ERFA3 — —

2 ERFA2 — —

1— 0 0

0 PNPEN 1 EE

Bits 7-2: ERFA7-2, Early Receive Failure Address T his regis ter contains the lower eight bits of the addr es s where the earl y recei ve logic detected an underrun. T he comparis on has a granularity of 4 bytes s o the leas t s ignificant two bits are z ero. T his va lue is rea d -only. Bit 0: PNPEN, Plug and Play Enable Whe n PNPEN = 1 a lo n g w it h t he in st a lla tio n o f JUM PER6, Plug a nd Pla y lo g ic is e na b le d . Th is b it is r eadable but can only be s et by the initial E E R OM loa d .

5.1.18 ERFAH - Early Receive Fail Address

Re a d / Write Po rt = O F SWH = 1 T his regis ter contains the higher eight bits for the addr es s at whi ch the earl y receive logic detected an underrun. BIT ERFAH RESET RECALL

7 ERFA15 — —

6 ERFA14 — —

5 ERFA13 — —

4 ERFA12 — —

3 ERFA11 — —

2 ERFA10 — —

1 ERFA09 — —

0 ERFA08 — —

Bits 7-0: ERFA15-8, Early Receive Failure Address T his r egi s ter contains the higher eight bits of the addr es s where the earl y recei ve logic detected an underrun. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

5.2 LAN CONTROLLER REGISTER

T o s i mpl i fy the pr ogr ammi ng model for the L AN controller and retain compatibility with the S MC 83C 690 LAN C o ntro lle r, the inte rna l re g iste rs a re di vi ded i nto two addr es s maps . T he defaul t addr es s map is us ed for R ing-s tyle buffering (like the 83C690). T hose reg isters nee d ed for linke d -list bufferi ng ar e grouped together i n the alter nate addr es s map and ar e enabl ed thr ough the E nhancement (E NH) r egis ter des cr ibed s tarti ng on p a g e 26. E ach map pr ovi des acces s to al l r egi s ter s ne c e ssa ry fo r o p e ra ting tha t p a rtic ula r b uffe ring mode. Many r egi s ter s ar e vi s i bl e i n both maps , al though not al ways at the s ame addr es s i n each. To facilitate manufacturing tes t of the device, many inter nal regis ters can be acces s ed in one or both of thes e maps . Within each map, the regis ters are or gani z ed i nto 4 pages of 16 r egi s ter s each. Onl y o ne p a g e is visib le a t a tim e . Pa g e se le c tio n is m a d e through the Command (CMD) regis ter des cribed st a rt in g o n p a g e 2 4. T he addr es s es l i s ted i n thi s s peci fi cati on ar e i n an abbr evi ated for m. T he fir s t hex di gi t is r eal ly a two-bit ’page’ value which is written into the L AN C O M M A N D ( C M D ) re g ist e r t o a c c e ss t h e 1 6 re g ist e rs v isib le f o r t h a t p a g e . Th e d ig it s a f t e r t h e colon are the offs et within the 83C795’s L AN Controller I /O s egment i n this manner : page:offset T o deter mine the corr ect addres s , you mus t fi rs t kn o w t h e 8 3C 795 ’ s b a se a d d re ss t h e n se le c t t h e cor r ect page and fi nal l y s el ect the cor r ect offs et. S o, f o r e xa m p le , "3: 1C " in d ic a t e s t h a t t h e a d d re ss f o r t h is p a rt ic u l a r re g ist e r is f o u n d o n p a g e 3 a t t h e offs et value 1C. In the following des criptions , the mos t s ignificant bit pos i ti on i s number ed ’7’. T he l i ne l abel l ed R E S E T s hows the ini tial values loaded into the r egis ter by as s er tion of the R E S E T pin. T he s ymbol ’0’ denotes void bits whic h always return zero when read .

5.2.1 ALICNT - Alignment Error Counter

Norma l Ma p Rea d Port = 0:1D Link-List Ma p Rea d Po rt = 0:1D T his r egi s ter is the alignment er ror counter. I t is incremented by the receive unit when a packet is r eceived with a fr ame al ignment er ror. Onl y packets whos e addres s es are r ecogni z ed will be included in this ta lly. T he c ounter w ill inc re me nt to 255 a nd s top if addi tional al ignment er rors are detected. T he counter i s cl ear ed when r ead. BIT ALICNT RESET

7 CT7 0

6 CT6 0

5 CT5 0

4 CT4 0

3 CT3 0

2 CT2 0

1 CT1 0

0 CT0 0

5.2.2 BOUND - Receive Boundary Page

Nor mal Map R ead/Wr i te P or t = 0 :1 3 Th e Re c e iv e Bo u n d a ry Pa g e Re g ist e r p o in t s t o t h e oldes t us ed recei ve buffer in the ring. I t is us ed to pr event over fl ow i n the buffer r i ng. T he DMA compar es the contents of thi s r egi s ter to the nex t buffer addr es s when l i nking buffer s together for s torage of a r eceived frame. I f the contents match the next buffer addr es s , the DMA oper ati on is a b orte d . O nly A08-A15 a re sp e c ifie d sinc e a ll buffer s are aligned on 256-byte boundaries . F or more information, refer to page 85. BIT BOUND RESET

7 A15 X

6 A14 X

5 A13 X

4 A12 X

2 A10 X

1 A09 X

0 A08 X

ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.2.3 CMD - Command Register

Nor mal Map R ead/Wr i te P or t = X : 1 0 L i nk ed- L i s t Map R ead/Wr i te P or t = X :10 BIT CMD RESET

7 PS1 0

6 PS0 0

5 RFU 0

4 ENETCH 0

3 DISETCH 0

2 TXP 0

0 STP 1

T he Command regis ter is us ed to i ni tializ e the 83C795 c hip, start transmissions, a nd switc h pages . Bits 7-6: PS1-PS0, Page Select T hi s 2 -bi t fi el d des i gnates whi ch of 4 pages i s s howi ng. T hey decode as fol l ows : PS1 PS0 Page Select 00P a g e 1 10P a g e 2 01P a g e 3 11P a g e 4 TABLE 5-8. PAGE SELECT FIELD Bit 5: RFU, Reserved for Future Use T his bit is not us ed by 83C795 and always returns ze ro w h e n re a d . Bit 4: ENETCH, Enable Early Transmit Checking B y s etting this bit to 1, it enables comparis on of t ra n sm it D M A a d d re ss a g a in st t h e h o st m e m o ry wr ite addr es s . Once s et, thi s bit can be cleared and the 83C795 continues to check trans mis s ion ad- d re sse s u n t il D ISETC H is se t . Se e p a g e 78 f o r m o re d eta ils. Bit 3: DISETCH, Disable Early Transmit Checking B y s etting this bit to 1, it dis ables the early trans mit addr es s checking. Once s et, the bi t can be cl ear ed a n d t ra n sm it a d d re ss c h e c kin g is su p p re sse d u n t il EN ETC H is se t . Se e p a g e 7 8 f o r m o re d e t a ils. Bit 2: TXP, Transmit packet S et thi s bi t after l oadi ng the T r ans mi t B uffer and Control regis ters to initiate trans mis s ion of a packet. T he 83C795 clears this bit upon completion or abor ti on of the tr ans mi s s i on. Bit 1: STA, Start Bit S et the S T A bit to activate the 83C795 after power up or when the 83C795 ha s b een reset b y a soft- ware command. No frames can be s ent or received u n t il t h is b it h a s b e e n se t . Th e u se r’ s so f t w a re sh o u ld se t u p t h e o t h e r re g ist e rs p rio r t o b rin g in g the device on line, but s etting this bit is the actual command whi ch br i ngs the T r ans mi t and R ecei ve por ti ons of the devi ce onl i ne. Once s et, thi s bi t may be cl ear ed and the 8 3 C79 5 wi l l conti nue to r emai n online. Bit 0: STP, Stop Bit S et the S T P bit to take the chip offline and dis en- gage fr om the L AN. F r ames partially trans mitted or re c e ive d a re c o m p le te d b e fo re re se t o c c urs. INT - STA T.RST is se t hig h w h e n t he Tra nsm it a n d Re - c eive se c tio n ha ve c om p leted a ll o utsta nd ing oper ations (s ee page 28). No frames will be r e- ceived or trans mitted until the s tart bit has been s et.

5.2.4 COLCNT - Collision Count Register

Nor mal Map R ead P or t = 0 :1 5 L i nk ed- L i s t Map R ead P or t = 0 :15 T hi s r egis ter contains the number of col lis ions detected while attempting to trans mit the current (or mos t recent) packet. It is cleared to z ero at the s tart of tra nsm ission. If no c ollisions a re d etec ted , the c ounter w ill rea d zero . Fo r e a c h c o llisio n encountered, the count is incremented. If more than 1 5 col l i s i ons occur, the abor t bi t of T S T AT i s s et and the count is res et to z ero (s ee page 38). BIT COLCNT RESET

7 T10 0

Bits 7-4: T10-T7, Backoff Counter T hes e 4 cons ecutive bi ts always r eturn z ero. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

Bits 3-0: CT3-CT0, Collision Counter T he se b its ind ic a te the va lue of the c ollisio n counter. T hey ar e al ways r eadabl e.

5.2.5 CRCCNT - CRC Error Counter

Nor mal Map R ead P or t = 0 :1 E L i nk ed- L i s t Map R ead P or t = 0 :1E T his r egis ter is incr emented by the r eceive unit when a packet is r eceived wi th a CR C er ror. Only p a c kets w hose a d d re ss is rec og nized w ill b e included in this tally. When a ’runt’ frame is received with a CR C err or, CR CCNT is incremented if R CON.R U NT S is enabled (s ee page 32). T he c ounter w ill inc re me nt to 255 a nd stic k if a d d itio na l CR C err ors are detected. T he counter is cl ear ed when r ead. BIT CRCCNT RESET

5.2.6 CURR - Current Frame Buffer Pointer

Nor mal Map R ead/Wr i te P or t = 1 :1 7 T his regis ter points to the firs t buffer us ed for s torage of the pres ent fr ame. I t is us ed by DMA as a backup addr es s for r ecover i ng buffer s i n cas e of a fla w e d p a c ke t a nd fa c ilita te s stora g e of b uffer header i nfor mati on. T he CU R R r egi s ter s houl d be initializ ed to the s ame val ue as R S T AR T (s ee page 33) and not alter ed thereafter by the us er unles s the c o ntro lle r is re se t. O nly A08-A15 a re sp e c ifie d s i nce al l buffer s ar e al i gned on 256- byte boundar i es . BIT CURR RESET

5.2.7 CURRH - Current Frame Buffer

Descriptor Pointer Register High L i nk ed- L i s t Map R ead/Wr i te P or t = 1 :17 T his regis ter is one of a pair of r egi s ter s (CU R R H and CU R R L ) that point to the firs t buffer des criptor us ed for s torage of the pres ent frame. T hey are us ed by DMA as a backup addr es s for r ecover i ng buffers in the cas e of a fl awed packet and to fa c ilita te stora g e o f b uffer hea d e r info rm a tion. N e it h e r t h e C URRH n o r C URRL re g ist e rs sh o u ld be alter ed by the us er. T hey are acces s ible for tes t purpos es only. BIT CURRH RESET

5.2.8 CURRL - Current Frame Buffer

Descriptor Pointer Register Low L i nk ed- L i s t Map R ead/Wr i te P or t = 0 :13 T his regis ter is one of a pair of r egi s ter s (CU R R H and CU R R L ) that point to the firs t buffer des criptor us ed for s torage of the pres ent frame. T hey are us ed by DMA as a backup addr es s for r ecover i ng buffers in the cas e of a fl awed packet and to fa c ilita te stora g e o f b uffer hea d e r info rm a tion. N e it h e r t h e C URRH n o r C URRL re g ist e rs sh o u ld be alter ed by the us er. T hey are acces s ible for tes t purpos es only. ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

7 A07 X

6 A06 X

5 A05 X

4 A04 X

3 A03 X

2 A02 X

1 A01 X

0 A00 X

5.2.9 DCON - Data Configuration Register

L inked-Lis t Map R ead P ort = 2:1E L inked-L is t Map Write Port = 0:1E T his regis ter always returns 41h. In the 83C790 this regis ter controlled DMA burs t lengths ; however, the 83C795 is ha rd w ired for 8-b yte b ursts. Refer to p a g e 65 fo r m o re info rm a tio n.

5.2.10 ENH - Enhancement Register

Nor mal Map R ead/Wr i te P or t = 2 :1 7 L i nk ed- L i s t Map R ead/Wr i te P or t = 2 :17 T his regis ter enables enhancement features . BIT ENH RESET 7— 0 6— 1

5 ALTEGO 0

4 SLOT1 0

3 SLOT0 0

2 EOTINT 0

1— 0

0 SBACK 0

Bits 7-6: Unused Bit 5: ALTEGO, Buffering Format Selection ALTEGO = 0 - Des i gnates r i ng buffer i ng and s i ngl e fr ame tr ans - m issio n fo rm a t. T his is e sse ntia lly 8390/ 83C 690 c om p a tib ility m od e. ALTEGO = 1 - Des ignates l inked-l is t r eceive buffering and multi - pl e fr ame tr ans mi s s i on for mat. T he r egi s ter ad- dr es s map i s s el ected wi th thi s bi t, ex pos i ng the r egis ter s as s ociated with the s elected bufferi ng mode. Bits 4-3: SLOT1-0, Slot Time Selection T his two-bit field s elects the s lot time according to Ta b le 5-10. SLOT1 SLOT0 Slot Time

0 X 512 bit times (Ethernet)

TABLE 5-9. SLOT TIME SELECTION FIELD Bit 2: EOTINT, Interrupt on End-of-Transmit EOTINT = 1 - Interrupt on E nd-of-T rans mit chain ins tead of each trans mitted frame. T his bit is ignored if not operating in m u lt ip le f ra m e t ra n sm issio n m o d e . EOTINT = 0 - Interrupt on each trans mitted frame. Bit 0: SBACK, Enable Stop Backup Modifications SBACK = 1 - E nable the S top B ackoff modifications to the back- off timer. SBACK = 0 - Normal backoff.

5.2.11 ERWCNT - Early Receive Warning

Nor mal Map R ead/Wr i te P or t = 0 :1 8 L i nk ed- L i s t Map R ead/Wr i te P or t = 0 :18 T hi s r egi s ter contai ns the R ecei ved B y te Count thre sho ld a t w hic h the Ea rly Re c e ive Wa rning inte rrup t is g e ne ra te d . T he ERW inte rrup t is gener ated when R B C ≥ ERW. Bits 3-0 of RBC a re ig nored . For m ore inform a tio n on this reg iste r, refer to page 71. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

7 ERW11 0

6 ERW10 0

5 ERW9 0

4 ERW8 0

3 ERW7 0

2 ERW6 0

1 ERW5 0

0 ERW4 0

5.2.12 GROUP0-GROUP7 - Multicast Filter

GROUP0 1:18 1:18 1:18 1:18 GROUP1 1:19 1:19 1:19 1:19 GROUP2 1:1A 1:1A 1:1A 1:1A GROUP3 1:1B 1:1B 1:1B 1:1B GROUP4 1:1C 1:1C 1:1C 1:1C GROUP5 1:1D 1:1D 1:1D 1:1D GROUP6 1:1E 1:1E 1:1E 1:1E GROUP7 1:1F 1:1F 1:1F 1:1F T hes e 8 r egi s ter s hol d the node’s Mul ti cas t fi l ter t a b le . See Ta b le 5-10 for the re g iste rs’ b it as s i gnments .

5.2.13 INTMASK - Interrupt Mask Register

Nor mal Map R ead P or t = 2 :1 F Nor mal Map Wr i te Po rt = 0:1F L i n k e d - L i s t M a p R e a d P o r t = 2 : 1 F L i n k e d - L i s t Write Port = 0:1F T he Interrupt Mas k R egis ter is us ed to mas k out c e rt a in in t e rru p t so u rc e s se le c t iv e ly . M a sk b it s se t to ’1’ allow the corres ponding interrupts to caus e an IR Q. Mas k bits s et to ’0’ block their res pective interrupt s ources . BIT INTMASK RESET 7— 0

6 ERWE 0

5 CNTE 0

3 TXEE 0

2 RXEE 0

1 PTXE 0

0 PRXE 0

Bit 6: ERWE, Early Receive Warning Enable When E R WE = 1, this bit enables E arly R eceive War ni ng as defi ned by the E R W bi t i n the I nter r upt S tatus R egis ter. (S ee the next regis ter, INT S T AT .) Bit 5: CNTE, Counter Overflow Enable When CNT E = 1, this bit enables Counter Overflow as defined by the CNT bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT .) Bit 4: OVWE, Overwrite Warning Enable When OVWE = 1, this bit enables Overwrite Warn- ing as defined by the OVW bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT .) GROUP Registers BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GROUP0 GA07 GA06 GA05 GA04 GA03 GA02 GA01 GA00 GROUP1 GA15 GA14 GA13 GA12 GA11 GA10 GA09 GA08 GROUP2 GA23 GA22 GA21 GA20 GA19 GA18 GA17 GA16 GROUP3 GA31 GA30 GA29 GA28 GA27 GA26 GA25 GA24 GROUP4 GA39 GA38 GA37 GA36 GA35 GA34 GA33 GA32 GROUP5 GA47 GA46 GA45 GA44 GA43 GA42 GA41 GA40 GROUP6 GA55 GA54 GA53 GA52 GA51 GA50 GA49 GA48 GROUP7 GA63 GA62 GA61 GA60 GA59 GA58 GA57 GA56 TABLE 5-10. GROUP REGISTER BITS ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

Bit 3: TXEE, Transmit Error Enable W h e n TXEE = 1 , t h is b it e n a b le s Tra n sm it Erro r a s defi ned by the T X E bi t i n the I nter r upt S tatus R eg- is ter. (S ee the next r egis ter, I NT S T AT .) Bit 2: RXEE, Receive Error Enable W h e n RXEE = 1, t h is b it e n a b le s Re c e iv e Erro r a s defined by the R XE bit in the Interrupt S tatus R eg- is ter. (S ee the next r egis ter, I NT S T AT .) Bit 1: PTXE, Packet Transmitted Enable When T XE E = 1, this bit enables Pac ket T ra nsmit- ted as defined by the P T X bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT .) Bit 0: PRXE, Packet Received Enable When P R X E = 1, thi s bit enables P acket R eceived as defined by the P R XE bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT .)

5.2.14 INTSTAT - Interrupt Status Register

Nor mal Map R ead/Wr i te P or t = 0 :1 7 L i nk ed- L i s t Map R ead/Wr i te P or t = 0 :17 T he I nter rupt S tatus R egis ter enables the hos t to determine the caus e of an interrupt and to evaluate p end ing or m a ske d interrup ts. Ma ske d -o ut interrupts are vis ible in this regis ter although they will not generate an IR Q to the hos t. Pending inte rrup ts c a n b e c lea re d b y w riting ’ 1’ to the as s ociated bit of this regis ter. T he I R Q s ignal is acti ve as l ong as any unmas ked i nter r upt bi t re m a in s se t . Fo r m o re d e t a ils, se e p a g e 80. BIT INTSTAT RESET

7 RST 1

6 ERW 0

5 CNT 0

3 TXE 0

2 RXE 0

1 PTX 0

0 PRX 0

Bit 7: RST, Reset Status T his b it is set b y 83C795 w hen its Tra nsm it a nd Re c e iv e se c t io n s a re st o p p e d in re sp o n se t o t h e as s er ti on of the R E S E T pi n or the s etti ng of the CMD. S T P bi t. T he R S T bi t does not gener ate an interrupt. Bit 6: ERW, Early Receive Warning When this bit is s et it indicates that the number of bytes r eceived in the cur rent fr ame has exceeded the programmable l imit of the E R WCNT r egi s ter. Bit 5: CNT, Counter Overflow When this bit is s et it indicates that the MS B of one or more network err or counter s has been s et. Bit 4: OVW, Overwrite Warning T hi s bi t i s s et when the r ecei ve DMA mus t abor t fr ame reception due to a l ack of r eceive buffer s . Bit 3: TXE, Transmit Error T his b it is set w hen exc essive c ollisions, out-of-w in- d o w c o llisio n s, FIFO u n d e rru n , o r e a rly t ra n sm it addr es s vi ol ati ons pr event trans mis s i on of a pack et. Bit 2: RXE, Receive Error T his bit is s et when a packet is received with one or mor e of the following err ors :

• CRC error (happens when SEP is enabled)
• Frame alignment error (happens when SEP is enabled)
• FIFO overrun
• Missed packet (monitor mode) T hi s i nter r upt wi l l not be pos ted i f a DMA Abor t occurs , a condition indicated by the as s ertion of an OVW inte rrup t. If RXE is p reviously set, it w ill not be changed due to OVW. Bit 1: PTX, Packet Transmitted Th is b it is se t w h e n a p a c ke t is t ra n sm it t e d su c c e ss- fully. When the bit E NH.E OT I NT is s et i n Multiple P acket T rans mit mode (s ee page 5-26), s etting of this interrupt is deferred until the entire trans mit chai n has been proces s ed. P T X is then s et if any packet in the chain was trans mitted s ucces s fully, or if a ze ro le n g t h t ra n sm it c h a in w a s p ro c e sse d . Bit 0: PRX, Packet Received When P R X = 1 , i t i ndi cates that a pack et was re c e ive d w ith no e rro rs. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

5.2.15 MANCH - Manchester Management

Nor mal Map R ead/Wr i te P or t = 3 :1 F L i nk ed- L i s t Map R ead/Wr i te P or t = 3 :1F T his r egi s ter al l ows the r eadi ng back of the 10B as eT s tatus L E D dr i ver s to s uppor t networ k and s tati on management functi ons . I t al s o enabl es and controls the 83C795’s internal Manches ter encoder /decoder. BIT MANCH RESET

7 MANDIS 0

6 SEL 1

4 ENAPOL 1

3 PLED 0

2 LLED 0

1 RLED 0

0 TLED 0

Bit 7: MANDIS, Manchester Disable MANDIS = 1 - dis ables the internal Manches ter E ncoder /Decoder . When di s abl ed, the L AN Con- troller us es the decoder s erial interface cons is ting o f the se line s: XTXD, XTXE, XTXC , XRXD, XRXC , X CR S , X COL , X L OOP. MANDI S = 0 - E nables the Manches ter E ncoder /Decoder . Bit 6: SEL, Select AUI Mode For Idle State S E L = 0 - T X+ is pos itive in relation to T X-. S E L = 1 - T X+ = T X-. Bit 4: ENAPOL, Automatic Polarity Correct E NAP OL = 1 - E nable Auto P olarity Correct E NAP OL = 0 - Dis able Auto P olarity Correct Bit 3: PLED, TPRX Polarity LED Readback When PLE D = 1, this LE D is on. Note There is no PLED pin onto which this signal might be driven. Bit 2: LLED, Link Status LED Readback W h e n LLED = 1 , t h i s LED i s o n ( o u t p u t si n k i n g cur r ent). Bit 1: RLED, Receive LED Readback W h e n RLED = 1 , t h is LED is o n ( o u t p u t si n k in g cur r ent). Bit 0: TLED, Transmit LED Readback W h e n TLED = 1 , t h i s LED i s o n ( o u t p u t si n k i n g cur r ent).

5.2.16 MPCNT - Missed Packet Error Counter

N o rm a l M a p Re a d Po rt = 0 : 1 F Li n k e d -List M a p Re a d Po rt = 0:1F T his r egis ter is incr emented by the r eceive unit whenever it cannot r eceive a packet due to a lack of r eceive buffer s , r eceive F I F O over flow, or becaus e the r ecei ver i s in moni tor mode. Only p a c kets w hose a d d re ss is rec og nized w ill b e inc lud ed in this ta lly. T he c ounter w ill inc rement to 255 and s ti ck i f addi ti onal pack ets ar e mi s s ed. T he counter i s cl ear ed when r ead. BIT MPCNT RESET ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.2.17 NEXT - DMA Controller Next Buffer

Nor mal Map R ead/Wr i te P or t = 2 :1 5 T hi s i s a wor k i ng r egi s ter of the DMA contr ol l er. I t holds a pointer to the next buffer to be opened. BIT NEXT RESET

5.2.18 RADDH - Receive Burst Starting

Nor mal Map R ead/Wr i te P or t = 2 :1 9 T his i s the hi gher 8 bi ts of a r egi s ter pair us ed internally by the DMA controller as a s cratch pad for the bur s t addres s of the r eceive pr oces s . Wri ting to the R ADDH and R ADDL regis ters while communi cati on i s taking pl ace may caus e er r or s in the DMA pr oces s . BIT RADDH RESET

5.2.19 RADDL - Receive Burst Starting

Nor mal Map R ead/Wr i te P or t = 2 :1 8 Th i s i s t h e l o w e r 8 b i t s o f a r e g i s t e r p a i r u se d internally by the DMA controller as a s cratch pad for the bur s t addres s of the r eceive pr oces s . Wri ting to the R ADDH and R ADDL regis ters while communi cati on i s taking pl ace may caus e er r or s in the DMA pr oces s . BIT RADDL RESET

5.2.20 RBEGIN - Receive Buffer Starting

L inked-Lis t Map R ead Port = 2:11 L inked-L is t Map Write Port = 0:11 T his regis ter holds the upper 8 bits of the s tarting addr es s of the recei ve buffer des cri ptor table. T he l ower 8 bi ts ar e as s umed to be z er o. BIT RBEGIN RESET

7 RB15 X

6 RB14 X

5 RB13 X

4 RB12 X

3 RB11 X

2 RB10 X

1 RB09 X

0 RB08 X

83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

5.2.21 RCNTH - Receive Byte Count High

Nor mal Map R ead P or t = 0 :1 B T his regis ter contains the upper 8 bits of the receive uni t’s count of bytes r ecei ved i n the mos t r ecent fr ame. I t i s cl ear ed by the r ecei ve uni t at the s tar t of re c e p tio n. BIT RCNTH RESET

7 CT15 0

6 CT14 0

5 CT13 0

4 CT12 0

3 CT11 0

2 CT10 0

1 CT09 0

0 CT08 0

5.2.22 RCNTL - Receive Byte Count Low

Nor mal Map R ead P or t = 0 :1 A T his regis ter contains the lower 8 bits of the receive uni t’s count of bytes r ecei ved i n the mos t r ecent fr ame. I t i s cl ear ed by the r ecei ve uni t at the s tar t of re c e p tio n. BIT RCNTL RESET

7 CT07 0

6 CT06 0

5 CT05 0

4 CT04 0

3 CT03 0

2 CT02 0

1 CT01 0

0 CT00 0

5.2.23 RCON - Receive Configuration

Normal Map R ead Port = 2:1C Normal Map Write Po rt = 0:1C L i nk ed- L i s t Map R ead P or t = 2 :1 C L i nk ed- L i s t Map Write Port = 0:1C T he R ecei ve Confi gur ati on R egi s ter defi nes optional behavior of the recei ve unit. I t controls addr es s r ecogni ti on and the acceptance of abnor mal packets . T hes e bi ts can be s et independently, although the monitor mode takes precedence over the other bits . BIT RCON RESET 70 0

6 RCA 0

4 PROM 0

3 GROUP 0

2 BROAD 0

1 RUNTS 0

0 SEP 0

Bit 7: Unused T his b it is unused in 83C795. When rea d , it a lw a ys re turns ze ro . Bit 6: RCA, Receive Abort Frame on Collision S etting this bit allows the receiver unit to abort r ecepti on of any fr ame i n whi ch the COL pi n i s acti ve after the s tar t of fr ame del i mi ter. R ecepti on of any fr ame whos e prefi x contai ns cons ecuti ve ’0’ b its is a lso a b orted . Neither c a use results in RXE bei ng s et. I t i s not over r i dden by the S E P bi t. T hi s bit was unus ed in the 83C690. Bit 5: MON , Check Addresses/CRC Without Buffering MON = 1 - T his bit enables the receive unit to check addr es s es and CR C on i ncoming packets without bufferi ng them to memor y. T he Mis s ed P acket Counter (MP CNT ) will be incremented for each rec ognized pac ket. MON = 0 - T his is normal operation. Bit 4: PROM, Promiscuous Reception When P R OM = 1, this bit enables promis cuous r ecepti on of al l fr ames havi ng i ndi vi dual addr es s es . ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

Bit 3: GROUP, Receive Multicast Frames When GR OU P = 1, thi s bi t enabl es r ecepti on of al l frames that:

• have multicast addresses
• pass the multicast address hashing filter Bit 2: BROAD, Receive Broadcast Frames When B R OAD = 1, this bit enables r eception of all fr ames havi ng a B r oadcas t (al l ’1’s ) des ti nati on addr es s . Bit 1: RUNTS, Receive Runts Frames When R U NT S = 1, this bit allows reception of fr ames havi ng l es s than 6 4 bytes , pr ovi ded that they other wis e meet the requirements of the 802.3 protocol. Bit 0: SEP, Save Errored Packets When S E P = 1, it di rects the receive unit to s ave packets having CR C or fr ame al ignment er rors in the buffers .

5.2.24 RDOWNH - Buffer Room Remaining

L i nk ed- L i s t Map R ead/Wr i te P or t = 2 :19 T his reg ister c onta ins the up p er 8 b its of a reg ister pair us ed by the DMA contr ol l er as a s cr atch pad fo r the b uffe r ro o m re m a ining c o unt d uring the r ecepti on pr oces s . Note Writing to these registers while commu- nication is taking place may cause er- rors in the DMA process. BIT RDOWNH RESET

5.2.25 RDOWNL - Buffer Room Remaining

L i nk ed- L i s t Map R ead/Wr i te P or t = 2 :18 T hi s r egi s ter contai ns the l ower 8 bi ts of a r egi s ter pair us ed by the DMA contr ol l er as a s cr atch pad fo r the b uffe r ro o m re m a ining c o unt d uring the r ecepti on pr oces s . Note Writing to these registers while commu- nication is taking place may cause er- rors in the DMA process. BIT RDOWNL RESET

5.2.26 REND - Receive Buffer End Register

L inked-Lis t Map R ead Port = 2:12 L inked-L is t Map Write Port = 0:12 T his r egis ter holds the upper 8 bits of the fi rs t addr es s beyond the end of the r ecei ve buffer des cr i ptor tabl e. T he l ower 8 bi ts ar e as s umed to be z er o. T he tabl e l i es between the number s (R BE GIN * 256) and (R E ND * 256 - 1). R efer to p a g e 88 for more d eta ils. BIT REND RESET

7 RE15 X

6 RE14 X

5 RE13 X

4 RE12 X

3 RE11 X

2 RE10 X

1 RE9 X

0 RE8 X

83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

5.2.27 RSTART - Receive Start Page Register

Norma l Ma p Rea d Port = 2:11 Norm a l Ma p Write Po rt = 0:1 1 R eceive S tart P age regis ter points to the s tart of the r eceive buffer r ing. Only A08-A15 ar e s pecifi ed s i nce al l buffer s ar e al i gned on 256- byte b ound a ries. Refer to p a g e 88 for m ore info rm a tion. BIT RSTART RESET

5.2.28 RSTAT - Receive Packet Status

Norma l Ma p Rea d Port = 0:1C Linked -List Ma p Re a d Po rt = 0:1C T his r egis ter r eports the s tatus of the mos t-r ecently re c e ive d p a c ke t. It c a te g o rize s a ny e rro rs tha t w e re detected and repor ts on the type of addr es s r ecogniz ed. All bi ts are clear ed at the s tart of r ecepti on ex cept for DI S . BIT RSTAT RESET

7 DRF 0

5 GROUP 0

3 OVER 0

1 CRC 0

Bit 7: DFR, Deferring IGSM T his bit i s s et when the I nter frame Gap S tate Ma- c h i n e ( I G SM ) i s d e f e rr i n g . If t h e t r a n sc e i v e r h a s a sse rt e d th e C D lin e a s a re sult o f ja b b e r, t his b it w ill st a y se t in d ic a t in g t h e ja b b e r c o n d it io n . Bit 6: DIS, Receiver Disabled T his b it is set w hen the rec eive r is in Monitor Mo d e. I t is clear ed when the r eceiver leaves Moni tor Mode. Bit 5: GROUP, Group Address Recognized T his bit is s et when the recogniz ed addres s was either a gr oup addres s (multicas t) or br oadcas t. I t i s cl ear ed to i ndi cate an i ndi vi dual (phys i cal ) ad- d re ss m a t c h . Bit 4: MPA, Missed Packet T his bit is s et when a packet intended for this s tation cannot be accepted by the devi ce due to a l ack of rec eive b uffers or bec a use the devic e is in monitor mode. T he Mi s s ed P acket Counter (MP CNT ) i s als o incremented when this occur s . Bit 3: OVER, FIFO Overrun T his bit is s et when the receiver attempts to write i nto a F I F O that i s alr eady ful l . T hi s occur s when the DMA fails to keep up with the received data. Bit 2: FAE, Frame Alignment Error When F AE = 1, it indicates that the incoming packet di d not end on a byte boundar y and the CR C di d not match at the las t byte boundary. T he Alignment E r ror Counter is incremented when this conditi on occur s . Bit 1: CRC, CRC Error When this bit is s et, it indicates that the frame’s computed CR C fai l ed to cor r es pond wi th the CR C appended to the end of the fr ame. T hi s er r or al s o caus es the CR C Counter to be incremented. Bit 0: PRX, Packet Received Intact When s et to ’1’, this bit indicates that a packet was received without error. T his means that CR C = F AE = OVE R = MPA = 0. ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.2.29 RSTOP - Receive Stop Page Register

Nor mal Map R ead P or t = 2 :1 2 Normal Map Write Port = 0:12 T he R eceive S top P age R egis ter poi nts to the fi rs t addr es s beyond the las t receive buffer in the ri ng before wrapping around to the R S T ART buffer. Only A08-A15 ar e s pecified s ince all buffer s are aligned on 256-b yte b ound a ries. BIT RSTOP RESET

5.2.30 RTABH - Receive Buffer Table Pointer

L i nk ed- L i s t Map R ead/Wr i te P or t = 0 :19 T hi s r egi s ter contai ns the upper 8 bi ts for the regis ter pair us ed as a pointer to the receive buffer d e sc rip t o rs t a b le . Th e se re g ist e rs sh o u ld b e initializ ed to the s ame value as the R B E GIN regis ter when the des cr i ptor tabl e i s cr eated and ther eafter left una ltered unless the rec eive r b uffer p oo l is re b uilt. For mo re informa tion, refer to p a g e 89. BIT RTABH RESET

5.2.31 RTABL - Receive Buffer Table Pointer

L i nk ed- L i s t Map R ead/Wr i te P or t = 0 :18 T his regis ter contains the lower 8 bits for the regis ter pair us ed as a pointer to the receive buffer d e sc rip t o rs t a b le . Th e se re g ist e rs sh o u ld b e initializ ed to the s ame value as the R B E GIN regis ter when the des cr i ptor tabl e i s cr eated and ther eafter left una ltered unless the rec eive r b uffer p oo l is re b uilt. For mo re informa tion, refer to p a g e 89. BIT RTABL RESET

5.2.32 STA0-STA5 - Station Address

STA0 1:11 1:11 1:11 1:11 STA1 1:12 1:12 1:12 1:12 STA2 1:13 1:13 1:13 1:13 STA3 1:14 1:14 1:14 1:14 STA4 1:15 1:15 1:15 1:15 STA5 1:16 1:16 1:16 1:16 T hes e 6 regis ters hol d the node’s individual s tati on a d d re ss. Ta b le 5 -1 1 sh o w s t h e b it s d e f in e d f o r t h e se re g iste rs. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

5.2.33 TADDH - Transmit Burst Starting

Nor mal Map R ead/Wr i te P or t = 2 :1 B T his i s the hi gher 8 bi ts of a r egi s ter pair us ed internally by the DMA controller as a s cratch pad for the bur s t addres s of the trans mit proces s . Wr iti ng t o t h e TA D D H a n d TA D D L Re g ist e rs w h ile communi cati on i s taking pl ace may caus e er r or s in the DMA pr oces s . BIT TADDH RESET

5.2.34 TADDL - Transmit Burst Starting

Nor mal Map R ead/Wr i te P or t = 2 :1 A T hi s r egi s ter contai ns the l ower 8 bi ts for a r egi s ter p a ir used interna lly b y the DMA c ontroller a s a s cratch pad for the burs t addres s of the trans mit p roc ess. Writing to the TADDH a nd TADDL regis ters while communication is taking place may caus e err ors in the DMA proces s . BIT TADDL RESET STA Registers BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STA0 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 STA1 DA15 DA14 DA13 DA12 DA11 DA10 DA09 DA08 STA2 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 STA3 DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24 STA4 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32 STA5 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40 RESET XXXXXXXX TABLE 5-11. STATION ADDRESS REGISTER BITS ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.2.35 TBEGIN - Transmit Buffer Starting

L i nk ed- L i s t Map R ead P or t = 2 :13 L i nk ed- L i s t Map Wr i te P or t = 0 :15 T his regis ter holds the upper 8 bits of the s tarting addr es s of the trans mit buffer des cr iptor tabl e. T he l ower 8 bi ts ar e as s umed to be z er o. R efer to page 80 for m ore inform a tion. BIT TBEGIN RESET

7 TB15 X

6 TB14 X

5 TB13 X

4 TB12 X

3 TB11 X

2 TB10 X

1 TB09 X

0 TB08 X

5.2.36 TCNTH - Transmit Frame Length High

Norma l Ma p Rea d Port = 2:16 Norm a l Ma p Write Po rt = 0:16 T his regis ter contains the upper 8 bits of a two-regis ter s et that holds the byte count for the frame to be trans mitted. T his byte count mus t i nclude the DA, S A, and data fields . I f CR C gener ati on i s i nhi bi ted, thi s count mus t al s o i ncl ude the CR C field in the buffer. BIT TCNTH RESET

7 L15 X

6 L14 X

5 L13 X

4 L12 X

2 L10 X

1 L09 X

0 L08 X

5.2.37 TCNTL - Transmit Frame Length Low

Norma l Ma p Rea d Port = 2:13 Norm a l Ma p Write Po rt = 0:15 T hi s r egi s ter contai ns the l ower 8 bits of a two-regis ter s et that holds the byte count for the frame to be trans mitted. T his byte count mus t i nclude the DA, S A, and data fields . I f CR C gener ati on i s i nhi bi ted, thi s count mus t al s o i ncl ude the CR C field in the buffer. BIT TCNTL RESET

7 L07 X

6 L06 X

5 L05 X

4 L04 X

3 L03 X

2 L02 X

1 L01 X

0 L00 X

5.2.38 TCON - Transmit Configuration

Normal Map R ead Port = 2:1D Normal Map Write Po rt = 0:1D L i nk ed- L i s t Map R ead P or t = 2 :1D L i nk ed- L i s t Map Write Port = 0:1D T his re g ister c o ntro ls loo p b a c k op tions a nd trans mitter mode operations . BIT TCON RESET 70 0 60 0 50 0 40 0 30 0

2 LB1 0

1 LB0 0

0 CRCN 0

Bits 2-1: LB1, LB0, Loopback Test Selection T hes e two bi ts ar e decoded as s hown i n T abl e 5 -1 2 . 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

0 0 Normal (no loopback) 0 1 Internal loopback (before MAN CODEC) 1 0 Internal loopback, LOOP pin is high (after MAN CODEC) 1 1 External loopback with LOOP pin low TABLE 5-12. LOOPBACK TEST SELECTION Bit 0: CRCN, CRC Generation Inhibition S etting this bit inhibits generation of CR C during t ra n sm issio n o f f ra m e . Th e u se r is re sp o n sib le f o r cal cul ati ng the fr ame’s CR C and pl aci ng i t i n the b u f f e r in su c h a w a y t h a t w h e n t h e la st 4 b y t e s o f the buffer are s hifted out, they for m the cor rect CR C for the frame. Note that the s erializ er s hifts bytes out L S B fir s t whereas the CR C mus t be s hi fted MS B firs t. T he operation of the receiver is not affected by this bit.

5.2.39 TDOWNH - Transfer Count High

L i nk ed- L i s t Map R ead/Wr i te P or t = 2 :1 B T hi s r egi s ter contai ns the upper 8 bi ts for the r egis ter pai r us ed by the DMA contr oller as a s cratch pad for the bytes remaining to trans fer count dur ing the trans mis s i on pr oces s . T hey can be acces s ed for manufactur i ng tes t pur pos es . Note Writing to these registers while commu- nication is taking place may cause er- rors in the DMA process. BIT TDOWNH RESET 7A 1 5 X 6A 1 4 X 5A 1 3 X 4A 1 2 X 3A 1 1 X 2A 1 0 X 1A 0 9 X 0A 0 8 X

5.2.40 TDOWNL - Transfer Count Low

L i nk ed- L i s t Map R ead/Wr i te P or t = 2 :1A T his regis ter contains the lower 8 bits for the r egis ter pai r us ed by the DMA contr oller as a s cratch pad for the bytes remaining to trans fer count dur ing the trans mis s i on pr oces s . T hey can be acces s ed for manufactur i ng tes t pur pos es . Note Writing to these registers while commu- nication is taking place may cause er- rors in the DMA process. BIT TDOWNL RESET

5.2.41 TEND - Transfer Buffer End Register

L i nk ed- L i s t Map R ead P or t = 2 :14 L i nk ed- L i s t Map Wr i te P or t = 0 :14 T his r egis ter holds the upper 8 bits of the fi rs t addr es s beyond the end of the tr ans mi t buffer des cr i ptor tabl e. T he l ower 8 bi ts ar e as s umed to be zero. T he table lies b etween (T BEGIN * 256) and (T END * 256 - 1). Refer to pa ge 80 for more informa tion. BIT TEND RESET

7 TE15 X

6 TE14 X

5 TE13 X

4 TE12 X

3 TE11 X

2 TE10 X

1 TE9 X

0 TE8 X

ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.2.42 TLEVEL - Transmit FIFO Track Register

Nor mal Map R ead P or t = 3 :1 E L i nk ed- L i s t Map R ead P or t = 3 :1E T his counter tracks the number of empty bytes in the trans mit F I F O. An empty F IF O has 10h in this c o u n t e r. A f u ll FIFO h a s 0 0h . BIT TLEVEL RESET 7— 0 6— 0 5— 0

5.2.43 TSTARTH - Transmit Start Page High

Nor mal Map R ead P or t = 2 :1 4 Normal Map Write Port = 0:14 T his r egis ter is the hi gher 8 bi ts of a r egis ter pai r that poi nts to the as s embl ed packet to be trans mitted. To retain compatibility with 83C690 dri ver s , the us er s hould s tar t all fr ames on 256-byte boundar i es and not wr i te to T S T AR T L . BIT TSTARTH RESET 7A 1 5 0 6A 1 4 0 5A 1 3 0 4A 1 2 0 3A 1 1 0 2A 1 0 0 1A 0 9 0 0A 0 8 0

5.2.44 TSTARTL - Transmit Start Page Low

Nor mal Map R ead/Wr i te P or t = 3 :1 5 L i nk ed- L i s t Map R ead/Wr i te P or t = 3 :15 T hi s r egi s ter i s the l ower 8 bi ts of a r egi s ter pair that points to the as s embled packet to be trans mitted. To reta in c omp a tib ility with 83C690 d rivers, the user s houl d s tar t al l fr ames on 256 - byte boundar i es and only write to the T S T AR T H regis ter. BIT TSTARTL RESET

7 A07 0

6 A06 0

5 A05 0

4 A04 0

3 A03 0

2 A02 0

1 A01 0

0 A00 0

5.2.45 TSTAT - Transmit Status Register

Nor mal Map R ead P or t = 0 :1 4 L i nk ed- L i s t Map R ead P or t = 0 :14 T he T r ans mi t S tatus R egis ter r eports events that occur on the medi a at the end of packet tr ans mi s s i on. All bi ts ar e cl ear ed pr i or to tr ans mi s s ion of a packet and ar e s et as needed. When ALT E GO = 1, the regis ter is cleared only at the begi nni ng of a tr ans mi t chai n and i s s et after each packet has completed. BIT TSTAT RESET 7O W C 0

6 CDH 0

5 UNDER 0

4 CRL 0

3 ABORT 0

1 NDT 0

0 PTX 0

Bit 7: OWC, Out of Window Collision T his bit is s et if a collis ion is detected more than one s lot time after the s tart of trans mis s ion. T rans mis - s i on i s abor ted under thes e condi ti ons . 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

Bit 6: CDH, Collision Detect Heartbeat T hi s bi t i s s et to a ’1’ dur i ng tr ans mi s s i on of each p a c ke t. It is se t to ’ 0’ if a c o llisio n is d e te c te d w ithin 3.6 µs ec of the end of each packet trans mis s i on. If no col l i s i on i s detected wi thi n thi s wi ndow, i t r e- mains ’1’. Bit 5: UNDERFIFO, FIFO or Buffer Underrun When this bit is s et, it means either :

• a FIFO underrun condition has occurred. This condition results when the transmit unit at- tempts to read from an empty FIFO prior to receiving the transmit done flag from DMA. This means that the FIFO failed to supply enough data for the serializer to maintain frame genera- tion.
• a Buffer underrun has occurred. This condition happens when the transmit DMA accesses an address that is greater than or equal to the most recent host-written location in memory, pro- vided that the Early Transmit Check feature is enabled. Bit 4: CRL, Carrier Sense Lost T his bit is s et if the carrier is los t during packet t ra n sm issio n . C a rrie r se n se is m o n it o re d f ro m it s r is ing edge at the s tar t of the outgoing frame’s echo. Tra n sm issio n is n o t a b o rt e d u p o n lo ss o f c a rrie r. It is re p o rte d fo r sta tistic a l p urp o se s. Bit 3: ABORT, Abort Transmission T his bit is s et if the trans mis s ion is aborted due to e xc e ssiv e c o llisio n s. Bit 2: TWC, Transmitted With Collisions T hi s bi t i s s et i f the fr ame col l i ded at l eas t once wi th another frame on the network. It is not s et for either out-o f-w ind ow c o llisio ns o r e xc essive c o llisio n abor ts . Bit 1: NDT, Non-deferred Transmission Th is b it is se t if t h e f ra m e w a s t ra n sm it t e d su c c e ss- fully without deferring. A deferred trans mis s ion can only occur the firs t time an attempt is made to s end a p a c ket. Collisions a re not d eferre d tra nsmissio ns. Bit 0: PTX, Packet Transmitted T his bit is s et to indicate trans mis s ion of a packet without exc essive c ollisions or a F IF O und errun.

5.2.46 TTABH - Transmit Buffer Pointer High

L i nk ed- L i s t Map R ead/Wr i te P or t = 0 :1 B T his regis ter contains the higher 8 bits of the r egis ter pair us ed as a pointer to the trans mit buffer d e sc rip t o rs t a b le . Th e se re g ist e rs sh o u ld b e initializ ed to the s ame value as T B E GI N when the des criptor table is created, and not altered thereafter by the us er unles s the tr ans mit buffer p oo l is reb uilt. Fo r mo re inform a tion, refer to p a g e 80. BIT TTABH RESET

5.2.47 TTABL - Transmit Buffer Pointer Low

L i nk ed- L i s t Map R ead/Wr i te P or t = 0 :1A T hi s r egi s ter contai ns the l ower 8 bi ts of the r egi s ter pai r us ed as a poi nter to the tr ans mi t buffer d e sc rip t o r t a b le . Th e se re g iste rs sh o uld b e initializ ed to the s ame value as T B E GI N when the des criptor table is created, and not altered thereafter by the us er unles s the tr ans mit buffer pool i s r ebui l t. BIT TTABL RESET ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

5.2.48 RENH - Receive Enhancement Register

Nor mal Map R ead/Wr i te P or t = 0 :1 9 T he R eceive E nhancement R egis ter contai ns se ve ra l b its re q uire d fo r the ne w re c e ive fe a ture s o f the 83C795 c hip . BIT RENH RESET 7— 0 6— 0 5— 0 4— 0 3— 0

2 REMPTY 0

1 ERFBIT 0

0 WRAPEN 0

Bit 2: REMPTY, Ring Bit Empty When R E MP T Y = 1, this read-only bit indicates that the r eceive buffer r ing has no completely received frames . Bit 1: ERFBIT, Early Receive Fail Bit When E R F B I T = 1 i t i ndi cates that an under r un has occur red dur ing the reception of a frame. T he hos t cl ear s thi s bi t after r eadi ng the addr es s wher e the failur e occurr ed from the E R F A R egis ter s . Bit 0: WRAPEN, Automatic Ring-Wrap Enable When WR APE N = 1 it enables the auto-wrapping fe a ture . Fo r m o re info rm a tio n o n Auto m a tic Ring - Wra p , refer to p a g e 87. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

ADDRESS FUNCTION NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00 CONTROL CR RNIC MENB — CR4 CR3 RP15 RP14 RP13

01 EEROM RD ER STORE RC EA4 UNLOCK JMP3 JMP2 JMP1 JMP0

01 EEROM WR ER STORE RC EA4 UNLOCK EA3 EA2 EA1 EA0

02 IO PIPE LOW IOPL IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0

03 IO PIPE HIGH IOPH IOP15 IOP14 IOP13 IOP12 IOP11 IOP10 IOP9 IOP8

04 HW SUPP RD HWR SWH — ETHER HOST16 — ISTAT PNPJMP GPOE

HW SUPP WR HWR SWH —— — NUKE —— GPOE

05 BIOS PAGE BPR M16EN BP15 BP14 BP13 —— SOFT1 SOFT0

06 INT CONTROL ICR MCTEST STAG IOPAV IOPEN SINT MASK2 M ASK1 EIL

07 REVISION REV CHIP3 CHIP2 CHIP1 CHIP0 REV3 REV2 REV1 REV0

IO PIPE ADDR IOPA IOPA7 IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0

08 SWH=0 LAN ADDR0 LAN0 LN07 LN06 LN05 LN04 LN03 LN02 LN01 LN00

09 SWH=0 LAN ADDR1 LAN1 LN15 LN14 LN13 LN12 LN11 LN10 LN09 LN08

0A SWH=0 LAN ADDR2 LAN2 LN23 LN22 LN21 LN20 LN19 LN18 LN17 LN16 0B SWH=0 LAN ADDR3 LAN3 LN31 LN30 LN29 LN28 LN27 LN26 LN25 LN24 0C SWH=0 LAN ADDR4 LAN4 LN39 LN38 LN37 LN36 LN35 LN34 LN33 LN32 0D SWH=0 LAN ADDR5 LAN5 LNMSB LN46 LN45 LN44 LN43 LN42 LN41 LN40 0E SWH=0 BOARD ID BDID BDID7 BDID6 BDID5 BDID4 BDID3 BDID2 BDID1 BDID0 0F SWH=0 CHECKSUM CKSM CHK7 CHK6 CHK5 CHK4 CHK3 CHK2 CHK1 CHK0

08 SWH=1 GENERAL CNTL2 GCR2 — — — — — — — PNPIOP

0A SWH=1 I/O ADDRESS IAR IA15 IA14 IA13 IA8 IA7 IA6 IA5 PNPBOOT 0B SWH=1 RAM BASE RAR HRAM RA17 RAMSZ1 RAMSZ0 RA16 RA15 RA14 RA13 0C SWH=1 BIOS BASE BIO FINE BA17 BIOSZ1 BIOSZ0 BA16 BA15 BA14 BA13 0D SWH=1 GEN CONTROL GCR XLENGTH IR2 OWS RIPL IR1 IR0 GPOUT LIT 0E SWH=1 ERF ADDR LOW ERFAL ERFA7 ERFA6 ERFA5 ERFA4 ERFA3 ERFA2 — PNPEN 0F SWH=1 ERF ADDR HIGH ERFAH ERFA15 ERFA14 ERFA13 ERFA12 ERFA11 ERFA10 ERFA9 ERFA8 TABLE 5-13. HOST INTERFACE REGISTER SUMMARY ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

REGISTER RING LINKED BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ALICNT 0:1D — 0:1D — CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 BOUND 0:13 0:13 — — A15 A14 A13 A12 A11 A10 A09 A08 CMD X:10 X:10 X:10 X:10 PS1 PS0 0 ENETCH DISETCH TXP STA STP COLCNT 0:15 — 0:15 — T10 T9 T8 T7 CT3 CT2 CT1 CT0 CRCCNT 0:1E — 0:1E — CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 CURR 1:17 1:17 — — CURR15 CURR14 CURR13 CURR12 CURR11 CURR10 CURR09 CURR08 CURRH — — 1:17 1:17 CURR15 CURR14 CURR13 CURR12 CURR11 CURR10 CURR09 CURR08 CURRL — — 0:13 0:13 CURR07 CURR06 CURR05 CURR04 CURR03 CURR02 CURR01 CURR00 DCON 2:1E 0:1E 2:1E 0:1E 01000001 ENH 2:17 2:17 2:17 2:17 0 1 ALTEGO SLOT1 SLOT0 EOTINT — S BACK ERWCNT 0:18 0:18 0:18 0:18 ERW11 ERW10 ERW9 ERW8 ERW7 ERW6 ERW5 ERW4 GROUP0 1:18 1:18 1:18 1:18 GA07 GA06 GA05 GA04 GA03 GA02 GA01 GA00 GROUP1 1:19 1:19 1:19 1:19 GA15 GA14 GA13 GA12 GA11 GA10 GA09 GA08 GROUP2 1:1A 1:1A 1:1A 1:1A GA23 GA22 GA21 GA20 GA19 GA18 GA17 GA16 GROUP3 1:1B 1:1B 1:1B 1:1B GA31 GA30 GA29 GA28 GA27 GA26 GA25 GA24 GROUP4 1:1C 1:1C 1:1C 1:1C GA39 GA38 GA37 GA36 GA35 GA34 GA33 GA32 GROUP5 1:1D 1:1D 1:1D 1:1D GA47 GA46 GA45 GA44 GA43 GA42 GA41 GA40 GROUP6 1:1E 1:1E 1:1E 1:1E GA55 GA54 GA53 GA52 GA51 GA50 GA49 GA48 GROUP7 1:1F 1:1F 1:1F 1:1F GA63 GA62 GA61 GA60 GA59 GA58 GA57 GA56 INTMASK 2:1F 0:1F 2:1F 0:1F 0 ERWE CNTE OVWE TXEE RXEE PTXE PRXE INTSTAT 0:17 0:17 0:17 0:17 RST ERW CNT OVW TXE RXE PTX PRX MANCH 3:1F 3:1F 3:1F 3:1F MANDIS SEL 0 ENAPOL TPOL LNK RLED XLED MPCNT 0:1F — 0:1F — CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 NEXT 2:15 2:15 — — A15 A14 A13 A12 A11 A10 A09 A08 RADDH 2:19 2:19 — — A15 A14 A13 A12 A11 A10 A09 A08 RADDL 2:18 2:18 — — A07 A06 A05 A04 A03 A02 A01 A00 RBEGIN — — 2:11 0:11 A15 A14 A13 A12 A11 A10 A09 A08 RCNTH 0:1B — — — CT15 CT14 CT13 CT12 CT11 CT10 CT09 CT08 RCNTL 0:1A — — — CT07 CT06 CT05 CT04 CT03 CT02 CT01 CT00 RCON 2:1C 0:1C 2:1C 0:1C 0 RCA MON PROM GROUP BROAD RUNTS SEP RDOWNH — — 2:19 2:19 A15 A14 A13 A12 A11 A10 A09 A08 RDOWNL — — 2:18 2:18 A07 A06 A05 A04 A03 A02 A01 A00 REND — — 2:12 0:12 A15 A14 A13 A12 A11 A10 A09 A08 RENH 0:19 0:19 —————R E MPTY ERFBIT WRAPEN RSTART 2:11 0:11 — — A15 A14 A13 A12 A11 A10 A09 A08 RSTAT 0:1C — 0:1C — DFR DIS GROUP MPA OVER FAE CRC PRX RSTOP 2:12 0:12 — — A15 A14 A13 A12 A11 A10 A09 A08 RTABH — — 0:19 0:19 A15 A14 A13 A12 A11 A10 A09 A08 TABLE 5-14. LAN CONTROLLER REGISTER SUMMARY 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS

REGISTER RING LINKED BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RTABL — — 0:18 0:18 A07 A06 A05 A04 A03 A02 A01 A00 STA0 1:11 1:11 1:11 1:11 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 STA1 1:12 1:12 1:12 1:12 DA15 DA14 DA13 DA12 DA11 DA10 DA09 DA08 STA2 1:13 1:13 1:13 1:13 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 STA3 1:14 1:14 1:14 1:14 DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24 STA4 1:15 1:15 1:15 1:15 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32 STA5 1:16 1:16 1:16 1:16 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40 TADDH 2:1B 2:1B — — A15 A14 A13 A12 A11 A10 A09 A08 TADDL 2:1A 2:1A — — A07 A06 A05 A04 A03 A02 A01 A00 TBEGIN — — 2:13 0:15 A15 A14 A13 A12 A11 A10 A09 A08 TCNTH 2:16 0:16 — — L15 L14 L13 L12 L11 L10 L09 L08 TCNTL 2:15 2:15 — — L07 L06 L05 L04 L03 L02 L01 L00 TCON 2:1D 0:1D 2:1D 0:1D —————L B 1 L B 0 CRCN TDOWNH — — 2:1B 2:1B A15 A14 A13 A12 A11 A10 A9 A8 TDOWNL — — 2:1A 2:1A A07 A06 A05 A04 A03 A02 A01 A00 TEND — — 2:14 0:14 TE15 TE14 TE13 TE12 TE11 TE10 TE09 TE08 TLEVEL 3:1E 3:1E ———C T 0 4 C T 0 3 CT02 CT01 CT00 TSTARTH 2:14 0:14 — — A15 A14 A13 A12 A11 A10 A09 A08 TSTARTL 3:15 3:15 3:15 3:15 A07 A06 A05 A04 A03 A02 A01 A00 T S T A T 0 : 1 4— 0 : 1 4— OWC CDH UNDER CRL ABORT TWC NDT PTX TTABH — — 0:1B 0:1B A15 A14 A13 A12 A11 A10 A09 A08 TTABL — — 0:1A 0:1A A07 A06 A05 A04 A03 A02 A01 A00 TABLE 5-14. LAN CONTROLLER REGISTER SUMMARY (cont.) ETHERNET SYSTEM CONTROLLER REGISTERS 83C795

6.0 HOST INTERFACE SECTION

T he H os t I nter face i s a confi gur abl e i nter face b e tw e e n a n Ind ustry Sta nd a rd Arc hite c ture b us (like IBM PC/ XT / A T ) a nd the LAN c ontro ller with its buffer memor y. T he inter face i s a s l ave per i pher al wi th s har ed R AM and s uppor t for an I ni ti al P r ogr am Lo a d RO M . Th e b a sic f u n c t io n s o f t h e h o st in t e rf a c e se c t io n a re the:

• Address decode
• Memory address generation
• Retrieval and storage of configuration parame- ters and LAN address
• Interrupt mapping and control
• Control over certain HW functions for support circuitry

6.1 MEMORY CACHE

T he memory c a c he in the 83C795 c o nsists of a 4-byte-deep F IF O which s erves as an intermediate buffer between the I S A bus and the l ocal buffer R AM. F or read oper ations , the cache acts as a sm a ll p re fe tc h b uffe r w hic h fills itself w ith d a ta from locations in the buffer R AM that depend on the a d d re ss o f the la st d a ta lo c a tio n re a d b y the ho st. F or write oper ations , the cache acts as s everal tempor ar y r egi s ter s that can be as ynchr onous ly written by the hos t, then s ynchronous ly flus hed to buffer RAM a s time permits. T his method provides s ever al advantages over pr evi ous methods :

• Host accesses to shared memory can be treated more like register accesses, thus simpli- fying zero-wait state timing.
• A single 8-bit wide buffer RAM is used but the chip can accommodate 8- or 16-bit accesses by the host.
• Asynchronous arbitration between the host and the DMA controller for access to the buffer RAM is not necessary. In addition to the data F IF O, the cache requires two a d d re ss c o u n t e rs f o r it s o p e ra t io n . Th e f irst , c a lle d the Hos t Counter, is compared with the incoming hos t addr es s . T he s econd, cal led the B uffer Counter, is us ed to generate the addres s to the local buffer R AM. T he s ame data F IF O is us ed for both r eads and wr ites res ul ting i n two different modes of oper ati on: R ead Mode and Wr i te Mode. REA D M O D E I f the hos t addr es s does not equal the value in the Hos t Counter, then both counter s ar e loaded with the incomi ng addr es s . T hen the cache i s filled with data fr om the buffer R AM a byte at a ti me by incrementing the B uffer Counter. T he hos t acces s i s s tal l ed dur i ng thi s ti me by dr i vi ng the I OR DY s i gnal l ow. Once the cache has a val i d wor d of data from the buffer R AM, the IOR DY line is driven high. T hi s s i gnal s the hos t that the data i s val i d, and the host, in turn, ends the a c c ess. Onc e the host ha s fini s hed, the Hos t Counter is incr emented (the inc rem ent step w ill b e either 1 or 2 d ep end ing o n w he the r the ho st a c c e ss w a s fo r a b yte o r fo r a wor d), and the F I F O poi nter s ar e updated. T he c a c he c ontinues to fill w ith d a ta a s long a s there is room in the F IF O. If the host a ddress ma tc hes the value in the Hos t Counter (and there is valid data in the cache), the read can be s erviced immediately. WR IT E MODE T he Write Mo d e is ha nd le d like the Rea d Mod e except that the data moves in the oppos ite direction thr ough the F I F O. Al s o, i f an addr es s mi s s occur s in wri te mode, the cache mus t fir s t flus h al l valid data in the F IF O out to the buffer R AM before loading new values into the addres s counters . T he I OR DY s i gnal i s us ed when the cache needs to s tall a hos t acces s . T his s ignal is outputted by a high current, tri-s tatable driver which is normally turned off between acces s es to the board. It drives low to indicate that the board is not IOR DY and d riv e s h ig h w h e n m a k i n g t h e t ra n sit io n f ro m ’ n o t re a d y’ to ’ re a d y’ . When the acces s completes , the I OR DY line is tri-s tated by the ending of the hos t’s s trobes . F igure 6-1 depicts the memory cache ar rangement. 83C795 HOST INTERFACE SECTION

6.1.1 Zero Wait State Response to Host

T he Zero Wa it S ta te sig na l tells the mic rop roc e ssor that it can compl ete the pres ent bus cycle without inserting a ny a d d itio na l w a it c yc le s. Fo r 16-b it memor y acces s , thi s means z er o wai t s tates ar e i ns er ted by the hos t bus l ogi c and the acces s cycl e c o m p le t e s in 2 b u s c lo c ks. Wh e n a sse rt e d f o r a n 8 bi t memor y acces s , an I S A bus automati cal ly in se rt s t h e m in im u m o f 2 w a it st a t e s. Th e re sp o n se a lg o rit h m f o r t h e ZWS line d e p end s upon the memory width, the hos t acces s type and whether the boar d has been enabl ed to act as a 16-bi t devi ce. T he appr opr i ate ZWS re sp o n se lo g ic is se le c t e d o n t h e b a sis o f t h e BPR.M 16EN c o n t ro l bi t and whether the boar d i s i n an 8 - or 1 6 -bi t s l ot. T he memor y cache can accommodate z er o wai t s tate timing if the following conditions are met: 1. The type of host access matches the current mode of the cache, 2. The host address matches the value in the host counter, and 3. The cache either contains at least one valid data word for reads or has room for at least one more word for writes. F or wr i tes , z er o wai t s tates ar e al s o al ways pos s i bl e if the c a c he is in re a d m o d e , o r if it is c urre ntly empty. T he re is a Ze ro Wa it Ena b le b it in o ne o f the ho st inter face regis ters (CR .Z WS E N) which can be us ed to prevent the 83C795 from as s erting the Z ero Wait S tate s i gnal .

6.1.2 Staggered Address Transfers

St a g g e re d a d d re ss t ra n sf e rs o c c u r w h e n t h e h o st a t t e m p t s 16 -b it d a t a t ra n sf e rs f ro m sy st e m m e m o ry to the l ocal buffer R AM and fi nds that the addr es s of the s ys tem data differs fr om the local addres s in the leas t s ignificant bit (one is even, one is odd). In c o n se q u e n c e , t h e ISA b u s f o rb id s 16- b it a c c e sse s to odd locations and breaks the trans fer into two 8 -bi t cycl es whi ch r un cons i der abl y s l ower. To overc ome this o n the 795: FIGURE 6-1. MEMORY CACHE ARRANGEMENT HOST INTERFACE SECTION 83C795

1. Make sure the system address is even. If the address comes out odd, transfer one byte. 2. Set the STAG bit (ICR.6). This forces a ’1’ into bit 0 of the Buffer Counter when the address is loaded NOTE This only happens on a cache miss. Th is m a k e s it p o ssib le f o r t h e h o st t o p e rf o rm a n even- to-even tr ans fer, but the i nter nal addr es s to the l ocal R AM i s tr ans for med to an odd addr es s .

6.1.3 Operation on Micro-Channel Adapters

Do not us e this chip for micro-channel applications . A future variant may be created with the neces s ary interfa c e lo gic .

6.2 I/O-MAPPED PIPE

T he I /O- mapped pi pe pr ovi des another method for acces s ing the local buffer R AM. When enabl ed, all memor y acces s es take pl ace thr ough two I /O r egis ter s in the hos t i nter face I/O s pace (I OP L and IOP H). T he data in thes e two I/O locations corres ponds to the the location in the buffer memor y indi cated by the B uffer Counter. When r un i n thi s mode, the memor y- s pace addr es s decoder s a re d isa b led , so the a d a p ter w ill no t use a ny host memor y s pace for the buffer R AM. T he mechani s m us ed by the I /O- pi pe i s s i mi l ar to that us ed by the memory cache except for addr es s handling. In this method, the addres s is loaded into the B uffer Counter by per forming two cons ecuti ve wr ites to the I OPA regis ter. T he firs t write s tor es the l ower hal f of the addr es s i nto a tempor ar y r egi s ter. T he s econd write s tores data directly into the upper half of the buffer counter and moves the temporary regis ter into the lower half. Any acces s to the chip between the two writes will caus e the s tate machi ne to not load the addres s . T he Hos t Counter is not use d d uring this p roc ess. To us e the I/O-pipe, the IOPE N bit (ICR .4) mus t be s et to 1, and the ME NB bit (CR .6) mus t be s et to 0. A ll 8-b it t ra n sf e rs m u st t a ke p la c e t h ro u g h IO PL only. Als o, it is imperative that when s witching from R ead Mode to Wr i te Mode, the addr es s mus t be reloaded even if the counter holds the correct value.

6.3 ADDRESS DECODERS

T hr ee addr es s decoder s ar e us ed to detect hos t a c c e sse s t o t h e b u f f e r m e m o ry , I/ O re g ist e rs, a n d I P L R OM. T hes e decoders obs er ve the S A19-S A05 lin e s t o d e c o d e a c c e ss w it h in a ra n g e o f a d d re sse s (a wi ndow). T he buffer and I P L R OM decoder s allow pl acement of their res pecti ve windows on any 8K boundary between C0000H and E FFFFH r egardles s of window s i z e. T hi s al lows windows to s tart on even or odd 8K boundar ies . T he R AM and I P L R OM are s cr ollable (and therefor e can be paged) thr ough their pr ogr ammabl e wi ndow s i z e as s hown i n T abl e 6 -1 bel ow. DECODER MIN BASE MAX BASE INCREMENT WINDOW SIZES BUFFER C0000H EE000H 2000H 8K 16K 32K 64K* DISABLED IPL ROM C0000H EE000H 2000H 8K 16K 32K DISABLED I/O BASE 0200H E3E0H 20H, 2000H 32 Bytes TABLE 6-1. HOST INTERFACE ADDRESS DECODERS * Plug a nd Pla y c a nnot utilize this wind ow size. 83C795 HOST INTERFACE SECTION

B ecaus e of the 16- bi t memor y mechani s m empl oyed i n I S A bus es , do not al l ow the memor y window to overlap the DF F F F H to E 0000H b ound a ry w hen using 16-b it m e m ory. If the b o u n d a ry c ro sse s, h o st m e m o ry a c c e sse s t o p o rtio ns a b o ve E0000H a re m a d e into 8-b it c yc le s. Note Use caution when overlapping the ROM and RAM windows if the RAM is 16-bit wide and both windows are en- abled. With 16-bit access enabled, the M16CS is asserted for all accesses within the same 128K address block as the RAM base window address. Should the access actually be intended to the ROM, the host falsely expects the ROM to return 16-bit data. THIS CAN CRASH THE OPERATING SYSTEM. To avoid such problems on 16-bit boards, copy ROM code to system RAM and disable the ROM window. Alternatively, map the ROM into other 128K address block. P r ogr am contr ol enables buffer memor y decodi ng thr ough a regis ter i n the hos t interface s ection. When connected to a 1 6 -bi t bus , thi s compar i s on i s qual i fi ed by ME MR , ME MW, and the inver s e of AE N. When connected to an 8-bit bus , the q ua lific a tio n is b y SM EM R, SM EM W , a n d t h e inver s e of AE N. T he buffer memor y window s iz e i s program-selec table as 8K, 16K, 32K, 64K b ytes or di s abl ed. T he buffer bas e addr es s can be s et to any 8K boundary from C0000H through EE000H. B y s etti ng a bit i n the R AM Addr es s R egis ter (RAR.HRAM), the dec oded buffer rang e c a n b e changed to the range F C0000h - F E E 000h. (T his ra ng e is no t p o ssib le w he n using Plug a nd Pla y .) When connected to a P C/X T bus having no L A lines, it is req uired tha t the BPR.M16EN b e ke p t a zero (ina c tive). T he I P L R OM decodi ng i s enabl ed by pr ogr am control through the B I O regis ter in the hos t interface s ecti on. Decoder qual i fi cati on i s by SM EM R a n d a n i n v e r t e d A EN . RO M w i n d o w si z e i s p r o g r a m selec ta ble from 8K, 16K, 32K bytes or disa bled. T he R OM window pl acement i n hos t memory s pace FIGURE 6-2. OVERLAPPING ADDRESS STRUCTURE HOST INTERFACE SECTION 83C795

is pr ogr ammable on any 8K boundary fr om C0000H to E E 0 00 H . Wher e R OM and R AM decodi ng over laps , R OM takes pr ecedence. F igure 6-2 sh o w s h o w t h e o v e rla p p in g a d d re ss st ru c t u re wor ks . You can r el ocate R AM and R OM bas e addr es s es in tandem a bove 1M (100000H) with the ap plic ation of an ex ter nal cas caded addr es s decoder. T hi s i s i l l us tr ated i n F i gur e 6 -3 . Note Relocation of the memory windows in this way is not supported when Plug and Play is enabled.

6.3.1 Memory Address Generation

ROMs a nd b uffer m em orie s la rg er tha n the ir programmed windows can be s crolled (paged) by us i ng pr ogr ammabl e addr es s modi fi er s (adder s ) that lie between the hos t addres s and the R OM or buffer memor y. T hes e addres s modi fiers can add independentl y to either addres s any of the followi ng values and expos e differ ent par ts of the tar geted memor y wi thin the window: 0000H 2000H 4000H 6000H 8000H A000H C000H E000H T he l ower addres s lines (S A12-0) fr om the hos t are multiplexed with the DMA addres s lines to generate par t of the memor y addr es s . T wo potenti al memor y a d d re sse s a re g e n e ra t e d b y su b t ra c t in g t h e re sp e c t iv e RA M a n d RO M b a se a d d re ss b it s (17-13) from S A17-S A13, then adding the RP15-RP13 f ie ld o f t h e C R Re g ist e r f o r t h e RA M FIGURE 6-3. EXTERNAL CASCADED ADDRESS DECODER 83C795 HOST INTERFACE SECTION

addr es s or the B P 15-B P 13 fi eld of the B P R R egi s ter for the R OM addr es s . Dependi ng on whether the buffer memor y or the R OM window is bei ng acces s ed, one of thos e two pos s i bl e s ums becomes MA15-MA13 to the memory cache counter s . R efer to F igure 6-4 for an illus tration of the addres s gener ati on path. FIGURE 6-4. ADDRESS GENERATION PATH HOST INTERFACE SECTION 83C795

6.3.2 I/O Address Decode

T he I /O addres s decoder compares the s ys tem a d d re ss l i n e s SA 1 5 - SA 1 3 a n d SA 8 - SA 5 a g a i n st a p ro g ra m m a b le va lue . SA9 is c o m p a re d to ’ 1’ . T he l ower gr oup of l ines gi ves a window s i z e of 32 bytes l ocated on 3 2 -byte boundar i es over the r ange of 200H to 3E 0H . T he compar i s on wi th upper addr es s bi ts al l ows the wi ndow to be l ocated outs i de the bas e I /O ar ea i n the event ther e ar e mul ti pl e L AN c a rd s on the sa m e b a c kp la ne. T his c om p a rison is qual i fi ed by the IO R, IO W, a nd the inve rse o f the A EN lin e s. I/ O b a se lo c a t io n p o ssib ilit ie s a re : ... Note Only the first base location option is supported by Plug and Play. T he I /O addr es s i s fur ther decoded to r es ol ve between the L AN controller and regis ters as s ociated wi th the hos t inter face bas ed on the A4 addr es s l i ne.

6.3.2.1 PC-98 Bus Support

T hi s featur e al l ows the I /O addr es s decodi ng to be changed to s uppor t the NE C P C-9 8 bus . T hi s i s done by ins tal ling J U MP E R 7, whi ch connects an ex ter nal r es i s tor between MA7 and gr ound. When e n a b l e d , t h e SA 9 - SA 1 li n e s re p la c e t h e SA 8 - SA 0 lin e s, t h e SA 12 -SA 10 lin e s m u st b e a ll 1’ s, a n d t h e SA0 line m ust b e ze ro fo r a n I/ O a c c e ss to o c c ur. Th is re m a p p in g o n ly a f f e c t s I/ O a c c e sse s a n d leaves memor y decoding unchanged.

6.4 BUS CONTROL SIGNALS

T wo s i gnal s contr ol much of the bus acti vi ty. T hey ar e I /O Channel R eady (I OR DY ) and Z er o Wai t St a t e ( Z WS ). E ach i s ex pl ai ned bel ow.

6.4.1 IORDY

T he I OR DY output is a high current, tri-s tate driver which is normally turned off between acces s es to the board. It will actively drive low to indicate that the boar d i s not I OR DY and dr i ves hi gh when making the trans ition from ’not ready’ to ’ready’. Acces s to the internal regis ters of the L AN contr ol l er i s ar bi tr ated by the L AN contr ol l er. T hi s ar bi tr ati on i s tr ans par ent to the hos t. When host a c c ess is c om p leted , IORDY is tri-sta te d by the ending of the hos t’s s tr obes .

6.4.2 Zero Wait State Response To Host

Th e Ze r o W a i t St a t e ( Z WS ) s ignal tells the mi cr opr oces s or that i t can compl ete the pr es ent bus cycl e wi thout ins er ti ng any addi ti onal wai t c y c le s. Th e re sp o n se a lg o rit h m f o r t h e ZW S lin e depends on the memory width, the hos t acces s type, and whether the board has been enabled to act as a 1 6 -bi t devi ce. T he appr opr i ate type of ZW S re sp o n se lo g ic is se le c t e d o n t h e b a sis o f m e m o ry wi dth and the M16E N contr ol bi t s tate. T he re is a Ze ro Wa it Ena b le b it in o ne o f the ho st inter face regis ters (CR .Z WS E N) which can be us ed to prevent the 83C795 from as s erting the Z ero Wait S tate s i gnal . 83C795 HOST INTERFACE SECTION

6.5 MEMORY BUS STRUCTURE AND

6.5.1 Memory Bus Width Control

B ecaus e of the 83C795’s memor y cache, the width o f th e m e m o ry p a t h is fixe d a t 8 b it . By m e a n s o f the memory cache, the I/O pipe can s er vi ce either a n 8 -b it o r 16- b it h o st a c c e ss. Th e Ho st a n d h o st interfa c e log ic a re p ro g ra m m e d for a sp ec ific memory width by s etting bit 7 in the B I OS P age R egis ter, M16E N. (S ee page 17 for more on this bi t. ) T he 83C795 c a lc ula tes the wid th of the host b us b y obs er vi ng the ME MR line for trans itions . An internal fl ag (E E R OM.HOS T 16) is s et to indicate a 16-bit hos t bus after 2 r i s i ng edges ar e s een on thi s pi n. When connected to an 8-bit hos t, this pin is left unc onnected or is tied to VDD and s hould not have any tr ans i ti ons . 6.5.2 16-Bit Response To Host Access Th e BPR.M 16EN b it in t h e BIO S Pa g e Re g ist e r tells the hos t interface logic whether to make the L AN adapter r es pond as a 16-bi t or an 8-bi t p erip hera l to the ho st. T he 83C795 resp ond s to either hos t bus width. When the hos t acces s es memor y, an addres s c omparator within the 83C795 looks at the LA23-LA17 lines to determine if the 83C795’ s memor y ter r i tor y i s being acces s ed. I f i t i s and i f MP R .M16E N i s s et, the M16CS line is activated to tell the hos t to run a 16-bit trans fer cycle. When this deci s i on i s bas ed onl y on the L A addr es s l i nes , i t i s pos s ible that the M16CS w ill b e sent out w hen the h o st is a c c e ssin g a d e v ic e o t h e r t h a n 83C 795 w it h in t h e sa m e a d d re ss ra n g e . To a llo w fine r re so lutio n fo r the M1 6 CS decode, ther e i s an opti onal means of i ncl udi ng the decodi ng of S A16-S A13 lines in the generation of the M16CS r es pons e. T hi s can be enabl ed by the F I NE 16 bi t of the Memor y P age R egis ter. B ecaus e the S A l ines are not guar anteed s table as early as L A lines , this for m of decodi ng can l ead to er r oneous r es ul ts . B e careful when you us e this method. To avoid bus width conflicts between buffer memory and the R OM as wel l as confl i cts wi th other car ds i n the syst e m , t h e 16-b it re sp o n se sh o u ld b e t u rn e d o n b y s oftwar e only when that s oftwar e can guar antee that no acces s to the R OM is taking place and that the only acces s es within the 128K memory range ar e to 16 - bi t devi ces . T hi s may mean ens ur i ng that no acces s to any other card can take place. In existing d rivers, this is d one b y p erform ing a ll 16-b it trans fers within interrupt s ervice routines that keep all other interrupts dis abled during the trans fer. T ake s peci al car e when wr i ti ng I P L R OM code. I f the code actually gets executed out of R OM, the R OM can potentially be configured within the s ame 128K bl ock . T he bes t advi ce i s to copy code fr om R OM to s ys tem memory outs ide the bl ock or to wr ite code that does not enable 16-bit trans fers . T he Host is p rovid e d with the ZWS sig n a l in accor dance wi th whether the memor y cache can accommodate the tr ans fer. T he ti ming of this s i gnal is dependent upon the width of the trans fer being per for med wi th the hos t. T o meet the memor y bandwi dth r equir ed by the I S A bus , i t i s neces s ar y to i mpl ement the buffer memor y HOST INTERFACE SECTION 83C795

with fast (35 nsec ) RAMs. F or more details, see the A C t im in g sp e c s in Se c t io n 10.

6.6 INTERRUPT REQUEST CONTROL

T here are two s ources of interrupt reques ts to the hos t: the L AN Contr ol l er and a pr ogr ammabl e bi t (S I NT ) i n the I CR regi s ter. T he L AN contr ol ler s ection pr ovi des for the mas king, pol ling, and c le a ring o f its ind ivid ua l inte rrup t c o nd itio ns. T he s um of the mas ked L AN inter r upt condi ti ons i s ’OR ’ed with the programmable interrupt from the hos t i nter face s ecti on (S I NT ) and gated by the E I L bit from the I CR r egis ter pr ior to tur ni ng on one of the s even program-s electable tri-s tate drivers . T he d rive r se le c tio n is m a d e via b its in the G C R re g iste r. I nter r upt di s abl i ng s houl d be accompl i s hed vi a the ICR .E IL bit, not by changing the interrupt level to ’0’, becaus e during the trans ition from an active level to tri-s tate, fals e interrupts may be generated. T he I nterr upt R eques t Control l ogic is depi cted in Fig u re 6- 5. FIGURE 6-5. INTERRUPT CONTROL LOGIC 83C795 HOST INTERFACE SECTION

6.7 EEROM CONTROLLER AND ITS

T he 83C795 is d esig ned to op era te in c onjunc tio n wi th a s er i al E E R OM memor y that s tor es the confi gur ation of the hos t i nter face and the per manently-as s i gned L AN s tati on addr es s . I t can r educe the number of jumpers needed on a board and al l ows for r econfi gur ati on wi thout r emovi ng the boar d fr om the s ys tem. T he E E R OM is us ed to initializ e s ome of the hos t inter face configurati on regis ters at res et time.

6.7.1 Initialization Of 83C795

Activation of the res et pin forces the internal s tate of the 83C795 to a known va lue. T here is a g roup of opti on bi ts that can be confi gur ed by attachi ng r es is ti ve pull-downs to four of the memory addr es s output lines (MA09-MA00). T hese pins are s ometimes referred to as the I NIT pins . T hey s till per for m thei r functi on as memor y addr es s l i nes but al s o act as i nput pi ns dur i ng the R E S E T pr oces s . Ea c h p in ha s a hig h im p ed a nc e interna l p ull-up r es i s tor that caus es the pi n to r ead as ’1’ unl es s a low er-im p ed a nc e externa l p ull-d ow n resisto r b ring s the natural s tate of the line to a logic ’0’ level. It is ex pected that an appl i cati on of thi s chi p woul d us e a se t o f ju m p e rs t o se le c t iv e ly c o n n e c t t h e se p in s to the external pull-downs , as s hown in T able 6-2 bel ow. Jumpers Pins Effect These jumpers are installed to mark 0 bits JMP0-3 MA0-3 EEROM Config. field, bits 0-3. These jumpers are installed to activate features JMP4 MA4 Switching PS HIDUTY option. JMP5 MA5 Switching PS output from GPOUT. JMP6 MA6 Plug and Play logic enable. JMP7 MA7 NEC PC-98 Bus support. JMP8 MA8 Drive 20 MHz clock out TLED pin. JMP9 MA9 Use 83C790 Chip ID field instead of the 83C795 ID field. TABLE 6-2. JUMPER EXAMPLE At the end of r es et, thes e I NI T pins are s ampl ed and latched. One of thes e combinations determines whether the E E R OM is read into the hos t inter face reg iste rs. O rd ina rily , the 83C 795 loa d s its confi gur ati on r egi s ter s fr om E E R OM, but s el ecti on o f o ne sp e c ia l c o m b ina tio n o f jum p e rs (w he n a ll I NIT s ar e pul led down) pr ovides a means of bypas s i ng the E E R OM l oad to al l ow r api d s imulation and tes ting of the device. U tiliz e the bypas s mode to pr oduce a l es s expens i ve adapter d e sig n w hic h d oe s no t reta in c o nfig ura tion or addr es s permanently. T her e i s al s o a means of accel er ati ng the E E R OM cl ock and as s oci ated E E R OM i nter face pi ns ( EED O , EEC S, LLED, RLED ) f o r t e st p u rp o se s. LLED is c o n n e c t e d t o t h e EERO M c lo c k p in ( EESK) and i s nor mal l y the pr i mar y cl ock (2 0 MH z ) di vi ded d own b y 128 d uring EEROM a c c esses. T he IOR and I OW pi ns ar e l atched on the r i s i ng edge of R E S E T . If both are active (low) at the s ame time, the clock accelerates to 10 MHz . To res tore the norma l 156 kHz c loc k ra te, the c hip is reset without activating IOR or I OW. R L E D is connected to the EERO M ’ s d a t a -in p in , EED I. U nl es s bypas s ed, the E E R OM data i s r ead automatically into the hos t interface regis ters jus t after the 83C795 is res et. T his takes approximately 2 millisec ond s. During this tim e, m em ory, ROM, and r egi s ter acces s i s di s abl ed. I /O acces s es to any ho st inte rfa c e re g iste r re turn g a rb a g e e xc e p t fo r b it 6 , whi ch wi l l r etur n ’1’ unti l the r egi s ter s ar e l oaded at which time bit 6 returns ’0’. T o determine when the initia l lo a d o f re g iste rs is c o m p le te d , p o ll the EER Re g ist e r. If t he REC A LL b it (Bit 6) e q u a ls 0, the initial load is complete. Th e re g ist e rs st a rt o u t w it h t h e ir re se t v a lu e s a n d ar e changed one r egi s ter at a ti me as the E E R OM i s r ead out. T he buffer memor y i s al ways di s abl ed upon r es et and mus t be enabl ed by s oftwar e. T he first tim e a n EERO M is p o w e re d up , it ha s ra nd om d a ta . T he 83C795 c a n b e a c c essed a t kno w n initia l a d d re sses if a sp ec ia l setting of the I NI T pi ns i s chos en when R E S E T pi n i s acti ve. T hi s i s ex pl ai ned i n mor e detai l i n the fol l owi ng s ecti on. HOST INTERFACE SECTION 83C795

6.7.2 Retrieval And Storage Of Host

6.7.2.1 EEROM Interface Overview

An externa l 9356 seria l EEROM is used to store up to 256 bytes of data. It takes about 2 ms to read all 16 regis ters after the end of the r es et puls e. I t takes a bout 200 ms to store the EEROM. T he LAN Controller s hould not be online (tr ans mi tting or able to r eceive) while E E R OM r ecall or s tore oper ations ar e ongoi ng, nor s hould any of the r egi s ter s i n the LAN c o ntro lle r o r ho st inte rfa c e se c tio n b e a c c e sse d d u rin g t h a t t im e . Un p re d ic t a b le re su lt s m a y oc c ur b ec a use the interna l d a ta b usses w ill b e s upporting the data movement to or from the E E R OM during that time interval. An exc eption to this rule is ma de in the c a se of the E E R r egi s ter, whi ch may be pol l ed to deter mi ne when the r ecall or s tor e oper ation completes . When the E E R r egis ter is r ead, the E E R .S T O and E E R .R C bits are vis ible to the hos t. Other bits from that regis ter are meani ngful only when ther e is no o n g o in g EERO M o p e ra t io n . All 256 b ytes of EEROM c a n b e written to a nd rea d fr om. T hey are r ead into the L AN Addres s regis ters 8 bytes at a ti me. Once ther e, they can be changed and s tor ed. T he E E R OM contr oller can be oper ated under pr ogr am contr ol to do par ti al r etr i eval s fr om and s ave configuration data into the E E R OM. E E R OMs have a l i mi ted number of s tor age cycl es . T he s tor e operation s hould onl y take pl ace at i ni tial board configuration or at initial ins tallation in a cus tomer ’s computer .

6.7.2.2 EEROM Recall Operation Details

All rec a lls from EEROM into host interfa c e reg isters are made in gr oups of either 8 or 16 regis ters . T he choices are programmed into the E E R regis ter in the hos t interface s ection according to T able 6-3. Reset Recall Action 0 0 No Recall 0 1 Recall from bank ’EA’ into LAN ADDR registers

1 X Recall from bank ’6’ into LAN

ADDR registers and from bank ’INIT’ into configuration registers. TABLE 6-3. EEROM RECALL OPERATIONS T he recall of hos t interface configuration regis ters ( a d d re sse s 08- 0Fh , SW H= 1) a re d o n e f ro m t h e bank s elected by 4 INIT jumpers . T able 6-4 defines which bank of configuration regis ters corres ponds to each arrangement of the INIT pins . INIT: MA3-0 Bank Notes 0000 NONE All pins jumpered to ground. This is the bypass condition. 0001 14 0010 13 0011 12 0100 11 0101 10 0110 9 0111 8 1000 7 1001 6 Initial recall defaults: I/O = 280h ROM= disabled at C0000h RAM = 8K at C8000h INT = 0 (no interrupt mapped) LIT = disabled, GPOUT = 0 Configuration Registers (IAR, RAR, BIO, GCR, GCR2) are not recalled after this RESET. 1010 5 1011 4 1100 3 1101 2 1110 1 1111 0 No jumpers are atta ched to pins. TABLE 6-4. CONFIG REGISTER/INIT PINS 83C795 HOST INTERFACE SECTION

T he recal l of L AN addres s regis ters are from the bank s el ected by the 4 -bi t E A fi el d and ar e wr i tten to reg isters a t I/ O lo c a tio ns 08H-0FH, S WH=0. Upon R E S E T, the E A field points to Bank 6. Unless the E E R OM load i s bypas s ed by jumpers (I NI T = 0000), the 83C795 r ecalls either 8 or 16 regis ters . When Config #6 is jumpered, only 8 r egi s ter s are r ecal l ed and the har dwar e defaul ts ar e us ed for the c onfig ura tio n reg iste rs. All o the r initia l confi gur ati ons r es ul t i n 1 6 r egi s ter l oads . T hes e ar e d o ne a uto m a tic a lly . Sinc e EA a lw a ys initia lize s to B ank 6, the initial load from the E E R OM always pulls in the L AN addres s from s ame l ocation. Refer to Fig ure 6-6 for a d ep ic tion of the EEROM r egi s ter l ogi c. A A LAR0 LAR0 GCR2 ALWAYS TO BANK EA ALWAYS FROM BANK EA (EA powers up at ’6’) UPON RESET, RECALL CONFIGURATION REGISTERS FROM THE BANK ACCORDING TO INIT JUMPERS. (No recall from Bank 6.) BANKS OF 8 REGISTERS IN EEROM LAR1 LAR1 GCR2 ERFAL ERFAL LAR2 LAR2 RESET DISABLE ADAPTER LOAD DEFAULT VALUES INTO REGISTERS BYPASS EEROM LOAD? ARE INIT JUMPERS IN POSITION ’6’? RECALL? YES YES NO NO YES NO ENABLE ADAPTER RETRIEVE 8 REGISTERS FROM BANK DESIGNATED BY EA FIELD INTO LAN ADDRESS REGISTERS RETRIEVE CONFIGURATION REGISTERS PIDL, PIDH, IAR, RAR, BIO, GCR FROM BANK INDEXED BY INIT JUMPERS RETRIEVE LAN ADDRESS REGISTERS FROM BANK INDEXED BY EA FIELD IAR IAR LAR3 LAR3 RAR RAR LAR4 LAR4 BIO BIO LAR5 LAR5 GCR GCR BDID BDID CHK CHK B B C C D D E E F F FIGURE 6-6. EEROM REGISTER LOGIC HOST INTERFACE SECTION 83C795

6.7.2.3 Storage Operations

T he S tore oper ation only copies the 8 L AN addr es s r egis ter s to the E E R OM. T his does not depend upon I NI T j umper s etti ngs . T he s tor e oper ati on al ways moves the L AN Addr es s r egi s ter s i nto the bank s elected by the 4-bi t E A field. Ta b le 6-5 d e fine s how ea c h b a nk of 8 EEROM l ocati ons has been al l ocated: BANK ALLOCATION

00 USER PROGRAMMABLE (’SOFT’)

01 CONFIGURATION 1

02 CONFIGURATION 2

03 CONFIGURATION 3

04 CONFIGURATION 4

05 CONFIGURATION 5

06 PERMANENT LAN ADDRESS

07 CONFIGURATION 7

08 CONFIGURATION 8

09 CONFIGURATION 9

TABLE 6-5. EEROM LOCATION ALLOCATION Unlo c king the EERO M Fo r Write O p e ra tio ns T hi s convol uted method i s us ed to protect the E E R OM fr om getti ng accidental l y er as ed by s omeone els e’s s oftware. T he EEROM re gister (EER) looks like this: BIT EER WRITE RESET 7S T O 0 6R C 0 T he s cheme r equir es a s equence of thr ee writes into the E E R OM regis ter to s tart a s tor e operation. T he firs t two writes are required to s et the U NL OCK bit and the thir d wri te executes the s tor e. T he 1s t wr i te mus t be: STORE=0, RECA LL=0, EA4=X, UNLOCK=0, EA[3–0] = Ch. T he 2nd write must be: STORE=0, RECA LL=0, EA4=X, UNLOCK=1, EA[3–0] = Ah. Th e 3 r d w r i t e i s: STORE=1, RECALL=0, UNLOCK=0, EA[4–0] = EEROM bank. Th e v a lu e f o r t h e EA 4- EA 0 f ie ld is t h e EERO M b a n k you intend to store in it. T he wri ting of any other value to the E E R other than the r equir ed ones in the s equence wi ll s et the l ock i ng mechani s m back to i ts i ni ti al condi ti on and a ll three w rites w ill o nc e a g a in b e re q uire d in s equence to unlock the wr ite pr otecti on. I nterveni ng I /O oper ations to other r egi s ter s and r eads of the E E R OM regis ter do not affect the unl ock s equence. 83C795 HOST INTERFACE SECTION

S tor age of U s er-Defined Initial Confi gur ations To d e fine a ny o f the 15 re c a lla b le c o nfig ura tio ns, follow thes e s teps . 1. Build an image of the desired configuration registers in the LAN register bank (SWH=0, addr=8:F). 2. Write the unlock/store sequence with the fi- nal EA field of the EEROM register selecting the desired configuration bank. Do not use Bank 6 because that is reserved for the per- manent device LAN address. Do not use Bank 10 either because that is reserved for driver-related information storage and can- not be recalled as a board configuration. 3. Wait about 200 msec or poll the STORE bit to determine whether that operation has completed. S tor age of U s er-Defined L AN Addr es s T o s tor e a us er - defined L AN addr es s , fol l ow thes e st e p s. 1. Program the desired LAN address, board ID register, and checksum register with desired values. 2. Write the unlock store sequence with the final EA field of EEROM register selecting the Bank 6. 3. Wait about 200 msec or poll the STORE bit to determine that operation has completed. S tor age of U s er-Defined Data I n s ome appl i cati ons , ther e may be other data you need to s ave in the E E R OM, like board type and r evi s i on number s , mul ti cas t fi l ter acceptance mas k , s oftwar e dr i ver par ameter s , and the hos t machi ne type. S ince s ome E E R OM locations may not be needed for configuration or LAN addres s s torage, they can be us ed for this purpos e. 1. Overwrite LAN address, board ID, and checksum registers with the data you need to save. 2. Store the data as if it were a board configu- ration. The driver setup program uses this method to store driver related parameters into EEROM Bank 10. T o recall this us er defined data, program the E A fi el d for the bank and do a R ecal l oper ati on.

6.8 PLUG AND PLAY

T he 83C795 s upports the P lug and P lay IS A Sp e c ific a tio n. T his sp e c ific a tio n p ro vid e s full a nd inte ra c tive c o nfig ura tio n o f a ll PnP-c o m p lia nt b o a rd s in st a lle d o n t h e ISA b u s. Th e e sse n t ia l st e p s in this p roc ess a re the a b ilities to:

• Power up and reset Plug and Play devices
• Send out an initiation key to bring all PnP de- vices into a known state
• Isolate each ISA adapter in turn
• Read the adapter’s resource requirements
• Arbitrate the available resources to all of the PnP cards
• Identify each board and configure its resources
• Activate the cards on the ISA bus
• Locate a suitable driver for the adapter, if nec- essary T o be effective i n thi s new environment, the 83C795 contai ns the l ogi c neces s ar y to pr epar e any boar d o n w hic h it is p la c e d fo r Plug a nd Pla y sta nd a rd s. T hi s l ogi c wi l l be active only when both the P NP E N bi t (E R F AL .0 as r ead fr om E E R OM) i s s et and a 3.6kΩ re sist o r is c o n n e c t e d t o t h e M A [ 6] p in (JM P6) between MA6 and GND. T his s ection contains a brief overview of how Plug and P l ay wor ks , al ong wi th infor mati on s peci fi c to the 83C795’s implementation of P nP. F or more detail on the P lug and P lay proces s and protocol, pleas e refer to the lates t vers ion of the Plug a n d Pla y ISA Sp e c ific a tio n.

6.8.1 Auto-Configuration Ports

T he P l ug and P l ay pr otocol r equir es that al l l ogi c not r el ated to P nP on a P nP boar d not r es pond to a n y ISA b u s a c c e ss u n t il t h e Pn P lo g ic a c t iv a t e s t h e car d, ex cept for devi ces r equir ed for boot (s ee S ection 6.8.5). U ntil this happens , the only acces s to the card is through the P nP auto-configurations por ts . T hes e por ts cons i s t of thr ee 8- bi t I /O re gisters, a s shown in Ta b le 6-6. HOST INTERFACE SECTION 83C795

(LPT2 Status Port) Write-only WRITE_DAT A Fixed at 0A79h (LPT2 Status Port + 0800h) Write-only READ_DATA Relocatable in range 0200h – 03FFh Read-only TABLE 6-6. AUTO-CONFIGURATION PORTS All wr ites to the ADDR E S S por t ar e s tor ed in an addr es s r egi s ter. T he val ue in this regis ter is us ed a s a n ind ex into the interna l 256-b yte ra ng e tha t h o ld s t h e Pn P c o n f ig u ra t io n re g ist e rs. A n y a c c e sse s t o t h e W RITE_D A TA o r REA D _D A TA p o rt will be to the PnP configuration regis ter that is cur r entl y i ndex ed by the addr es s r egi s ter . S ee sec tion 6.8.3 for details on the c onfiguration re g iste rs.

6.8.2 Plug And Play States

The m a in Plu g a nd Pla y st a t e m a c h in e c o n ta in s four s tates and i s i l l us tr ated i n F i gur e 6 -7 . All c a rd s w ill e nte r the Wa itForKe y sta te in r es pons e to either a power -up r es et or the R es et and Wai t for K ey commands . No commands ar e a c tive in this sta te until the Initia tio n Ke y is d e te c te d on the I S A bus . T he WaitF orK ey s tate is the default sta te for Plug a nd Pla y c a rd s d uring norm a l system oper ati on. T he I ni ti ati on K ey pl aces the P l ug and P l ay s tate machi ne i nto the S l eep s tate. T he I nitiation K ey cons is ts of a pr edefi ned s er ies of wr ites to the ADDR E S S port. T he wr ite s equence i s decoded by on-car d l ogi c. I f the pr oper s equence of I /O wri tes is detected, the P l ug and P lay auto-configur ation ports are enabled. T he s equence of writes that ar e expected is : 0x6A,0xB5,0xDA,0xED,0xF6,0xFB,0x7D,0xBE, 0xDF,0x6F,0x37,0x1B,0x0D,0x86,0xC3,0x61, 0xB0,0x58,0x2C,0x16,0x8B,0x45,0xA2,0xD1, 0xE8,0x74,0x3A,0x9D,0xCE,0xE7,0x73,0x39 FIGURE 6-7. PLUG AND PLAY STATE MACHINE 83C795 HOST INTERFACE SECTION

Any writes to the ADDR E S S port that do not match the Initiation K ey s equence will caus e the logic to res et back to the s tart of the Key. While the PnP s tate machine is in the WaitF or K ey s tate, all acces s to the R E AD_DAT A or WR I T E _DAT A ports is di s abl ed. Once the s tate machine i s i n the S l eep s tate, the boar d r es ponds to a WAK E [CS N] command. E ach P nP boar d has a r egi s ter to s tor e a Car d S el ect Number, and this regis ter contains a z ero at p ow e r-up . T he c a rd resp ond s to a WAKE[CS N] command onl y i f the CS N in the command matches the value in the Card S elect Number regis ter. I f the card’s CS N does not match the CS N in the WAK E [CS N], it goes into the s leep s tate. T he card st a y s in t h e sle e p st a t e u n t il a w a ke n e d b y t h e correct WAK E [CS N]. If the CS N is z ero, then the card enters the Is olation s tate, otherwis e it moves into the Configuration s tate.

6.8.2.1 Isolation

A sim p le a lg orithm is used to isola te e a c h Plug a nd P l ay car d. T he i s ol ati on pr otocol r equir es that each car d contai n a uni que number , r efer r ed to as the se ria l id e n t if ie r. T his is a 72-b it num b er c om p ose d of two 32-bit fields and an 8-bit checks um. T he fi rs t field is a vendor identifier. T he s econd can be any val ue - for ex ampl e, a s er i al number or par t of a L AN a d d re ss. Th e n u m b e r is a c c e sse d se ria lly , b it b y b it , by the i s ol ati on l ogi c and i s us ed to di ffer enti ate the adapter s . T he PnP so ftw a re b e g ins the iso la tio n b y se nd ing out a Wa ke[0] c om m a nd . T his w ill c a use a ll PnP cards that have not been is olated to trans ition to the Is olation s tate. I f this is the firs t pas s through the p rotoc ol, the n the softw a re w ill p ic k a n initia l location for the R E AD_DAT A port at this time. T he softw a re then issue s tw o rea d s to the IS OLA T ION r egis ter for each bi t i n the s erial identifier. I f the c urre nt b it is a ’1’, then the PnP b oa rd is e xp ec te d to return 0x55 on the firs t read, and 0xAA on the s econd. I f the cur rent bit is a ’0’, then the P nP l ogic will d rive no thing o n the b us, b ut w ill inste a d obs er ve the bus to s ee if another card i s driving the 0x55, 0xAA pattern. If it does s ee that pattern for the two reads , then that card mus t put its elf back into the S leep s tate. T his ens ures that onl y one P nP card will be in the I s olation s tate at the end of the protocol. T he P nP s oftwar e wi l l r ecogniz e the 0x 55, 0x AA pattern as a ’1’ for that bit pos ition, and any other p a t t e rn a s a ’ 0’ . O nc e a ll 72 b it s h a ve b e e n re a d , the P nP s oftwar e wi ll then verify that the checks um matches the data. If it does , then the s oftware will as s i gn a uni que, non- z er o CS N to the one car d that made i t to the end of the pr otocol . T hi s wi l l caus e that one card to trans is tion to the Configuration s tate. I f the checks um does not match, then the s oftware will move the location of the R E AD_DAT A port, and s tar t the protocol over.

6.8.2.2 Configuration And Activation

T he I s olation protocol ens ur es that only one card can be in the Configuration s tate at a time. T his makes it pos s ible to read out the res ource s tring byte-s erially when in thi s s tate. T hi s is done through the R es our ce_ Data R egi s ter (l ocati on 0 x 04), after p olling the sta tus b it (loc a tion 0x05, b it 0) to ma ke s ure the data in the regis ter is valid. T he P nP s oftware will us e this method to read the entire re so u rc e st rin g f ro m t h e Pn P c a rd . Th is st rin g list s the res ource requirements of the card, along with what the car d i s capabl e of us i ng (s ee s ecti on 6 .8 .5 f o r m o re o n t h e re so u rc e st rin g ) . Th e so f t w a re r epeats thi s pr oces s wi th al l of the P nP car ds i n the s ys tem, and thus obtai ns an i mage of al l of the r es our ce r equir ements i n the s ys tem. T he s oftwar e then arbitr ates the available r es ources to meet the needs of each car d. I f a confi gur ati on can be found, then the as s igned configurati on for each car d wi ll be written to the cards . T he s oftware then activates the c ard by setting the Ac tivate bit (loc ation 0x30, bit 0). On the 83C795, this caus es the s oftware to tr ans fer the appr opr iate s etti ngs i n the P nP c onfigura tion reg isters to the 83C795’ s confi gur ati on r egi s ter s by way of a s hi ft chai n. Once this trans fer is complete, the res t of the logic in the 83C795 b ec omes a c tive.

6.8.3 Configuration Registers

F i gur e 6 - 8 contai ns a map s howi ng al l of the configur ati on r egi s ter s i mpl emented by the 83C795. T his figure als o illus trates the relations hip between the auto-confi gur ati on por ts , the P nP s econdar y addr es s s pace, and the r es our ce s tr i ng. Mos t of the confi gur ati on r egi s ter s can onl y be acces s ed when the P nP s tate machine is in certain s tates . Any unus ed regis ters or bi ts in the P nP re g ist e r sp a c e m u st re t u rn ze ro s w h e n re a d . Th e HOST INTERFACE SECTION 83C795

r egi s ter map s hown in T abl e 6-7 changes when the a d a p te r is run in I/ O -m a p p e d m o d e (se e se c tio n 6.8.6). Also, when the ROM sp a c e is d isa b led (w h e n BIO .4 a n d BIO .5 a re b o t h se t ) , t h e RO M conf i gur ati on r egi s ter s become r ead- onl y and al ways r ead z er os . T here a re 22-b its o f inform a tio n in the PnP confi gur ati on r egi s ter s that ar e us ed for confi gur i ng the 83C795. T hes e bits are s hifted fr om the P nP s ection to the 83C795 s ection whenever the chip is activated. T he s ame bits are s hifted from the 83C 795 se c t io n b a c k to t he Pn P se c tio n a t t he e n d o f the initia l EERO M lo a d (to g e t the d e fa ult va lue s into the P nP regis ters ). S ome of thes e bits may have to be r emapped befor e they ar e s hi fted s o as to match the formats of the two different regis ter Address Function Name READ_DATA PORT ADDRESS Resource String Number Secondary Address 01 0 - 7 02 8 03 9 - N N + 1 N + 2 SERIAL ISOLATION CONFIGURATION CONTROL WAKE (CSN) RESOURCE DATA STATUS CARD SELECT NUMBER (CSN) LOGICAL DEVICE NUMBER ACTIVATE I/O RANGE CHECK RAM BASE ADDRESS [23-16] RAM BASE ADDRESS [15-08] ROM BASE ADDRESS [23-16] RAM RANGE LENGTH [15-08] ROM BASE ADDRESS [15-08] RAM CONTROL RAM RANGE LENGTH [23-16] ROM CONTROL ROM RANGE LENGTH [23-16] ROM RANGE LENGTH [15-08] I/O BASE ADDRESS [15-08] I/O BASE ADDRESS [07-00] IRQ NUMBER IRQ TYPE Serial ID Checksum Resource Data End Tag Checksum Item ADDRESS WRITE_DATA READ_DATA 0x0279 0x0A79 0x0200 - 0x03FF ISA ADDRESS SPACE EEROM CONTENTSPNP SECONDARY ADDRESS SPACE FIGURE 6-8. PLUG AND PLAY CONFIGURATION REGISTERS 83C795 HOST INTERFACE SECTION

Field PnP Bit 795 Bit Mapping Function Name No. Location Location PNP Bits 795 Bits RAM Base 1 0x40.1 RAR.6 direct mapping 2 0x40.0 RAR.3 3 0x41.7 RAR.2 4 0x41.6 RAR.1 5 0x41.5 RAR.0 RAM Size 6 0x44.6 RAR.5 6 7 RAR.5 RAR.4 7 0x44.5 RAR.4 0 0 1 0 0111 1001 1100 ROM Base 8 0x48.1 BIO.6 direct mapping 9 0x48.0 BIO.3 10 0x49.7 BIO.2 11 0x49.6 BIO.1 12 0x49.5 BIO.0 ROM Size 13 0x4C.6 BIO.5 13 14 BIO.5 BIO.4 14 0x4C.5 BIO.4 0 0 1 0 0111 1001 1100 I/O Base 15 0x60.0 IAR.4 direct mapping 16 0x61.7 IAR.3 17 0x61.6 IAR.2 18 0x61.5 IAR.1 IRQ Level Used 20 0x70.2 GCR.3 0 0 0 0 0 0 0 21 0x70.1 GCR.2 0 0 1 0 0 0 1 22 0x70.0 0 0 1 1 0 1 0 0101011 0111100 1001001 1010101 1011110 1111111 TABLE 6-7. PLUG AND PLAY BIT REMAPPING HOST INTERFACE SECTION 83C795

s ets . T hes e bi ts ar e lis ted in T able 6-7, along with any neces s ar y mappi ng i nfor mati on.

6.8.4 Resource String

Th e Plu g a n d Pla y re so u rc e st rin g is st o re d in E E R OM and can be acces s ed ei ther bi twi s e thr ough the S er i al I s ol ati on r egi s ter or byte- s er i al l y through the R es ource Data regis ter. T his s tring sh o u ld c o m p le t e ly d e sc rib e t h e re so u rc e n e e d s a nd o p tio ns for a 83C795 b a sed c a rd . A s ample vers ion of this s tructure is lis ted in T able 6-8. Once the 83C795 has been activated by the Pn P lo g ic , t h e re so u rc e st rin g is a c c e sse d in t h e Byte Value Swapped Value Name Description 00 4D B2 Vendor_ID.0 Serial Identifier 01 A3 C5 Vendor_ID.1 02 84 21 Vendor_ID.2 03 16 68 Vendor_ID.3 04 C0 03 LAN_Addr.0 05 01 80 LAN_Addr.1 06 23 C4 LAN_Addr.2 07 45 A2 LAN_Addr.3 08 4C 32 Checksum 09 0A 50 PnP_Version_Type Plug and Play Version Descriptor 0A 10 08 PnP_Version 0B 10 08 Vendor_Version 0C 82 41 ANSI_Identifier_Type ANSI Descriptor for Card 0D 0D 30 Descriptor_Length [7-0] 0E 00 00 Descriptor_Length [15-8] 0F 53 CA ANSI Character – S 10 4D B2 ANSI Character – M 11 43 C2 ANSI Character – C

12 FF FF ANSI Character –

13 38 1C ANSI Character – 8 14 34 2C ANSI Character – 4 15 31 8C ANSI Character – 1 16 36 6C ANSI Character – 6

17 FF FF ANSI Character –

18 43 C2 ANSI Character – C 19 61 86 ANSI Character – a 1A 72 4E ANSI Character – r 1B 64 26 ANSI Character – d TABLE 6-8. PLUG AND PLAY RESOURCE STRING STRUCTURE 83C795 HOST INTERFACE SECTION

1C 15 A8 Logical_Device_Type Logical Device Descriptor 1D 4D B2 Logical_Device_ID.0 1E A3 C5 Logical_Device_ID.1 1F 84 21 Logical_Device_ID.2 20 16 68 Logical_Device_ID.3 21 02 40 Logical_Device_Flags (Non-boot, does I/O range checking) 22 23 C4 Interrupt_Descriptor_Type Interrupt Format Descriptor

23 A8 15 IRQ_Mask [7-0] – Interrupts supported: 3, 5, 7

24 8E 71 IRQ_Mask [15-8] – Interrupts supported: 9, 10, 11, 15 25 16 68 IRQ_Information 26 47 E2 I/O_Port_Descriptor_Type I/O Port Descriptor 27 00 00 I/O_Port_Info 28 00 00 I/O_Min_Base_Addr [7-0] 29 02 40 I/O_Min_Base_Addr [15-8] – Minimum Base Address = 0x0200 2A E0 07 I/O_Max_Base_Addr [7-0] 2B 03 C0 I/O_Max_Base_Addr [15-8] – Maximum Base Address = 0x03E0 2C 20 04 I/O_Base_Alignment – Alignment = 32-byte blocks 2D 20 04 I/O_Range_Length – Length = 32 bytes 2E 81 18 Memory_Range_Descriptor_Type Memory Range Descriptor #1 2F 09 90 Descriptor_Length [7-0] (two would be required for cards using 30 00 00 Descriptor_Length [15-8] both ROM and shared RAM) 31 11 88 Memory_Range_Information – 8-/16-bit, writable 32 00 00 Mem1_Min_Base_Addr [15-8] 33 0C 30 Mem1_Min_Base_Addr [23-16] – Minimum Base Address = 0x0C0000

34 E0 07 Mem1_Max_Base_Addr [15-8]

35 0F F0 Mem1_Max_Base_Addr [23-16] – Maximum Base Address = 0x0FE000 36 00 00 Mem1_Base_Alignment [7-0] 37 40 02 Mem1_Base_Alignment [15-8] – Alignment = 16-kbyte blocks 38 40 02 Mem1_Range_Length [7-0] 39 00 00 Mem1_Range_Length [15-8] – Length = 16 kbytes 3A 79 9E End_Tag_Type End Tag 3B 0E 70 Checksum – Covers all data bytes TABLE 6-8. PLUG AND PLAY RESOURCE STRING STRUCTURE (cont.) HOST INTERFACE SECTION 83C795

s ame manner (for both r eads and wr i tes ) as the r es t o f t h e EERO M c o n t e n t s, e xc e p t t h a t EA [ 4 ] ( EER. 5) m u st b e se t .

6.8.5 Configuring As A Boot Card

Many L AN adapter s ar e confi gur ed as boot car ds . S ince thes e cards mus t be vis ible to the B I OS at boot time, they may have to be activated before the P nP s oftware has had a chance to run. T he PNPBOOT bit (IAR.0) was imp lemented to do this. When this bit is read out of E E R OM as s et, the chip becomes active on the IS A bus . T his bit als o forces bit 0 of the I AR regis ter to ’1’ which identifies the car d as a boot car d to the P nP s oftwar e.

6.8.6 Configuring With An I/O-Mapped Pipe

When the 83C795 is c onfigured with a n I /O-mapped pi pe ins tead of s har ed memor y, the boar d wi l l not us e any memor y addr es s s pace for the buffer R AM. T her efor e, the P nP R AM control re g ist e rs ( u su a lly lo c a t io n s 4 0h –4 4h ) a re n o t n e c e ssa ry . If t h is c a rd re q u ire s a RO M , t h e n t h e des cr i ptor for the R OM memor y wi ndow wi l l be the first one in the reso urc e string . T his req uires tha t the PnP RO M c o ntro l re g iste rs b e re -m a p p e d fro m 48h-4Ch to 40h-44h. T his is acc omplished by s etting the P NPIOP bit (GCR 2.0). T his bit mus t be r e a d o u t o f EER O M b e c a u s e i t m u s t h a v e t h e correct value before the chip is activated by the P nP logic. S etting this bit als o caus es locations 48h- 4 Ch to r ead as z er oes .

6.8.7 Buffer Memory Limitations

Nor mal ly, buffer memor y can be l ocated above the 1MB DOS lim it b y se tting the b uffer a d d ress line (L A23-L A20) decoder to match at ’F ’ rather than zero (done by s etting the HR AM bit, R AR .7). T his is no t sup p o rted b y the PnP ha rd w a re a s i mpl emented in the 83C795 .

6.9 EXTERNAL POWER SUPPLY CONTROL

T he GP OU T pi n can be us ed to contr ol an ex ter nal p o w e r su p p ly su p p o rt in g a 1 0Ba se 2 M A U c irc u it . T his pin can be us ed to s ource either a s imple DC contr ol s i gnal or a pul s e tr ai n. T he DC s i gnal i s us ed to enabl e or di s abl e a contr ol l abl e power s uppl y. Note The DC signal’s polarity on the 83C795 is the opposite of the 83C790’s. T he puls e train is des igned to be the s witching contr ol s i gnal for a s peci fi c des i gn of s wi tchi ng power s uppl y. T he pul s e tr ai n i ncl udes a s tar t- up s equence as well as a choice of two normal oper ati ng pul s e tr ai ns . B efor e the GP OU T pi n can emi t a pul s e tr ai n, i ns tal l the INIT 5 jumper to pull down the MA5 pin. T he I NI T 4 j umper deter mines whi ch of the two pul s e trains is emitted. T he puls e train is turned on or off us ing the GCR .GP OU T bit (s ee page 21 for detail s ). T he pul s e tr ai n i s a 312 K H z s i gnal wi th 1 /8 duty c yc le for the first 1024 c loc ks after GPOUT is enabl ed. T hi s i s fol l owed by 1/4 duty cycl e for 1K cl ocks , 3 /8 duty cycl e for 1 K cl ock s , and 1 /2 (5 0% ) duty cycl e ther eafter . Ins tallation of the INI T 4 jumper caus es the final duty cyc le to be 17/ 32 (53% ) ins tead of 1/ 2. 83C795 HOST INTERFACE SECTION

7.0 LAN CONTROLLER OVERVIEW

T he L AN Contr ol l er cons i s ts of 3 bas i c bl ock s : DMA c ontroller, tra nsmitter, a nd re c eiver. Ea c h of thes e blocks cons is ts of s ub-s ections . T he DMA contr ol l er i ncl udes a memor y i nter face uni t, contr ol r egi s ter s , and a mi cr o- coded s equencer that handles data buffering for the trans mitter and r ecei ver s ecti ons . T he trans mitter block has a MAC (Media Acces s C o n t ro l) se c t io n t h a t p e rf o rm s t h e IEEE 802.3 tr ans mi s s i on pr otocol and a P hys i cal L ayer I nter face (P L I ) s ecti on that does Manches ter encodi ng and dr i ves the cabl es . T he r ecei ver bl ock has a MAC s ecti on that per for ms the 80 2 .3 r ecepti on pr otocol and a P L I s ecti on that converts line level differential s i gnals to internal logic s ignals while doing clock r ecover y, and manches ter decoding.

7.1 DMA CONTROLLER

T he DMA controller handles data movement between the F I F Os and buffer memor y for tr ans mi s s i on and r ecepti on of fr ames . Al l DMA data tra ffic is 8-b it w id e . One DMA c ontrolle r is sha re d between the trans mit and receive functions . T he contr ol l er gr oups memor y tr ans fer s i nto bur s ts of 8 bytes for both tr ans mi t and r ecei ve functi ons . T he DMA contr ol l er al ways acces s es memor y by doi ng t w o sin g le -b y t e t ra n sf e rs in a ro w . Th e b u rst size and i ts tr i gger l evel s ar e s hown i n T abl e 7 -1 . BURST TRIGGER LEVEL RX TX 8 bytes R ≥ 8T ≤ 8 TABLE 7-1. DMA BURST LENGTH FIELD T hough internally 8 bits wide, the DMA controller g e n e ra t e s 16 -b it a d d re sse s. It a c c e sse s m e m o ry in 2 cycl es of the chi p’s mas ter cl ock (per byte). When conducti ng a l oop- back tes t, thi s contr ol l er c a n ha nd le full-d up lex b uffering of full leng th fra me s at s erial data rates up to 10 Mbps . It does not handle the general cas e of independent (concurrent) tr ans mi t and r ecepti on pr oces s es .

7.1.1 Assembly and Disassembly Latches

T hes e l atches are us ed to match up the internal 8-bit data path with the external data bus . As s embly latches build a 16-bit word out of two 8-bit wor ds or s upplies the cons ecutive bytes when inter faci ng to a n 8-b it b u s. D isa sse m b ly la t c h e s p e rf o rm t h e i nver s e functi on. T hes e ar e us ed dur i ng DMA oper ati ons and ar e bypas s ed when the chi p’s r egis ter s ar e wri tten or r ead.

7.1.2 Memory Interface Unit

T he memor y inter face uni t (MI U ) tr ans fer s data from buffer memory to the internal dis as s embly latches and from the internal as s embly latches to buffer memor y. I t i s a par t of the DMA contr ol l er. T hi s bl ock gener ates the memor y s tr obes (RA M O E, RA M W R) w h e n t h e D M A is a c c e ssin g the buffer R AM. M IU o p e ra tio n is initia te d b y the DM A c o ntro lle r after it s ets up the addres s for the trans fer and puts outgoi ng data (r ecei ver functi ons ) i nto the as s embly latches . T he MIU then performs the m e m o ry t ra n sf e r in t h e n e xt t im e slo t a ssig n e d t o the DMA. Th e b a s i c D M A c y c l e s a r e i n Fi g u r e 7 - 1 . R e a l detai l s can be found i n the AC ti mi ng s ecti on. LAN CONTROLLER OVERVIEW 83C795

FIGURE 7-1. BASIC DMA CYCLES 83C795 LAN CONTROLLER OVERVIEW

7.1.3 LAN Controller Internal Bus Arbitration

T his portion of the 83C795 is used to resolve confl i cts that can occur on data bus es us ed by both the DMA controller and hos t acces s es to the inter nal regis ters of the L AN Contr ol ler s ection. T he L AN bus ar bi tr ati on s ecti on obs er ves a L AN s elect (CS ) s ignal derived from the memory bus ar bi ter and pr ovi des a ’r eady’ hands hake s i gnal i n re turn. It a lso c o ntro ls inte rna l d a ta flo w w ithin the LA N c o n t ro lle r a n d h o ld s o f f t h e DM A m ic ro c o n t ro lle r d u rin g I/ O a c c e sse s.

7.1.4 DMA Microcontroller

T he cor e of the DMA contr ol l er i s a R OM-bas ed mi cr ocontr ol l er whi ch i ncl udes an addr es s counter for the memor y pos i ti on, compar ator s for inter nal a d d re ss c o m p a riso n s, so m e d e c re m e n t e rs f o r lo o p c ontrol, reg isters for stora g e of op era ting va ria b les, and I/O control s ignals that attach to many circuits w ithin the LAN c o ntro lle r se c tio n o f the c hip . I n additi on to the microcode as s ociated wi th nor mal tr ans mi t, r eceive and loopback pr oces s es , there is additional code to facilitate tes ting of the L AN c ontroller.

7.1.5 How to Access Registers

A r eques t for L AN regis ter acces s i s made when the hos t pr es ents an I /O addr es s that decodes to a register w ithin the up p er 16 b ytes of the 83C795’ s I /O bl ock and a val i d IO R o r IO W is p re se nte d . T he c hip w ill resp ond w ith a n I/ O Cha nnel Not R eady s i gnal (I OR DY ) whi l e i nter nal ar bi tr ati on proc eeds. It remains NOT IORDY until the d esired tr ans fer i s r eady to be compl eted. A c c e ss t o t h e re g ist e rs o f t h e LA N c o n t ro lle r se c t io n is a llowed a fter a ny ong oing DMA b urst is completed. At that time, the DMA may wis h to become acti ve agai n i n r es pons e to new needs , but the ar bi tr ati on l ogi c wi l l al l ow hos t acces s to the chi p until the I /O s trobe becomes fals e. T he ar bi ter generates the IOR DY s ignal as an indication to the hos t that the i nter nal bus has been made avai l abl e and that the reques ted I/O acces s has been made. B etween acces s es to the chip, I OR DY is undri ven. T o r ead fr om a r egi s ter, an I /O addr es s i s pl aced on the S Axx p ins a nd IO R is a sse rt e d b y t h e h o st ( m u st be as s er ted after a val i d addr es s ) and r ecogni z ed by the bus ar bi tr ati on l ogi c whi ch enabl es data fl ow fr om the addr es s ed regis ter to the D00-D07 pins . R egi s ter r eads ar e al ways done thr ough the D00-D07 p ins, exc ep t for 16-b it I/ O p ip e a c c esses. T he D08-D15 pins will be tri-stated during read op e ra tions. IORDY w ill ind ic a te w he n the ho st ma y s ample data and ter minate the read oper ation. T o wr i te to a r egi s ter, an I /O addr es s i s pl aced on the S Axx pins and I OW i s as s er ted by the hos t and r ecogni z ed by the bus ar bi ter. Addr es s mus t become s tabl e befor e I OW is as s er ted. When the bus is fr ee for the trans fer, I OR DY is as s er ted. Data is latched into an intermediate trans fer latch with the trailing edge of IOW and then trans ferred to the des ti nati on r egi s ter two cl ock s l ater. T his delayed wri te operation r equir es an internal re c o v e ry p e rio d b e t w e e n h o st a c c e sse s t o r egis ter s . T hi s per iod i s documented in the detailed ti mi ng di agr ams .

7.1.6 Memory Interface

T he interna l DMA c ontro ller m oves p a c ke ts between buffer memor y and the F I F Os . LAN CONTROLLER OVERVIEW 83C795

7.2 FIFOS

T her e are two F I F O s tr uctur es us ed to expedite the tr ans fer pr oces s between the DMA proces s or and the T r ans mit/R eceive units . E ach F I F O i s 16-bytes deep. As s ociated with each F I F O ar e up/down counters that keep track of how full each F IF O is . T he nor mal l oadi ng s our ce for each F I F O r ecei ves an over flow indi cati on when it occur s and the nor mal unl oadi ng des ti nati on has an empty s i gnal to prevent drawing of nonexis tent data.

7.3 RECEIVER NETWORK INTERFACE

(PHY-TO-MAC) T his sec tion of the 83C795 has squelc hed , differential receivers for the AUI and T WP interfaces . T he inputs from thes e interfaces are multiplexed together with a feedback path to a common phas e-l ock ed- l oop ci r cui t for cl ock r ecover y and data decodi ng. F i gur e 7 -2 s hows the AU I and T wi s ted-P air i nter face r el ati ons hi p. FIGURE 7-2. AUI/TWISTED-PAIR INTERFACE 83C795 LAN CONTROLLER OVERVIEW

7.3.1 AUI Differential Receiver

With the standard 78Ω tr ans ceiver AU I cable, the di ffer enti al input mus t be external ly ter minated. T his r equi r ement may be s ati s fi ed by connecti ng two 39Ω re sist o rs in se rie s w it h o n e o p t io n a l c o m m o n m o d e bypas s capaci tor. T o pr event nois e at the AU I R X +/- input from fal s ely triggering the decoder, a s quelch circuit rejects sig n a ls w it h p ulse w id t h s le ss t h a n 25 n se c (nega tive go ing), or w ith levels less tha n 175 mV. When the input exceeds the s quel ch l evels , the a na lo g p ha se -lo c ke d lo o p lo c ks into the inc o m ing s i gnal and Manches ter decodi ng takes pl ace. T he i nter nal car r i er s ens e s i gnal i s acti vated and the r ecei ve data (R X D) and the r ecei ve cl ock (R X C) become avai l abl e wi thi n s even bi t ti mes . At the end of a fr ame when nor mal mi d-bi t tr ans i ti on on the d ifferentia l inp ut c ea ses, c a rrier se nse is deactivated. T he receive clock remains active for an addi ti onal 5 bi t ti mes .

7.3.2 Twisted-Pair Differential Receiver

T he r ecei ved s i gnal fr om the uns hi el ded cabl e may b e n o isy , so m in im u m v o lt a g e a n d t im in g lim it s m u st be met before the r eceiver logi c is enabled. A ’S mar t S quel ch’ di gi tal noi s e fi l ter i s us ed i n addi ti on to the anal og s quel ch ci r cui t i n the r ecei ver. If the inp ut p ola rity is reversed it will b e automatically detected and corrected. When p ola rity is no rm a l, the PLED (MANCH.3) b it w ill b e se t . T he phas e-l ock ed l oop and Manches ter decoder are the s ame cir cuits us ed by the AU I r eceiver.

7.3.2.1 Extended Length For Twisted-Pair

S etting the XL E NGT H bit (GCR .7) increas es the sq uelc h le ve ls used b y the T P rec eiver. T his enables the adapter to be connected to a cable that is lo nger tha n sp ec ified b y the 802.3 sta nd a rd .

7.3.3 Manchester Decoder

Decodi ng i s accompl i s hed by an anal og phas e-locked loop that s eparates the Manches ter-encoded data s tream into clock s i gnal s and NR Z data. T hi s l oop can tol er ate up to 20 ns ec of jitter on each s ignal edge, exceeding the 802.3 requi rements .

7.3.4 Carrier Sense

T he AUI interfa c e d eterm ines c a rrier p resenc e b y r equir ing the di ffer ential r eceived s ignal to exceed the negative s quelch level for a minimal period, nom ina lly 25 nsec . T he twisted -p a ir interfa c e r equir es that the pos i ti ve and negati ve s quel ch levels be exceeded s ever al times for a per iod of at lea st 20 nsec . When op era ting in loop b a c k mod e, interna l tra nsmit enable s ignal is returned to the MAC as the carrier ind ic a tion.

7.3.5 Collision Detect

Collis ion detection for the AUI interface is indicated when the differential s ignal on the CD input pai r exceeds the negati ve s quelch thres hol d. Collis i on detection for the twis ted-pair interface is indicated when there i s car ri er s ens ed while the tr ans mitter is a c tive.

7.3.6 Loopback Mode

When the L AN controller is programmed to operate in loop b a c k m od e 2, it p ro vid es a sig na l to the line receiver s ection which caus es the Manches ter decoder to derive its input from the encoded trans mit data ins tead of the differential receivers of AU I and T P i nter faces . T he AU I and T P i nter faces a re ig no re d w hile the lo o p b a c k ind ic a tio n is a c tive . LAN CONTROLLER OVERVIEW 83C795

7.4 MAC RECEIVER

7.4.1 Basic Functions

T he 83C795’s rec eiver sec tion proc esses a serial s tr eam of NR Z data. T he s tar t of the fr ame i s i denti fi ed, des ti nati on addr es s i s check ed agai ns t t h e st a t io n a d d re ss, re c o g n ize d f ra m e s a re tr ans fer r ed to memor y and checked for val i d formation. E rror conditions are reported.

7.4.2 Interface to the MAC Receiver

T he s erial interface to the MAC receiver s ection is ha nd le d b y fo ur sig na ls: C a rrie r Se nse (XC RS), Collision Detect (XCOL), R eceive Data (XR XD), and R eceive Cl ock (X R X C). T he group may come fr om one of three s our ces :

• internally from the Manchester Decoder
• direct from the pins
• internally from the transmit section. All s ources are treated equally. S election of s ource i s done by pr ogr ammi ng confi gur ati on r egi s ter s . R efer to the T CON and MANDIS R egis ters for furthe r info rm a tio n. Note These signals are multiplexed with the IRQ pins and are used for testing pur- poses only.

7.4.3 Loopback Paths

Th e 8 3C 795 h a s 3 lo o p b a c k m o d e s. Mode 1 pr ovi des the path between r ecei ver and trans mitter ins ide the L AN controller. In this mode, NR Z data from the trans mitter connects to the r ecei ver ’s R X D i nput, bypas s i ng Manches ter encoder /decoder. X R X C i s gener ated i nter nal l y for thi s mode by di vi di ng 20 Mhz cl ock by two. T he mi ni mum fr ame l ength for mode 1 l oopback i s 25 bytes . Mode 2 connects tr ans mi t and r ecei ve data thr ough the Manches ter encoder /decoder. T he s erial data i s wr apped ar ound j us t i ns i de the devi ce pi ns wi th ne ithe r AUI no r T P inte rfa c e s a c tua lly d riving the outs i de wor l d. T he mi ni mum fr ame l ength for mode 2 loop b a c k is 25 b ytes. M o d e 3 h a s t ra n sm it t e r a n d re c e iv e r p in s a c t iv e wi th l oopback pi ns i nacti ve. T he DMA contr ol l er wi l l run its sp ec ia l lo op b a c k c od e to a llow rec e p tio n of the o utg o ing tra nsm issio n if it is e c ho e d b a c k. In this mode, the DMA can handle delay of the echo pr ovided that the frame’s l ength exceeds echo d ela y b y a t lea st 200 b it tim es (25 b ytes). When run in this mod e, the b oa rd b eing tested should b e c onnec ted to a n 802.3-c omp lia nt c a b le. T ha t c a b le may or may not have other 802.3 nodes attached. Note Caution is advised when running this test on a live network or when other nodes on the test cable could send a frame to the node under test. Reception of a frame destined to the loopback node could confuse the results of the loopback test as the node will be able to receive the incoming frame.

7.4.4 Receive Deserialization

R ecei ve des er i al i z er i s acti vated by car r i er s ens e. B yte alignment is determined by a s ynch circuit w hic h d e te c ts the S ta rt-o f-Fra m e Delimiter (S FD) when it sees the serial sequenc e ’ 10101011’ a fter the s tart of carrier s ens e. T his pattern marks the fi r s t octet boundar y and deter mi nes byte al i gnment for the entire frame. Inc oming RXD b its a re c lo c ked into a n 8 b it wid e seria l-to-p a ra lle l shift reg ister. T he b its a re rec eive d in o rd e r f ro m le a st sig n if ic a n t t o m o st sig n if ic a n t within e a c h b yte . Whe n a n o c tet is c o m p le te , parallel data is l oaded into the r eceiver F I F O. When Carr ier is los t, the frame is cons i der ed to have termina ted ; a nd a ll rem a ining seria l d a ta a re dr opped. S er i al data i s pas s ed to the CR C check er whi ch i s i ni ti al i z ed upon r ecogni ti on of the S F D. T his pr oces s or di nar i l y di s car ds al l bi ts that pr ecede the S F D pattern wi thout pr ejudi cing r ecepti on of the fr ame. S ome ex cepti ons can be made to this proces s to improve the robus tnes s of the r eceiver. T hey are dis cus s ed below. T her e i s a s el ectabl e mode (us i ng the R CON.R CA b it) d uring the rec eiver op era tio n w hic h a d d s robus tnes s by monitoring the XCOL s ignal continuous ly throughout reception, s tarting after the S tart-of-F rame delimiter. I f collis ion is detected, r ecepti on of the fr ame i s abor ted. 83C795 LAN CONTROLLER OVERVIEW

Op era ting in ALT EGO mod e enga g es a sec ond impr ovement to the r eception proces s . T he r ecei ver check s for cor r upti on of the pr eambl e and ter mi nates r ecepti on of any fr ame whi ch has cons ecutive ’0’ bits . All valid preambles have an alternating ’10’ pattern followed by the S tart-of-F rame delimiter (’11’). T he above is checked i mmedi atel y on the as s er ti on of the inte rna l c a rrie r se nse w itho ut a ny g ra c e p e rio d s. Neither of thes e caus es for abor t forces logic to s et RXE.

7.4.5 CRC Checker

T he R eceiver computes the CR C of an incomi ng fra me seria lly. CRC c omp uta tion inc lud es a d d ress, data, and CR C fr ame fields . I t excludes pr eamble and S F D. Computation s tops after recepti on of las t w ho le o c te t fo llo w ing lo ss o f c a rrie r. T he fina l va lue of the CR C mus t be " C704DD7B " for the packet to be val i dated. T he CR C pol ynomial us ed is AU T ODI N I I : X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1. I f the r eceived frame’s CR C does not check out, a CR C err or is indicated i n the S tatus R egi s ter and the C RC Erro r Co unte r is inc re m e nte d . Fra m e re c e p tio n w ill term ina te unle ss the R ecei ve- wi th-E r r or s mode i s enabl ed. I n addi ti on, if the number of bits received in the las t octet (when the carrier is terminated) is greater than one and les s than 8 (a full octet), and the CR C check for all complete octets fails , the frame is als o labeled as an ’al i gnment er r or ’ and an er r or fl ag i s s et i n the St a t u s Re g ist e r; if t h is o c c u rs, t h e A lig n m e n t Erro r Counter will be incremented.

7.4.6 Address Recognition Logic

De stina tio n a d d resse s tha t a re ’ ind ivid ua l’ a re compar ed to a 6-byte s tation addres s s tored in regis ters. If all bits matc h or if the PR OMIS CUOUS mode is enabled, the frame is r eceived. A s naps hot is taken of the par tially-computed CR C as the end of the des ti nati on field pas s es through the CR C check er . I f the addr es s has the ’gr oup’ or ’mul ti cas t’ bi t s et, 6 bi ts of thi s check s um ar e us ed as a has hed index to a 64-bit Multicas t F ilter table. I f reception of multi cas t frames has been enabl ed and if the 6-bit partial CR C points to a bit in the table that has been turned on, the multicas t frame wi ll be r ecogni z ed. B roadcas t fr ames ar e r eceived when the B roadcas t E nable bit (R CON.BR OAD) is active or when the has hed bit in the Mul ticas t F i lter table has been s et. T o caus e promi s cuous reception of multi cas t and broadcas t frames , the entir e Gr oup Addres s table s houl d be tur ned on and r ecepti on of mul ti cas t fr ames enabl ed. I f the addr es s i s r ej ected, the fr ame i s al s o r ej ected and none of the frame is trans ported to the buffer memor y. I f the addres s is recogniz ed, bufferi ng of the fr ame begins .

7.4.7 Received Byte Counter and Early

T his cir cui t counts the number of bytes in each completed frame and filters out runt frames (les s than 64 bytes ) unles s the runt filter is defeated by s etting the Accept R unt bit in the R eceive Configuration R egis ter (R CON.R U NT S ). T he E ar ly R eceive War ning (E R W) i nterr upt is gener ated when the recei ved byte count equals or exceeds a value s pecified in the E ar ly R ecei ve War ning Count R egi s ter (E R WCNT ). T he value of E R WCNT i s l eft-s hi fted four bi ts (mul ti pl i ed by 1 6 ) before it is compared to the receive byte count. T he value is 8 bits wide, allowing the E R W thres hold to be s et between 0 and 4K with a res olution of 16 bytes . T he E R W interrupt is only generated if an active re c ep tion is in p rog ress. Onc e a n ea rly rec e ive interrupt has been s et, it may be cleared and will not be s et agai n unti l another pack et ex ceeds the E R W thr es hold or the E R WCNT R egis ter i s wr itten to. Writing a value to E R WCNT that is les s than the cur r ent r ecei ve byte count (whi l e r ecepti on i s i n progres s ) will automatically s et the E R W interrupt. T he E R W interrupt is mapped to bit 6 in the I nterrupt S tatus R egis ter (I NS T AT ). T he E R W interr upt is ena b led or d isa b led like a ll o ther interrup ts b y the cor r es pondi ng bi t i n the I nter r upt Mas k R egi s ter (INT MAS K). LAN CONTROLLER OVERVIEW 83C795

7.4.7.1 Early Receive Failure Detection

Dur i ng the r ecepti on of a fr ame wi th ear ly r ecei ve enabled, it is pos s ible for the hos t to read frame data from the buffer R AM before the DMA writes it if the ea rly rec e ive threshold is set too low . T he fa ilure detection logic enables the hos t to detect if this has happened; i f s o, i t goes back and r ecopi es the correct data. T he lo g ic re q uire d fo r this is sim ila r to the lo g ic use d fo r e a rly tra nsm it und e rrun d e te c tio n. T he lo c a l memor y addr es s i s l atched ever y ti me the DMA writes to the buffer R AM. When the memory cache or I /O pipe reads data from the R AM, the local memory addres s is compared to the las t latched addr es s . (T he l eas t s i gni fi cant 2 bi ts ar e not compar ed s o the detecti on mechani s m has a gr anul ar i ty of 4 bytes ). T hi s compar i s on i s tur ned off when the DMA fi ni s hes pl acing the frame in s har ed memory. I f the two addr es s es ar e equal, E R F B IT (U B R CV.1) is s et and the latched addres s i s s tored in the E R F A r egis ter s (E R F AL and E R F AH). When the hos t reads that E R F B IT is s et, it s hould begin recopying data from a point at or b e f o re ERFA a n d re se t ERFBIT. Note The value in ERFA contains the local memory address where the failure oc- curred, not the host address. T he E R F A regis ters remain s et until the hos t clears t h e ERFBIT. Fo r m o re o n ERFBIT, se e p a g e 40. Fo r m o re o n the ERFA re g iste rs, se e p a g e 22.

7.4.8 Receive Protocol FSM

T he R eceive P rotocol F S M controls r eception of fr ames , checks for err or s , and pos ts s tatus to a reg iste r a fte r c om p letio n of ea c h rec ep tion. It oper ates counter s for the number of bytes in the fr ame and for three types of er ror conditions . T he r eceiver protocol F S M can be confi gur ed via a r egi s ter, al l owing s ome fl ex i bi l i ty as to whi ch fr ames are to be r eceived. T he r ecei ved byte counter i s 1 6 -bi ts wi de. T he thr ee err or counters are each 8-bits wide. T hes e wi ll count fr om z er o up to 255, where they s tick to avoid w ra p -a ro und . T he e rro r c o unte rs a re se lf-c le a ring when r ead and they can gener ate a s har ed i nter r upt condition when any of them have counted up to 192. T he R eceive P rotocol F S M inter faces with the DMA s ection to c oordinate buffering of received frames . It info rm s the DM A o f a b o rt c o nd itio ns, sho uld the y o c c ur a s w e ll a s va lid c o m p le tio ns o f re c e ive d fr ames . After the fr ame has been buffer ed to memor y by the DMA, the DMA s ecti on copi es the R ecei ver S tatus R egis ter (R S T AT ) and the number of bytes r eceived from the receiver into the header of the buffer. T he rec e ive r FIFO is m o nito re d fo r o ve rflo w conditions and if one occurs , frame reception is terminated and an error flag is pos ted to the S tatus Re g ist e r . T he Re c e ive r se c tio n is e na b le d b y se tting the Sta rt and cl ear ing the S top bits in the Command R egis ter - CMD.S TA a nd CMD.ST P. Until ena b le d , the r ecei ver s ecti on i gnor es i ncomi ng fr ames . Once the S ta rt b it ha s b een set, it rema ins true interna lly until the S top b it is set or the c hip is rese t. Clea ring the S tar t bi t in Command R egis ter does not caus e the r ecei ver s ecti on to s top oper ati ng. If the Sto p b it is se t w hile re c e ive r is o p e ra tio na l, it will complete the handling of any ongoing frame and then go to a s oft res et condition, ignoring new incoming frames . T he r eceiver wi ll clear the R S T AT R egis ter when the curr ent frame is finis hed and pos ted. When both trans mitter and receiver s ections are s topped, the R S T bit in the i nter rupt sta tus reg ister w ill b e set. It should b e noted tha t the DMA c ontroller ma y rem a in a c tive w hile S top is set. T he pr otocol machine can be configured to operate in a "Monitor Mod e" whic h c hec ks va lid ity of inc oming fra mes a nd ma inta ins error sta tistic s for them but does not s tore them in memory. E ach time an acceptabl e fr ame i s compl eted whi l e i n thi s mode, the Mi s s ed P ack et Counter (MP CNT ) i s incremented. T his counter is not incr emented by FIFO o v e rf lo w s.

7.4.9 Reception Process

IEEE 802.3 p a c ke ts c onsist o f these field s a nd a re therefor e pr oces s ed i n this order:

• Preamble field
• SFD field
• DA field
• SA field 83C795 LAN CONTROLLER OVERVIEW

• Data field
• CRC field E ach of thes e fields is explained i n the followi ng se c t io n s.

7.4.9.1 Start of Frame

T he pr eambl e field is us ed to train the Manches ter d e c o d e r a nd to d e te c t c a rrie r. If c a rrie r is d e te c te d , preamble pas s es thr ough the receive des er ializ er w hic h d isc a rd s it w hile se a rc hing fo r the S tar t-of-F r ame Del imiter (S F D) s ymbol . On detec ting a good S F D, a VALID_F R AME s ignal is as s er ted and the r ecei ve F I F O i s cl ear ed to accept the r eceived frame. T he r eceive F I F O is loaded by the des erializ er with octets (bytes ) s tarting with the firs t bit after S F D. Whi l e the des ti nati on addr es s (DA fi el d) i s bei ng check ed for r ecogni ti on, the r ecei ve D MA i s di s abl ed. I f the addr es s i s r ecogniz ed, the DMA i s enabled and trans fer to memory begins when the F IF O fills to the programmed burs t level. If the fr ame’s addres s i s not recogniz ed, the receive unit c lea rs out the FIFO, stop s filling it, a nd wa its for the st a rt o f t h e n e xt f ra m e . T he s our ce addr es s and data fi el ds ar e pas s ed to buffer memory. In s ome pr otocols , the fi rs t 2 bytes of the data field denote a frame length. T hes e bytes a re not interp reted b y the S MC795. T hey a re tr eated as or di nar y data.

7.4.9.2 End of Frame

If the re is a lo ss o f c a rrie r se nse , 3 d rib b le c lo c ks (receive clocks that occur after the los s of carrier s ens e) are needed to ens ur e the s ynchroniz ations of all line s ignals to the receiver circuits . When us ing the internal Manches ter decoder (either 10B AS E -T or AU I interfaces ), this decoder automatically su p p lie s su f f ic ie n t d rib b le c lo c ks t o t h e re c e iv e r t o complete proces s ing of the fr ame. When the M a n c h e st e r d e c o d e r is b y p a sse d , it is n e c e ssa ry t o s uppl y dr i bbl e cl ock s at the X R X C pi n after X CR S terminates . T he CR C from the received frame is s ent to memory with the frame via DMA and is included in the byte count pos ted in the buffer header. I f the r eceive uni t detects err ors in the frame (s uch as an incorr ect CR C, an al ignment problem, a fores hortened frame), it can abort reception dependi ng on the confi gur ati on of the S ave E r r or ed P ackets and Accept R unt F r ames bi ts of the Re c e iv e C o n fig u ra t io n Re g ist e r - RC O N .SEP a n d R CON.R U NT S res pecti vely. Cer tain other types of e rro rs (in c lu d in g FIFO o v e rflo w a n d Re c e iv e r Bu f f e r Overwr ite) al ways abor t r ecepti on. I f r ecepti on i s abor ted, the DMA contr ol l er s tops s ending bytes to the buffer, the R eceive S tatus R egis ter (R S R ) and the I nterr upt S tatus R egis ter (I S R ) ar e updated, and the r ecei ve uni t wai ts for the next frame to begin. No buffer header will be pos ted for the frames that have not been accepted; the pr evi ous contents of the header locati on wi ll r emain unchanged. T he r ecei ved pack et l ength s houl d be l es s than 32,764 b ytes, inc lud ing DA, S A, d a ta , a nd CRC. T he r eceiver does not reject longer fr ames but it may be hard to fit the contents into available buffer s pace. T he buffer r ing mus t always have enough s pace to contain the entire frame with a 4-byte header. P ackets lar ger than the avai labl e buffer sp a c e w ill not b e rec eive d , reg a rd less of the S EP bit in the R CON R egis ter. S uch fr ames will be pos ted as ring overwr ites and caus es the OVW interrupt to be s et. Re c e ive r inte rrup ts (RXE fo r fra m e s w ith e rro rs a nd P R X for frames without errors ) indicate the DMA has compl etel y pos ted the frame to memor y. I f the DMA aborts , thes e interrupts are not s et for the cur r ent fr ame. I f s et previ ous ly, they remain unc ha ng ed . Pa c kets sho rter tha n 64 b yte s w ill b e r eceived only when the Accept R unts bit (R CON.R UNT S ) is enabled.

7.4.10 Receiver Blinding

T he R ecei ver Car r i er S ens e functi on i s bl i nded for a p eriod of 4.0 µs ec s tarting at the end of (XCR S + X COL ) when the devi ce has tr ans mi tted a fr ame. T his allows the heartbeat to be detected without res etting the deference timer and ens ures that an imp rop erly-sp a ced frame will not interfere with pr oper pos ti ng of s tatus for a new r ecepti on. LAN CONTROLLER OVERVIEW 83C795

7.5 TRANSMITTER NETWORK INTERFACE

(MAC-TO-PHY)

7.5.1 Oscillator

A 20 Mhz p a ra lle l re so na nt c rysta l c a n b e connected between pi ns X 1 and X 2 ; or an ex ter nal cl ock can be connected at X 1 . T he os ci l l ator ’s 20 Mhz output is divided in half internally to provide the cl ock s i gnal s for the encodi ng and decodi ng ci r cui ts . Oper ati on at s er i al data r ates other than 10 MHz requi res an externally-s uppl ied clock s i nce the o sc illa t o r is o n ly t u n e d f o r 2 0 M Hz. Th e IEEE 80 2. 3 s tandar d r equir es 0 .01% abs ol ute accur acy on the trans mitted s ignal frequency; however, s tray capaci tance can s hi ft the cr ys tal ’s fr equency out of r ange caus ing it to exceed the 0.01 tol er ance.

7.5.2 Manchester Encoder

Data encoding and trans mis s ion begin when the i nter nal tr ans mi t enabl e s i gnal fr om the L AN c ontroller g oes hig h a nd c ontinue s a s long a s it re m a in s h ig h . Tra n sm issio n e n d s w h e n t h e T r ans mi t E nabl e s i gnal goes l ow. T he l as t tr ans i ti on occur s at the center of the bit cel l if the las t bit is ’1’ or at the boundar y of the bi t cel l i f the l as t bi t i s ’0’.

7.5.3 AUI Differential Driver

T he AU I di ffer enti al l i ne dr i ver has the abi l i ty to dr i ve up to 50 meters of twis ted-pair AU I/E thernet tr ans ceiver cabl e. T hes e dr iver s pr ovi de em itte r-c oup le d log ic (ECL) le vel sig na ls. T he outputs cons is t of current drivers that mus t be l o a d e d w i t h e x t e rn a l 1 5 0Ω p ull-up resisto rs. T he inter face can be pr ogr ammed to operate in either ha lf-ste p or full-step m od e in the id le sta te . T his is done via the S E L bit in the MANCH R egis ter. I n full-s tep mode, T X+ is pos itive in relation to T X- when idle. In half-step mode, T X+ and T X- are eq ua l, resulting in nea rly zero d ifferentia l o utp ut voltage. B y s etting a bit in the MANCH R egis ter, Manches ter encoder /decoder l ogi c can be bypas s ed completely. E xternal circuitry s hould drive XT XC, XRXC , XC RS, XRXD, a nd XC O L p ins.

7.5.4 Collision Translator

When the 83C795 is us ed as an AU I device, a se p a ra t e Et h e rn e t t ra n sc e iv e r ( M A U) d e t e c t s c ollisions o n the c o a xia l c a b le a nd g ene ra tes a 10 Mhz s i gnal whi ch i s moni tor ed by the 83C795 through the collis ion detect pins (CD+, CD-). T he pres ence of this s ignal activates the internal c ollision d e te c t sig na l (CD) c onnec ted to the LAN contr ol l er . T he col l i s i on detect s i gnal i s deacti vated withi n 160 ns ec after the abs ence of the 10 Mhz sig n a l. With the s tandard 78Ω trans ceiver AU I cable, the CD+/CD- di ffer enti al i nput pair mus t be ex ter nal l y terminated. T his requirement may be s atis fied by connecting two 39Ω re sist o rs in se rie s w it h o n e opti onal common mode bypas s capaci tor . When 83C795 is used in twisted -p a ir c onfig ura tion, the collis ion is generated if the Manches ter decoder detects carrier while the trans mit enable is active.

7.5.5 Twisted-Pair Differential Driver

T he T P Driver can trans mit through up to 100 meters of uns hielded twis ted pair cable. T he driver i ncl udes a ci r cui t for tr ans mi t equal i z ati on whi ch attenuates the trans mit waveform’s low-frequency components . T hi s r educes the r ecei ved s i gnal ’s z er o-cr os s i ng j i tter and mak es the r ecei ver des i gn sim p le r. In the trans mitter, phas e compens ation is us ed to r educe j i tter . T hi s i s accompl i s hed by us i ng ex ter nal res is tors to determine the drive s trength during the s econd half of a double-width puls e as compared to the dr ive s tr ength of the fir s t half. T here ar e two p a irs o f t w ist e d -p a ir t ra n sm it d riv e rs: TPX1 a n d TPX2. TPX2 is a m uc h w e a ke r d rive r th a n TPX1. During the firs t half-bit-time of each puls e, both pair s of dr i ver s dr i ve out the encoded tr ans mi t data. If the p ulse is a full-b it-tim e in le ng th, T PX2 sw itc he s polarity during the s econd half of the puls e and acts to reduce the amplitude of the trans mitted s ignal. A s implified example of exter nal trans mit cir cui try is sho wn in Fig ure 7-3. 83C795 LAN CONTROLLER OVERVIEW

7.5.6 Link Integrity Test Function

E ach T P dr i ver tr ans mi ts a s hor t pos i ti ve pul s e p eriod ic a lly when it is not send ing d a ta . T hese puls es are recei ved at the other end of the twi s ted p a ir c a b le, sig na ling tha t the link is o p e ra ting cor r ectl y. T he time between link tes t puls es is compar ed to the expected range at the recei ver to help ignore nois e puls es . If the link tes t fails (no pul s es or data r ecei ved wi thi n a fi x ed ti me per i od) then the L L E D pi n i s s et hi gh and AU I i nter face i s s el ected. I f the li nk i s r es tor ed, the chip automatically s elects T P interface. T he L ink Integrity T es t is als o us ed to correct the r eceiver connection’s polar ity. T he L ink I ntegr ity Te st sig n a l a n d St a rt -o f -Id le b o t h h a v e p o sit iv e polarity. T he polar ity cor rection s tate machine looks at both of thes e to determine whether to flip receiver p ola rity. Pola rity c orrec tion c a n b e d isa b le d b y a b it in the MANCH Reg ister (MANCH.E NAPOL). T he L i nk I ntegr i ty T es t can be di s abl ed by a bi t i n the General Control R egis ter (GCR .L I T ). Dis abling Link Test forc es the 83C795 to s elec t the twis ted-pair interface.

7.5.7 Jabber Protection

If the inte rna l tra nsm it e na b le sig na l is a c tive fo r more than 46 ms ec, the twis ted-pair trans mitter will be di s abl ed and a col l i s i on i ndi cati on i s s ent to the MAC trans mitter circuit. When the internal trans mit enable s ignal has been inactive for more than 368 m sec , the interna l c o llision ind ic a tor w ill b ec om e inactive and the twis ted-pair trans mitter will be r e-enabled. Jabber pr otection for the AU I por t is provided by an external MAU .

7.5.8 SQE Test (Heartbeat Test)

In twis ted-pair operation, a brief internal collis ion indication will be s ent to the MAC trans mitter after each pack et i s tr ans mi tted. When an AU I por t i s i n us e, an ex ter nal MAU wi l l pr ovi de thi s s i gnal .

7.5.9 Status Indications

To a ssist in in st a lla t io n a n d m a n a g e m e n t o f t h e network, indicator L E Ds can be driven directly by four outputs fr om the 83C795. T hes e s how the res ult of L ink Tes t, polarity check, trans mit and receive activity. T he L E D outputs can be read back through the MANCH regis ter to s upport network management functions . 83C795

20 MHz

100 Ohms

R31 || R32 = 50 Ohm = R33 || R34 Ratio of R31 to R32 determines how much smaller the second half of the pulse is than the first half 1 1 0 01 01 Polarity TPX1 TPX2 FIGURE 7-3. SIMPLIFIED TRANSMIT CIRCUITRY LAN CONTROLLER OVERVIEW 83C795

7.6 TRANSMITTER SECTION

7.6.1 Basic Function

T he trans mitter s ection generates s erial s tream of NR Z data. I t produces preamble and the S F D field at the beginning of a frame, then data is s hifted from the F I F O s er i ally fol l owed by the CR C fi el d. T he t ra n sm it t e r c h e c ks f o r c o llisio n s a n d re t ra n sm it s t h e fr ames i f neces s ar y, i t counts i nter fr ame gap and im p le m e nts ra nd o m b a c ko ff a lg o rithm . It m a inta ins the trans mit s tatis tics and generates s tatus information on each attempted trans mis s ion. S el ecti on of optional oper ating modes of the T ra nsmitte r sec tion is d one p rim a rily b y programming the T r ans mit Configur ation regis ter.

7.6.2 Preamble Generator

At the beginning of each frame, the trans mitter gener ates 5 6 bi ts of pr eambl e (an al ter nati ng ’1 01 0 ’ pattern). Immediately after this , it generates a S tart Frame Delimiter sequenc e whic h is ’ 10101011.’

7.6.3 Transmit Serializer

T he T r ans mi t S er i al i z er conver ts 8 bi ts of par al l el data from the F IF O into s erial trans mit NR Z data. Data is s hifted out leas t-s ignificant-bit (L S B ) firs t. S er i al data i s cl ock ed onto an i nter nal s i gnal (T X D) by the r is ing edge of the trans mit cl ock. T his s i gnal pas s es to the Manches ter E ncoder which encodes it and dr ives the s elected s eri al interface. When the encoder i s bei ng bypas s ed, the s er i al data dr i ves the XTXD p in d ire c tly .

7.6.4 CRC Generator

T he trans mitter calculates the CR C s erially and appends it to each fr ame. CR C is clocked out mos t-s ignificant-bit (MS B ) firs t. T he trans mitter can be configured to exclude attachment of the computed CR C by s etting the CR CN option bit in the T ra nsm it Co nfig ura tion Re gister (T CON.CR CN). T hi s is us eful for s ome br idgi ng a p p lic a tio ns in w hic h the o rig ina l c he c ksum m ust remain attached to the packet until the final des ti nati on.

7.6.5 Transmit Protocol FSM

T rans mit P rotocol F S M controls tr ans mi s s ion of fr ames , defer s to acti ve car r i er s and col l i s i ons , monitors collis ion conditions , and initiates both backoff and re-trans mis s ion when needed.

7.6.5.1 Interframe Gap and Deference

Deferenc e is initia te d w hen b oth XCRS a nd XCOL have ter minated at the end of a fr ame. T he trans mitter deference logic initiates a 2-part timer at the end of network activity. While this timer is running, no frame trans mis s ion will be initiated. T he firs t part of the timer (interF rame S pacingP art1) is us ed to obs erve the network for trans mis s i on a c t iv it y b y o t h e r st a t io n s. If t h is st a t io n is tra nsmitting, c a rrie r is se nsed , or c o llision is detected during this part of the timer, the timer will be res et to z ero and held there until the termination of line activity. When the firs t part of the timer elaps es , line acti vi ty i s no longer obs er ved and the ti mer r uns to compl eti on. I f any fr ame i s queued up for tr ans mi s s i on at the m om ent o f tim er exp ira tio n, tra nsm ission w ill b e initia ted rega rd less of line a c tivity. T he c omb ina tion o f interFra me S p a c ingPa rt1 a nd i nter F r ame S paci ngP ar t2 makes up the In t e r- Fra m e G a p ( IFG ) a s d e f in e d b y t h e 80 2. 3 sp e c ific a tion. T he interFra me S p a c ing Pa rt1 is 6.0 µs ec a nd interFrame S pacingPart2 is 3.6 µse c .

7.6.5.2 Collision Handling Logic

When c ollision is d e te c ted b y the tra nsm itter s ection during the firs t s lot time of an active trans mis s ion, the trans mis s ion does not terminate immedi atel y. I ns tead, the preamble is al lowed to fi ni s h and the jam s equence is trans mitted. T he jam s equence cons is ts of 32 bits of logic ’1’s . If collis ion is detected after the s lot time is pas s ed, the 83C795 wi l l abor t the tr ans mi s s i on wi th jam and wi thout re try a nd ’ Out o f Wind ow Collision’ b it is set in the t ra n sm issio n st a t u s re g ist e r . 83C795 LAN CONTROLLER OVERVIEW

7.6.6 Timers

7.6.6.1 Slot Timer

During trans mit, the s lot timer s tarts counting once the r eceiver recogniz es that a car ri er is pr es ent at the s tar t of a r etur ning preamble. When backing off, the s lot timer s tarts with the end of T XE for the c ollid ed fra me a nd d oe s not get reset b y a ny other inc oming fra mes. S lot time is programmable through the E nha nc ement Register. T he c hoic es a re 256-, 512-, a nd 1024-b it times. T he d efa ult va lue is 512-bit times.

7.6.6.2 Backoff Timer

After a tr ans mi s s i on i s ter mi nated becaus e of a c ollision, a retra nsm ission is a ttem p ted . Timing of it is deter mined by the ’truncated binar y exponential back off’ al gor i thm. T hi s al gor i thm i s : draw random integer r: 0 <= r < 2**k where k equal s the number of retr ies al ready on this t ra n sm issio n . K st a rt s a t 0. W a it ’ r’ n u m b e r o f slo t times and then s tart normal trans mit deferral. T he backoff timer is a 12-bit counter that is initializ ed to a random number when an attempted t ra n sm issio n re su lt s in a c o llisio n . Th e c o u n t e r d ec rem ents onc e p er slo t time until it rea c hes zero. T he T rans mit P rotocol S tate machine uti liz es this ti mer to i ns er t a var i abl e amount of del ay ahead of its attempt to retrans mit the frame. T her e is a s electable enhancement to backoff ti mer oper ati on which caus es it to s us pend counti ng while there is network activity and r es ume duri ng id le t im e s. In t h is m o d e o f o p e ra t io n , t h e b a c k o f f ti mer conti nues to oper ate whi l e a car r i er s ens e rem a ins from the initia l c o llisio n b ut d o es no t op e ra te d uring a ny othe r c a rrier ind ic a tion. T his is re fe rre d to a s the ’ Sto p Ba c ko ff’ a lg o rithm . It m a y put s tati ons that us e i t at a di s advantage when operating on the s ame network with s tations not utiliz ing it and caution in its us e is advis ed. T his al gor i thm can be enabl ed by s etti ng the S B ACK bi t in t h e EN H Re g ist e r.

7.6.6.3 Collision Counter

All retrans mis s ion attempts are counted by the c ollision c ounter. Afte r the m a xim um numb er of attempts is reached (16), the trans mis s ion of the frame is aborted, an interrupt is generated and event is r epor ted as an err or in the tr ans mi t s tatus re g iste r.

7.6.6.4 Heartbeat Detection

After each tr ans mi s s i on, the tr ans mi t l ogi c opens a wind ow 3.6 µse c lo ng d uring w hic h it lo o ks fo r a p ulse on the XCOL sig na l. T his p ulse is no rm a lly generated by the MAU and is received through the AU I interface. I f the pul s e is r eceived, the CDH st a t u s b it o f t h e TSTA T Re g ist e r is c le a re d . If n o p ulse is rec eive d d uring the w ind ow , the CDH b it is se t .

7.6.7 Transmitter Operation

7.6.7.1 Transmission Initialization

Packets to be trans mitted are built in buffer memory by the hos t. T hes e packets mus t i nclude the DA, S A, and data fields . CR C is not read fr om buffer memor y unl es s CR C gener ati on i s di s abl ed. T he trans mitter reques ts the frame from the DMA when the T X P bit of the CMD R egis ter is s et by the h o st . Th e TSTA RT a n d TC N T Re g i st e r s m u st b e pr oper ly pr ogr ammed pr i or to s etti ng T X P. Once s et by the hos t, T XP can be cleared only by the DMA after the trans mitter has s ignalled completion of an attempted trans mis s ion.

7.6.7.2 Transmission Process

T he DMA s tarts to fill the trans mit F IF O with burs ts of data then notifies the trans mitter that it is ready for trans mis s ion. T he trans mitter defers until the medi a i s cl ear and an i nter fr ame gap has pas s ed then generates preamble and S F D fields . It then pulls bytes out of the trans mit F I F O, s erializ es them, and s hifts bits to the output pins while computing the CR C on the packet. T he DMA al s o monitor s the amount of r oom r emai ni ng in the F I F O and initi ates a bur s t of memory tr ans fer s when there is enough room for the entire burs t to fit. LAN CONTROLLER OVERVIEW 83C795

Onc e the DMA ha s filled the T ra nsmit FIFO w ith the las t byte of the packet, i t s ets a flag. When the F I F O becomes empty, it s i gnifies the end of the frame. CR C computation s tops and the CR C is appended se ria lly t o t h e f ra m e , m o st sig n if ic a n t b it f irst .

7.6.7.3 Transmit Underrun

I f the F I F O becomes empty befor e the i nter nal fl ag is se t, it is c o nsid e re d a tra nsm it und e rflo w a nd is pos ted as a tr ans mi t er r or i n the T r ans mi t S tatus (TSTA T) Re g iste r. In this c a se , tra nsm issio n o f the packet i s abor ted and an i nter r upt can be gener ated.

7.6.7.4 Early Transmit Underrun Protection

T his fea ture is used to fa c ilita te initia tion of t ra n sm issio n p rio r t o c o m p le t io n o f a sse m b ly o f t h e outgoi ng frame in the trans mit buffer. E arly trans mit underrun protection is controlled by two bits in the Command R egis ter - CMD.DI S E T CH and CMD.E NE T CH. S etting DIS E T CH to ’1’ di s abl es ear l y tr ans mi t under r un checking and s etting E NE T CH to ’1’ enables checking. Writing both bits to z ero leaves trans mit checking in its p revious sta te. S etting b oth b its to ’1’ is illeg a l. T his oper ati on wor ks the s ame as the Command R egi s ter s tar t and s top bi ts for br i ngi ng the chi p on and offline. While earl y trans mit under run checki ng is enabled, the memory addres s is latched each time the hos t does a wr i te to the buffer memor y (the actual memor y addres s i s us ed, not the hos t addres s ). When the DMA r eads packet data fr om the buffer memor y, the memor y addr es s i s compar ed to the mos t r ecentl y- l atched memor y wr i te addr es s (written fr om the hos t wi th E T CHON only). T he DMA di s ti ngui s hes between acces s es to des cr i ptor tabl e entr i es and actual pack et data. I f ear l y tr ans mi t check i ng i s on, and the DMA’s memor y r ead addr es s i s gr eater than the abs ol ute value of the latched memor y wr i te addres s , a "buffer underrun" condition is s et. T his condition aborts the trans mitter which in turn aborts the DMA. T he condi ti on i s cl ear ed when the DMA detects the abort and clears the trans mit F I F O. T he trans mit abor t i s r epor ted as though i t wer e a F I F O under r un and both the T S T AT .U NDE R and INT S T AT .R XE flag bits are s et.

7.6.7.5 Collisions

W h e n a c o l l i si o n i s re p o r t e d o n t h e C D p i n , t h e t ra n sm it t e r se n d s a 32-b it se q u e n c e c o m p o se d o f al l ’1’ bi ts as a j am s i gnal , then ter mi nates i ts tr ans mi s s i on. I f col l i s i on occur s dur i ng the pr eambl e of a fr ame, the r emai nder of the pr eambl e is se n t b e f o re se n d in g t h e ja m sig n a l. I f the collis i on occur red after the end of one s lot time, trans mis s ion is aborted without retry after se nd ing a ja m p a tte rn. T his is c o nsid e re d a n o u t -o f -w in d o w c o llisio n a n d p o st s a st a t u s b it in t h e T S T AT r egi s ter (T S T AT .OWC) and i s a contr i butor to the T X E flag in the I NT S T AT R egis ter. F or col l i s i ons that occur wi thi n the fir s t s l ot ti me of a fr ame, a counter of r etr i es i s i ncr emented and checked agains t the retry limit (16). If the number of retries is less tha n the limit, a b a c k-o ff d e la y (in uni ts of s lot-time) i s chos en at r andom. T he trans mitter then reques ts the frame’s r etr ans mi s s i on fr om memor y and del ay i s i ni ti ated. T he DMA contr ol ler clears out the trans mit F I F O, loads its pointer to the s tart of frame in memory, and waits for the abort s ignal to s ubs ide. T he F IF O is loaded in the same ma nner as it was initially. If the maximum number of col lis ions (16) is exceeded, trans mis s ion is aborted without further retries and no back-off delay is executed. 83C795 LAN CONTROLLER OVERVIEW

7.6.7.6 Extensions Beyond 802.3 10Base5 Protocol T he 802.3 10B as e5 pr otocol uti liz es frame lengths between 64 and 1518 bytes inc lusively. T he trans mitter s ection is capable of s ending frames greater than 17 and les s than 32,768 bytes in le n g t h . Tra n sm issio n o f lo n g e r o r sh o rt e r f ra m e s than permitted within the 10B as e5 definition may b e useful in other va ria tio ns of 802.3 p rotoc o ls. When cons i der ing the trans mis s ion of gi ant fr ames o n a n o n -802.3 n e t w o rk, b e a w a re t h a t v e ry lo n g frames can activate jabber detectors in exis ting 10B as eX MAU s and r epeaters . T he us e of s uch frames in non-s tandard networks requires cons iderable planning and s ome caution. To sup p ort non-802.3 p rotoc o ls, the 83C795’ s slot ti me i s program-s electable. Choos e from 256-bi t, 512-bit, or 1024-b it times. T he S top B ackoff al gor i thm i s s el ectabl e for backoff modi fi cati on fol l owing col l i s i ons . When op era ting in ALT EGO Mod e, d etec tion o f a ny pair of cons ecutive ’0’ bits within the pr eamble caus es the reception of that fr ame to be a b a nd oned . No error is rep orted . T he R CON.R CA bit enables the receiver to abandon r ecepti on of any fr ame whi ch caus es a c ollision. No error is rep orted .

7.6.7.7 Extended Length

When the XL E NGT H bit (GCR .7) is s et, the twi s ted- pai r por t can be connected to cabl es l onger than the 100-meter limit spec ified by the 802.3 sp e c if ic a t io n LAN CONTROLLER OVERVIEW 83C795

8.0 BUFFER STRUCTURING AND DATA

8.1 TRANSMIT PACKETS

8.1.1 Single Packet Transmission

A packet for tr ans mi s s i on i s pl aced by the hos t i nto buffer memor y. T hi s packet mus t i nclude the DA, S A, and data fi el ds . T he pr eambl e, S F D, and CR C (norma lly) a re not inc lud ed in the b uffer. If CRC g e ne ra tio n is sup p re sse d , the C RC fie ld fo r the pack et i s al s o s uppl i ed by the hos t. T he pack et i s p l a c e d i n a c o n t i g u o u s b l o c k o f m e m o r y i n t h e buffer, s tar ti ng on a 25 6 -byte boundar y. Val i d 80 2 .3 pack ets have at l eas t 48 bytes of data. If less d a ta is to b e tra nsmitted on a n 802.3 network, it is the re sp o nsib ility o f the ho st to b uild a p a c ke t with p a d d a ta inc lud ed . T he 83C795 will tra nsmit fr ames of any pr ogr ammed l ength (gr eater than 17 bytes ), even thos e which are too s hor t to be valid fr ames i n an 80 2 .3 networ k . DMA wi l l tr ans fer the number of bytes pr ogr ammed i nto the T CNT H and TC NTL Re g ist e r p a ir st a rt in g f ro m a d d re ss (T S TART * 100H).

8.1.2 Multiple Packet Transmissions

To su p p o rt m u lt ip le t ra n sm issio n s p e r c o m m a n d , a tr ans mi t queue can be enabl ed by s etting the ALT E GO bi t in the E nhancement R egi s ter (E NH . 5). I n thi s mode, a tabl e of fr ame des cr i ptor s defi nes the s tarting locati on and length of all enqueued t ra n sm issio n s. Th is d e sc rip t o r t a b le is p ro c e sse d in a c irc ula r m a nn e r b y t he LA N c o ntro lle r. T he table is treated as a ring of entries whos e s tar ti ng and endi ng poi nts ar e defi ned by a pair of regis ters (T B E GIN and T E ND) in the L AN controller. T hes e r egis ter s are initi al iz ed with the upper 8-bits of addres s for the firs t location of the table and the firs t location after the end of the table. T E ND is not within the table. When table proces s ing reaches the location defined by T E ND, it is s witched b a c k t o TBEG I N . Th e t a b l e m u st b e a l i g n e d w i t h 256 byte boundar y i n the buffer memor y. E ach entr y is 8 b yte s long . T he form a t of this b uffering is defi ned i n F i gur e 8 -1 . To se n d m u lt ip le t ra n sm issio n s, t h e d riv e r b u ild s t h e fr ames in buffer memor y in the s ame conti guous for m pr es ently expected. T he dr iver then adds an entry for each frame into a table of trans mit des criptors . T his entry contains the s tarting location and l ength, and tr ans mi t confi gur ati on for each fr ame in the tr ans mi t queue. P l aces ar e pr ovi ded in the table for return of the T rans mit S tatus (T S T AT ) R egi s ter and col l i s i on count as s oci ated wi th each tr ans mi s s ion. A s i mple s emaphor e protocol wi ll be use d to c o ntro l o w ne rship o f tra nsm it b uffe rs. T he LAN c ontroller keep s a p ointer in the T TABH and T T AB L R egis ters to the trans mit des criptor tabl e. T hi s poi nter i s i ni ti al i z ed by the dr i ver when the table is firs t built and s hould not need re-initialization thereafter. When trans mit command has been s et and devi ce i s onl i ne, tr ans mi t begi ns from the entry pointed to by the T T AB H and T T AB L Re g iste rs. T he LAN c o ntro lle r first c he c ks the TSTA T fie ld . If it e n c o un te rs a fie ld e q ua l t o FF, it will attempt to trans mit the frame pointed to by the entry. T he s tatus field will be changed to z ero after the remainder of the entry has been read. When it encounters a T S T AT field not equal to F F, no frame will be s ent, the trans mit complete interrupt will be s ent and the fi el d wi l l not be al ter ed. If the fra me is m a rked fo r tra nsm ission, the DMA c ontroller loa d s its T S TART H, T S TART L, T CNT H, TC N TL, a n d TC O N Re g i st e r s f r o m t h e d e sc r i p t o r . T S T AT gets mar ked as having been opened by the LA N c o n t ro lle r a n d t ra n sm issio n p ro c e e d s a s w it h s ingle trans mis s ions except that when the t ra n sm issio n h a s c o m p le t e d , t h e t ra n sm it st a t u s and col l i s i on count ar e moved by DMA i nto the tabl e. T he tabl e poi nter i s updated and tr ans mi s s i on of next entry begins . If a tra nsmit a b o rt oc c urs (too ma ny c ollisions) the tr ans mi tter wi l l s top pr oces s i ng the chai n and pos t the current trans mit and interrupt s tatus . If the CMD.S T P bit is s et, the trans mis s ion of any ongoing fr ame proceeds until completion or abor t b u t n o su c c e ssiv e f ra m e s in t h e c h a in a re p ro c e sse d . Th e TTA B in d ic e s w ill p o in t t o t h e f irst unpr oces s ed fr ame in the table s o that none are lost. An al ter nati ve mode of contr ol l i ng the tr ans mi t interrupt can be enabled by the E OT INT bit in the E nhancement (E NH) R egis ter. When enabled, the trans mit interrupt will be generated only upon 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES

FIGURE 8-1. MULTIPLE FRAME TRANSMIT BUFFER FORMAT BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795

completion of the trans mit chain. Normal mas king appl i es on top of thi s del ay mechani s m. Witho ut ena b ling this ne w m o d e o f c o ntro lling trans mit interrupts , an interrupt will be generated on a frame by frame bas is but the interrupt s tatus may not be cur r ent by the ti me i t can be r ead by the dr i ver so f t w a re .

8.1.2.1 Ownership of Buffers

T he T S T AT fi el d of the tabl e entr y i s us ed to contr ol owner s hi p of the frame buffers . Hands hake over control of trans mit frame buffers is governed by the following conventions : TSTAT Field Value Meaning TSTAT field = 00 83C795 has begun transmission. TSTAT field > 00 and < FFh Frame completed. TSTAT field = FF Assembled frame, not yet transmitted. TABLE 8-1. TSTAT FIELD VALUES T he dr i ver s oftwar e fi l l s the T S T AT tabl e entr y wi th F F h when i t r el eas es the fr ame to the L AN contr ol l er f o r t ra n sm issio n . W h e n t ra n sm it c o m m a n d h a s been s et and devi ce i s onl i ne, the DMA l ooks at TSTA T f i e l d . I f i t e n c o u n t e r s a f i e l d = FF , i t w i l l attempt to trans mit the frame pointed to by the entry. T he s tatus fi el d wi l l be changed to z er o after des cr i ptor entr y i s r ead and tr ans mi tter commi ts to s ending. I f DMA encounter s a T S T AT fi el d gr eater than or l es s than F F h, no fr ame wi l l be tr ans mi tted, the trans mit complete interrupt will be s ent. T he fie ld is no t a ltered . Wh e n a t ra n sm issio n c o m p le t e s, t h e c o n t e n t s o f T S T AT regis ter will be moved into that location.

8.1.2.2 Modifying the Transmit Queue

T o add a fr ame to the tr ans mi t queue, bui l d the frame in buffer memory then find the table entry following the l as t enqueued frame. E nter the des cr i ptor for the new fr ame wi th a T S T AT that i s neither 00 nor F F in value. When des criptor is compl ete, wr i te T S T AT wi th F F . T he des cr i ptor entr y followi ng the las t enqueued fr ame entry mus t have i ts T S T AT val ue mar k ed wi th a non-F F val ue. T hat defines the end of the enqueued fr ames for the DMA. S et the T XP bit of the COMMAND regis ter to ens ure that the new trans mis s ion goes out. T he T XP bit can be wr i tten r egar dl es s of compl eti on s tatus and wi l l ens ure that the lates t frame does get trans mitted. If the L AN contr ol ler r eaches the end of the trans mit queue befor e the new frame has been added, a trans mit complete interrupt is generated for the old porti on of the queue and another tr ans mi t complete i nter r upt wi l l be gener ated when the added por ti on compl etes . T he driver s hould not attempt to alter any buffered fr ame whos e T S T AT i s ei ther 00 or F F whi le CMD.T XP is turned on. Wait until all trans mis s ions are complete or s et the CMD.S T P bit and wait for the S T OP s tatus to be confirmed in the I nterrupt S tatus regis ter. E xami ne T S T AT table entri es to determi ne which fr ames have been trans mitted. T hos e whos e entr ies ar e F F have not been opened by trans mitter. R efer to Tables 8-2 and 8-3 for a s ummary of the tr ans mi t des cr i ptor tabl e for mat. 8-BIT MEMORY 16-BIT MEMORY D15-D08 D07-D00 COLCNT TSTAT COLCNT TSTAT TSTARTH TSTARTL TSTARTL TCNTH TCNTL TSTARTH not used TCON TCNTL TCNTH TCON not used TABLE 8-2. FORMAT OF TRANSMIT DESCRIPTOR TABLE 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES

COLCNT Written with the number of collisions experiences by the LAN controller while attempting to transmit this frame. TSTAT This entry in the table is used to control ownership of the frame buffer: TSTAT = 00 means the 83C795 has begun transmission TSTAT>00 but <FFh means the frame has been completed and the contents of the transmit status register have been moved into that location. TSTAT = FFh means assembled frame has not yet been transmitted. TSTARTH,L Pointer to start of transmit buffer. 16-bits wide. TCNTH, L Number of bytes to transmit, exclusive of computed FCS. TCON Transmit configuration desired for this frame. This entire byte is DMA’d into the internal TCON register and applies to this frame. not used Ignored by the LAN controller. TABLE 8-3. MEANING OF DESCRIPTOR TABLE

8.2 RECEIVE PACKET BUFFERING

T wo alternative modes of buffering received packets are s upported: ring of buffers and linked-lis t. S election between thes e two modes is m a d e b y a b it in t h e EN H Re g ist e r, EN H. A LTEG O .

8.2.1 Ring of Buffers

All received packets ar e s tor ed i n one ci rcularly connected, conti guous s et of 2 56 - byte buffer s . T he num b e r a nd loc a tion of b uffers in the ring is determined by the values written into the R S T AR T a n d RSTO P Re g ist e rs b y t h e h o st w h e n t h e 83C795 is initializ ed. R S T AR T points to the firs t buffer in the ring and R S T OP points to the buffer after the las t one in the ring. E ach packet r eceived will be s tored into one or mor e of thes e buffers , wi th a 4-byte header i ns erted at the s tar t of the fir s t buffer. F i gur e 8 -2 detai l s the for mat of a r ecei ved pack et in memor y. BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795

FIGURE 8-2. RECEIVER BUFFER FORMAT 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES

F rames that extend to the buffer des ignated by R S T OP ar e conti nued i n the buffer des i gnated by RSTA RT a n d su c c e ssiv e lo c a t io n s. RSTO P m a y b e either greater than R S T AR T +1 or les s than RSTA RT. M a kin g RSTO P e q u a l t o RSTA RT o r RSTA RT + 1 le a d s t o u n p re d ic t a b le re su lt s. Th e r el ations hip of thes e r egi s ter s to ring placement in m em ory is illustra ted in Fig ure 8-3. U p to 254 buffers can be allocated to the ring. T he receiver DMA will us e as many as required to s tore a pack et. T hi s al l ows the chi p to be confi gur ed to r ecei ve fr ames near ly as l ong as 64K bytes . T hi s can be us eful in cus tomiz ed CS MA networ ks ; however, allocating s o many buffers to the r ecepti on pr oces s l eaves ver y l i ttl e capabi l i ty for buffer i ng tr ans mi t fr ames al though i t i s wi thi n the capability of the 83C795. T he recei ve DMA uti liz es two additional regis ters to manage the buffer ri ng. T hes e are the Curr ent P age Re g ist e r ( C URR) a n d t h e Bo u n d a ry Pa g e Re g ist e r (B OU ND). T he CU R R R egis ter points to the firs t b uffe r tha t is no t p a rt o f a c o m p le te ly re c e ive d packet. When R DMA i s s tori ng a frame, this regis ter points to the s tart of the frame being s tored. When R DMA is not s toring a frame, it points to the firs t buffer that will be us ed for the next frame to be re c e ive d . T he B OU ND R egi s ter pr otects r ecei ved fr ames from being overwritten by later frames . It points to the firs t buffer in the ring that is not to be overwritten. FIGURE 8-3. RING BUFFER STRUCTURE BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795

When the receive DMA proces s attempts to open the buffer that B OU ND points to for s torage of a packet, it aborts the reception and s ets the INT S T AT .OVW flag (in the Interrupt S tatus R egis ter) and the R S T AT .MPA bit (i n the R eceiver S tatus R egis ter). T he pr otected buffer i s not wr itten to. Normally, B OU ND is s et up to point to the oldes t r ecei ved pack et i n the r i ng. T hi s poi nter can be managed by the hos t. T o di s car d an unwanted fr ame, the hos t may s impl y r ewrite B OU ND to point to the next packet. A good prac tice is to write zeros into the firs t byte of the dis carded packet to prevent future interpretation as a received packet. When B OU ND and CU R R have the s ame value, the ring may be either ful l or empty. T he 83C795 c a n d isting uish b e twe en full a nd e m p ty rings. CU R R is updated by the DMA controller at the end of a frame recepti on. T he r ing is cons idered ful l if thes e two r egi s ter s ar e equal and the DMA contr ol l er updated CU R R mor e r ecentl y than the hos t updated B OU ND. Conver s el y, when data i s b e ing re m o ve d fro m the ring , the ho st up d a te s B OU ND after r emoval. When i t has been advanced pas t the end of the las t recei ved fr ame, it s hould have the s ame val ue as CU R R . T he chip treats the r ing as empty when thes e two r egis ter val ues are equal and B OU ND has been updated after CU R R . When initia lizing the b uffer ring, BOUND a nd CURR may be given the s ame or di ffer ent values . T hes e regis ters may be initializ ed to point to any buffer within the ring. T hey may point to R S T AR T but may not point to R S T OP. I f CU R R points outs ide the ring, the RDMA w ill store fra me s outsid e the ring in a n unp re d ic ta b le m a nne r. If BO UND p o ints o utsid e the r ing, the received frames will not be protected from o ve rw rite s b y la te r fra m e s. Fig ure 8-4 illustra te s the b uffer ring in two c om mo n st a t e s. Th e t o p rin g , INITRBUF, illu st ra t e s t h e relations hip between thes e pointers in a typical ring initialization. T he b ottom ring, RBUF, shows a ring that has r eceived a few frames - the normal condition for the ring. FIGURE 8-4. RECEIVER BUFFER RING 1 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES

Fig ure 8-5 shows the same ring after prop er r emoval of the oldes t r eceived packet. T he top ring, FULLRIN G , sh o w s a rin g t h a t is c o m p le t e ly f u ll. Th e bottom ri ng, OVE R F L OW, s hows a ring on the verge of over flow.

8.2.1.1 Automatic Ring Wrapping

Automatic ring wrapping enables the hos t to read a contiguous block of data from the buffer R AM without having to check whether the block is s o long that the acces s wr aps ar ound the end of the buffer r ing. T his is accomplis hed by checki ng whether the next value to be l oaded into the memor y cache’s buffer counter is equal to the regis ter R S T OP. If this is true, then the value of the R S T AR T regis ter is loaded into the counter ins tead. T he memory c a c h e ’ s Ho st C o u n t e r is le f t u n c h a n g e d so t h e h o st can conti nue acces s i ng memor y pas t the end of the r ing, but i ns tead recei ves the cor rect data fr om the s tart of the r ing. T he comparis on is onl y made when the counter is incrementing s o it is not pos s ible to s tart the block of data pas t the ring’s end. Als o, sin c e t h e h o st is se n d in g a d d re sse s t h a t a re g re a t e r than the end of the ring, it is required that the 83C795’s memory s pace extend beyond the end of the r i ng. T hi s can be accompl i s hed by ar r angi ng the memory s pace s uch that the trans mit buffers come after the r eceive buffer ring. T his featur e is enabl ed by s etting the WR AP E N bit (U B R CV.0). F or more on this, refer to p age 40.

8.2.1.2 Ring-Empty Bit

T hi s i s a r ead- onl y bi t l ocated at U B R CV.2 whi ch indicates to the hos t that there are no completely r eceived fr ames in the buffer ring yet. T he hos t check s thi s bi t after i t fi ni s hes r ecei vi ng a fr ame and quickl y determi nes whether there ar e mor e fr ames to copy. T his bit is s et when B OUND equals CUR R . B OU ND is updated after CU R R . S ince this bit is only cleared for completely received frames , another method mus t be us ed to determine if there is a par tial frame i n the buffer that exceeds FIGURE 8-5. RECEIVER BUFFER RING 2 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795

the e a rly re c e ive thre sho ld (e a rly re c e ive m o d e only). T his i s done by checki ng the interr upt s tatus r egis ter after checki ng the r ing-empty bit.

8.2.2 Linked-List Receiver Buffering

L i nk ed- L i s t R ecei ver B uffer i ng i s enabl ed by a bi t i n the E nhancement regis ter, E NH.ALT E GO, and is a n a lte rna tive to re c e ive ring fo rm o f b uffe ring . In this mode, the receiver directs its input to a group of i ndi vi dual l y- s i z ed buffer s that ar e not neces s ar i l y contiguous . All buffers need not be the s ame s ize. Multiple buffers can be chai ned together as needed to receive an incoming frame. T hes e buffers are linked together via a table of b u f f e r d e sc rip t o rs w h ic h d e f in e t h e st a rt in g lo c a t io n , size, a nd usa g e of a ll rec eive r b uffers. T his ta b le contr ol s both the r ecei ved fr ames and the avai l abl e buffer pool . T he des criptor table is treated as a ring of entries whos e s tar ti ng and endi ng poi nts ar e defi ned by a pair of regis ters (R BE GIN and R E ND) in the LAN controller. T hes e r egis ter s are initi al iz ed with the upper 8-bits of addres s for the firs t location of the table and the firs t location after the end of the table. R E ND is not within the table. When table proces s ing r eaches the location defi ned by R E ND, it is sw itc he d b a c k to RBEG IN. T he ta b le m ust b e aligned with 256-byte boundary in the buffer memory. E a c h entry is 8-bytes long. T he forma t of this buffer ing arr angement is depicted in F i gur e 8-6. FIGURE 8-6. LINKED-LIST BUFFER FORMAT 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES

T he L AN contr ol ler keeps a poi nter (R egis ters RTA BH a n d RTA BL) t o t h e Re c e iv e D e sc rip t o r tabl e. T hi s poi nter i s i ni ti al i z ed by the dr i ver when the table is firs t built and s hould not need re -initia liza tio n the re a fte r. When the L AN controller’s DMA becomes active to r eceive a frame, it wi ll us e R T AB as a poi nter to the firs t free receive buffer. R S T AT field of des criptor is checked to s ee if the buffer is free (R S T AT =00). If free, the s iz e and s tarting location of the buffer are l oaded fr om the des cr i ptor and r ounded down to even values . S torage of the fr ame into the buffer begi ns . T he value of R T AB is s aved at the s tar t of r ecepti on for each fr ame i n cas e the fr ame gets aborted and R T AB has already been updated to the next table entry. While a frame is being buffered, the LAN controller will follow the entries in the des criptor table to obtain additional buffers as needed to receive the entire frame. Upon c ompletion, the des criptor for the firs t buffer of that frame i s wri tten with the r eceiver s tatus regis ter and the total byte count for that frame. T he byte count i ncl udes s tor age of the r ecei ved F CS . S houl d a partially r eceived fr ame be r ejected by the LAN c o ntroller, it w ill rec la im the b uffers b y re setting the R T AB poi nter to i ts val ue pr evi ous to s tar t of re c e p tio n o f this fra m e . T o add free buffers to the end of the des criptor table, fill in the firs t new table entry with R S T AT =non-z ero, bui l d al l other tabl e entr i es wi th R S T AT =0 , then change the firs t R S T AT to 00 to indicate availability. BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795

9.0 ELECTRICAL SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Ab so lute m a xim um ra ting s ind ic a te lim its b e yond w hic h p erma nent d a m a g e ma y oc c ur. Continuous oper ating at thes e l i mi ts i s not r ecommended; oper ati on s houl d be l i mi ted to condi ti ons s peci fi ed under " DC Oper ating Char acter is tics ."

9.2 RECOMMENDED OPERATING CONDITIONS

Supply Voltage (V

9.3 DC OPERATING CHARACTERISTICS

T a = 0° C (32° F ) to 70° C (158° F ) Vdd = +5V ± 5% Note All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.

9.3.1 Input Pins

SYMBOL PARAMETER MIN MAX UNIT CONDITIONS Idd Su p p l y C u rr e n t 110 mA Vih Inp ut Hig h V o lta g e (MA09-MA00) 2.0 — V Interna l p ull-d o w n resisto r val ue between 35KΩ and 150KΩ . Inp ut Hig h V o lta g e (MA07-MA00, ME MR , ME MW, SBH E) 1.65 1.94 V V when Vcc=4.5V when Vcc=5.5V for S c hm itt-trig g ered inp uts, T T L-c omp a tib le leve ls Inp ut Hig h V o lta g e (X1) 3.5 — V C M O S le ve l inp ut Inp ut Hig h V o lta g e (All o the r inp uts) 2.0 — V TTL l e v e l s, h i g h im p ed a nc e 83C795 ELECTRICAL SPECIFICATIONS

SYMBOL PARAMETER MIN MAX UNIT CONDITIONS Vil Inp ut Lo w V o lta g e (MA09-MA00) —0 . 8 V Interna l p ull-d o w n resisto r val ue between 35KΩ and 150KΩ . Inp ut Lo w V o lta g e (MA07-MA00, ME MR , ME MW, SBH E) 1.04 1.20 V when Vdd=4.5V when Vdd=5.5V Interna l p ull-d o w n resisto r val ue between 35KΩ and 150KΩ . Inp ut Lo w V o lta g e (X1) —1 . 5 V C M O S le ve l inp ut Inp ut Lo w V o lta g e (All o the r inp uts) — 1.04 1.20 V V when V dd=4.5V when Vdd=5.5V Vhys I nput Voltage Hys ter es is (S chmitt Inputs ) 0.40 0.39 0.51 0.59 V V when Vdd=4.5V when Vdd=5.5V Vt+ Inp ut V o lta g e TT L + (S chmitt Inputs ) 1.45 1.65 1.65 1.94 V V when Vdd=4.5V when Vdd=5.5V Vt- Inp ut V o lta g e TT L- (S chmitt Inputs ) 1.04 1.20 1.18 1.35 V V when Vdd=4.5V when Vdd=5.5V Vds Differential S quelch T hr es hold (R X±, CD±) -175 -300 mV Differential S quelch T hr es hold (T PR±) 300 500 mV Iil Inp ut Lo w C urre nt (R X±, CD±, T PR±) — -500 uA Inp ut Lo w C urre nt (MA09-MA00, MD07-MD00, ME MR , ME MW, SBH E) -25 -200 uA Inp ut Lo w C urre nt (X1) —- 5 0 u A Inp ut Lo w C urre nt (All o the r inp uts) —- 1 0 u A Iih Inp ut Hig h C urre nt (R X±, CD±, T PR±) — 500 uA Inp ut Hig h C urre nt (X1) —5 0 u A Inp ut Hig h C urre nt (All o the r inp uts) —1 0 u A Iin Inp ut C urre nt (CAP) -1.0 -1.0 mA when Vin = 2.5V TABLE 9-1. INPUT PIN VALUES ELECTRICAL SPECIFICATIONS 83C795

9.3.2 Output Pins

SYMBOL PARAMETER MIN MAX UNIT CONDITIONS Vol Output L ow Vol tage (X2) 0.7 V Iol = 8mA Output L ow Vol tage (T PX1± ) 0.6 V I ol = 30m A Output L ow Vol tage (T PX2±)0 . 7 5 V I ol = 14m A Output L ow Vol tage (ZW S) 0. 4 V I ol = 24mA Output L ow Vol tage (GPOUT, IOR DY, IO 16C S, M16CS , SD 0 0 - SD 1 6 )

0.4 V I ol = 24m A

(Al l other outputs ) 0.4 V I ol = 4mA Voh Output H igh Voltage (X2) 3.5 V Ioh = -100mA Output H igh Voltage (T PX1±)V dd-0.6 V I oh = 30m A Output H igh Voltage (T PX2±)V dd-0.75 V I oh = 14m A Output H igh Voltage (ZW S) 2 .4 V I oh = 24m A Output H igh Voltage (GPOUT, IOR DY, IO 16C S, M16CS , SD 0 0 - SD 1 6 )

2.4 V I oh = 24m A

(Al l other outputs ) 2.4 V I oh = 4mA Vod Differential Output Vol tage (T X±) -500 500 -1200 1200 mV mV 78Ω ter mi nati on and 150Ω fr om each output to Vdd. Vout Output Voltage (BS R) 2.25 2.75 V 10.0 K Ω ex ter nal resistor to Vdd. Output Voltage (OS R) 2.25 2.75 V 24.9 K Ω ex ter nal resistor to Vdd. TABLE 9-2. OUTPUT PIN VALUES 83C795 ELECTRICAL SPECIFICATIONS

10.0 AC OPERATING CHARACTERISTICS AND TIMING

T his sec tions p rovid es timing d ia gra ms a nd p a ra meters for 83C795 sig na ls. Ta b le 10-1 ind ic a tes the tim ing diagrams included in this s ection. T able 10-2 indicates the timing parameters applying to each timing diagram. E xcept where otherwis e noted, timing units ar e in nanos econds . FIGURE TITLE 10-1 S ys tem Clock T iming 10 - 2 R egi s ter Acces s T i mi ng – R ead 10 - 3 R egi s ter Acces s T i mi ng – Wr i te 10-4 16-b it Register Ac c ess (I/ O Pip e Only) 10-5 Ho st M e m o ry A c c e ss (16-b it , ZWS) 10-6 Ho st M e m o ry A c c e ss (8-b it , No ZWS) 10-7 Ho st M e m o ry A c c e ss (8-b it , ZWS) 10-8 Ho st M e m o ry A c c e ss (8-b it , No ZWS) 1 0-9 Ro m A c c e ss (8 -b it O n ly , Re a d O n ly) 10-10 DMA or Memory Cache Wr ites 10-11 DMA or Memory Cache R eads 10-12 EEPROM Interfa c e 10-13 T rans mit T iming – S tart Of T rans mis s ion 10-14 Tra n sm it Tim in g – En d O f Tra n sm issio n ( la st b it = 1) 10-15 Tra n sm it Tim in g – En d O f Tra n sm issio n ( la st b it = 0) 10-16 R eceive T iming – S tar t Of P acket 10 - 17 R ecei ve T i mi ng – E nd Of P ack et 10-18 Collision T im ing – AUI 10-19 Collision T im ing – T P 10 - 20 L oopback T i mi ng 10-21 S QE Test Timing 10-22 Link Test Pulse 10-23 ROM Dump (Test Mod e) TABLE 10-1. LIST OF TIMING DIAGRAMS AC OPERATING CHARACTERISTICS AND TIMING 83C795

PARAMETER DESCRIPTION MIN TYP MAX UNITS T 1 R egi s ter R ead: data val i d del ay 3 – 5 Cycl es T2 Re g ist e r Re a d : d a t a h o ld t im e – – 15 n se c T 6 Addres s s etup for regis ter I/O – – 18 T 7 Ad d re ss ho ld fo r re g iste r I/ O – – 0 T 8 IO RDY ina c tive d e la y fro m I/ O stro b e – – 20 T 9 IO RDY a c tive d e la y fro m X1 – – 28 T 10 IOR DY tris tate delay from I/O s trobe – – 14 T 11 R egis ter write: data s et up time 15 – – T 12 R egis ter write: data hold time 20 – – T1 3 I O W a c t i v e t i m e 3 0 0 – – T1 4 I O R a c t i v e t i m e 3 0 0 – – T1 5 MCS 16 acti ve fr om L A addr es s (FINE16=0) – – 15 T2 0 M16CS i nacti ve fr om L A addr es s – – 13 T2 1 IO 1 6 C S a c t i v e f ro m SA a d d re ss – – 1 7 T2 2 IO 1 6 C S i n a c t i v e f ro m SA a d d re ss – – 1 5 T 23 I OR DY active del ay from HOS T CL K – – 25 T2 7 Z WS tris tate delay from S ME Mx s trobe – – 11 T2 8 Z WS acti ve fr om ME Mx s tr obe (1 6 bi t) – 9 13 T2 9 Z WS tris tate from ME Mx s trobe – – 11 T3 0 S ME MR acti ve to i nacti ve 425 – – T3 1 SM EM R a c t i v e t o ROMCS ac tive – – 155 T 32 ROMCS a c tive to S D va lid – – 270 T 33 R OM read: data hold time 15 – – T 35 S A addres s s etup for ME Mx s tr obe 18 – – T 36 S A a d ress ho ld for MEMx strob e – – 0 T 41 IORDY inac tive dela y from ME M strobe – – 23 T 42 IORDY ac tive dela y from X1 – – 27 T 43 IOR DY tris tate delay from ME M s trobe – – 17 T4 6 Z WS active delay from HOS T CL K – – 17 T 48 E E CS s et up time 100 – – T4 9 EEC S h o ld t im e 1 00 – – T5 0 R L E D s et up time 100 – – T5 1 RLED h o ld t im e 1 00 – – T5 2 EED O d e la y – – 200 TABLE 10-2. TIMING PARAMETERS 83C795 AC OPERATING CHARACTERISTICS AND TIMING

PARAMETER DESCRIPTION MIN TYP MAX UNITS T 53 MA addr es s acti ve del ay fr om X 1 – – 26 ns ec T 54 MA addr es s i nacti ve del ay fr om X 1 – – 10 T5 7 RAMWR a c tive d ela y from X1 – – 11 T5 8 RAMWR ina c tive d ela y from X1 – – 9 T5 9 M A a d d re ss se t u p t o RA M W R, RA M O E 1 0 – – T 60 MA addr es s hol d fr om RA M W R 1 5 – – T 61 Data val i d del ay ti me fr om X 1 – – 24 T 62 Data hol d ti me fr om RA M W R 1 5 – – T6 4 RA M O E a c t iv e d e la y f ro m X1 – – 12 T6 5 RA M O E in a c t iv e d e la y f ro m X1 – – 9 T 66 Data s etup ti me to X 1 12 – – T 67 Data hol d ti me to X 1 0 – – T6 8 XTXE se t u p t i m e t o XTXC 2 5 – – T6 9 XTXE h o l d t i m e f r o m XTXC 0 – – T7 0 XTXD h o l d t i m e f r o m XTXC 0 – – T 71 T X outputs delay to idle – – 310 T 72 T X outputs sta y high before idle 240 – – T7 3 XTXD se t u p t i m e t o XTXC 2 0 – – T74 TX o utp uts d e la y fro m XTXC - AUI – – 100 T X outputs delay fr om X T X C - T P – – 100 T 75 XCOL a c tive d ela y - AUI – – 60 T7 6 XC O L a c t i v e d e l a y - TP – – 9 0 0 T 77 XCOL ina c tive d ela y - AUI – – 350 T7 8 XC O L i n a c t i v e d e l a y - TP – – 1 6 0 T 79 XCRS ac tive delay - AUI – – 300 XC RS a c tive d e la y - TP – – 60 T 80 XCRS inac tive delay - AUI – – 250 XCRS inac tive delay - T P – – 160 T 81 Diffe re ntia l inp ut re je c t p ulse w id th - AUI 8 – 35 Differe ntia l inp ut rejec t p ulse w id th - T P 8 20 30 T 82 Acquis ition time from P L L - AU I – – 700 Ac q uisitio n tim e fro m PLL - T P – – 950 T83 XRXD sta b le fro m XRXC ±40 – – T 84 S QE test sta rt delay - T P – 900 – T 85 S QE test d ura tion - T P – 1000 – T 86 L oopback s etup ti me – – – T 87 L oopback hol d ti me – – – TABLE 10-2. TIMING PARAMETERS (cont.) AC OPERATING CHARACTERISTICS AND TIMING 83C795

PARAMETER DESCRIPTION MIN TYP MAX UNITS T 88 X 1 clock per iod 45 50 – ns ec T 89 X 1 cl ock wi dth hi gh 22 .5 25 – T9 0 X1 c l o c k r i se t i m e – – 3 T 91 X1 c loc k fa ll tim e – – 3 T 92 X 1 cl ock wi dth l ow 22 .5 25 – T 93 L i nk tes t pul s e wi dth – 100 – T9 4 I / O w r i t e r e c o v e r y t i m e 2 – – c y c l e s TABLE 10-2. TIMING PARAMETERS (cont.) NOTES 1. All numbers are in nanoseconds except where otherwise designated. 2. All outputs are measured under 50pF load. 3. The external Manchester Encoder/Decoder port is multiplexed out on other pins in certain test modes only. Use the table below to determine which Manchester signals correspond to which pin names. MANCHESTER SIGNALS 83C795 I/O PINS XTXD IRQ1 XLOOP IRQ2 XCRS IRQ3 XRXC IRQ4 XRXD IRQ5 XCOL IRQ6 XTXC IRQ7 XTXE ROMCS TABLE 10-3. TEST PIN I/O MATCHING Refer to Chapter 4 for more details. 83C795 AC OPERATING CHARACTERISTICS AND TIMING

MEMR, MEMW M16CS ZWS SA15 - SA00 LA23 - LA17 FIGURE 10-5. HOST MEMORY ACCESS (16-BIT, ZWS) AC OPERATING CHARACTERISTICS AND TIMING 83C795

MEMR, MEMW M16CS SA15 - SA00 LA23 - LA17 FIGURE 10-6. HOST MEMORY ACCESS (16-BIT, NO ZWS) 83C795 AC OPERATING CHARACTERISTICS AND TIMING 100

SMEMR, SMEMW SA15 - SA00 LA23 - LA17 FIGURE 10-7. HOST MEMORY ACCESS (8-BIT, ZWS) AC OPERATING CHARACTERISTICS AND TIMING 83C795 101

SMEMR, SMEMW SA15 - SA00 LA23 - LA17 FIGURE 10-8. HOST MEMORY ACCESS (8-BIT, NO ZWS) 83C795 AC OPERATING CHARACTERISTICS AND TIMING 102

FIGURE 10-9. ROM ACCESS (8-BIT ONLY, READ ONLY) AC OPERATING CHARACTERISTICS AND TIMING 83C795 103

FIGURE 10-10. DMA OR MEMORY CACHE WRITES 83C795 AC OPERATING CHARACTERISTICS AND TIMING 104

FIGURE 10-11. DMA OR MEMORY CACHE READS AC OPERATING CHARACTERISTICS AND TIMING 83C795 105

FIGURE 10-12. EEPROM INTERFACE 83C795 AC OPERATING CHARACTERISTICS AND TIMING 106

FIGURE 10-13. TRANSMIT TIMING - START OF TRANSMISSION AC OPERATING CHARACTERISTICS AND TIMING 83C795 107

(LAST BIT = 1) FIGURE 10-14. TRANSMIT TIMING - END OF TRANSMISSION 83C795 AC OPERATING CHARACTERISTICS AND TIMING 108

(LAST BIT = 0) FIGURE 10-15. TRANSMIT TIMING - END OF TRANSMISSION AC OPERATING CHARACTERISTICS AND TIMING 83C795 109

FIGURE 10-16. RECEIVE TIMING - START OF PACKET 83C795 AC OPERATING CHARACTERISTICS AND TIMING 110

FIGURE 10-17. RECEIVE TIMING - END OF PACKET AC OPERATING CHARACTERISTICS AND TIMING 83C795 111

FIGURE 10-22. LINK TEST PULSE 83C795 AC OPERATING CHARACTERISTICS AND TIMING 114

FIGURE 10-23. ROM DUMP (TEST MODE) AC OPERATING CHARACTERISTICS AND TIMING 83C795 115

11.0 PACKAGE DIMENSIONS

Fig ure 11-1 illustra tes the 160-p in PQFP p a c ka g e. FIGURE 11-1. 160-PIN PQFP PACKAGE 83C795 PACKAGE DIMENSIONS 116

LETTER MIN NOM MAX MIN NOM MAX A4 . 0 7 L 1 . 6 0 A1 0.05 0.5 P 0.65BSC A2 3.10 3.67 Θ 0° 7° D1 27.90 28.00 28.10 R1 0.20 E3 30.95 31.20 31.45 R2 0.30 E1 27.90 28.00 28.10 T D 30.45 H 0.10 2.20 T E 30.45 L 0.65 0.80 0.95 TABLE 11-1. PACKAGE DIMENSIONS Notes: 1. Coplanarity is 0.100 mm. maximum. 2. Tolerance on the position of the leads is 0.120 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimensions T D and TE are important for testing by robotic handler. 5. Dimensions for foot length L when measured at the centerline of the leads are given at the table. Dimension for foot length L when measured at the gauge plane 0.25 mm above the seating plane, is 0.78-1.03 mm. 6. Controlling dimension is millimeter. 7. Details of pin 1 identifier are optional but must be located within the zone indicated. PACKAGE DIMENSIONS 83C795 117

10BASE-T status LED driver reading back 29 16-bit host bus indicator 51 16-bit response to host access 51 83C585 compatibility with 83C790 19 83C690 similarities to 83C790 1 83C790 operating conditions 90 A Abort transmission field 39 AC operating characteristics 93 Accessing LAN register 67 Address decoders 46 Address generation path 49 Address modifiers 48 Address recognition logic 71 AEN 6 Alignment error counter register 23 ALTEGO 80 See buffering format selection Arbitration internal bus 50 AUI Collisions 6 AUI differential driver transmitter 74 AUI differential receiver receiver 69 Auto-configuration ports 57 Automatic polarity correct field 29, 75 Automatic ring wrapping 87 Avoiding SA and LA line conflicts 51 B Backoff counter field 24 Backoff timer 77 BALE 6 BIOS page register 17 Block diagram 1 Board ID register 19 Boundary page register 85 Broadcast frames 71 receiving 32 BSR 6 Buffer memory decoding 47 Buffer room remaining count registers 32 Buffer structure and data movement processes 80 - 89 Buffer underrun field 39 Buffer window size field 20 Buffering format selection field 26, 79 Burst starting address 35 C CAP 6 Carrier sense 69 Carrier sense lost field 39 Carrier sense monitoring 39 CD 69 CD+/CD- 6 Chaining multiple buffers 88 Check addresses/CRC without buffering field 31 Chip type indication field 18 Collision count register 24 Collision counter 77 Collision counter field 25 Collision detect heartbeat field 39 Collision detection 78 receiver 69 Collision handling logic 76 Collision translator 74 Command register 23 - 24, 78 Configuration register 55 Configuring Plug and Play as a boot card 64 Configuring Plug and Play with an I/O-mapped pipe 64 Control register 14 Controller registers 12 Conventions 3 Counter overflow enable field 27 Counter overflow field 28 Counting packet collisions 24 CRC checking 71 CRC error counter 25 CRC error field 33 CRC generation inhibition field 37 CRC generator 76 WAKE 59 Current frame buffer descriptor pointer registers 25 Current frame buffer pointer register 25 D Data configuration register 26 Data path description 3 INDEX 83C795 118

DC operating characteristics 90, 92 Deserialization of the receiver 70 Designating linked-list buffering 26 Designating ring buffering 26, 79 Designating the next DMA buffer 30 Determining the cause of an interrupt 28 DMA controller 65 assembly and disassembly latches 65 loopback testing 65 memory interface 68 memory interface unit (MIU) 65 microcontroller 67 DMA controller next buffer register 30 DMA memory interface 67 DMA microcontroller 67 E Early receive warning 71 Early receive warning count register 71 Early receive warning enable field 27 Early receive warning field 28 Early transmit checking 78 Early transmit checking (ENETCH & DISETCH) fields 24 Early transmit underrun protection 78 EECS 6 EEDO 6 EEROM interface overview 54 recall operations 54 register logic 55 storage of user-defined initial configurations 57 storage of user-defined LAN address 57 storage operations 56 unlocking write operations 56 EEROM address field 15 EEROM controller and its utilization 53 EEROM register 14, 54 Electrical specifications 90 - 92 Emitter-coupled logic 74 Enable interrupts field 17 End-of-transmit interrupt 26 Enhancement register 23, 26, 77 ERFBIT 72 ERW interrupt 71 Extensions beyond 802.3 79 External power supply control 64 F Features 1 FIFO structure 68 FIFO overrun field 33 FIFO underrun field 39 Frame alignment error field 33 Functional description 3 G General control register 21 - 22 General description 1 General purpose output (GPOUT) field 21, 64 Giant frames accommodating on a non-802.3 network 79 GPOUT 64 GPX pin value selection 16 Group address recognized field 33 H Hardware support register 16 Heartbeat detection 77 Heartbeat test 75 High RAM address field 20 Host bit width selection 16 Host interface address decoders 46 basic functions 44 EEROM controller and its utilization 53 I/O address decode 50 I/O-mapped pipe 46 internal bus arbitration 50 interrupt request control logic 52 introduction 44 memory address generation 48 memory bus structure 51 memory cache 44 Plug and Play 57 zero wait state response to the host 50 Host interface internal registers introduction 14 Host registers BIOS page register 17 board ID register 19 control register 14 EEROM register 14 general control register 21 - 22 hardware support register 16 I/O address register 19 LAN address registers 18 POS ID registers 19 RAM address register 20 ROM control register 20 83C795 119

I I/O address decode 50 I/O address register 19 I/O-mapped pipe 46 IGSM deferral field 33 INIT pins See MA03-MA00 Initialization 53 Initialize EEROM jumpers 15 INITRBUF 86 Inter-frame gap definition 76 Interframe gap and deference 76 Internal bus arbitration 50 LAN controller 67 Interrupt disabling 52 Interrupt mask register 27 Interrupt on end-of-transmit field 26, 82 Interrupt request control 52 Interrupt request field 21 Interrupt status field 16 Interrupt status register 28 INTMASK 71 IOR 6 IORDY 6, 44, 50, 67 IOW 6, 67 IPL ROM code 51 IRQ lines 6 J Jabber protection 75 Jumper6 22 L LA address bus 7 LAN address registers 18 LAN controller DMA 65 DMA memory interface 67 DMA microcontroller 67 FIFOs 68 how to access registers 67 internal bus arbitration 67 overview 65 - 79 receiver network interface 68 LAN controller registers alignment error counter register 23 buffer room remaining count registers 32 collision count register 24 command register 24 CRC error counter 25 current frame buffer descriptor pointer registers 25 current frame buffer pointer register 25 data configuration register 26 DMA controller next buffer register 30 enhancement register 26 interrupt mask register 27 interrupt status register 28 introduction 23 LAN Command register 23 manchester management register 29 missed packet error counter register 29 multicast filter table registers 27 offset addressing 23 page select 24 receive boundary page register 23 receive buffer end register 32 receive buffer starting address register 30 receive buffer table pointer registers 34 receive burst starting address registers 30 receive byte count registers 31 receive configuration register 31 receive packet status register 33 receive start page register 33 receive stop page register 34 received byte count register 26 station address registers 34 transfer buffer end register 37 - 38 transfer count registers 37 transmit buffer pointer registers 39 transmit buffer starting address register 36 transmit burst starting address registers 35 transmit configuration register 36 transmit frame length registers 36 transmit start page registers 38 transmit status register 38 LED test and enable fields 29 LEDs 76 Link integrity test field 21, 75 Link integrity test function 21, 75 Link status LED readback field 29 Linked-list buffering introduction 23 selecting 26 Linked-list buffering format 88 Linked-list receiver buffering 88 LIT 22, 75 LLED 7, 75 Loopback mode 69 LPOE 7 83C795 120

M M16CS 7, 51 M16EN 17 M16EN bit 45 MA lines 7 MAC protocol type select field 16 MAC receiver address recognition logic 71 basic functions 70 CRC checking 71 interface to manchester decoder 70 loopback paths 70 receive deserialization 70 receive protocol FSM 72 received byte counter and early receive warning 71 receiver blinding 73 reception process 72 MAC-to-PHY interface 74 Manchester decoder 69 Manchester enable/disable field 29 Manchester encoder 74 Manchester encoder/decoder enabling and controlling 29 Manchester management register 29, 74 Mask interrupt sources field 17 Memory 16-bit enable field 17 Memory address generation 48 Memory bit width select 7 Memory bus structure 51 Memory bus width control 51 Memory cache 44 advantages 44 read mode 44 staggered address transfers 45 using Micro-channel adapters 46 zero wait state response to host 45 Memory enable field 14 MEMR 7 MEMW 7 Missed packet counter register 72 Missed packet error counter register 29 Missed packet field 33 Modifying the transmit queue 82 Monitor mode 33 Multicast field table registers 27 Multicast frames receiving 32 Multiple packet transmissions 80 Multiple packet transmit mode 28 N Non-802.3 protocols 79 Non-8390 features enabling 26 Non-deferred field 39 - 40 Normal map buffering See ring-style buffering O Operating conditions 90 Operation on Micro-Channel adapters 46 Oscillator 74 OSR 7 Out-of-window collision field 38, 78 Overwrite warning enable field 27 Overwrite warning field 28 Ownership of buffers 82 P Package description 116 Package dimensions 116 - 117 Packet received enable field 28 Packet received field 28 Packet received intact field 33 Packet transmitted enable field 28 Packet transmitted field 28, 39 - 40 Page select field 24 PC-98 bus support 50 PHY-to-MAC interface 68 Pin list 5 - 11 PLED 69 PLI 1 Plug and play 57 auto-configuration ports 57 boot bit 20 buffer memory limitations 64 configuration and activation 59 configuration registers 59 configuring as a boot card 64 configuring with an I/O-mapped pipe 64 enable bit 22 isolation 59 plug and play jumper installed bit 16 PnP and I/O mapped pipe bit 19 resource string 62 states 58 PNJMP 16 PNPBOOT 20, 64 PNPEN 22 PNPIOP 19, 64 POS ID registers 19 83C795 121

Promiscuous reception field 31 Pulse train sourcing 64 R RAM address register 20 RAM base address field 20 RAM offset field 14 RAMCS1 8 RAMOE 7 RAMWR 7 Recall EEROM field 15 Receieve boundary page register 23 Receive abort frame field 31 Receive broadcast frames field 32 Receive buffer end register 32, 88 Receive buffer starting address register 30 Receive buffer table pointer registers 34, 89 Receive burst starting address registers 30 Receive byte count registers 31 Receive configuration register 31, 71, 73 Receive error enable field 28 Receive error field 28 Receive LED readback 29 Receive multicast frames 32 Receive packet buffering 83 Receive packet status register 33 Receive runt frames field 32 Receive start page register 33, 88 Receive stop page register 34 Received byte count register 26 Received byte counter 71 Receiver blinding 73 Receiver disable field 33 Receiver fields 72 CRC field 73 DA field 73 end-of-frame 73 SA and data fields 73 SFD field 73 Receiver network interface 68 Receiver protocol FSM 72 Recommended operating conditions 90 Register overview 12 Relocating RAM and ROM base addresses in tandem 48 RESET 7, 53 Reset network interface controller field 14 Reset status field 28 Resource string 62 Restart field 16 Retrieval and storage of host configuration registers 54 Revision number indication field 18 Ring arrangements 86 Ring of buffers 83 Ring-buffering selecting 26, 79 Ring-style buffering introduction 23 RLED 8 ROM base address field 21 ROM control register 20 ROM offset field 17 ROM size selection 48 ROM window size field 20 Runt frames receiving 32 Runts frames receiving 71 RX+/RX- 8 S SA address lines 8 Save error packets field 32 SBHE 8, 51 SD data lines 8 Sending multiple transmissions 80 Single packet transmission 80 Slot timer 77 Smart squelch digital noise filter 69 SMEMR 8 SMEMW 8 Software interrupt field 17 SQE test 75 Squelch circuitry 69 Staggered address transfers 45 Start bit field 24, 72 Start page 38 Start page register 33 Start-of-frame delimiter (SFD) 70, 73 Station address registers 34 Status indicators 75 Stop backup modifications 26 Stop bit field 24, 72 Stop page register 34 Store to non-volatile field 15 Supporting non-802.3 protocols 79 Switch register bit 14 Switch register set 16 83C795 122

T Timers backoff timer 77 collision counter 77 heartbeat detection 77 slot timer 77 truncated binary exponential backoff algorithm 77 Timing diagrams 93 - 115 parameters 94 TLED 9 TPR+/TPR- 9 TPRX polarity LED readback field 29 TPX+/TPX- 9 TPX1/TPX2 74 TPX2+/TPX2- 9 Transfer buffer end register 37 - 38, 80 Transfer count registers 37 Transmission initialization 77 Transmission process 77 Transmit buffer pointer registers 39, 80 Transmit buffer starting address register 36, 80 Transmit burst starting address registers 35 Transmit configuration register 36, 76 Transmit error enable field 28 Transmit error field 28, 78 Transmit frame length registers 36, 80 Transmit LED readback 29 Transmit packet initiation field 24 Transmit packets buffer ownership 82 multiple packet transmissions 80 single packet transmission 80 transmit queue modification 82 Transmit protocol FSM 76 Transmit queue modifying 82 Transmit serializer 76 Transmit start page registers 38 Transmit status register 38, 78, 80, 82 Transmit underrun 78 Transmitted with collisions field 39 - 40 Transmitter basic function 76 collisions 78 CRC generator 76 early transmit underrun protection 78 extensions beyond 802.3 79 FIFO 77 initialization 77 operation 77 preamble generator 76 timers 77 transmission process 77 transmit protocol FSM 76 transmit serializer 76 transmit underrun 78 Transmitter network interface 74 Transmitter operation 77 Twisted-pair differential driver transmitter 74 Twisted-pair differential receiver 69 TX+/TX- 9, 74 TXD 76 U Unlock EEROM storage field 15 Using an external EEROM 54 V VDD pins 9 VSS pins 9 W Wait state selection 26 WaitForKey 58 WRAPEN 87 X X1/X2 9, 74 XTXD 76 Z Zero wait state enable field 21 Zero wait state in 16-bit transfers 52 Zero wait state response to the host 50 ZWS 9, 50 - 51 response to host 45 83C795 123