SMC34C60

SMC34C60 ETC1 | Alldatasheet

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@ SMC34C60 PRELIMINARY STANDARD MICROSYSTEMS CORPORATION Parallel Port Interface Chip - Peripheral Side

FEATURES

®@ Creates PC/AT-Style Bus from Parallel @ FIFO Operation Permits Overlapping Printer Port Signals Parallel Port and Peripheral Bus Cycles for © Single Chip Interface to Any Bus Capable Maximum Data Transfer Rate Peripheral © Flexible DRAM Buffer Support and DMA © Supports Standard, Bi-Directional, EPP, Capability and ECP Parallel Ports © Four Output Lines Individually ®@ Burst Mode for Improved Data Transfer Configurable as Chip Selects or General Rates Purpose Outputs ® Adaptive Interface Optimizes Transfer © =Three Output Lines Individually Rates to Parallel Port Characteristics Configurable as Strobes or General ® Digital Signal Filtering increases Noise Purpose Outputs Immunity @ Four Uncommitted Inputs ® Allows Daisy-Chain of up to Eight © Watchdog Monitors Host Computer Peripherals Including Standard Printer Activity @ Provides Interrupt Sharing with ®@ Low Battery Detect Input Daisy-Chained Devices © Direct Output for Piezo Transducer @ 16-Bit Product ID Support © Support for Automatic Power Up/Down © Peripheral Bus Clock Selectable at System © Prevents Host System Latchup with Clock /2, /3, /5, or /6 Powerback Control ®@ = Interfaces to 8-Bit and/or 16-Bit ©@ On Chip Crystal Oscillator Peripherals GENERAL DESCRIPTION The SMC34C60 provides a means of handles breaking up 8- and 16-bit ISA data into re-generating an IBM® AT® style (ISA) bus from 4- or 8-bit chunks for the parallel port. the PC printer port signals. in addition to Standard (Compatible) printer ports, the The SMC34C60 also provides a piezo SMC34C60 supports PS/2® (bi-directional), EPP, transducer driver for battery-powered systems. and ECP ports. Up to eight peripherals may be The transducer will signal low battery with two daisy chained between the computer and the repeated beeps. If the cable to the computer is printer. Printer operation is unaffected. disconnected, or if the host is dormant for about a minute, the transducer will signal The SMC34C60 performs as an intelligent data inactivity with four beeps. Additionally, a mux. It multiplexes the printer port signals Power-down signal can be provided to external between the daisy chain (pass-through) outputs Circuitry to automatically shut down system and the re-generated ISA bus. Furthermore, it power during inactivity. M@™ 4564646 0011155 T2T

TABLE OF CONTENTS : FEATURES oo 0... ccc cc cecee cece eee eeeeeeeseeteeteteerereese 4 PIN CONFIGURATION 1.0.0.0 0 000s ceseeeeeveeseseeeseeeeseeeeees 3 FUNCTIONAL DESCRIPTION . 0.0.0.0 6 000 ccc ccesceeeeveveeseeeesses 13 SMC Component Products Division

300 Kennedy Drive

Hauppauge, NY 11788 (516) 435-6000 FAX (516) 231-6004 ME 8564686 OOLL1Sb Sbb

‘ PIN CONFIGURATION 353339358359 909555508822555553 fatuvalafatalstalatelaletststolnlalsVals\\atalabetatalatalatel (00 70 7077 707674787271 70.008 67 68 06 846342 6160 6060.7 Ga5 6469 2 81 meg a 9D nd 436 scr nO ew 4D Ro cod 476 oreo oar ws “5 ced 465 DK cad 0 4B sto HOO ob st ein] 0 |b sr voo C] #0 1B vos woe SMC34C60 SB oSan asd a 205 Piezo sas] wore erst Cl os a6 sa xanscux) C] 00 as tot our c] a6) RESET pox C] 9 200 sense Ne] 9 2D vw esr Cf 100 a1 Fyour 1294507 so wnsUs BTU DAZ BABA w GRE OG BESS HE SIGE Eagee SEEGER) DESCRIPTION OF PIN FUNCTIONS BUFFER SYMBOL TYPE DESCRIPTION PARALLEL PORT HOST CONTROL AND COMMON DATA BUS INTERFACE Host:Strobe HSTB 1,PU An active low pulse on this input is used to strobe printer data into the printer. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. Host:Auto Line HALF This input goes low to cause the Feed printer to automatically feed one line after each line is printed. Connects to AUTOFD output from Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. M™ 6564686 001115? 672

DESCRIPTION OF PIN FUNCTIONS t BUFFER TYPE DESCRIPTION Host:Selectin HSEL This active low input is driven by the host to select the printer. Connects to SELECT IN output from Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. (See Note 1 on Page 11.) Host:Initiate Fini This active low input initiates the printer when low. Connects to INIT output from Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. (See Note 1 on Page 11.) Host: HACK This active low output from the Acknowiedge printer is used to indicate that the printer has received the data and is ready to accept new data. Connects to the ACK input to the Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes.

26 Host:Busy HBSY This status output, generated by the

printer, goes high to indicate that it is not ready to receive new data from the host. Connects to the BUSY input to the Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. Host:Paper End This status output, generated by the printer, goes high to indicate that the printer is out of paper. Connects to the PERROR input to the Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. M@™ 6564646 0011158 7395

: DESCRIPTION OF PIN FUNCTIONS BUFFER SYMBOL TYPE DESCRIPTION Host:Printer HSLCT This status output, generated by the Selected printer, goes high to indicate that the printer is selected. Connects to the SELECT input to the Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. Host:Printer Error | HERR. This status output, generated by the printer, goes low to indicate an error condition at the printer. Connects to the ERROR input to the Host. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. 5,8,13, | Host:Data[0:7] HD[0:7] O16, | Parallel port bi-directional data bus 15-18, PU connected to host system is used by

20 SPP, ECP and EPP to transfer data

peripherals. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. Pass-Through: PSTB An active low pulse on this output is Strobe used to strobe printer data into the printer. Connects to the STROBE input on the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. 27 ‘| Pass-Through: PALF This output goes low to cause the Auto Line Feed printer to automatically feed one line after each line is printed. Connects to the AUTOFD input on the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. MM 6564686 0033159 675 a

DESCRIPTION OF PIN FUNCTIONS : BUFFER SYMBOL TYPE DESCRIPTION Pass-Through: PSEL 016 This active low output selects the Selectin printer. Connects to the SELECT IN input on the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. Pass-Through: PINIT This active low output initiates the Initiate printer when low. Connects to the INIT input on the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. Pass-Through: PACK This active low input from the printer Acknowledge is used to indicate that the printer has received the data and is ready to accept new data. Connects to the ACK output from the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes.

7 Pass-Through: PBSY This status input, generated by the

Busy printer goes high to indicate that it is not ready to receive new data from the Pass-Through. Connects to the BUSY output from the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP/EPP modes. Pass-Through: 4, PU This status input, generated by the Paper End printer, goes high to indicate that the printer is out of paper. Connects to the PERROR output from the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. M@™@ 6564686 0011140 397

DESCRIPTION OF PIN FUNCTIONS BUFFER SYMBOL TYPE DESCRIPTION

1 Pass-Through: PSLCT This status input, generated by the

Printer Selected printer, goes high to indicate that the printer is selected. Connects to the SELECT output from the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP/EPP modes. Pass-Through: 1, PU This status output, generated by the Printer Error printer, goes low to indicate an error condition at the printer. Connects to the ERROR output from the next device along the chain. Refer to Section 4 of the IEEE STD 1284 (Reference 1) for use of this pin in ECP and EPP modes. SYSTEM (REGENERATED ISA PERIPHERAL) INTERFACE

96 System XIN (SCLK) XIN may be connected to a ttl

Clock/Crystal peripheral system clock or a crystal may be placed across XIN/XOUT 97 XOUT (typically 24MHz). This is used to derive the internal clock (BUSCLK) used for all system interface timing. 80-73 | System Address | SA[0:7] These lower eight address bits are [0:7] presented to the system bus directly by the SMC34C60 during bus and DRAM access. Upper address bits, if needed, should be latched through use of the SMC34C60's strobe lines prior to generating bus accesses. 70,69 | Memory Address | MA[8:9] These address bits are appended to 18,9] SAIO:7] to create a 10-bit row or column address for DRAM access. 68-61, | System Data SD[0:15] 08, These bi-directional pins are used to 58-51 | [0:15] PU transfer data during bus or DRAM cycles to or from the system. MB 65b4b6b 0011161 223

DESCRIPTION OF PIN FUNCTIONS , BUFFER SYMBOL TYPE DESCRIPTION

88 System Read ‘SRD This indicates that a bus read cycle is

occurring, similar to an ISA MEMR signal. System Write SWR This indicates that a bus write cycle is occurring, similar to an ISA MEMW signal. 16-Bit 1/0 This signal is asserted by the remote system to indicate whether or not the address being accessed is capable of a 16-bit transfer. Interrupt Request This rising edge activated signal indicates an interrupt request from the System. System Reset SRST This low going signal can be used to reset the System. This signal is asserted for 16 SCLKs. System Reset SRST This high going signal can be used to reset the System. This signal is asserted for 16 SCLKs.

92 Row Address RAS This low going strobe signal is used

Strobe by the DRAM to latch the row address, present on the SA[0:7] and MAI8:9] pins. This output drives the DRAM directly, however a series resistor is recommended on this line. Column Address | CAS This low going strobe signal is used Strobe by the DRAM to latch the column address, present on the SA[0:7] and MAI8:9] pins. This output drives the DRAM directly, however a series resistor is recommended on this line. DMA DACK This active low output signal is issued Acknowledge to inform the System that data is to be transferred using DMA transfer cycles. WM! 4564686 OOlL1b2 1bT

DESCRIPTION OF PIN FUNCTIONS BUFFER SYMBOL TYPE DESCRIPTION Terminal Count | TC This active high output is asserted with the last DMA data transfer to indicate to the System that the DMA data transfer is complete. TC is asserted in conjunction with DACK.

47 DMA Request The remote system indicates that it is

ready to perform DMA transfers by driving this line high. This signal is asserted as long as the System is ready to receive or send data and is deasserted on the last byte of the data transfer. MISCELLANEOUS Watchdog Enable | WOOGEN Pulling this line low enables the watchdog. The watchdog will generate four beeps on the piezo driver if there are no transitions on the host port lines for a minute. This circuitry can also automatically power down the system when the watchdog "barks". This feature requires software to tickle the port every 30 seconds. Reset Chip RESET Pulling this line low for two SYSCLKs will reset the SMC34C60 to its initial state. This will reset all internal registers to their default values. Low Battery TBAT A low level on this input line signals Indicator that the battery power is low and the SMC34C60 will generate low battery tones. It is the responsibility of the emote system to monitor battery power and generate this input signal. 82,83, | General Purpose The host may obtain the level at 37,36 | Inputs [0:3] these pins by reading the Internal . Input Register. MH 8564686 0011163 OTL

DESCRIPTION OF PIN FUNCTIONS 1 BUFFER SYMBOL TYPE DESCRIPTION Piezo Crystal This high current output can be Drive directly hooked up to a piezo speaker to provide audio tones. 44,43, | Strobes(0:2] ST(0:2] These pins are individually configured 42 (special function) as general purpose outputs or as strobe outputs as programmed in the Output Configuration Register. ST2 may also be programmed as the Auto-Power pin. 84-87 | Chip Selects(0:3] | CS[0:3) These pins are individually configured (special function) as general purpose outputs or as chip select outputs as programmed in the Output Configuration Register.

32 Oscillator Input YIN A parallel resonant crystal or RC

network may be placed across YIN 31 Oscillator Output | YOUT and YOUT. This nominal 32KHz clock (32.768KHz) is used by the internal piezo driver and watchdog timer. Selected Device | SLCTD This signal is an active high output that indicates that the device is the active device on the daisy chain. This may be used for debug purposes, to enable drivers, or to qualify signals. Product !D This signal is an active low output asserted when the host performs a request for the peripheral’s Product ID. This function is used by the daisy chain and multiplexor protocols. MB 65b4b8b OOL11b4 T32 ml

, DESCRIPTION OF PIN FUNCTIONS BUFFER SYMBOL TYPE DESCRIPTION Sense VCC When pulled high, this input will enable all output drivers of the SMC34C60. When low, all outputs are tri-stated. This resolves the back- power problem inherent in parallel port peripherals. Isolate the chip‘s VCC from the rest of the peripheral’s VCC using a schottky diode. The SENSE input should be tied to the peripheral’s VCC and the anode of the diode. In this manner, when the peripheral’s power is off, the sense input will shut down all outputs, preventing the chip from driving into a low impedance load and consequently damaging the chip‘s input protection diodes. Test Counters TEST This is an active high signal that allows access to some large counter chains that are normally buried within the chip. For normal operation this input should be left unconnected, or tied to ground. For more information on the test mode contact the factory. BUSCLK BCLK BUSCLK is the SCLK divided by the value programmed in the Configuration Register. | 99 [Reserved [RESERVED |__| Leave floating, no connection 9,21, vcc +5 Volt supply pins. 41,60, 72,90 10,22, Ground pins 40,59, 71,91 Note 1: By pulling both these lines low (illegal state), the SMC34C60’s output ports can be disabled. M@™@ 6564686 0011165 979

1 Input, Schmitt Trigger

08 Input, Schmitt Trigger/8mA Output

016 Input, Schmitt Trigger/16mA Output

PU Pull Up, nominal 100K PD Pull Down, nominal 100K GENERAL CONVENTIONS Throughout this document, the following various terms and conventions will be used: Compatible = “Centronics” SPP = "Standard Bi-Directional Parallel Port" (PS/2) EPP = "Enhanced Parallel Port" ECP = "Extended Capabilities Port” REFERENCE DOCUMENTS 1. IEEE STD 1284, February 2, 1993. 2. The Enhanced Parallel Port, an Introduction; FarPoint Communications. 3. Daisy Chain Specification, Rev. 1.1, September 16, 1993; Disctec Corporation. 4. Enhanced Parallel Port BIOS Specification, Rev 3, February 12, 1993; FarPoint Communications. 5. ECP: Specification Kit, Rev 1.03, February 10, 1993; Microsoft Corporation. MM 656486 OOll1bb 805 mm

SMC34C60 BLOCK DESCRIPTION The Protocol Translator block gives the SMC34C60 its capability to communicate with The SMC34C60 can be broken down into eight the parallel port in either SPP, EPP, or ECP functional blocks as shown in Figure 1. mode. The Protocol Translator interprets the Multiport Access Protocol (MAP) packets The SMC34C60 implements and complies with described in the Daisy Chain Specification the Daisy Chain Specification (Reference 3) (Reference 3), The MAP packets and command through the Daisy Chain Protocol block. Under codes are described in the Daisy Chain the Daisy Chain protocol, the SMC34C60 Command Protocol. The Protocol Translator operates in either Pass-Through or Selected also decodes the type of parallel port transfer mode. Pass-Through mode is the power up (ie. Address Write/Data Read_Write Cycle) and default, and is electrically transparent to devices provides the proper control of the data to the further down the chain. When in Pass-Through Registers and Control block and to the Bus mode, the Data Switch gates the control and Interface block. The SMC34C60‘s internal Status lines of the parallel port to the Pass- registers, contained in the Register and Control Through port. Selected mode connects the block, control the operation of the chip’s System Interface bus to the parallel port. When internal DRAM Controller, DMA Controller, and in Selected mode, the Data Switch gates the Watchdog Controller. The Bus Interface block control and status lines to the SMC34C60's controls data transfers between the Parallel Port Protocol Translator functional block. and the peripheral’s System Interface Bus. The MUX block routes data and control signals to the System Interface. [=] Registers Heed pany end |) doen | Chain in Control ‘SPEAKER Protocol i [ee | a] "SPP mynd EA cpp P88] Jey tes ECP eve Parale! DRAM Port Controller fw f=) z i—l sysreM < INTERFACE | Pass-Through sy Port : a aon Se BS Sst mm Om ro FIGURE 1 - INTERNAL BLOCK DIAGRAM ME 8564686 0012167 741 Mm

DAISY CHAIN COMMAND PROTOCOL format of the MAP packets is as follows: . . - - AA 55 00 FF 87 78 x FE The daisy chain protocol is used to select the “Escape Sequence | Command Terminator mode of each device and to allow connection of up to eight devices on one paraliel port. The The cornmand byte in the MAP packet daisy chain commands use the Multiport Access represents a code and possibly an address as Protocol (MAP) to access the devices. The well. The currently defined codes are: (00-07) 0000 Oaaa Assign address aaa to the current device (08-OF) 0000 1aa@ Query Interrupt from device aaa (10-17) 0001 Oaaa Query Product ID from device aaa (20-27) 0010 0aaa Select device aaa in EPP mode (30) 0011 xxxx De-select all devices (40) 0100 Oxxx Disable Daisy Chain Interrupts (48) 0100 1xxx Enable Daisy Chain Interrupts (50-57) 0101 Oaaa Clear Interrupt Latches on device aaa (58-5F) 0101 1aaa_ Set Interrupt Latch on device aaa (DO-D7) 1101 Oaaa Select device aaa in ECP mode (E0-E7) 1110 Oaaa Select device aga in Compatible Mode - SPP aaa = Device Address xxx = Undefined - set to zero Refer to the Daisy Chain Specification (Reference 3) for rnore information. M@@ 8564686 0011158 645

PERIPHERAL SYSTEM DESIGN Note that the Parallel Port Data Bus is not switched through the SMC34C60; this allows The SMC34C60 simplifies the design of a all daisy chained devices to receive a special peripheral to exploit the benefits of IEEE STD “out of band” Control Packet as defined in the 1284, Standard Signaling for a Bi-Directional Distec Daisy Chain Specification (Reference 3). Parallel Port (Reference 1). Figure 2 depicts a hightevel System Block Diagram which shows the peripheral chip’s three primary data paths. System Interface __ BsTe P16 tar a nar AF ser pe | ant a P fg —— | ack Pack Lag | sx SMC34C60 wv ds 7 <<] he vo [gs Sg ister psicr [ay] er era Pp T ° H R R T Parallel Port Data Bus u Host Pass-Through Parallel Post Parallel Port Connector Connector FIGURE 2 - SYSTEM BLOCK DIAGRAM MH 4564686 00143169 514

DEVICE ADDRESSING The SMC34C60’'s address mode is set through an SPP, EPP, or ECP address write operation. The Bi-Directional Parallel Peripheral Interface Table 1 specifies the control signals used by Protocol, defined by the IEEE STD 1284 each protocol to perform Address and Data (Reference 1), describes two basic types of 8- Cycles and to indicate reverse data flow. Refer bit information transfers: data read/write to the IEEE STD 1284 (Reference 1) for further operations and address read/write operations. information. The SMC34C60's bus and internal registers are accessed via data read/write operations. Table 1 - Key Address/Data Cycle Signals Address = Data _ Reverse Channel INIT=0 IMPLICIT INIT =0 Signal The Parallel Port provides a byte-wide parallel this parallel port data path during an address data path. Figure 4 defines the data bits of write operation to the SMC34C60. D7 Dé DS D4 D3 D2 D1 DO pt [wietu|atatalal ~ Bus or Register Address Type of Access Write/Read FIGURE 4 - PARALLEL PORT ADDRESS WRITE DATA BITS MH 46564686 OOLL171 172

An address write cycle is used to select the Unrestricted System Data Bus access can also SMC34C60's address mode for subsequent occur following Address Write operations where data write cycles. Table 2 shows ten types of 1WBMA,A,A,Ag = 1X00{(A3-A0), except that Address Modes into which the SMC34C60 may in this short hand addressing mode A3-A0 is be placed. The address write data byte required also written to the least significant four bits of for each mode is encoded as ‘1WBMA,A,A,A,’. the SMC34C60 internal Address Register. Address Write operations where Table 2 also illustrates three separate System JWBMA;A,A,Ay = 1X01{A3-A0) provides Data Bus addressing modes along with DRAM block count limited System Data Bus access and Internal Registers addressing. with shorthand addressing. When the Host Address Write data is For example, an Address Write operation in 1X100XXX, the SMC34C60 provides which B = 1, M = 0, and A,A,A,Ay = 0000 unrestricted System Data Bus access for all selects System Data Bus access but does not subsequent Host Parallel Port data exchanges. alter the value of the SMC34C60 Address Bus, SAIO:7]. Table 2 - Address Mode Operations 1WBM A,A,A,A,| Access Type | | W=1(Write) | _W=O'Read) 1X00 = (A3-A0) Unrestricted Bus Write | Unrestricted Bus Read (Shorthand Mode) (Shorthand Mode) 1X01 (A3-A0) Block Restricted Bus Block Restricted Bus SYSTEM DATA Write (Shorthand Read (Shorthand Mode) Mode) 1X10, OXXX Unrestricted Bus Write | Unrestricted Bus Read (BUS) Access Access 1X10 1XXX DRAM Write Access DRAM Read Access (DRAM) 1X11 RRRR INTERNAL Write Internal Register | Read Internal Register REGISTERS RRAR RRRR W = Write B = Bus M = Max Count A,AAiAy = Address Selector RRRR = Register Selector MH 6564686 0011172 OOF

INTERNAL REGISTER MAP the binary value of AjA,A,Aq (bits-3:0), also . shown as RRRR. Internal register RARR is made The internal registers of the SMC34C60 are available for Read or Write based on the bit selected by performing an Address Write Cycle value of W (bit 6) as shown below. All internal with bits B and M (bits 5 and 4) set to 1,1 (see registers are eight bits wide. Table 2). The desired register is selected by Table 3 - Internal Register Map [we] em | Aaaa [REGISTER DESCRIPTION | DEFAULTS [x [11 [0000 [Adress Resist 00+ [x [11 [0001 | Ovtput Conigwtion Rea | __10 | [fr [coro | __outnut Reniter | ao [1 [11 | 0011 | sound Register| _na__| De [| 001 | toput Resistor its | [x [11 [0100 | peration Reiter | 00 _| [ac] 11 [0101 | DRam Butter sre Reser | _oc | Px [ [oro | Host BRAM Butter Poiner | 00 | Da [ 11] 0111 _|__oMA ona autterPonter [00 | Px [11 [1000 | — Host Max lock Count -Low | 00 _| Pac] 11001 | — Host wax Black Count “High [10 Pf 1 | to1o | BMA Byte Count tow | 00 | Px fom ftom | pMasyte Count -High | 00 Px [11100 | contigration Reaister | 04 _| [ro [11 [1101 | Ovo Revision tever | 00 _| [a1 _[_1110_[ Por Test Register | Wa [oe [1 _|_1110 | Port Test Resister | 00 _| [a [ 1 [a1 [bata Transtar Convot nasier | 01] X = Read/Write 1 = Write 0 = Read MH 6564646 0011173 THS

REGISTER DESCRIPTIONS (sector). Set MAXCNT (Configuration Register bit 6) and set the value of Host Max Block . ADDRESS REGISTER - 0000 (Read/Write) Count Register to the length of the IDE data block to read only the desired amount of data The value in the Address Register represents (1 sector) from the peripheral. the current address presented to the Bus Address lines SA[0:7]. The primary method of If M = O, then the current setting of MAXCNT updating this value is the following sequence. and Host Max Block Count are ignored. This First the Address Register is selected to be allows polling of a status register without written to by performing an Address Write limiting the number of times the register may be operation (KWBMA,A,A,Ap =x1 110000). Next accessed. a Data Write operation is issued to write A<0:7> as a group equal to the value The SMC34C60 directly provides eight address presented on the parallel port host data lines lines. If more than eight bits of address are HD[O:7]. necessary, three strobe lines are available which may be used with external circuitry to latch A shorthand mode is also provided to allow the higher-order address bits off of SA[O:7]. For Address to be modified and Bus Operation to be example, the address register can be written selected in one Address Write operation. If B = with higher order address bits and latched with 0, then bus operation is selected and A,;A,A,Ag one or more of the three programmable strobe is written to A<0-3>; A<4-7> are lines. The address register is then written with unaffected. In this mode, if M = 1, then the AO-A7, and normal bus reads/writes follow. bus access will be limited by the Host Max This scheme may be extended to any size Block Count Register. Any attempts to read address bus needed. more data will return invalid data. The SMC34C60 contains an integrated FIFO to An auto-increment option may be activated by enhance performance by reading the Bus one or setting AUTOINC (bit 4 in the Operation two bytes ahead of the Host Port. As an Register, RRRR=0100} which will increment example, some devices such as IDE hard drives A<0:7> after each bus access. expect data to be read ina fixed block length M@™ 6564686 0011174 16)

OUTPUT CONFIGURATION REGISTER - 0001 (Read/Write) [eer [are [oes [ oee [ oes | oa [ oni | ono] [_ser_[ seo [ sor [ soo | cos [coz [cor [coo | The Output Configuration Register defines the pins (inverting), or as special function output operation of the bits in the Output Register. pins. The special functions are: Chip Select, Strobe, and Auto-Power. The SMC34C60 has eight independent output lines. The functionality of seven of these The eighth (non-programmable) output line is output lines is selected through the Output controlled by Output Register bit 7. This output Configuration Register. All eight output lines line is defined as "Bus Reset", but it is simply are then controlled or activated through the an output bit. It may be used for other Output Register (RRRR =0010). purposes if a Bus Reset signal is not required or generated elsewhere. This bit is present on two The seven programmable output lines controlled pins (95 and 94) in both normal and inverted by Output Register bits 0-6 can be selected to polarities. operate as either general purpose output Bits 0-3: SPECIAL FUNCTIONS FOR PROGRAMMABLE OUTPUT LINES 0-3: Programmable output lines 0-3 can be Output line WV (N = 0...3) is controlled through individually configured as General Purpose Output Register Bit N. Output line WN, {inverting) outputs or as chip select outputs. configured as a General Purpose output, will Chip selects are generated by the bus cycle Present the inverted value written to Output state machine. Register bit V. Output line W, configured as a Chip Select, will follow the bus chip select if During a bus cycle, the chip select goes low at Output Register bit Vis a 1. the start of the cycle and remains low until the end of the cycle. Bit 0:COO - Chip Select 0/Standard Output 0 ; oF Select Output line O (Pin 84) as a General Purpose inverting output. 1 Select Output line 0 (Pin 84) as a Chip Select output. Bit 1:CO1 - Chip Select 1/Standard Output 1 ; od Select Output line 1 (Pin 85) as a General Purpose inverting output. [____1 ___] Select Output tine 1 (Pin 85) as a Chip Select output. ME 6564646 0011175 618

Bit 2:CO2 - Chip Select 2/Standard Output 2 . a ee Select Output line 2 (Pin 86) as a General Purpose inverting output. [1 J Select Output tine 2 (Pin 86) as a Chip Select output. Bit 3:CO3 - Chip Select 3/Standard Output 3 fos Select Output line 3 (Pin 87) as a General Purpose inverting output. [1 __] Select Output line 3 (Pin 87) as a Chip Select output. Bits 4-7: SPECIAL FUNCTIONS FOR PROGRAMMABLE OUTPUT LINES 4-6 Programmable Output lines 4-6 can be necessary for this passively pulls down the INIT individually configured as general purpose line from the host. The power supply is turned (inverting) outputs or as strobe outputs. These on when the INIT line rises to a high logic level. strobe signals may be used to clock any The SMC34C60 will then monitor the host, and edge-triggered flip-flop or register. Additionally, will bring the Auto-Power pin to a logic low Programmable Output line 6 may be level when the power can be shut off. programmed as an Auto-Power pin. This signal allows a peripheral to automatically control its Output line N, configured as a Strobe signal, is power on state, so that a separate power normally high and pulses low momentarily when switch is not necessary. The external circuitry a 1 is written to Output Register bit WV. Bit 4:SO0 - Strobe O/Standard Output 4 fo sd” Select Output line 4 (Pin 44) as a General Purpose inverting output. [a Select Output line 4 (Pin 44) as a Strobe output. Bit 5:S01 - Strobe 1/Standard Output 5 food Select Output line 5 (Pin 43) as a General Purpose inverting output. [| _—_1 ——_J Select Output line 5 (Pin 43) as a Strobe output. Bit 6,7:SP0,SP1 - Auto-Power/Strobe 2/Standard Output 6 | ___Ox __| Select Output line 6 (Pin 42) as an Auto-Power Pin. [| tos” Select Output line 6 (Pin 42) as a General Purpose inverting output. [14,1 _| Select Output line 6 (Pin 42) as a Strobe output. MM 4564686 OOLL17b 754 me

OUTPUT REGISTER - 0010 (Read/Write) [ev [ons | one [ore | ms [m2 [| om [ ero] STB1 STBO cs3 cs2 cst cso STB2 Each Output Register bit independently controls AUTO-POWER OUTPUT the operation of its respective Output pin. The function of each output pin, except for BRST Output line 6 (Pin 42), when programmed as (Pins 94 and 95), is determined by the data Auto-Power (PWR), via the Output stored in the Output Configuration Register. Configuration Register, will remain at a high level as long as host activity is detected. When CHIP SELECT OUTPUTS. the chip determines that power may be shut off, this pin will go low. Output lines 0-3 (Pins 84-87} are programmable as Chip Selects (CSO-CS3) via the Output There are two mechanisms driving this output. Configuration Register. When programmed as The first mechanism monitors the levels on the a Chip Select, the output pin will go low during host port. If the port assumes the terminated bus operations if its associated bit in the Output levels or all low levels for 16 to 20 seconds, Register is set. If ihe associated bit is not set then the host is presumed off (or disconnected). in this register, the output pin will remain high. The second mechanism monitors Host port activity (signal transitions). After a one minute period of inactivity (given that the WOOGEN pin STROBE OUTPUTS is tied low) the watchdog will be triggered sending four beeps to the piezo driver. After Output lines 4-6 (Pins 44-42), when completion of the tones the Auto-Power pin will programmed as strobes {STBO-STB2) via the go low. Output Configuration Register, will pulse low for two BUSCLK periods when the associated GENERAL PURPOSE OUTPUTS bit is set. The strobes recover and may be re-written at any time. Note: the strobe Output Bit 7 (BRESET) and any other bits that are Register bits are reset automatically after the programmed through the Output Configuration strobe is generated. Register as general purpose output bits are inverted and passed to the associated output pin. MM 8564686 0011177 690

SOUND REGISTER - 0011 (Write Only) [ae7 [eee [ees [ees [ers [ sr2 [| err | sito | [raco | trone | srone [source [eva | rod | rows | vow] These bits allow the piezo driver to generate Bit 5:STONE tones under program control. Setting this bit generates a 1/8 second tone. This bit self-clears after the tone is generated Bits 0-3:rsvrd and when set again will generate another 1/8 These bits are reserved and should be written second tone. as zeros. Bit 6:LTONE Bit 4:SQULCH Setting this bit generates a 1/2 second tone. Setting this bit terminates currently active low This bit self-clears after the tone is generated battery tones. If the low battery input (Pin 35) and when set again will generate another 1/2 goes high, and then low again after this bit is second tone. set, low battery tones will resume. In order to squeich these low battery tones, this bit simply Bit 7:FREQ needs to be re-written with a logic "1". This bit selects the Nominal frequency for the piezo driver circuit. O selects 2KHz, 1 selects 4 KHz. MH 85646486 0011178 5c?

INPUT REGISTER - 0011 (Read Only) [ei [one [oes [ae] ons] ma] eet | mo] IRQ few fm [ue fee [om fw [mf me | The SMC34C60 has six Input pins, of which Bit 4:01C-80 two are dedicated and four are uncommitted. This bit will be set if more than 2.5ms have The Input Register provides the Host with bit passed since the last rising edge of IRQ (pin access to each of these input pins. Bit 4 is a 48). This function is designed for QIC-80 tape special purpose bit useful for QIC-80 tape drive drives that require 2.5ms between the peripherals. completion of one command and the start of a subsequent command. Bit O:INO (Pin 82) This bit represents the current state of the Bit 5:IRQ LATCH uncommitted input pin INO. This bit is used to latch an interrupt request event and is enabled by setting INTEN (bit 6 of Bit 1:IN1 (Pin 83) the Operation Register). When enabled this bit This bit represents the current state of the is set by a rising edge on the IRQ pin (Pin 48), uncommitted input pin IN1. and cleared by setting INTCLR (bit 7of the Operation Register), or by following a Clear Bit 2:IN2 (Pin 37) Interrupt command from the Daisy Chain control This bit represents the current state of the packet (see the Daisy Chain Specification - uncommitted input pin IN2. Reference 3). Bit 3:IN3 (Pin 36) Bit 6:IRQ (Pin 48) This bit represents the current state of the This bit represents the current state of the IRQ uncommitted input pin IN3. pin. Bit 7:LOBATT (Pin 35) This bit represents the current state of the LOBATT input. When low, the piezo driver circuitry will provide a "low battery beep.” M™ 6564686 0011179 463

OPERATION REGISTER - 0100 (Read/Write) [arr [ae [eee | ome | ond | ona | oi] ono | Foren [a [A [vm [ome foun [ow | ne | The bits in this register control the operation of Bit 4:PDMA the SMC34C60. Setting this bit enables the psuedo-DMA mode. In the PDMA mode DMA functions are Bit 0:F16 performed, but CS is used instead of DACK to Setting this bit overrides Pin 81 (1016), forcing qualify the bus cycles. Use the PDMA mode to all bus accesses to 16-bit. Use this bit to DMA to or from a device which does not access a 16-bit peripheral which does not explicitly support DMA. generate 1016. Bit 5:AUTOINC Bit 1:D16 Setting this bit causes the bus address (AO-A7) This bit controls the bus width of the DMA to increment after every bus access. cycles. 1 selects 16-bit, O selects 8-bit. IOT6 and F16 are ignored during DMA cycles. Bit 6:INTEN Setting this bit enables the interrupt latch. Bit 2:DMAEN This bit must be set for the DMA state machine Bit 7:INTCLR to recognize DREQs. This bit will be | Writing a 1 to this bit will clear any pending automatically cleared when the DMA is interrupt. This bit always reads 0. complete. Bit 3:DIREC This bit controls the direction of DRAM - BUS DMA cycles. 1 selects a write from DRAM to BUS, 0 selects a read from BUS to DRAM. M@™ 6564686 0011140 145

DRAM BUFFER SIZE REGISTER - 0101 (Read/Write) | ee7 | ere [ cs [see [ors [ ora | oni | ano] DMA DRAM BUFFER SIZE HOST DRAM BUFFER SIZE This register determines the size of the DRAM accesses. The buffer sizes are encoded as buffers, both for DMA DRAM and Host DRAM follows: 0001 = 2 Bytes 1001 = 512 Bytes 0010 = 4 Bytes 1010, = 1K Bytes 0011 = 8 Bytes 1011, = 2K Bytes 0100 = 16 Bytes 1100 = 4k Bytes 0101 = 32 Bytes 1101) = 8K Bytes 0110 = 64 Bytes 11100 = 16K Bytes 0111 = 128 Bytes 1110 = 32K = Bytes 1000 = 256 Bytes 0000 = 64K Bytes HOST DRAM BUFFER POINTER REGISTER - 0110 (Read/Write) |_se7 J ees [ers [oes [ exs | ore] ont | no] HOST DRAM BUFFER POINTER (0-255) This register sets the Host’s DRAM pointer to A maximum of 256 buffers are available in this the selected buffer. The DRAM address is register. The actual number of buffers depends calculated using this pointer, the DRAM Buffer on the DRAM loaded, and the buffer size Size Register, and the DRAM bus width from selected. If the pointer is incremented Past the the Configuration Register. If MAXCNT is set last buffer, it will wrap back around to the first during the Host to DRAM transfer, then this buffer. No active buffer count is maintained; register is incremented upon reaching maximum the driver software must prevent overwriting Count, and the DRAM address is recalculated existing buffers. for the next buffer. MH 65b4b8b 0011181 011

DMA DRAM BUFFER POINTER REGISTER - 0111 (Read/Write) [ec7 [exe T exs 7 ses T ses [ se2 [ ses [ sro | DMA DRAM BUFFER POINTER (0-255) This register sets the DMA DRAM pointer to the register is incremented upon completion of a selected buffer. Its operation is similar to the DMA transfer and the DRAM address is Host DRAM Buffer Pointer Register. This recalculated for the next buffer. HOST MAX BLOCK BYTE-COUNT LOW REGISTER - 1000 (Read/Write) Te HOST MAX BLOCK BYTE-COUNT LOW (HBC{7:0]) This register sets the low byte of the counter register to limit external DRAM and bus read for Host block transfers. It is used in accesses. The counter is reloaded with this conjunction with MAXCNT in the Configuration value at every Address Write cycle. HOST MAX BLOCK BYTE-COUNT HIGH REGISTER - 1001 (Read/Write) [ory [exe [oes [ one | ona | ona [ oer | x0 | HOST MAX BLOCK BYTE-COUNT HIGH (HBC/{15:8]) This register sets the high byte of the counter register to limit external DRAM and bus read for Host block transfers. It is used in accesses. The counter is reloaded with this conjunction with MAXCNT in the Configuration value at every Address Write cycle. M™ 4564686 0011182 T58 a

DMA BYTE-COUNT LOW REGISTER - 1010 (Read/Write) [sev [oes [eee | ore | os | m2 ] or [| no] DMA BYTE-COUNT LOW (DBCI7:0}) This register sets the low byte of the 16-bit same byte count can be kicked off by resetting byte counter used for terminating DMA the DMA Enable bit in the Operation Register. transfers. Subsequent DMA transfers with the DMA BYTE-COUNT HIGH REGISTER - 1011 (Read/Write) [ ee? [ore [oes [ore | os | oi? ] or | ono] DMA BYTE-COUNT HIGH (DBC[15:8]) This register sets the high byte of the 16-bit same byte count can be kicked off by resetting byte counter used for terminating DMA the DMA Enable bit in the Operation Register. transfers. Subsequent DMA transfers with the MH 4564686 0011183 994

CONFIGURATION REGISTER - 1100 (Read/Write) . [err [ere [os] exe | oxo [ ona | oes | oro | waxcnt_| SAFO | —rewa | RAMSZi | RaMSZO | CKSELT | CxSELO | The bits in this register define the configuration Bit 5:SFIFO of the system. This bit selects the operating mode of the Read FIFO. Setting this bit causes the internal Read Bit 7:RST FIFO to operate as a single-word read-ahead. If Setting this bit resets the storage elements in this bit is clear, the Read FIFO will operate as a the chip. two-word read-ahead. Bit 6:MAXCNT Bit 4:rsvrd When this bit is set, the Max Block Count This bit is reserved and should be written as Registers are used to limit the bus and DRAM zeros. accesses. Bits[3:2)}:RAMSZ[1:0] [Raws21 [ RAMSz | DRAM BUS WIDTH | 0 | 0 _|Selects DRAM data width of 4 bits. jo [| 1 | Selects DRAM data width of 8 bits. [1 [x [Ssetects ORAM cata watn of 16 ws ——_—| Bits[1:0]:CKSEL[1:0] CKSEL1 | CKSELO BUS CYCLE (BUSCLK) | o | 0 | Bus Cycle (BUSCLK) = System Clock / 2 | o | 1 [Bus Cycle (BUSCLK) = System Clock / 3 [1 | 0 _ | Bus Cycle (BUSCLK) = System Clock / 5 [ 1 | 1 [Bus Cycle BUSCLK) = System Clock / 6 BUSCLK clocks the Bus Interface State Machine responsible for generating Bus Access, DRAM access, and DRAM Refresh timing. BUSCLK is also responsible for Output Strobe timing. System Clock is the SCLK input (pin 96) and is typically 24MHz. MMH 4564686 0011184 420

CHIP REVISION LEVEL REGISTER - 1101 (Read Only) [ ex7 | sre | ses [ exs [ors [sez T sei | eno | TYPE ID REVISION It is expected that the SMC34C60 will be used identify different masks and/or process types. in various designs at different integration levels. This document refers to chips with Revision This register provides a means of determining Level values: which type of chip is in use. The most significant five bits are reserved for a Type ID; 0000 0000 the least significant three bits may be used to PORT TEST WRITE REGISTER - 1110 (Write Only) | _ee7 [ ses | ers [ ers [srs [ ee2 7 eri | sto | INCREMENTING WRITE TEST PATTERN The Port Test Write Register is used to cycle. After being selected, the register looks determine the highest reliable printer port data for an incrementing pattern starting at OO. If transfer rate. An interface test must be data is written out of sequence, or if a performed at various speeds until data integrity communications error occurs, the ERR bit in the can be assured. To enable this test, select the Data Transfer Control Register will be set. Port Test Write Register with an Address Write PORT TEST READ REGISTER - 1110 (Read Only) Jer? [ sire [ers 7 see Tees [ea [ ort | seo | INCREMENTING READ TEST PATTERN The Port Test Read Register verifies the read reads 00 when first addressed, and increments data transfer rate. To enable this test, select with every access. The ERR bit in the Data the Port Test Read Register with an Address Transfer Control Register is not affected by the Write cycle. After being selected, this Register Port Test Read. MH 8Sb4b8b 0011185 767

DATA TRANSFER CONTROL REGISTER - 1111 (Read/Write) [Vee7 [ers [ees [ses [es | era | eri | sito | [ena | ow | rovea | roved | reves | rows | unst | oor Bits O and 1 of this register provide options to Bit 1:BURST regulate data transfer on non-enhanced ports. This bit is valid if the SMC34C60 is selected for Bit 7 provides data transfer rate status Compatibility mode. Burst mode applies for information as described in the Port Test Write reads and writes in Byte mode and reads in Register. Nibble mode (see IEEE STD 1284 - Reference 1). Setting this bit maximizes data transfer by Bit 7:ERR minimizing handshaking requirements. Data is This bit is set if an error occurs writing to the latched on each edge of the Burst strobe as Port Test Write Register. It is cleared by shown in Figure 5. selecting the Port Test Register with an Address Write cycle. Bit 0:8BIT This bit is only valid with a bi-directional port in Bits 6-2:rsvrd Compatibility mode. Setting this bit selects These bits are reserved and should be written Reverse Transfer Byte mode. Clearing this bit as zeros. selects Reverse Transfer Nibble mode (see IEEE STD 1284 - Reference 1). on: —< > HSTB — | i FIGURE 5 - BURST MODE MH 4564686 0011186 bT3 a

DRAM BUFFER OPERATION addressed as a number of buffers. The buffer size is programmable to ‘power of 2’ sizes The SMC34C60 provides support for a DRAM between 2 and 64K bytes. A byte counter is buffer with DMA capability. DRAM bus widths used to control the DRAM access. It may be of 4, 8, or 16 bits may be used, with linear 20 Programmed to any value from 1 up to the bit addressing. DMA to and from the DRAM buffer size. To prevent overwriting data, the may be either 8 or 16 bit cycles. The byte counter should not be set to a value SMC34C60 will take care of matching the bus exceeding the buffer size. widths between the DMA Controller and the DRAM. If multiple DRAM accesses are The DRAM may be independently accessed by necessary for a DMA cycle, they will use fast the host and the DMA Controller. There are page mode. separate buffer and byte counters for each. When a DRAM transfer is complete, the buffer DRAM refresh is automatic, and uses a CAS number is incremented, and further DRAM before RAS refresh method. The DRAM is access is blocked. DRAM Linear Address Mapping [was [wae | sar | sas [ sas | saa | saa] saz] sat] 600 | [row [ato [ai [ats [ara [ara | aie [ an [ato | a | as | Lco. | are | are | a7 | as [as [as [as [a2 [ar [a0 | M@@ 4564666 0011167 S3T

DRAM PHYSICAL ADDRESSING and 3, in the Configuration Register (1100h). The System DMA Data Bus width is determined Users access the SMC34C60 DRAM through by D16, bit 1 in the Operation Register (0100h). the Host and DMA logical addressing controls Host access is always eight bits. found in the Internal Registers. The system automatically calculates the physical DRAM The SMC34C60 determines physical DRAM addresses based on the values stored in these addresses by calculating the buffer start registers and the width of the system data address and adjusting this value for bus width. paths. The buffer start address is the buffer pointer multiplied by the buffer size. If the DRAM Bus The logical addressing controls are the 4-bit width is greater than or equal to the System encoded Host and DMA DRAM buffer size Bus width then the buffer start address is the controls in the DRAM Buffer Size Register physical DRAM address, otherwise the physical (0101h) and the 8-bit DRAM buffer pointers in DRAM address is the buffer start address the Host DRAM Buffer Pointer Register (0110h) multiplied by the System Bus width divided by and the OMA DRAM Buffer Pointer Register the DRAM Bus width as shown in the Figure 6 {0111h). The DRAM Data Bus width is below. determined by RAMSZO and RAMSZ1, bits 2 HOST/DMA Bus Width Greater Than DRAM Bus Width Physical Address = Buffer Ptr * Buffer Size * System Bus Width / DRAM Bus Width HOST/DMA Bus Width Less Than or Equal to DRAM Bus Width Physical Address = Buffer Ptr * Buffer Size For example, during a DMA transfer where; 1, the DRAM data bus width is four bits, 2. the DMA device data bus width is sixteen bits, 3. the DMA Buffer Size is 4096 bytes (1000h), 4, the DRAM Buffer Pointer is 2, the Physical DRAM Address for the start of this transfer will be 32768 (8000h) FIGURE 6 - DRAM PHYSICAL ADDRESSING MMH 6564686 0011188 476

SYSTEM DATA BUS CYCLES Three types of operations are performed by the ° bus interface: a Bus Cycle, a DRAM Access, The System Data Bus is controlled by an and a DRAM Refresh. Refer to Tables 4-6 for internal state machine with seven states as the state flow description for each operation. shown below in Figure 7. The state machine is The bus controller normally sits in the idle state. clocked by the BUSCLK which is software- When a bus interface operation is kicked off, it programmable as SCLK divided by 2, 3, 5, or advances to state 1. It then advances to the 6. next state at every BUSCLK cycle. After state 7, the controller returns to idle. FIGURE 7 - GENERIC SYSTEM DATA BUS CYCLE BUS CYCLE TIMING Started from the Address Write cycle. This "pre-write” cycle asserts chip select and When an Address Write cycle selects a bus samples and latches 1016. The write cycle is write, the next data received is written to the initiated after the first byte received for 8 bit bus. The interface must, however, know writes, or after the second byte of data for 16 whether to expect an 8 or 16 bit bus address. bit writes. To determine the bus width, a bus cycle is M@™ 6564686 0011189 302 me

Table 4 - Bus Cycle State Flow Description IDLE Write: Data bus drivers are disabled, RAS and CAS are inactive. STATE 1 Read: If necessary, data advances to next element in the FIFO buffer. CAS goes active for first refresh. STATE 2 Write: Data is latched into bus latches. RAS goes active for first refresh. STATE 3 Chip Select goes active. STATE 4 | O76 is sampled. Read: RD goes active. _ Write: If 1076 is sampled low and this is the first byte received, then WR remains inactive. If TOT6 is sampled high or if IOT6 is sampled low and this is the second byte received, then WR goes active and data bus drivers are enabled. RAS and CAS go inactive. STATE 5 Wait for data bus to stabilize, CAS goes active for second refresh. STATE 6 Read: Data is latched, RD goes inactive. Write: WR goes inactive. RAS goes active for second refresh. STATE 7 Chip select goes inactive. Read: Data advances to next element if possible. Write: Data bus drivers are disabled. Table 5 - DRAM Access State Flow Description (DLE RAS and CAS go inactive. STATE 1 Row Address output. STATE 2 RAS goes active. Read: RD goes active. Write: WR goes active. STATE 3 Column Address output Write: Data bus drivers enabled. STATE 5 Column Address incremented. Read: Data is latched. Write: Data bus drivers disabled. (If multiple accesses are needed, States 3-5 are repeated ) STATE 6 RAS, CAS, RD, WR go inactive. STATE 7 RAS precharge time. MM 4564686 0011190 dc4 mm

Table 6 - DRAM Refresh State Flow Description® | imei RAS and CAS go inactive. STATE 1 CAS goes active for first refresh. STATE 2 _| RAS goes active for first refresh. sares | OOSOSOOOCOCCCSC*dY STATE 4 RAS and TAS go inactive. STATE 5 CAS goes active for second refresh. STATE 6 RAS goes active for second refresh. “For SCLK = 24 MHz, a DRAM Refresh Cycle is performed every 30uS. Bus cycles have built-in DRAM refresh which reset the 30yS refresh timer. M@™@ 8564646 0011191 Tho

OPERATIONAL DESCRIPTION. . MAXIMUM GUARANTEED RATINGS* * Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (T, = 0°C - 70°C, Voc = +5.0 V + 10%) PARAMETER symeot | min | tye | max | units | COMMENTS

1 Type Input Buffer

Low Input Level Vius Vv Schmitt Trigger High Input Level Vas Vv Schmitt Trigger Schmitt Trigger Hysteresis Vuvs mV lox Input Buffer Low Input Level Vieck v High Input Level Vinsex v Input Leakage (All | and IS buffers) Low Input Leakage A +10 uA Vin = 0 High Input Leakage In +10 uA Vin = Veco [Pu Up Current ft ffs [iso | vA [vw 0 | [Pu Down Curent | ta TT 200 [wa [v=o | MM 8564686 0011194 777

PARAMETER symeot | min | typ | MAX | UNITS | COMMENTS 1/08 Type Buffer Low Output Level Vo 0.4 Vv ln = 8 mA High Output Level Vou Vv lon = -4 mA Output Leakage tow +10 uA Vin = 0 tO Voc

016 Type Buffer

Low Output Level Vor 0.4 Vv Io = 16 mA High Output Level Vou v lon = -12 MA Output Leakage Loy +10 uA Vin = 0 to Veg O8 Type Buffer Low Output Level Vow 0.4 v ln = 8 mA High Output Level Vou Vv lon = -4 mA Output Leakage boy +10 uA Vin = 0 t0 Voc Low Output Level Vor 0.4 Vtg = 16 ma High Output Level Vow Vv loy = -12 mA Output Leakage lou +10 wA Vin = 0 to Veg

024 Type Buffer

Low Output Level Vow 0.4 v lq = 24mA High Output Level Vow v lon = -12 mA Output Leakage lo +10 uA Vin = 0 to Veg [Suoniy Curent Active | tee | | | 80 | ma [atronputs open | @™ 65b4b8b 0011195 bOb

CAPACITANCE T, = 25°C; fc = 1MHz; Vcc = 5V PARAMETER symeot | MIN | TYP | MAX | TEST CONDITION [ovine capacitance | Car || | 20 | oF _| M@™ 46564686 0011196 S42 mm

The SMC34C60 supports three communications Busy (HBSY). The ECP chip then raises Strobe. cycles: Address Write, Data Write, and Data The SMC34C60 latches the information, then Read. The signalling for these cycles in sets Busy low. Standard, EPP, and ECP modes is discussed below. DATA WRITE ADDRESS WRITE The data write cycle is used to send data to the SMC34C60 registers, DRAM, or the remote An Address Write cycle must be issued before system. A previous Address Write cycle must any Data cycles, since this tells the SMC34C60 have been sent to the SMC34C60 selecting whether the following Data cycles are Write, and the target of the write. write/read, and where the data should go/come from. Standard Mode Standard Mode If the SMC34C60 can accept data, busy (HBSY) will be low. The host places the data on the The host places the address information on the parallel port data lines, then strobes the data parallel port data lines, then strobes the address into the SMC34C60 by pulsing Strobe (HSTB) into the SMC34C60 by pulsing Select In (HSEL) low with a minimum 200 ns pulse width. If the low with a minimum 200 ns pulse width. The SMC34C60 is operating in the Burst Mode, then SMC34C60 will always accept the Address Strobe should only change state instead of Write cycle, there is no Busy hold off. pulsing low. EPP Mode EPP Mode The host sends address information by writing If the SMC34C60 can accept data, Busy to the EPP Address Register (base +3). The (HBSY) will be low. The host sends data by EPP interface chip places this data on the writing to the EPP Data Registers (base+4 - parallel port data lines, then brings Select In base+7). The EPP interface chip places the (HSEL) low. The SMC34C60 latches the data on the parallel port data lines, then lowers information, then acknowledges the transfer by Auto LF (HALF). The SMC34C60 latches the raising Busy (HBSY). The EPP interface chip data, then raises Busy to acknowledge the may terminate the cycle when it sees Busy go transfer. The EPP interface chip may terminate high. the cycle when it sees Busy go high. ECP Mode ECP Mode The host sends address information by writing if the SMC34C60 can accept data, Busy to the ECP Address FIFO (base +0). The ECP (HBSY) will be low. The host sends data by interface chip places this data on the parallel writing to the ECP Data FIFO (base +400h). port data lines, sets Auto LF (HALF) low to The ECP interface chip places this data on the indicate address information, then sets Strobe parallel port data lines, sets Auto LF (HALF) {HSTB) low to start the transfer. The high to indicate data cycle, then lowers Strobe SMC34C60 acknowledges the cycle by raising ({HSTB) to start the transfer. The SMC34C60 M@™@ 6564646 0011197 485

acknowledges the cycle by raising Busy. The If the SMC34C60 is operating in Burst Mode, ECP chip then raises Strobe. The SMC34C60 then the Strobe only changes State instead of ° latches the data, then sets Busy low. pulsing low in the above description. DATA READ EPP Mode A Data Read cycle is used to get data from the If the SMC34C60 has data ready, Busy (HBSY) SMC34C60 registers, DRAM, or the remote will be low. The host gets data from the system. A previous Address Write cycle must SMC34C60 by reading the EPP Data Registers have been sent to the SMC34C60 selecting (base +4-base+7). The EPP interface chip Read, and the source of the read. disables the port drivers, then lowers Auto LF (HALF). At this point, the SMC34C60 drives Standard Mode data onto the data lines, then raises Busy. The EPP Chip then latches the data, and raises Auto if the SMC34C60 has data ready, Busy (HBSY) LF to terminate the cycle. will be low. If the SMC34C60 is in 4 bit mode, the host reads the low nibble from the status ECP Mode lines Ack (HACK), PError (HPE), Sict (HSLCT), Error (HERR). The host then pulses Strobe The ECP interface requests a reverse transfer by (HSTB) low to acknowledge the low nibble. disabling the data line drivers, then lowering The SMC34C60 then places the high nibble on Inet (HINIT). The SMC34C60 acknowledges the same status lines, the host reads the high the reverse transfer by lowering PError (HPE), nibble, then pulses Strobe to signal receipt of and driving the data lines. When the the data. If the SMC34C60 is in 8 bit mode, SMC34C60 has data ready, it will lower Ack then the host disables it’s data drivers, floating (HACK). The ECP chip will respond by raising the parallel port data lines. The host enables Auto LF (HALF). The SMC34C60 then raises the SMC34C60 bus drivers by lowering Init Ack, signalling the ECP chip to latch the data. (HINIT), reads the data from the data lines, then The ECP chip then terminates the cycle by pulses Strobe low to acknowledge the transfer. lowering Auto LF. Table 7 - Timing Diagram Symbol Translations TIMING SYMBOL | SMC34C60 PIN NAME PIN NUMBER cc ee a a a [wr | aw] HBSY HACK a ee SucT HSLcT MB 8564646 0011198 315

: t 8 6 HD{0:7) ee AUF H __ 2 SEL H INT H a s—- BSY P if FE PEP SSeS SLCT P SSS ERR Po YO FIGURE 11 - SPP ADDRESS WRITE TIMING (PARALLEL PORT SIGNALS) All timing for SCLK = 24MHz. This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode. This timing sequence is not specified in the P1284 specification; it should not violate the P1284 spec. See Page 46 for SPP Address Write Timing Parameters. W™ 6564646 0011199 2S) a

SPP ADDRESS WRITE TIMING (PARALLEL PORT SIGNALS) [| Parameter | min tye max] units | INIT controls the direction of the 84 125 parallel port when in SPP mode. INIT] [2 SCLK] [3 SCLK) deasserted to HD[0:7] released to high impedance by the SMC34C60. The Host can now drive HD[0:7] with 125 an address byte and then strobe it into} [3 SCLK] the SMC34C60 by asserting the SEL signal. This time represents the address setup time required by the SMC34C60. Typically the address written to the 167 208 SMC34C60 is an instruction detailing | [4 SCLK] {5 SCLK]} the type of transfer to follow (i.e., Data Read/Write to DRAM, Bus, Register). Thus, once this address is received by the SMC34C60, it asserts the BSY signal to indicate that it is preparing for the upcoming transfer. This time represents the time for BSY to assert from the assertion of SEL. ‘SEL pulse width. This time represents 125 the duration that SEL must be asserted | [3 SCLK] in order for the SMC34C60 to recognize an edge. The Host is required to hold the 167 address valid for this amount of time} [4 SCLK] following assertion of the SEL line. INIT controls the direction of the 84 125 parallel port when in SPP mode. INIT] {2 SCLK] {3 SCLK] may be asserted anytime after the address hold time (tS) has been satisfied. This time represents the time from INIT asserted to HD[0:7] driven by the SMC34C60. ME 4564646 0011200 aT3 a

tt ‘8 : HOj0:7] {|} a L b Q | — 8 pa ae a | ee | INT H BSY P \\ / \\ / ACK P PE P Se SLCT P _ ERR P FIGURE 12 - SPP DATA WRITE TIMING (PARALLEL PORT SIGNALS) This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode. SPP DATA WRITE TIMING (PARALLEL PORT SIGNALS) INIT controls the direction of the parallel 84 125 port when in SPP mode. INIT deasserted to | [2 SCLK] [3 SCLK] HD[0:7] released to high impedance by the SMC34C60. = eewmernnese [og [| |_ 19 [sv deossorted tow) to STHatserededse. | 0 | | Si) re | ‘STB asserted pulse width. 125 [3 SCLK] Valid data hold from STB deasserted edge. 125 [3 SCLK} STB asserted edge to BSY asserted edge. 333 375 [8 SCLK] [9 SCLK] 17 _| BSY asserted pulse width. These values are 1,084 based on BCLK = 2 SCLK. (13 BCLK] MB 8564686 0011201 737

6 . HD{0:7] KT) KF kK i | | a |e INT H l ee U 2s 2 2 Cn ACK PO as PEP SLOT PO ERR P — FIGURE 13 - SPP DATA READ TIMING (PARALLEL PORT SIGNALS) This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode. The timing sequence shows three bytes being read from the SMC34C60. This is using Data line in the bi-directional mode for ports not supporting bi-directional mode. See Nibble Mode. See Page 49 for SPP Data Read Timing Parameters. MH 6564686 0011202 7b a

| of Parommeter minty [max [unite | INIT controls the direction of the parallel port when in 84 125 SPP mode. When INIT is asserted the data port is } (2 SCLK] {3 SCLK] driven by the SMC34C60 and read by the Host. This time represents the time from INIT asserted to HD[0:7] driven by the SMC34C60. Note: data is not necessarily valid. As soon as the SMC34C60 places valid data onto 20 the HD[0:7] port lines, the BSY signal is deasserted by the SMC34C60 to inform the Host that data is now valid. This time is determined by the host, the SMC34C60 nla nla places no restriction on this time. This time represents the time it takes the Host to recognize and latch the valid data on HD[0:7]. STB pulse width. This time represents the duration] 125 that SEL must be asserted in order for the | [3 SCLK] SMC34C60 to recognize an edge. Once the Host has latched the Data on HD(0:7] it 334 375 asserts the nSTB signal to inform the SMC34C60 to | [8 SCLK] {9 SCLK]} fetch another byte of data. If the SMC34C60 has to perform a DRAM or BUS cycle it may have to assert the BSY signal until it has completed the cycle and has placed valid data on HD{0:7]. This time represents the time from the assertion of STB to the assertion of BSY when appropriate. Once the Host has latchd the Data on HDIO:7] it 84 125 asserts the STB signal to inform the SMC34C60 to | [2 SCLK] {3 SCLK] fetch another byte of data. This time represents the time that the HD[0:7} data will remain valid from the assertion of STB. This time (+t6) represents the time it takes the 250 1,292 SMC34C60 to fetch and present the next valid data | [6 SCLK] [5 SCLK} byte on the HD[0:7] lines. This time will vary + significantly based on the type of access and the 113 BCLK currently selected. These valuse are based on BCLK] BCLK = 2 SCLK. INIT controls the direction of the parallel port when in 84 125 SPP mode. INIT deasserted to HD[O:7] released to | [2 SCLK] [3 SCLK} high impedance by the SMC34C60. MB 8564686 0011203 S02

té : ae cose: eee perce we TE" [EF | we PT ST rt we i BSY P — t t a— PEP MK Birb2 X BITDé X_BITDIO XBT D14 SCLT P MK Birb1 ~X BiTps X_BiTDs XBT O13) ERR P MK__BITDO C_Birb4 BI De XB i FIGURE 14 - SPP NIBBLE READ (PARALLEL PORT SIGNALS} This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode. This timing sequence deviates from that specified in the P1284 specification. It is implemented in a way that requires less host software overhead and therefore affords higher bandwidth. The timing shown is for a nibble read of a 16 bit wide resource (DRAM or peripheral BUS). See Page 51 for SPP Nibble Read Timing parameters. M™ 4564646 0011204 449 me

SPP NIBBLE READ (PARALLEL PORT SIGNALS) The SMC34C60 assembles a nibble of data and 42 places it on the status lines. The SMC34C60 then [SCLK] deasserts the BSY signal to inform the Host that a valid nibble is available. Once the Host senses that the BSY line is deasserted it will then internally latch the nibble and then assert STB to tell the SMC34C60 to get the next nibble. It will take the SMC34C60 this amount of time to 250 fetch and present the next nibble of data. (6 SCLK]} ‘STB asserted pulse width 125 [3 SCLK] ‘STB deasserted pulse width 125 [3 SCLK] t6 | Once the SMC34C60 has placed the next nibble, this 42 is the time for the Host to latch the nibble and then} [{SCLK] assert STB to tell the SMC34C60 to get the next nibble. t7 | Once the Host has latched the last nibble it asserts] 334 375 the STB signal to inform the SMC34C60 to fetch | [8 SCLK] (9 SCLK} another more data. If the SMC34C60 has to perform a DRAM or BUS cycle it may have to assert the BSY signal until it has completed the cycle and has placed a valid nibble on the status lines. This time represents the time from the assertion of STB to the assertion of BSY when appropriate. This time represents the time it takes the SMC34C60 1,084 to fetch and present the next valid nibble on the 113 status lines. This time will vary significantly based BCLK] on the type of access and the BCLK currently selected. These valuse are based on BCLK = 2 SCLK. M@@ 6564666 0011205 365

i HDJ0:7] _ VALID ADDRESS D — 7 STB H _ ALF H 2 tet INIT H ns —_ th BSY P / \\ pep [J [ff SLCL P / / / / / CC FIGURE 15 - EPP ADDRESS WRITE (PARALLEL PORT SIGNALS) EPP timing is IEEE P1284 compatible except the SMC34C60 : 1) does not use niNIT to terminate EPP Mode (return to compatibility mode) 2) does not support using nACK to generate interrupts to the Host while selected. See Page 53 for EPP Address Write Timing Parameters. MB 6564686 0011206 21)

EPP ADDRESS WRITE {PARALLEL PORT SIGNALS) SP pecametge Tin Tye mae Tanita] The Host asserts STB. At the same time the Host places the address byte on HD{0:7]._ This specifies the jitter between STB being asserted and an address appearing on HD[0:7]. The SMC34C60 does not rely on STB. The SLCTIN signal is asserted coincident with the above events to indicate that an EPP address cycle is to take place. This time represents the jitter margin between SLCTIN asserted and the above two events. The SMC34C60 will detect the 250 assertion of SLCTIN and will assert] [6 SCLK] BSY to indicate that it has latched the address on HD[0:7]. After the SMC34C60 asserts BSY the 42 ns Host will then indicate that the cycle is] [SCLK] complete by deasserting SLCTIN. This represents the response time requirements put on the Host. Seeing that the Host has indicated that 209 the cycle is complete, the SMC34C60 [5 SCLK} will then deassert the BSY line as soon as it is ready for another EPP transfer. As soon as the SMC34C60 deasserts BSY the Host may initiate another EPP transfer. This time represents the time between the SMC34C60 deasserting BSY to the Host starting a new transfer cycle. M™ 8564646 0011207 155

0 . HD{0:7] Klip pata — t6 STB H —_ 2 te -" ee gg INIT H BSY P rr PEP ISLCT P ERR PO FIGURE 16 - EPP DATA WRITE TIMING (PARALLEL PORT SIGNALS) See Page 55 for EPP Data Write Timing parameters. MB aSb4b4b 0011208 054 me

EPP DATA WRITE TIMING (PARALLEL PORT SIGNALS) P| Promoter in tye max Tuts | The Host asserts STB to indicate that the forthcoming transfer is a write cycle. At the same time or soon after the Host places the address byte on HD[0:7]. This specifies the time between STB being asserted and an address appearing on HD[0:7]._ The SMC34C60 does not rely on STB. After placing an address on HD[0:7], the Host then asserts ALF to inform the SMC34C60 that a data cycle is taking place. The SMC34C60 will detect the 250 assertion of ALF and will assert BSY to| [6 SCLK] indicate that it has latched the data on HD(0:7]. After the SMC34C60 asserts BSY the 42 Host will then indicate that the cycle is} [SCLK] complete by deasserting ALF. This represents the response time requirements put on the Host. Seeing that the Host has indicated that 209 the cycle is complete, the SMC34C60 {5 SCLK] will then deassert the BSY line as soon as it is ready for another EPP transfer. As soon as the SMC34C60 deasserts BSY the Host may initiate another EPP transfer. This time represents the time between the SMC34C60 deasserting BSY to the Host starting a new transfer cycle. M@ 6564646 0011209 Teo mm

is] . ey | ee ™ | nFH 2 . a — ey = re ee INT H t t BSY P / \\ ACK PO SS SLCT P ERRP OO FIGURE 17 - EPP DATA READ TIMING (PARALLEL PORT SIGNALS) See Page 57 for EPP Data Read Timing Parameters. MH 4564686 0011210 74°

EPP DATA READ TIMING (PARALLEL PORT SIGNALS) The Host deasserts STB to indicate that the forthcoming transfer is a read cycle. At the same time or soon after the Host will release the Parallel port data lines HD[0:7] to a high impedance State. This specifies the time between STB being asserted and an address appearing on HDIO:7]. The SMC34C60 does not rely on STB. After tri-stating the HD[0:7] lines, the Host then asserts ALF to inform the SMC34C60 that a data cycle is taking place. The SMC34C60 will respond by placing 125 1,084 data on HD[0:7]. [3 SCLK] {13 BCLK] Then the SMC34C60 will assert the 125 167 BSY line to inform the Host that it has} [3 SCLK] [4 SCLK} placed a valid byte of data on the parallel port data lines HD[0:7]. Next, the Host latches the data on 42 HD[0:7] and deasserts ALF to inform} [SCLK] the SMC34C60 that the cycle is complete. In response, the SMC34C60 tri-states 209 the parallel port data lines HD[O:7]. [5 SCLK]} t7 | After tri-stating HD[0:7] the 42 SMC34C60 deassert BSY to indicate [SCLK]} that it is now ready for the next EPP transfer. As soon as the SMC34C60 deasserts BSY the Host may initiate another EPP transfer. This time represents the time between the SMC34C60 deasserting BSY to the Host starting a new transfer cycle. Mi 65b4b48b OOl12e1) 689

HO(0:7} . — 2 tel 2 STB H __ 4 tt ALF SEL H INT H BSY Pf BOR P PEP ISLCT P ERR PO FIGURE 18 - ECP FORWARD COMMAND TRANSFER TIMING {ECP ADDRESS WRITE, PARALLEL PORT SIGNALS) See Page 59 for ECP Forward Command Transfer Timing Parameters MM 6564646 OOllele S15

ECP FORWARD COMMAND TRANSFER TIMING . (ECP ADDRESS WRITE, PARALLEL PORT SIGNALS) |__| Parameter min tye max | unite | The Host places data on HD[0:7] and at the same time asserts ALF to indicate that this is a Command transfer. (the SMC34C60 supports Address commands, not RLE commands) After placing data on HD[0:7] and asserting ALF, the host is required to meet this setup time before asserting STB. Assetion of STB informs the SMC34C60 that_valid data is on HD[0:7] and that ALF is valid. The peripheral acknowledges by 334 asserting BSY. (8 SCLK} Once the peripheral has sent its 42 acknowledgement the Host deasserts} [SCLK] STB to continue the handshake. The. SMC34C60 latches the address data on this rising edge of STB. As soon as the SMC34C60 has 334 accepted the data and is ready to} [8 SCLK] accept another byte it deasserts the BSY signal. Once the SMC34C60 has indicated it is 42 ready to receive another byte of data] [SCLK] from the Host, the Host if and when ready will place another byte on HD[0:7]. This time is the time required between the deassertion of BSY and new valid data on HD[0:7]. MMH 65b4b4b 0011213 451

t : HD{0:7) Fai pata > ALF | we ig a INIT H te t6 BSY P \\ / \\ BR PS PEP $$$ SLCT P ERR PO —nN0O——— FIGURE 19 - ECP FORWARD DATA TRANSFER TIMING (ECP DATA WRITE, PARALLEL PORT SIGNALS) See Page 61 for ECP Forward Data Transfer Timing Parameters MB 65b4b8b 0011214 398 ae

ECP FORWARD DATA TRANSFER TIMING . (ECP DATA WRITE, PARALLEL PORT SIGNALS) The SMC34C60 indicates it is ready to 42 receive another byte of data from the| [SCLK] Host by deasserting BSY. The Host if and when ready will place a byte on HD[0:7]. This time is the time required between the deassertion of BSY and data on HD[O:7]. The Host places data on HDIO:7]_and at the same time deasserts ALF to indicate that this is a Data transfer. After placing data on HD[0:7] and deasserting ALF, the host is required to meet this setup time before asserting STB. Assetion of nSTB informs the SMC34C60 that_valid data is on HD[0:7] and that ALF is valid. The peripheral acknowledges by 334 asserting BSY. [8 SCLK] Once the peripheral has sent its 42 acknowledgement the Host deasserts| [SCLK] ‘STB to continue the handshake. The SMC34C60 latches the data on this rising edge of STB. As soon as the SMC34C60 has 334 accepted the data and is ready to] [8 SCLK] accept another byte it deasserts the BSY signal. M@ 4564686 0011215 224

qe ‘9 tt : = EEO “ oe ee ee i a SEL H — 1 INIT H a BSY P la =< ic 6 ACK P t2 tto PEP OF [ ISLCT P ERR PO ———esseseeeeeeOOOOCSOSCSC“#NNCN FIGURE 20 - ECP REVERSE DATA TRANSFER TIMING (ECP DATA READ, PARALLEL PORT SIGNALS) Note: The optional use of the ERR (FAULT) line to "hint " to the Host that the peripheral has data to send to the Host is not supported in the SMC34C60. The driver should ignore any activity on this line. The SMC34C60 supports reverse data transfers only (not reverse command transfers) and, therefore, always asserts the BSY (CMD) signal during reverse transfers. See Page 63 for ECP Reverse Data Transfer Timing Parameters. MH 6564686 OOL121b 160

ECP REVERSE DATA TRANSFER TIMING (ECP DATA READ, PARALLEL PORT SIGNALS) To prepare for an ECP reverse channel transfer the Host tri-states the parallel data lines HD[0:7) and asserts ALF at the same time. Next the Host asserts INIT to initiate an ECP bus reversal. The SMC34C60 fequires this amout of time between these events, ‘The SMC34C60 acknowledges the bus reversal by deasserting the PE | 208 signal. At this point in time the parallel port bus is in the reverse idle | {5 SCLK) state. Along with deasserting the PE signal the SMC34C60 takes control of the 1,084 parallel port data bus HD{O;7]. The data on this bus remains undefined (13 BCLK] until the 34C60 has accessed and placed a data byte on the bus. Along with driving the data lines with valid data, the SMC34C60 asserts BSY to indicate that this is a data transfer. After placing data on the parallel port data lines the SMC34C60 asserte| 125 167 KCK to inform the Host that valid data is available. [3 SCLK) [4 SCLK] Next, the Host will acknowledge that it is ready for the data by doasserting ALF. Now the SMC34C60 will deassert ACK in response to the Host. The 167 Host will latch the data on HD[O:7] on this rising edge of ACK. (4 scLK) ‘The Host completes the ECP reverse transfer, acknowledging that it has accepted the data byte by asserting ALF. At the completion of the ECP reverse transfer cycle the SMC34C60 167 either places another valid data byte on the data lines or if it has no more {4 ScLK) Valid data to send drives undefined data onto the parallel port bus lines. As long as the port is in the reverse transfer mode, the SMC34C60 will always return data when a byte is requested. Once HOST MAX BLOCK byte-count has been reached, the SMC34C60 will present “pad” bytes to the Host. The Host will discard any extra bytes received, The extra “pad bytes are useful to provide alignment to wider buses. The Host requests that the parallel port be placed back into the forward 167 direction by deasserting INIT, and in response to this the SMC34C60 will [4 SCLK) terminate any ongoing data transfer and place the data bus HD(0:7} in a high impedance state and deassert the BSY line. After releasing the bus, the SMC34C60 acknowledges that it has 128 ralinquished the bus by asserting the PE signal. 13 SCLK] After the SMC34C60 has indicated that it has relinquished the bus, the Host may drive the data bus. MH 6564686 0011217 OT7

CAS \\ ] \\ / . RAS \\ / \\ / So _ __ 8 1016 t RD WR ~~ $0(0:15] (pea _ had AUTOINC bit set ‘SA(O:7] Address Valid \\—“Adgress+1 Busclk TT \\_ fT NN *N FIGURE 21 - PERIPHERAL BUS READ CYCLE TIMING a ee TS asserted to WA assorted. This applies to any and all] 74 84 94 of the general purpose output pins that have been] [1 BCLK | [1 BCLKI | [18CLK configured to operate as “special function” Chip Select} -10] +10] pins. This feature saves the designer from having to implement costly address decoders. [ «2 [TOE setup required to the assertion of RD. foi {| | [ars | | #3. | TOTE hold time required from the assertion of RD. [i | | ‘| rs | RD asserted pulse width. 158 168 178 [2 BCLK | [2 BCLK) | [2 BCLK = 10) +10) [15 | Data valid setup time required to deassertion of AD. | 15 | | __——sid|_ns_| [16 | Data valid hold time required from deassertion of RO. | 10 | | sins _| 17 | RD deasserted to nCS deasserted. 74 84 94 (ecuk | (1BcLK) | [1BCLK =101 +10) RD deasserted to the address incremented (this is valid | 74 84 94 only if the AUTOINC bit is set). (eck | (1 eciK) | (1BcLK -101 +10) M™ 45b4b4b 0011218 T33 a

: CAS ff RAS F*=E fF" _ ane ro _ ioe ‘RD — t “ WR s—| te— 0 {0:15} i 8} promo oes SA(O7] BusclK NF FIGURE 22 - PERIPHERAL BUS WRITE CYCLE TIMING ES asserted to nWR asserted. This applies to any and 74 84 94 all of the general purpose output pins that have been | [1 BCLK-10] | {1 BCLK) | [1BCLK +10} configured to operate as "special function” Chip Select pins. This feature saves the designer from having to implement costly address decoders. [13 [TOTS hold time required from the assertion of WR. | 10+| «dd WR asserted pulse width. 158 168 178 [2 BCLK-10] | [2 BCLK] | [2BCLK +10] Write data valid from the assertion of CS. 74 84 94 (1 BCLK-10] | [1 BCLK] | [18CLK +10] Write data valid hold time from the deassertion of WR. 74 84 94 {1 BCLK-10] | 11 BCLK] | [1BCLK + 10] 17 | WR deasserted to CS deasserted. 74 84 94 U1 BCLK-10] | [1 BCLK] | [1BCLK +10] WR deasserted to the address incremented (this is 74 84 94 valid only if the AUTOINC bit is set). [1 BCLK-101 | [1 BCLKI | {18CLK +10] M@® 6564646 0011219 97T

WARS . ‘SA(0:7] (sap Row Alsge Cotta YX Cot Addr [XK Cotaddrs2 Xe sas i on = ees CAS RAS RD 4 | |] “ RD We [OT s+ te 9 SD{0:15] pusciK 7 \\ VS VS VS VS NS NS NS NS NS NI NS FIGURE 23 - DRAM READ CYCLE TIMING When the DRAM bus width (4, 8 or 16 bits) is narrower than the Host bus (always 8-bits) or the Peripheral bus (8 or 16 bits) than the SMC34C60 will implement fast page mode DRAM cycles to complete the data transfer. These page mode transfers are performed for DMA as well as Host DRAM access. See Page 67 for DRAM Read Cycle Timing Parameters. MH 4564686 0011220 69)

Parameter sin tye Tmax urits 10-bit DRAM row address valid to RD 74 84 94 asserted. {1 BCLK [1 BCLK} [1BCLK -10) +10) 10-bit DRAM row address valid to RAS 74 84 94 asserted. {1 BCLK {1 BCLK}) [1BCLK -10) +10) RAS asserted to valid 10-bit DRAM 74 84 94 column address. {1 BCLK (1 BCLK) (1BCLK -10) +10) 10-bit DRAM column address valid to 74 84 94 TAS asserted. {1 BCLK | [1 BCLK] | [1BCLK +10) +10) 10-bit DRAM = column address 74 84 94 incremented and at the same time the| [1 BCLK {1 BCLK] [1BCLK data is latched into the SMC34C60 -10] +10) following CAS asserted. CAS deasserted after the column 74 84 94 address has been updated and the data} [1 BCLK {1 BCLK] [1 BCLK has been latched by the SMC34C60. -10) +10) TAS deasserted pulse width during 74 84 94 page mode accesses. {1 BCLK {1 BCLK} [1BCLK -10] +10} TAS asserted to valid data, i.e., 74 maximum acceptable DRAM access [1BCLK time. 710) t9 | TAS deasserted to DRAM releasing 74 data from the bus. (1BCLK -10) TAS and RAS both deasserted to RD 42 deasserted. {1 SCLK] MH 656486 OOll221 526

MAB:9] : ‘3 ts | | | CAS “s | wo a | am | ii = WR 6 8 9 18 SDj0:15} puscLK \\_/\\ VS NS NS NS NS NS NS NS NS NS Ns FIGURE 24 - DRAM WRITE CYCLE TIMING When the DRAM bus width (4, 8 or 16 bits) is narrower than the Host bus (always 8-bits) or the Peripheral bus (8 or 16 bits) than the SMC34C60 will implement fast page mode DRAM cycles to complete the data transfer. These page mode transfers are performed for DMA as well as Host DRAM access. See Page 69 for DRAM Write Cycle Timing parameters. MH 8564686 0011222 4b4 ml

10-bit DRAM row address valid to WR 74 84 94 asserted. {1 BCLK {1 BCLK] (BCLK +10) +10) 10-bit DRAM row address valid to RAS 74 84 94 asserted. (1 BCLK (1 BCLK] [1BCLK +10) +10) RAS asserted to valid 10-bit DRAM 74 84 94 column address. {1 BCLK {1 BCLK} (BCLK -10) +10) 10-bit DRAM column address valid to 74 84 94 TAS asserted. (1 BCLK (1 BCLK} (1BCLK -10) +10) 10-bit DRAM column address 74 84 94 incremented following CAS asserted. (1 BCLK {1 BCLK] (1BCLK -10) +10) Valid write data in relation to the 10-bit column address presented by the SMC34C60. DRAM column address incremented to 74 84 94 nCAS deasserted. (1 BCLK [1 BCLK] (1 BCLK -10) +10) Valid write data in relation to the 10-bit column address presented by the SMC34C60. | CAS deasserted to valid data placed on the data bus. TAS and RAS both deasserted to WR 42 deasserted. (1 SCLK] MH 6564646 0011223 3TO

MAS} ‘a : SA0:7] K CAST Lf L_ Ly _ to} 1 ts——4 HO{0:7] = BUSCLK Sn A ee A Es ee FIGURE 25 - DRAM WRITE REFRESH CYCLE [Parameter min Tt max | nits | CAS asserted to RAS asserted. 74 84 94 {1 BCLK {1 BCLK} [1BCLK -10) +10) CAS asserted pulse width 242 252 262 ns [3 BCLK | {3 BCLK] | [3 BCLK -10] +10) RAS asserted pulse width 158 168 178 {2 BCLK {2 BCLK] (2 BCLK -10] +10) CAS deasserted pulse width 74 84 94 (1 BCLK [1 BCLK] {1 BCLK -10] +10) RAS deasserted pulse width 158 168 178 [2 BCLK [2 BCLK} {2 BCLK 10) +10) M@™ 45646865 0011224 237

DMA Transfer Type (peripheral bus <--> DRAM) DMA Transfer Cycle DMA Transfer Rate 1,333 750 KB/S [16 BCLK} 1,583 632 KB/S (19 BCLK] 1,333 1.5 MB/S {16 BCLK} 1,583 1.263 MB/S {19 BCLK] 2,083 960 KB/S (25 BCLK} M™ 85b4b8b OO1122b OOT

ABAAAADARARRRAARRBRA ARARARAARA TYCO POAT AT — = E a = = ~~ == = w = j= ooo ileal alias alailslafalalalalifatlalalala alata A TOME whe es | mmm 4461)! 0 8 AGEN HNN —e [= [o.10] i A L MILLIMETERS INCHES u [a _[ 200 o | ats [sso {s24 | 1) Coptanarity is 0.100mm (.004") maximum. [ar [0.1 [04s {004 | 018 | >) Tolerance on the postion of the loads le [raat 257 [287 tor 113 | 200mm (.008") maximum. ["p | 234 [eats 921 [951 | 3) Package body dimensions D1 and E1 do not [pr [199 [20.1 [7a3_ [701 | include the mold protrusion. Maximum mokd ["e [ 174 | 18.15 | 685 | 715 | _ protrusion is 0.25mm (.010"). [er | 139 | 141 | 547 | 555 | 4) Dimensions TD and TE are important for testing [-H | 01 [02 [004 [008 | by robotic handler. Only above combinations of (1) [-u_ | oes [095 [026 [037 | oF @) are acceptable. Tir [18 [26 | 071 __|__.102 | _5) Controliing dimension: millimeter. Dimensions in [“e— | “oaspsc |" _9256 BSG] _inches for reloronce only and not necessary ep eae ae) eae. [lw | 2 a 008 06 iow) {aug {ag {ase far [tpg [2221 [2276 [eva [806 | [reg [1627 | 602 | eai_ 662) FIGURE 30 - 100 PIN QFP PACKAGE OUTLINES ©1994 STANDARD MICROSYSTEMS Circuit diagram utilizing SMC products are included as a means of illustrating typical CORP. applications; consequently complete information sufficient for construction purposes is not necessarily given, The information has been carefully checked and is believed ‘to be entirely reliable. However, no responsibility is assumed for inaccuracies. e Furthermore, euch information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best product possible. Rev. 11/2/94 2 ; 4ol7s M@@! 4564686 OOllecds 162