SMCXXXBF NUMONYX | Alldatasheet
Document overview
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- PDF pages: 91
Technical content
Datasheet sections
- 1 Summary description
- 2 Capacity specification
- 3 Card physical
- 3.1 Physical description
- 4 Electrical interface
- 4.1 Electrical description
- 4.2 Electrical Specification
- 4.3 Current Measurement
- 4.4 Additional requirements for CompactF lash Advanced Timing mode
- 5 Command Interface
- 5.1 Attribute Memory Read and Write
- 5.2 Common Memory Read and Write
- 5.3 I/O Read and Write
- 5.4 True IDE mode
- 6 Card Configuration
- 6.1 Configuration Option Register (200h in Attribute Memory)
- 6.1.1 SRESET
- 6.1.2 LevlREQ
- 6.1.3 Conf5 - Conf0 (Configuration Index)
- 6.2 Card Configuration and Status Register (202h in Attribute Memory)
- 6.2.1 Changed
- 6.2.2 SigChg
- 6.2.3 IOis8
- 6.2.4 PwrDwn
- 6.2.5 Int
- 6.3 Pin Replacement Register (204h in Attribute Memory)
- 6.3.1 CReady
- 6.3.2 CWProt
Datasheet sections
- 6.3.3 RReady
- 6.3.4 WProt
- 6.3.5 MReady
- 6.3.6 MWProt
- 6.4 Socket and Copy Register (206h in Attribute Memory)
- 6.4.1 Drive #
- 6.5 Attribute Memory Function
- 6.6 I/O Transfer Function
- 6.7 Common Memory Transfer Function
- 6.8 True IDE Mode I/O Function
- 7 Host configuration requirements
- 8 Software interface
- 8.1 CF-ATA Drive Register Set Definition and Protocol
- 8.2 Memory Mapped Addressing
- 8.3 Contiguous I/O Mapped Addressing
- 8.4 I/O Primary and Secondary Address Configurations
- 8.5 True IDE Mode Addressing
- 9 CF-ATA registers
- 9.1 Data Register
- 9.2 Error Register
- 9.2.1 Bit 7 (BBK)
- 9.2.2 Bit 6 (UNC)
- 9.2.3 Bit
- 9.2.4 Bit 4 (IDNF)
- 9.2.5 Bit
- 9.2.6 Bit 2 (Abort)
- 9.2.7 Bit
- 9.2.8 Bit 0 (AMNF)
- 9.3 Feature Register
- 9.4 Sector Count Register
- 9.5 Sector Number (LBA 7-0) Register
Datasheet sections
- 10.1 Check Power Mode (98h or E5h)
- 10.2 Execute Drive Diagnostic (90h)
- 10.3 Erase Sector(s) (C0h)
- 10.4 Identify Drive (ECh)
- 10.4.1 Word 0: General Configuration
- 10.4.2 Word 1: Default Number of Cylinders
- 10.4.3 Word 3: Default Number of Heads
- 10.4.4 Word 6: Default Number of Sectors per Track
- 10.4.5 Word 7-8: Number of Sectors per Card
- 10.4.6 Word 10-19: Memory Card Serial Number
- 10.4.7 Word 23-26: Firmware Revision
- 10.4.8 Word 27-46: Model Number
- 10.4.9 Word 47: Read/Write Multiple Sector Count
- 10.4.10 Word 49: Capabilities
- 10.4.11 Word 51: PIO Data Transfer Cycle Timing Mode
- 10.4.12 Word 53: Translation Parameter Valid
- 10.4.13 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track
- 10.4.14 Word 57-58: Current Capacity
- 10.4.15 Word 59: Multiple Sector Setting
- 10.4.16 Word 60-61: Total Sectors Addressable in LBA Mode
- 10.4.17 Word 63: Multi-Word DMA transfer
- 10.4.18 Word 64: Advanced PIO transfer modes supported
- 10.4.19 Word 65: Minimum Multi-Word DMA transfer cycle time
- 10.4.20 Word 66: Recommended Multi-Word DMA transfer cycle time
- 10.4.21 Word 67: Minimum PIO transfer cycle time without flow control
- 10.4.22 Word 68: Minimum PIO transfer cycle time with IORDY
- 10.4.24 Word 164: Advanced PCMCIA I/O and Memory Timing modes
- 10.5 Idle (97h or E3h)
- 10.6 Idle Immediate (95h or E1h)
- 10.7 Initialize Drive Parameters (91h)
- 10.8 NOP (00h)
- 10.9 Read Buffer (E4h)
- 10.10 Read DMA (C8h)
- 10.11 Read Multiple (C4h)
Features
■ Custom-designed, highly-integrated memory controller – Fully compliant with CompactFlash TM specification 3.0 – Fully compatible with PCMCIA specification – PC Card ATA Interface supported – True IDE mode compatible – Up to PIO mode 6 supported – Up to 4 Multi-Word DMA supported – Hardware RS-code ECC (4 Bytes/528 Bytes correction) ■ Small form factor – 36.4mm x 42.8mm x 3.3mm ■ Low-power CMOS technology ■ 3.3V / 5.0V power supply ■ Power saving mode (with Automatic Wake-up) ■ High reliability – MTBF > 3,000,000 hours – Data reliability: < 1 non-recoverable error per 10 14 bits read – Endurance: > 2,000,000 Erase/Program cycles – Number of card insertions/removals: >10,000 ■ Hot swappable ■ High performance – Up to 23.8MB/s transfer rate – Sustained Write performance (host to card): 12.5MB/s – Sustained Read Performance (Host to Card: 19MB/s) ■ Available densities (formatted) – 32 MBytes to 4 GBytes ■ Operating System support – Standard Software Drivers operation CompactFlashTM www.numonyx.com
Table 1. Product List
SMCxxxBF Summary description
1 Summary description
The CompactFlash is a small form factor non-volatile memory card which provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems. The Card operates in three basic modes:
- PCMCIA I/O mode
- PCMCIA memory mode
- True IDE mode The CompactFlash also supports Advanced Timing modes. Advanced Timing modes are PCMCIA style I/O modes that are 100ns or faster, PCMCIA Memory modes that are 100ns or faster, True IDE PIO Modes 5,6 and Multi-Word DMA Modes 3,4. It conforms to the PC Card Specification when operating in the PCMCIA I/O mode, and in the PCMCIA Memory mode (Personal Computer Memory Card International Association standard, JEIDA in Japan), and to the ATA specification when operating in True IDE Mode. CompactFlash Cards can be used with passive adapters in a PC-Card Type II or Type III socket. The Card has an internal intelligent controller which manages interface protocols, data storage and retrieval as well as hardware RS-code Error Correction Code (ECC), defect handling, diagnostics and clock control. Once the Card has been configured by the host, it behaves as a standard ATA (IDE) disk drive. The hardware RS-code ECC allows to detect and correct 4 Bytes per 528 Bytes. The Card has a super Cap on V CC and a powerful power-loss management feature to prevent data corruption after power-down. The specification has been realized and approved by the CompactFlash Association (CFA). This non-proprietary specification enables users to develop CF products that function correctly and are compatible with future CF design. The system highlights are shown in Table 2, Table 3, Table 4, Table 5, Table 6 and Table 7. Related Documentation
- PCMCIA PC Card Standard, 1995
- PCMCIA PC Card ATA Specification, 1995
- AT Attachment Interface Document, American National Standards Institute, X3.221- 1994
- CF+ and CompactFlash Specification Revision 3.0
Table 2. System Performance
- 162X, 130X and 85X, speed grade markings where 1X = 150 KBytes/s. All values are measured for an
80ns, File size = 20 MB sequential; sector count = 256. Table 3. Current Consumption (1)
- All values are typical at 25° C and nominal supply voltage and refer to 1GByte CompactFlash Card,
Table 4. Environmental Specifications Vibration (peak -to-peak) N/A 30Gmax. Table 5. Physical Dimensions
2 Capacity specification
number of heads, sector/tracks and cylinders. Table 6. CF capacity specification Table 7. System Reliability and Maintenance
- Dependent on final system qualification data.
3 Card physical
3.1 Physical description
female contacts on 50 mil (1.27mm) centers. Figure 10 shows Type I Card Dimensions. Figure 1. CompactFlash Me mory Card Block DiagramController Flash
4 Electrical interface
4.1 Electrical description
- PC Card ATA using I/O Mode
- PC Card ATA using Memory Mode
- True IDE Mode, which is compatible with most disk drives The signal/pin assignments are listed in Table 8 Low active signals have a ‘–’ prefix. Pin types are Input, Output or Input/Output. The configuration of the Card is controlled using the standard PCMCIA configuration registers starting at address 200h in the Attribute Memory space of the memory card. Table 9 describes the I/O signals. Inputs are signals sourced from the host while Outputs are signals sourced from the Card. The signals are described for each of the three operating modes. All outputs from the Card are totem pole except the data bus signals that are bi-directional tri-state. Refer to the section titled “Electrical Specifications” for definitions of Input and Output type.
Table 8. Pin Assignment and Pin Type
1 GND Ground GND Ground GND Ground
2 D03 I/O I1Z,OZ3 D03 I/O I1Z,OZ3 D03 I/O I1Z,OZ3
3 D04 I/O I1Z,OZ3 D04 I/O I1Z,OZ3 D04 I/O I1Z,OZ3
4 D05 I/O I1Z,OZ3 D05 I/O I1Z,OZ3 D05 I/O I1Z,OZ3
5 D06 I/O I1Z,OZ3 D06 I/O I1Z,OZ3 D06 I/O I1Z,OZ3
6 D07 I/O I1Z,OZ3 D07 I/O I1Z,OZ3 D07 I/O I1Z,OZ3
8 A10 I I1Z A10 I I1Z A10
10 A09 I I1Z A09 I I1Z A09 (2) II 1 Z
11 A08 I I1Z A08 I I1Z A08 (2) II 1 Z
12 A07 I I1Z A07 I I1Z A07 (2) II 1 Z
13 V CC Power V CC Power V CC Power
14 A06 I I1Z A06 I I1Z A06 (2) II 1 Z
15 A05 I I1Z A05 I I1Z A05 (2) II 1 Z
16 A04 I I1Z A04 I I1Z A04 (2) II 1 Z
17 A03 I I1Z A03 I I1Z A03 (2) II 1 Z
18 A02 I I1Z A02 I I1Z A02 I I1Z
19 A01 I I1Z A01 I I1Z A01 I I1Z
20 A00 I I1Z A00 I I1Z A00 I I1Z
21 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3
22 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3
23 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3
24 WP O OT3 –IOIS16 O OT3 –IOIS16 O ON3
27 D11
28 D12 (3) I/O I1Z,OZ3 D12 (3) I/O I1Z,OZ3 D12 (3) I/O I1Z,OZ3
29 D13 (3) I/O I1Z,OZ3 D13 (3) I/O I1Z,OZ3 D13 (3) I/O I1Z,OZ3
30 D14 (3) I/O I1Z,OZ3 D14 (3) I/O I1Z,OZ3 D14 (3) I/O I1Z,OZ3
31 D15 (3) I/O I1Z,OZ3 D15 (3) I/O I1Z,OZ3 D15 (3) I/O I1Z,OZ3
37 READY O OT1 -IREQ O OT1 INTRQ O OZ1
38 V CC Power V CC Power V CC Power
41 RESET I I2Z RESET I I2Z -RESET I I2Z
45 BVD2 I/O I1U,OT1 –SPKR I/O I1U,OT1 –DASP I/O I1U,ON1
46 BVD1 I/O I1U,OT1 –STSCHG I/O I1U,OT1 –PDIAG I/O I1U,ON1
47 D08 (3) I/O I1Z,OZ3 D08 (3) I/O I1Z,OZ3 D08 (3) I/O I1Z,OZ3
48 D09 (3) I/O I1Z,OZ3 D09 (3) I/O I1Z,OZ3 D09 (3) I/O I1Z,OZ3
Table 8. Pin Assignment and Pin Type (continued)
49 D10 (3) I/O I1Z,OZ3 D10 (3) I/O I1Z,OZ3 D10 (3) I/O I1Z,OZ3
50 GND Ground GND Ground GND Ground
- For True IDE Mode, pin 9 is grounded.
- The signal should be grounded by the host.
- These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow
for 3-state signals not to consume current.
- The signal should be tied to V
- The -CSEL signal is ignored by the Card in PC Card modes . However, because it is not pulled up on the Card in these
host to PC Card A25 or grounded by the host.
- When the device does not operate in DMA mode, the signal should be held High or tied to VCC by the host. To ensure
proper operation with older hosts when DMA mode is disabled, the Card should ignore the –DMACK signal. Table 9. Signal Description the Task File, the remaining lines should be grounded. required it is asserted High. required it is asserted High. as audio functions are not supported. the Master/Slave handshake protocol.
of the Word. D08 is the LSB of the Odd Byte of the Word. (PC Card I/O Mode) Same as PC Card Memory Mode. while all data transfers are 16 bit using D00 to D15. (PC Card I/O Mode) Same for all modes. (True IDE Mode) Same for all modes. Not used, should not be connected to the host. transfer is controlled by -IORD and -IOWR. DMARQ is not driven when the Card is not selected. (True IDE Mode) Same as PC Card I/O Mode. Table 9. Signal Description (continued)
(PC Card I/O Mode) Same for all modes. (True IDE Mode) Same for all modes. (PC Card I/O Mode) Same as PC Card Memory Mode. asserted and data width is 16 bits. (PC Card Memory Mode) Not used. (PC Card I/O Mode) I 39 Not used. Master, when open it is configured as a Slave. (True IDE Mode) Same as PC Card I/O Mode. (PC Card I/O Mode) Reads the CIS and configuration registers.
are completed. No access should be made during this time. mode interrupt or held Low for a level mode interrupt. (True IDE Mode) Active High Interrupt Request to the host. Memory, Low for Attribute Memory. up only if this pin is left High or unconnected. (PC Card I/O Mode) Same as PC Card Memory Mode. (True IDE Mode) Hardware Reset from the host (active Low). (PC Card I/O Mode) Same for all modes. (True IDE Mode) Same for all modes.
(PC Card I/O Mode) Same for all modes. (True IDE Mode) Same for all modes. (PC Card I/O Mode) Used for writing to the configuration registers. (True IDE Mode) Not used, should be connected to VCC by the host. completion of the reset initialization sequence.
4.2 Electrical Specification
- VCC = 5V ± 10%
- VCC = 3.3V ± 5%
- -40 °C to 85 °C Table 11 shows that the Card operates correctly in both the voltage ranges and that the current requirements must not exceed the maximum limit shown.
4.3 Current Measurement
Table 13 the Output Drive Type and Table 15 the Output Drive Characteristics. Table 10. Absolute Maximum Conditions Table 11. Input Power Table 12. Input Leakage Current (1)
- x refers to the char acteristics described in Table 13 For example, I1U indicates a pull up resistor with a
type 1 input characteristic.
4.4 Additional requirements for CompactFlash Advanced Timing
- Only one CompactFlash Card must be connected to the CompactFlash bus.
- The load capacitance (cable included) for all signals must be lower than 40pF .
- The cable length must be lower than 0.15m (6inches). The cable length is measured from the Card connector to the host controller. 0.46m (18inches) cables are not supported.
Table 13. Input Characteristics
1 Input Voltage
2 Input Voltage
Table 14. Output Drive Type (1)
- x refers to the char acteristics described in Table 15 For example, OT3 refers to totem pole output with a
type 3 output drive characteristic. Table 15. Output Drive Characteristics
1 Output Voltage
2 Output Voltage
3 Output Voltage
5 Command Interface
available in True IDE interface type: PIO transfer and Multi-Word DMA transfer. Figure 8 show the read and write timing diagrams.
5.1 Attribute Memory Read and Write
Figure 2. Attribute Memory Read waveforms
- D OUT signifies data provided by the CompactFlash Memory Card to the system. The -CE signal or both the -OE signal and
the -WE signal must be de-asserted between consecutive cycle operations. Table 16. Attribute Memory Read timing
Figure 3. Configuration Register (Attribute Memory) Write waveforms
- D IN signifies data provided by the system to the CompactFlash Card.
Table 16. Attribute Memory Read timing (continued) Table 17. Configuration Register (Attribute Memory) Write timing
5.2 Common Memory Read and Write
Figure 4. Common Memory Read waveforms
- D OUT means data provided by the CompactFlash Memory Card to the system.
Table 18. Common Memory Read timing (1)
- Numonyx CF does not assert the WAIT signal.
Figure 5. Common Memory Write waveforms
- D IN signifies data provided by the system to the CompactFlash Memory Card.
Table 19. Common Memory Write timing (1)
- Numonyx CF does not assert the WAIT signal.
5.3 I/O Read and Write
Figure 6. I/O Read waveforms
- D OUT signifies data provided by the CompactFlash Memory Card or to the system.
Table 20. I/O Read timing (1)
Figure 7. I/O Write waveforms
- D IN signifies data provided by the system to the CompactFlash Memory Card.
- -IOIS16 and -INPACK are not supported in this mode.
- Numonyx CF does not assert the WAIT signal.
- -IOIS16 is not supported in this mode.
Table 21. I/O Write timing (1) Table 20. I/O Read timing (1) (continued)
5.4 True IDE mode
the conventions used in the PCMCIA specification and earlier versions of this specification. signals are shown in the waveforms inverted from their electrical states on the bus. Figure 8. True IDE PIO mode Read/Write waveforms
- The device addresses consists of −CS0, −CS1, and A2-A0.
- The Data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit).
- −IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
- Numonyx CF does not assert the WAIT signal.
- -IOIS16 is not supported in this mode.
Table 21. I/O Write timing (1) (continued)
Table 22. True IDE PIO mode Read/Write timing (1)
- The maximum load on -IOCS16 is 1 LSTTL with a 50pF total load.
- t 0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time
Card implementation should support any legal host implementation.
- This parameter specifies the time from the falling edge of -I ORD to the moment when the data bus is no longer driven by the
CompactFlash Memory Card (tri-state).
- t 7 and t8 apply only to modes 0, 1 and 2. The -IOCS16 signal is not valid for other modes.
Figure 9. True IDE Multi-Word DMA Mode Read/Write waveforms Table 23. True IDE Multi-Word DMA Mode Read/Write timing
- t 0 is the minimum total cycle time. tD is the minimum command active time. tKR and tKW are the minimum command
data. A CompactFlash Storage Card implementation shall support any legal host implementation.
6 Card Configuration
Structure (CIS). The Card has four configuration registers (Table 24 and Table 25).
- Configuration Option Register
- Pin Replacement Register
- Card Configuration and Status Register
- Socket and Copy Register They are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, in I/O Card mode these registers provide a method for accessing status information that would normally appear on dedicated pins in Memory Card mode. The base address of the card configuration registers is 200h in the Attribute Memory space. No write operation should be performed to the attribute memory area except for the configuration register addresses. All other attribute memory locations are reserved. See Section 6.5: Attribute Memory Function.
Table 24. CompactFlash Memory Card Registers and Memory Space Decoding
6.1 Configuration Option Regist er (200h in Attribute Memory)
decoding and interrupt to the Card (see Table 26).
6.1.1 SRESET
This bit is set to ‘0’ at power-up and taking the Card through a hardware reset.
6.1.2 LevlREQ
Mode is selected. Set to zero (0) after Power Up.
6.1.3 Conf5 - Conf0 (Configuration Index)
is set to ‘0’ after Power Up. Table 25. CompactFlash Memory Card Configuration Registers Decoding Table 26. Configuration Option Register (default value: 00h)
6.2 Card Configuration and Status Register (202h in Attribute
6.2.1 Changed
the Card is configured for the I/O interface.
6.2.2 SigChg
6.2.3 IOis8
always configured for both 8 and 16 bit I/O, so this bit is ignored.
6.2.4 PwrDwn
6.2.5 Int
Control Register, this bit is ‘0’. Table 27. CompactFlash Memory Card Configurations
6.3 Pin Replacement Register (204h in Attribute Memory)
memory mode and the IREQ signal in I/O mode. See Table 29 and Table 30.
6.3.1 CReady
6.3.2 CWProt
6.3.3 RReady
6.3.4 WProt
switch. When written, this bit acts as a mask for writing the corresponding CWProt bit.
6.3.5 MReady
This bit acts as a mask for writing the corresponding CReady bit.
6.3.6 MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit. Table 28. Card Configuration and Status Register (default value: 00h) Table 29. Pin Replacement Register (default value: 0Ch)
6.4 Socket and Copy Register (206h in Attribute Memory)
Option Register (see Table 31).
6.4.1 Drive #
This value can be used to address two different cards in the case of twin card configuration. The socket number is ignored by the Card. Table 30. Pin Replacement Changed Bit/Mask Bit Values
0 X 0 0 Unchanged
1 X 0 1 Unchanged
Table 31. Socket and Copy Register (default value: 00h)
6.5 Attribute Memory Function
Attribute memory is a space where identification and configuration information are stored. configuration registers are also located in the Attribute Memory area, at base address 200h. Attribute memory is not accessible in True IDE mode of operation. Attribute Memory access. Refer to Table 32 for signal states and bus validity. Table 32. Attribute Memory Function
- The –CE signal or both the –OE signal and the –WE signal must be de-asserted between consecutive cycle operations.
6.6 I/O Transfer Function
port is addressed, the –IOIS16 signal is asserted by the Card, otherwise it is de-asserted. Table 33. I/O Function
6.7 Common Memory Transfer Function
the Common Memory addresses. (see Table 34).
6.8 True IDE Mode I/O Function
the Card to PC Card ATA mode. Table 34. Common Memory Function Table 35. True IDE Mode I/O Function
Table 35. True IDE Mode I/O Function (continued)
Host configuration requirements SMCxxxBF
7 Host configuration requirements
The CompactFlash Advanced Timing modes include PCMCIA-style I/O modes that are faster than the original 250 ns cycle time (see Section 1: Summary description). Before configuring the Card interface for the I/O mode, the host must ensure that all the cards connected to a given electrical interface support I/O transfers faster than 250ns. These modes must be used in the conditions described in Section 4.4. In particular, the host can be connected to one card only. Consequently, the host must not configure a card to operate in an CompactFlash Advanced Timing mode if two cards are sharing the same I/O lines in Master/Slave operation, or if it is connected to the card through a cable which length exceeds 0.15m.
8 Software interface
8.1 CF-ATA Drive Register Set Definition and Protocol
- Standard PC-AT disk I/O address spaces – 1F0h-1F7h, 3F6h-3F7h (primary); – 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
- Any system decoded 16 Byte I/O block using any available IRQ.
- Memory space. Communication to or from the Card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four-register mapping methods. Table 36 is a detailed description of these methods:
8.2 Memory Mapped Addressing
the Data Register FIFO. It does not allow random access to the data buffer within the Card. accesses the Error (read) or Feature (write) register.
- Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if
consecutive (even then odd) Bytes from the data buffer. Table 36. I/O Configurations
0 Memory 0h-Fh, 400h-7FFh Memory Mapped
1 I/O xx0h-xxFh I/O Mapped 16 Continuous Registers
2 I/O 1F0-1F7h, 3F6h-3F7h Primary I/O Mapped
3 I/O 170-177h, 376h-377h Secondary I/O Mapped
embedded auto incrementing address logic. the data bus, along with odd data at offset 9 on the most significant Byte of the data bus. Table 37. Memory Mapped Decoding
8.3 Contiguous I/O Mapped Addressing
- Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if
consecutive (even then odd) Bytes from the data buffer. Table 38. Contiguous I/O Decoding
0 X 0000 0 h E v e n D a t a R e g i s t e r E v e n D a t a R e g i s t e r
0 X 0001 1 h E r r o r R e g i s t e r F e a t u r e R e g i s t e r
0 X 0010 2 hS e c t o r C o u n t R e g i s t e r S e c t o r C o u n t R e g i s t e r
0 X 0011 3 h Sector Number
0 X 0100 4 hC y l i n d e r L o w R e g i s t e r C y l i n d e r L o w R e g i s t e r
0 X 0101 5 hC y l i nder High Register Cylinder High Register
0 X 0110 6 h Select Card/Head
0 X 0111 7 h S t a t u s R e g i s t e r C o m m a n d R e g i s t e r
0 X 1110 E h Alternate Status
0 X 1111 F h D r i v e A d d r e s s R e g i s t e r R e s e r v e d
8.4 I/O Primary and Secondar y Address Configurations
Table 39. Primary and Secondary I/O Decoding
8.5 True IDE Mode Addressing
Table 40. True IDE Mode I/O Decoding 1 0 0 1 1 1 Sector No. Sector No.
9 CF-ATA registers
commands to the Card. These registers are collectively referred to as the ‘task file’.
- Using the normal register address.
- Using the corresponding even address (normal address -1) when -CE1 is High and - CE2 Low, unless -IOIS16 is High (not asserted by the card) and an I/O cycle is in progress. Register data are input or output on data bus lines D15-D8. In True IDE mode, the size of the transfer is based solely on the register being addressed. All registers are 8-bit only except for the Data Register, which is normally 16 bits. However, they can be configured to be accessed in 8-bit mode for non-DMA operations, by using a Set Features command (see Section 10.17).
9.1 Data Register
The Data register is located at address 1F0h [170h], offset 0h, 8h, and 9h. restrictions on the operations that can be performed. Table 41. Data Register Access (Memory and I/O mode)
- -REG signal is mode dependent. It must be Low when the Card operates in I/O Mode and High when it operates in Memory
9.2 Error Register
The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
9.2.1 Bit 7 (BBK)
This bit is set when a Bad Block is detected.
9.2.2 Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
9.2.3 Bit 5
9.2.4 Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
9.2.5 Bit 3
9.2.6 Bit 2 (Abort)
Ready, Write Fault, etc.) or when an invalid command has been issued.
9.2.7 Bit 1
9.2.8 Bit 0 (AMNF)
This bit is set when there is a general error. Table 42. Data Register Access (True IDE mode)
9.3 Feature Register
The Feature register is a write-only register, located at address 1F1h [171h], offset 1h, Dh.
9.4 Sector Count Register
The Sector Count register is located at address 1F2h [172h], offset 2h. transferred in order to complete the request. The default value is 01h.
9.5 Sector Number (LBA 7-0) Register
The Sector Number register is located at address 1F3h [173h], offset 3h. (LBA), for any data access for the subsequent sector transfer command.
9.6 Cylinder Low (LBA 15-8) Register
The Cylinder Low register is located at address 1F4h [174h], offset 4h. 8 of the Logical Block Address.
9.7 Cylinder High (LBA 23-16) Register
The Cylinder High register is located at address 1F5h [175h], offset 5h. 16 of the Logical Block Address. Table 43. Error Register
9.8 Drive/Head (LBA 27-24) Register
The Driver/Head register is located at address 1F6h [176h], offset 6h. The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined in Table 44
9.8.1 Bit 7
This bit is set to ‘1’.
9.8.2 Bit 6 (LBA)
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA is set to ‘0’, Cylinder/Head/Sector mode is selected. When LBA is set to’1’, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows:
- LBA7-LBA0: Sector Number Register D7 to D0
- LBA15-LBA8: Cylinder Low Register D7 to D0
- LBA23-LBA16: Cylinder High Register D7 to D0
- LBA27-LBA24: Drive/Head Register bits HS3 to HS0
9.8.3 Bit 5
This bit is set to ‘1’.
9.8.4 Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (Master). When DRV is ‘1’, drive/card 1 is selected (Slave). The Card is set to Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register.
9.8.5 Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit 27 in the Logical Block Address mode.
9.8.6 Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit 26 in the Logical Block Address mode.
9.8.7 Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode.
9.8.8 Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.
9.9 Status & Alternate Status Registers
[376h], respectively. Offsets are 7h and Eh. These registers return the Card status when read by the host. Register does not clear a pending interrupt.
9.9.1 Bit 7 (BUSY)
host is denied access. No other bits in this register are valid when this bit is set to ‘1’.
9.9.2 Bit 6 (RDY)
9.9.3 Bit 5 (DWF)
When set this bit indicates a Write Fault has occurred.
9.9.4 Bit 4 (DSC)
This bit is set when the Card is ready.
9.9.5 Bit 3 (DRQ)
the host through the Data register. The bit is cleared by the next command.
9.9.6 Bit 2 (CORR)
corrected. This condition does not terminate a multi-sector read operation.
9.9.7 Bit 1 (IDX)
This bit is always set to ‘0’. Table 44. Drive/Head Register
1 LBA 1 DRV HS3 HS2 HS1 HS0
9.9.8 Bit 0 (ERR)
the command block registers. This bit is cleared by the next command.
9.10 Device Control Register
The Device COntrol register is located at address 3F6h [376h], offset Eh.
9.10.1 Bit 7 to 3
Don’t care. The host should reset this bit to ‘0’.
9.10.2 Bit 2 (SW Rst)
9.10.3 Bit 1 (–IEn)
Configuration and Status Register. It is set to ‘0’ at Power On.
9.10.4 Bit 0
Table 45. Status & Alternate Status Register Table 46. Device Control Register
9.11 Card (Drive) Address Register
The Card (Drived) Address register is located at address 3F7h [377h], offset Fh.
9.11.1 Bit 7
9.11.2 Bit 6 (–WTG)
This bit is ‘0’ when a write operation is in progress, otherwise, it is ‘1’.
9.11.3 Bit 5 (–HS3)
This bit is the negation of bit 3 in the Drive/Head register.
9.11.4 Bit 4 (–HS2)
This bit is the negation of bit 2 in the Drive/Head register.
9.11.5 Bit 3 (–HS1)
This bit is the negation of bit 1 in the Drive/Head register.
9.11.6 Bit 2 (–HS0)
This bit is the negation of bit 0 in the Drive/Head register.
9.11.7 Bit 1 (–nDS1)
This bit is ‘0’ when drive 1 is active and selected.
9.11.8 Bit 0 (–nDS0)
This bit is ‘0’ when the drive 0 is active and selected. Table 47. Card (Drive) Address Register
10 CF-ATA command description
the host not issuing commands unless the Card is not busy (BSY is ‘0’).
- Class 1:Upon receipt of a Class 1 command, the Card sets BSY within 400ns.
- Class 2:Upon receipt of a Class 2 command, the Card sets BSY within 400ns, sets up the sector buffer for a write operation, sets DRQ within 700µs, and clears BSY within 400ns of setting DRQ.
- Class 3:Upon receipt of a Class 3 command, the Card sets BSY within 400ns, sets up the sector buffer for a write operation, sets DRQ within 20ms (assuming no re- assignments), and clears BSY within 400ns of setting DRQ. For reasons of backward compatibility some commands are implemented as ‘no operation’ NOP . Table 48 summarizes the CF-ATA command set with the paragraphs that follow describing the individual commands and the task file for each.
Table 48. CF-ATA Command Set (1)
1 Check Power Mode E5h or 98h D
1 Execute Drive Diagnostic 90h YD
1 Erase Sector(s) C0h Y Y Y Y Y
1 Identify Drive ECh D
1 Idle E3h or 97h Y D
1 Idle Immediate E1h or 95h D
1 Initialize Drive Parameters 91h Y Y
1 NOP 00h D
1 Read Buffer E4h D
1 Read DMA C8 Y Y Y Y Y
1 Read Multiple C4h Y Y Y Y Y
1 Read Sector(s) 20h or 21h Y Y Y Y Y
1 Read Verify Sector(s) 40h or 41h Y Y Y Y Y
1 Recalibrate 1Xh D
1 Request Sense 03h D
1 Set Features EFh Y D
1 Set Multiple Mode C6h Y D
1 Set Sleep Mode E6h or 99h D
10.1 Check Power Mode (98h or E5h)
This command checks the power mode. Register to FFh, clear BSY and generate an interrupt. Table 49 defines the Byte sequence of the Check Power Mode command.
1 Stand By E2h or 96h D
1 Stand By Immediate E0h or 94h D
1 Translate Sector 87h Y Y Y Y Y
1 Wear Level F5h Y
2 Write Buffer E8h D
3 Write Multiple C5h Y Y Y Y Y
3 Write Multiple w/o Erase CDh Y Y Y Y Y
2 Write Sector(s) 30h or 31h Y Y Y Y Y
2 Write Sector(s) w/o Erase 38h Y Y Y Y Y
3 Write Verify 3Ch Y Y Y Y Y
- FR = Features Register, SC = Sector Count Regi ster, SN = Sector Number Register, CY = Cylinder
the Compact Flash Memory Card and head parameters are used. C - the register contains command specific data (see command descriptors for use). Table 48. CF-ATA Command Set (1) (continued) Table 49. Check Power Mode
10.2 Execute Drive Diagnostic (90h)
This command performs the internal diagnostic tests implemented by the Card. does not allow for direct inter-drive communication. the Master and the Slave with the Master responding with the status for both devices. codes shown in Table 51 are returned in the Error Register at the end of the command. Table 50. Execute Drive Diagnostic Table 51. Diagnostic Codes
10.3 Erase Sector(s) (C0h)
defines the Byte sequence of the Erase Sector command.
10.4 Identify Drive (ECh)
defines the Identify Drive command Byte sequence. All reserved bits or Words are zero. Table 54 shows the definition of each field in the Identify Drive Information.
10.4.1 Word 0: Gener al Configuration
This field indicates the general characteristics of the device. operation report only the 848Ah value as they are always intended as removable devices. Alternate Configuration Values for Word 0 is 044Ah. cards, alternate value of Word 0 is set in True IDE Mode of operation.
10.4.2 Word 1: Default Number of Cylinders
value will be the same as the number of cylinders.
10.4.3 Word 3: Default Number of Heads
This field contains the number of translated heads in the default translation mode. Table 52. Erase Sector(s)
SMCxxxBF CF-ATA command description
10.4.4 Word 6: Default Num ber of Sectors per Track
This field contains the number of sectors per track in the default translation mode.
10.4.5 Word 7-8: Number of Sectors per Card
This field contains the number of sectors per Card. This double Word value is also the first invalid address in LBA translation mode.
10.4.6 Word 10-19: Memory Card Serial Number
The contents of this field are right justified and padded with spaces (20h).
10.4.7 Word 23-26: Firmware Revision
This field contains the revision of the firmware for this product.
10.4.8 Word 27-46: Model Number
This field contains the model number for this product and is left justified and padded with spaces (20h).
10.4.9 Word 47: Read/Writ e Multiple Sector Count
This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands.
10.4.10 Word 49: Capabilities
- Bit 13 Standby Timer: is set to ’0’ to indicate that the Standby timer operation is defined by the manufacturer.
- Bit 9 LBA support: CompactFlash Memory Cards support LBA mode addressing.
- Bit 8 DMA Support: Read/Write DMA commands are supported.
10.4.11 Word 51: PIO Data Transfer Cycle Timing Mode
This field defines the mode for PIO data transfer. For backward compatibility with BIOSs written before Word 64 was defined for advanced modes, a device reports in Word 51, the highest original PIO mode it can support (PIO mode 0, 1 or 2). Bits 15-8: are set to 02H.
10.4.12 Word 53: Translation Parameter Valid
- Bit 1: is set to '1' to indicate that Words 64 to 70 are valid
- Bit 0: is set to '1' to indicate that Words 54 to 58 are valid
10.4.13 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track
These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode.
CF-ATA command description SMCxxxBF
10.4.14 Word 57-58: Current Capacity
This field contains the product of the current cylinders, heads and sectors.
10.4.15 Word 59: Mult iple Sector Setting
- Bits 15-9 are reserved and must be set to ‘0’.
- Bit 8 is set to ‘1’, to indicate that the Multiple Sector Setting is valid.
- Bits 7-0 are the current setting for the number of sectors to be transferred for every interrupt, on Read/Write Multiple commands; the only values returned are ‘00h’ or ‘01h’.
10.4.16 Word 60-61: Total S ectors Addressable in LBA Mode
This field contains the number of sectors addressable for the Card in LBA mode only.
10.4.17 Word 63: Multi-Word DMA transfer
Bits 15 through 8 of Word 63 of the Identify Device parameter information identifies which Multi-Word DMA mode that has been selected by host.Each bit of Word 0 is significant. Only one of these bits can be set to ‘1’ by the CompactFlash Storage Card to indicate the Multi- Word DMA mode which is currently selected:
- Bits 15 to 11 are reserved.
- Bit 10: when set to ‘1’, it indicates that Multi-Word DMA mode 1 has been selected.
- Bit 9: when set to ‘1’, it indicates that Multi-Word DMA mode 1 has been selected.
- Bit 8: when set to ‘1’, it indicates that Multi-Word DMA mode 0 has been selected. Bits 7 to 0 define the Multi-Word DMA data transfer supported field. Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate which Multi-Word DMA mode is supported:
- Bit 7 to 3 are reserved.
- Bit 2: when set to ‘1’, it indicates that the CompactFlash Storage Card supports Multi- Word DMA modes 2, 1 and 0.
- Bit 1: when set to ‘1’, it indicates that the CompactFlash Storage Card supports Multi- Word DMA modes 1 and 0.
- Bit 0: when set to ‘1’, it indicates that the CompactFlash Storage Card supports Multi- Word DMA mode 0. Note: 1 Selection of Multi-Word DMA modes 3 and above are specific to CompactFlash, and are reported in Word 163.
2 Support for Multi-Word DMA modes 3 and above are specific to CompactFlash are reported
in Word 163.
SMCxxxBF CF-ATA command description
10.4.18 Word 64: Advanced PIO transfer modes supported
This field is bit significant. Any number of bits may be set to ‘1’ in this field by the CompactFlash Memory Card to indicate the advanced PIO modes it is capable of supporting.
- Bits 7-2 are reserved for future advanced PIO modes.
- Bit 1 is set to ‘1’, indicates that the CompactFlash Memory Card supports PIO mode 4.
- Bit 0 is set to ‘1’ to indicate that the CompactFlash Memory Card supports PIO mode 3. Note: Support for PIO modes 5 and above are specific to CompactFlash are reported in Word 163
10.4.19 Word 65: Minimum Mult i-Word DMA transfer cycle time
Word 65 of the parameter information of the Identify Device command is defined as the minimum Multi-Word DMA transfer cycle time. It corresponds to the minimum cycle time for which the Card ensures data integrity during transfers. It is expressed in nanoseconds. The returned value is ‘50h’ (for Cycle time values refer to Table 22).
10.4.20 Word 66: Recommended Multi- Word DMA transfer cycle time
Word 66 of the parameter information of the Identify Device command is defined as the recommended Multi-Word DMA transfer cycle time. The returned value is ‘50h’ (for Cycle time values refer to Table 22).
10.4.21 Word 67: Minimum PIO transfer cycle time without flow control
This field gives the minimum cycle time (in ns) that the host should use for the CompactFlash Memory Card to ensure data integrity during transfers when flow control is not used. The returned value is ‘50h’ (for Cycle time values refer to Table 22).
10.4.22 Word 68: Minimum PIO tr ansfer cycle time with IORDY
This field gives the minimum cycle time (in ns) supported by the CompactFlash Memory Card to perform data transfers using IORDY flow control. The returned value is ‘50h’ (for Cycle time values refer to Table 22).
10.4.23 Word 163: Advanced True IDE Timing mode capabilities and settings
modes using the True IDE interface.
- Bits 2-0: Advanced True IDE PIO Mode supported. The returned value is ‘2h’ to indicate that PIO mode 6 is the highest PIO mode supported.
- Bits 5-3: Advanced True IDE Multi-Word DMA mode supported. The returned value is ‘2h’ to indicate that Multi-Word DMA mode 4 is the highest Multi- Word DMA mode supported.
- Bits 8-6: Advanced True IDE PIO mode selected. These bits indicate the current True IDE PIO mode selected on the Card.
- Bits 11-9: Advanced True IDE Multi-Word DMA mode selected. These bits indicate the current True IDE Multi-Word DMA mode selected on the Card.
10.4.24 Word 164: Advanced PCMCI A I/O and Memory Timing modes
- Bits 2-0: maximum Advanced PCMCIA I/O mode supported. The returned value is ‘3h’ to indicate that 80ns is the maximum I/O timing mode supported by the Card.
- Bits 5-3: maximum PCMCIA Memory timing mode supported. The returned value is ‘3h’ to indicate that 80ns is the maximum PCMCIA Memory timing mode supported by the Card.
Table 53. Identify Drive
Table 54. Identify Drive Information 044Ah 2 Alternate Configuration.
1 XXXXh 2 Default number of cylinders
6 XXXXh 2 Default number of sectors per track
54 XXXXh 2 Current numbers of cylinders
55 XXXXh 2 Current numbers of heads
56 XXXXh 2 Current sectors per track
10.5 Idle (97h or E3h)
ATA specification. Table 55 defines the Byte sequence of the Idle command. PCMCIA mode this value is ‘0h’. PCMCIA mode this value is ‘0h’. Table 54. Identify Drive Information (continued) Table 55. Idle
10.6 Idle Immedi ate (95h or E1h)
interrupt. Table 56 defines the Idle Immediate command Byte sequence.
10.7 Initialize Drive Parameters (91h)
this command. Table 57 defines the Initialize Drive Parameters command Byte sequence. Table 56. Idle Immediate Table 57. Initialize Drive Parameters
10.8 NOP (00h)
aborted. Table 58 defines the Byte sequence of the NOP command.
10.9 Read Buffer (E4h)
sector buffer. This command has the same protocol as the Read Sector(s) command. Table 59 defines the Read Buffer command Byte sequence. Table 58. NOP Table 59. Read Buffer
10.10 Read DMA (C8h)
once for each 16 bit Word to be transferred. transferred or when an error occurred during the operation. the 8-bit transfer mode has been enabled by the Set Features command. Table 60 defines the Read DMA command Byte sequence. Table 60. Read DMA
10.11 Read Multiple (C4h)
of sectors defined by a Set Multiple command. sectors defined by a Set Multiple command are transferred without intervening interrupts. n = (sector count) module (block count). Interrupts are generated when DRQ is set at the beginning of each block or partial block. where the error occurred. The flawed data are pending in the sector buffer. Table 61 defines the Read Multiple command Byte sequence. Table 61. Read Multiple
10.12 Read Sector(s) (20h or 21h)
Bytes of data from the buffer. the Read Sector command Byte sequence.
10.13 Read Verify Sector(s) (40h or 41h)
no data is transferred to the host. When the command is accepted, the Card sets BSY . occurred. The Sector Count Register contains the number of sectors not yet verified. Table 63 defines the Read Verify Sector command Byte sequence. Table 62. Read Sector(s)
10.14 Recalibrate (1Xh)
purposes. Table 64 defines the Recalibrate command Byte sequence. Table 63. Read Verify Sector(s) Table 64. Recalibrate
10.15 Request Sense (03h)
error codes. The extended error code is returned to the host in the Error Register. Table 65. Request Sense Table 66. Extended Error Codes
10.16 Seek (7Xh)
range. Table 67 shows the Seek command Byte sequence.
10.17 Set Features (EFh)
Set Features command Byte sequence. Table 69 defines all features that are supported.
- Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature command is issued all data transfers will occur on the D7- D0 data lines and the –IOIS16 signal will not be asserted for data register accesses. The host must not enable this feature for DMA transfers.
- Feature 03h allows the host to select the PIO or the Multi-Word DMA transfer mode. The number of sectors to be transferred must be specified in the Sector Count register (see Table 70 for values). The upper 5 bits define the type of transfer and the lower 3 bits encode the transfer mode. Only one PIO mode and one Multi-Word mode can be selected at a time. The host can change the selected mode by issuing the Set Features command.
- Feature code 9Ah allows the host to configure the Card to best meet the host system power requirements. The host programs the Sector Count register to a value that is equal to one-fourth of the desired maximum average current (in mA) that the Card should consume. For example, if the Sector Count register is set to ‘6’, the Card must be configured to provide the best possible performance without exceeding 24 mA. Upon completion of the command, the Card replies to the host with the range of values that it supports. The minimum value is set in the Cylinder Low Register, and the maximum value is set in the Cylinder Hi register. After power-up, the Card defaults to operate at the highest performance and therefore in the highest current mode. Values outside this programmable range are accepted by the card. However, the Card will operate either at the lowest power or highest performance as appropriate.
Table 67. Seek
Table 68. Set Features Table 69. Features Supported 01h Enable 8-bit data transfers. 03h Set transfer mode based on value in Sector Count register. 55h Disable Read Look Ahead. 69h NOP Accepted for backward compatibility. 81h Disable 8 bit data transfer. 96h NOP Accepted for backward compatibility. 97h Accepted for backward compatibility. Use of this Feature is not recommended. Table 70. Transfer Mode Values
- Mode = transfer mode number
10.18 Set Multiple Mode (C6h)
checks the Sector Count Register.
10.19 Set Sleep Mode (99h or E6h)
Table 71. Set Multiple Mode
10.20 Standby (96h or E2)
10.21 Standby Immediate (94h or E0h)
ATA Standby Mode), clear BSY and return the interrupt immediately. the Standby Immediate Byte sequence. Table 72. Set Sleep Mode Table 73. Standby
10.22 Translate Sector (87h)
command Byte sequence. Table 76 represents the information in the buffer. Table 74. Standby Immediate Table 75. Translate Sector Table 76. Translate Sector Information
10.23 Wear Level (F5h)
Table 77 defines the Wear Level command Byte sequence.
10.24 Write Buffer (E8h)
command and transfers 512 Bytes. Table 78 defines the Write Buffer command Byte sequence. Table 77. Wear level Table 78. Write Buffer
10.25 Write DMA (CAh)
asserts -IOWR once for each 16 bit Word to be transferred. transferred or when an error occurred during the operation. the 8-bit transfer mode has been enabled by the Set Features command. Table 79 defines the Write DMA command Byte sequence. Table 79. Write DMA
10.26 Write Multiple Command (C5h)
Multiple command is transferred without intervening interrupts. n = (sector count) module (block count). will be rejected with an aborted command error. sector. The Sector Count Register contains 6 and the address is that of the third sector. provided for compatibility with future products which may support a larger block count. Table 80 defines the Write Multiple command Byte sequence. Table 80. Write Multiple
10.27 Write Multiple without Erase (CDh)
Multiple without Erase command Byte sequence.
10.28 Write Sector(s) (30h or 31h)
by the host until BSY has been cleared by the host. Table 81. Write Multiple without Erase
10.29 Write Sector(s) without Erase (38h)
Table 82. Write Sector(s) Table 83. Write Sector(s) without Erase
10.30 Write Verify (3Ch)
command. Table 84 defines the Write Verify command Byte sequence. Table 84. Write Verify
SMCxxxBF CIS informa tion (typical)
11 CIS information (typical)
0000: Code 01, link 04 DF 79 01 FF – Tuple CISTPL_DEVICE (01), length 4 (04) – Device type is FUNCSPEC – Extended speed byte used – Device speed is 80ns – Write protect switch is not in control – Device size is 2K bytes 000C: Code 1C, link 05
02 DF 79 01 FF
– Tuple CISTPL_DEVICE_OC (1C), length 5 (05) – Device conditions: V CC = 3.3V – Device type is FUNCSPEC – Extended speed byte used – Device speed is 80ns – Write protect switch is not in control – Device size is 2K bytes 001A: Code 18, link 02 DF 01 – Tuple CISTPL_JEDEC_C (18), length 2 (02) – Device 0 JEDEC id: Manufacturer DF , ID 01 0022: Code 20, link 04 0A 00 00 00 – Tuple CISTPL_MANFID (20), length 4 (04) – Manufacturer # 0x000A hardware rev 0.00 002E: Code 15, link 12 04 01 53 54 4D 00 53 54 4D 2D x x x x 42 00 00 FF
CIS information (typical) SMCxxxBF – Tuple CISTPL_VERS_1 (15), length 18 (12) – Major version 4, minor version 1 – Product Information: Manufacturer: "Numonyx", – Product name: "Numonyx-xxxxB" 0056: Code 21, link 02 04 01 – Tuple CISTPL_FUNCID (21), length 2 (02) – Function code 04 (Fix ed Disk), system init 01 005E: Code 22, link 02 01 01 – Tuple CISTPL_FUNCE (22), length 2 (02) – This is a PC Card ATA Disk 0066: Code 22, link 03 02 0C 0F – Tuple CISTPL_FUNCE (22), length 3 (03) PP is not required – This is a silicon device – Identify Drive Model/Serial Number is guaranteed unique – Low-Power Modes supported: Sleep Standby Idle – Drive automatically minimizes power – All modes include 3F7 or 377 – Index bit is not supported – -IOIS16 is unspecified in Twin configurations 0070: Code 1A, link 05 01 03 00 02 0F – Tuple CISTPL_CONFIG (1A), length 5 (05) – Last valid configuration index is 3 – Configuration Register Base Address is 200 – Configuration Registers Present: Configuration Option Register at 200 – Card Configuration and Status Register at 202 – Pin Replacement Register at 204 – Socket and Copy Register at 206
SMCxxxBF CIS informa tion (typical) 007E: Code 1B, link 08 C0 C0 A1 01 55 08 00 20 – Tuple CISTPL_CFTABLE_ENTRY (1B), length 8 (08) – Configuration Table Index is 00 (default) – Interface type is Memory – BVDs not active, WP not active, RdyBsy active – Wait signal support required CC Power Description: Nom V = 5.0 V – map 2048 bytes of memory to Card address 0 – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 0092: Code 1B, link 06 00 01 21 B5 1E 4D – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration Table Index is 00 CC Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 00A2: Code 1B, link 0A C1 41 99 01 55 64 F0 FF FF 20 – Tuple CISTPL_CFTABLE_ENTR Y (1B), length 10 (0A) – Configuration Table Index is 01 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required CC Power Description: Nom V = 5.0 V – Decode 4 I/O lines, bus size 8 or 16 – IRQ may be shared, pulse and level mode interrupts are supported – Interrupts in mask FFFF are supported – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 00BA: Code 1B, link 06 01 01 21 B5 1E 4D Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) Configuration Table Index is 01 V CC Power Description: Nom V = 3.30 V,
CIS information (typical) SMCxxxBF Peak I = 45.0 mA 00CA: Code 1B, link 0F C2 41 99 01 55 EA 61 F0 01 07 F6 03 01 EE 20 – Tuple CISTPL_CFTABLE_ENTR Y (1B), length 15 (0F) – Configuration Table Index is 02 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required CC Power Description: – Nom V = 5.0 V – Decode 10 I/O lines, bus size 8 or 16 – I/O block at 01F0, length 8 – I/O block at 03F6, length 2 – IRQ may be shared, pulse and level mode interrupts are supported – Only IRQ14 is supported – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 00EC: Code 1B, link 06 02 01 21 B5 1E 4D – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration Table Index is 02 CC Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 00FC: Code 1B, link 0F C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20 – Tuple CISTPL_CFTABLE_ENTR Y (1B), length 15 (0F) – Configuration Table Index is 03 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required CC Power Description: Nom V = 5.0 V – Decode 10 I/O lines, bus size 8 or 16 – I/O block at 0170, length 8 – I/O block at 0376, length 2 – IRQ may be shared, pulse and level mode interrupts are supported – Only IRQ14 is supported – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
SMCxxxBF CIS informa tion (typical) 011E: Code 1B, link 06 03 01 21 B5 1E 4D – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration Table Index is 03 CC Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 012E: Code 14, link 00 – Tuple CISTPL_NO_LINK (14), length 0 (00) 0134: Code FF – Tuple CISTPL_END (FF)
Figure 10. Type I CompactFlash Memory Card Dimensions
13 Part numbering
Note: Other digits may be added to the ordering code for pre-programmed parts or other options. information on any aspect of the device, please contact your nearest Numonyx Sales Office. Table 85. Ordering Information Scheme
Table 86. Document Revision History 22-Sep-2006 1 Initial release. Note 1 updated below Figure 7: I/O Write waveforms. Table 32: Attribute Memory Function. 10-Dec-2007 3 Applied Numonyx branding.