SMCXXXAF NUMONYX | Alldatasheet
Document overview
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- PDF pages: 82
Technical content
Datasheet sections
- 1 Description
- 2 Capacity specification
- 3 Card physical description
- 4 Electrical interface
- 4.1 Electrical description
- 4.2 Electrical specification
- 4.3 Current measurement
- 5 Command interface
- 6 Card configuration
- 6.1 Configuration Option register (base + 00 h in attribute memory)
- 6.1.1 LevlREQ
- 6.1.2 Conf5 - Conf0 (configuration index)
- 6.2 Card Configuration and Status register (base + 02h in attribute memory)
- 6.2.1 Changed
- 6.2.2 SigChg
- 6.2.3 IOis8
- 6.2.4 PwrDwn
- 6.2.5 Int
- 6.3 Pin Replacement register (base + 04h in attribute memory)
- 6.3.1 CReady
- 6.3.2 CWProt
- 6.3.3 RReady
- 6.3.4 WProt
- 6.3.5 MReady
- 6.3.6 MWProt
- 6.4 Socket and Copy register (base + 06h in attribute memory)
- 6.4.1 Drive #
- 6.5 Attribute memory function
Datasheet sections
- 8.8.8 Bit 0 (HS0)
- 8.9 Status & alternate status registers (address 1F7h [177h] & 3F6h [376h];
- 8.9.1 Bit 7 (BUSY)
- 8.9.2 Bit 6 (RDY)
- 8.9.3 Bit 5 (DWF)
- 8.9.4 Bit 4 (DSC)
- 8.9.5 Bit 3 (DRQ)
- 8.9.6 Bit 2 (CORR)
- 8.9.7 Bit 1 (IDX)
- 8.9.8 Bit 0 (ERR)
- 8.10 Device control register (address 3F6h [376h]; offset Eh)
- 8.10.1 Bit 7 to
- 8.10.2 Bit 2 (SW Rst)
- 8.10.3 Bit 1 (–IEn)
- 8.10.4 Bit
- 8.11 Card (drive) address register (address 3f7h [377h]; offset Fh)
- 8.11.1 Bit
- 8.11.2 Bit 6 (–WTG)
- 8.11.3 Bit 5 (–HS3)
- 8.11.4 Bit 4 (–HS2)
- 8.11.5 Bit 3 (–HS1)
- 8.11.6 Bit 2 (–HS0)
- 8.11.7 Bit 1 (–nDS1)
- 8.11.8 Bit 0 (–nDS0)
- 9 CF-ATA command description
- 9.1 Check Power mode command (98h or E5h)
- 9.2 Execute Drive Diagnostic command (90h)
- 9.3 Erase Sector(s) command (C0h)
- 9.4 Identify Drive command (ECh)
- 9.4.1 Word 0: general configuration
- 9.4.2 Word 1: default number of cylinders
- 9.4.3 Word 3: default number of heads
- 9.4.4 Word 6: default number of sectors per track
- 9.4.5 Word 7-8: number of sectors per card
- 9.4.6 Word 10-19: memory card serial number
Datasheet sections
- 9.26 Write Sector(s) command (30h or 31h)
- 9.27 Write Sector(s) without Erase command (38h )
- 9.28 Write Verify command (3Ch)
- 10 CIS information (typical)
- 11 Package mechanical
- 12 Ordering information
- 13 Revision history
Features
■ Custom-designed, highly-integrated memory controller – Fully compliant with CompactFlash TM specification 2.0 – Fully compatible with PCMCIA specification – PC card ATA interface supported – True IDE mode compatible ■ Small form factor – 36.4 mm x 42.8 mm x 3.3 mm ■ Low-power CMOS technology ■ 3.3 V / 5.0 V power supply ■ Power saving mode (with automatic wake-up) ■ High reliability – MTBF > 3,000,000 hours – Data reliability: < 1 non-recoverable error per 10 14 bits read – Endurance: > 2,000,000 Erase/Program cycles – Number of card insertions/removals: > 10,000 ■ High performance – Up to 16.6 Mbit/s transfer rate – Sustained write performance (host to card: 7.2 Mbit/s) ■ Operating system support – Standard software drivers operation ■ Available densities (formatted) – 32 Mbytes to 512 Mbytes ■ Hot swappable CompactFlashTM Table 1. Device summary
1 Description
The CompactFlash is a small form factor non-volatile memory card which provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems. The card operates in three basic modes,
- PCMCIA I/O mode
- PCMCIA memory mode
- True IDE mode It conforms to the PC card specification when operating in the PCMCIA I/O mode and PCMCIA memory mode (Personal Computer Memory Card International Association standard, JEIDA in Japan) and to the ATA specification when operating in True IDE mode. CompactFlash cards can be used with passive adapters in a PC-card type II or type III socket. The card has an internal intelligent controller which manages interface protocols, data storage and retrieval as well as error correcting code (ECC), defect handling, diagnostics and clock control. Once the card has been configured by the host, it behaves as a standard ATA (IDE) disk drive. The card has a super cap on V CC and a powerful power-loss management feature to prevent data corruption after power-down. The specification has been realized and approved by the CompactFlash association (CFA). This non-proprietary specification enables users to develop CF products that function correctly and are compatible with future CF design. The system highlights are shown in Table 2, Table 3, Table 4, Table 5, Table 6 and Table 7. Related documentation
- PCMCIA PC card standard, 1995
- PCMCIA PC card ATA specification, 1995
- AT attachment interface document, American National Standards Institute, X3.221- 1994
- CF+ and CompactFlash specification revision 2.0.
Table 2. System performance
- 113X, 83X and 49X, speed grade markings where 1X = 150 Kbytes/s. All values refer to the 256-Mbyte
CompactFlash card in PIO mode 4, cycle time 120 ns. Table 3. Current consumption (1)
- All values are typical at 25 °C and nominal supply voltage and refer to 256-Mbyte CompactFlash card.
Table 4. Environmental specifications Table 5. Physical dimensions
2 Capacity specification
heads, sector/tracks and cylinders. Table 6. CF capacity specification Table 7. System reliability and maintenance
- Dependent on final system qualification data.
3 Card physical description
female contacts on 50 mil (1.27 mm) centers. Figure 9 shows type I card dimensions. Figure 1. CompactFlash memory card block diagram
4 Electrical interface
4.1 Electrical description
- PC card ATA using I/O mode,
- PC card ATA using memory mode,
- True IDE mode, which is compatible with most disk drives. The signal/pin assignments are listed in Table 8 where Low active signals have a ‘–’ prefix. Pin types are Input, Output or Input/Output. The configuration of the card is controlled using the standard PCMCIA Configuration registers starting at address 200h in the attribute memory space of the memory card. For True IDE mode, pin 9 is grounded. Table 9 describes the I/O signals. Inputs are signals sourced from the host while outputs are signals sourced from the card. The signals are described for each of the three operating modes. All outputs from the card are totem pole except the data bus signals that are bi-directional tri-state. Refer to Section 4.2: Electrical specification for definitions of Input and Output type.
Table 8. Pin assignment and pin type
1 GND Ground GND Ground GND Ground
2 D03 I/O I1Z,OZ3 D03 I/O I1Z,OZ3 D03 I/O I1Z,OZ3
3 D04 I/O I1Z,OZ3 D04 I/O I1Z,OZ3 D04 I/O I1Z,OZ3
4 D05 I/O I1Z,OZ3 D05 I/O I1Z,OZ3 D05 I/O I1Z,OZ3
5 D06 I/O I1Z,OZ3 D06 I/O I1Z,OZ3 D06 I/O I1Z,OZ3
6 D07 I/O I1Z,OZ3 D07 I/O I1Z,OZ3 D07 I/O I1Z,OZ3
8 A10 I I1Z A10 I I1Z A10
10 A09 I I1Z A09 I I1Z A09 (1) II 1 Z
11 A08 I I1Z A08 I I1Z A08 (1) II 1 Z
12 A07 I I1Z A07 I I1Z A07 (1) II 1 Z
13 V CC Power V CC Power V CC Power
14 A06 I I1Z A06 I I1Z A06 (1) II 1 Z
15 A05 I I1Z A05 I I1Z A05 (1) II 1 Z
16 A04 I I1Z A04 I I1Z A04 (1) II 1 Z
17 A03 I I1Z A03 I I1Z A03 (1) II 1 Z
18 A02 I I1Z A02 I I1Z A02 I I1Z
19 A01 I I1Z A01 I I1Z A01 I I1Z
20 A00 I I1Z A00 I I1Z A00 I I1Z
21 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3
22 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3
23 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3
24 WP O OT3 –IOIS16 O OT3 –IOIS16 O ON3
27 D11
28 D12 (2) I/O I1Z,OZ3 D12 (2) I/O I1Z,OZ3 D12 (2) I/O I1Z,OZ3
29 D13 (2) I/O I1Z,OZ3 D13 (2) I/O I1Z,OZ3 D13 (2) I/O I1Z,OZ3
30 D14 (2) I/O I1Z,OZ3 D14 (2) I/O I1Z,OZ3 D14 (2) I/O I1Z,OZ3
31 D15 (2) I/O I1Z,OZ3 D15 (2) I/O I1Z,OZ3 D15 (2) I/O I1Z,OZ3
37 READY O OT1 IREQ O OT1 INTRQ O OZ1
41 RESET I I2Z RESET I I2Z -RESET I I2Z
45 BVD2 I/O I1U,OT1 –SPKR I/O I1U,OT1 –DASP I/O I1U,ON1
46 BVD1 I/O I1U,OT1 –STSCHG I/O I1U,OT1 –PDIAG I/O I1U,ON1
47 D08 (2) I/O I1Z,OZ3 D08 (2) I/O I1Z,OZ3 D08 (2) I/O I1Z,OZ3
48 D09 (2) I/O I1Z,OZ3 D09 (2) I/O I1Z,OZ3 D09 (2) I/O I1Z,OZ3
49 D10 (2) I/O I1Z,OZ3 D10 (2) I/O I1Z,OZ3 D10 (2) I/O I1Z,OZ3
50 GND Ground GND Ground GND Ground
- The signal should be grounded by the host.
- These signals are required only for 16 bi t accesses and not required when installed in 8 bit systems. Devices should allow
for 3-state signals not to consume current.
- The signal should be tied to V CC by the host.
- The -CSEL signal is ignored by the card in PC Card m odes. However, because it is not pulled up on the card in these
host to PC Card A25 or grounded by the host.
- The signal should be held High or tied to V CC by the host and RFU is Reserved for Future Use.
Table 8. Pin assignment and pin type (continued)
Table 9. Signal description Configuration Control and Status registers. (PC card I/O mode) Same as PC card memory mode. in the task file, the remaining lines should be grounded. required it is asserted High. Configuration and Status register. required it is asserted High. as audio functions are not supported. the master/slave handshake protocol. (PC card I/O mode) Same as PC card memory mode. while all data transfers are 16 bit using D00 to D15. (PC card I/O mode) Same for all modes. (True IDE mode) Same for all modes. Not used, should not be connected to the host. (True IDE mode) Not used, should not be connected to the host.
(True IDE mode) Same as PC card I/O mode. (PC card I/O mode) Same for all modes. (True IDE mode) Same for all modes. (PC card I/O mode) Same as PC card memory mode. (PC card memory mode) Not used. (PC card I/O mode) I 39 Not used. as a master, when open it is configured as a slave. (True IDE mode) Same as PC card I/O mode. (PC card I/O mode) Reads the CIS and Configuration registers. (True IDE mode) Grounded by the host. Table 9. Signal description (continued)
mode interrupt or held Low for a level mode interrupt. (True IDE mode) Active High Interrupt request to the host. memory, Low for attribute memory. up only if this pin is left High or unconnected. (PC card I/O mode) Same as PC card memory mode. (True IDE mode) Hardware Reset from the host (active Low). (PC card I/O mode) Same for all modes. (True IDE mode) Same for all modes. (PC card I/O mode) Same for all modes. (True IDE mode) Same for all modes.
(PC card I/O mode) Used for writing to the configuration registers. (True IDE mode) Not used, should be connected to VCC by the host. completion of the reset initialization sequence.
4.2 Electrical specification
- VCC = 5 V ± 10%
- -40 °C to 85 °C Table 11 shows that the card operates correctly in both the voltage ranges and that the current requirements must not exceed the maximum limit shown.
4.3 Current measurement
Table 11. Table 12 shows the Input leakage current, Table 13 the Input characteristics, Table 14 the Output drive type and Table 15 the Output drive characteristics. Table 10. Absolute maximum conditions Table 11. Input power
3.3 V ± 10% 79 mA -40 + 85 °C
Table 12. Input leakage current (1)
- x refers to the characteristics described in Table 13. For example, I1U indicates a pull up resistor with a type 1 input
Table 13. Input characteristics
1 Input voltage
2 Input voltage
3 Input voltage CMOS
Table 14. Output drive type (1)
- x refers to the characteristics described in Table 15. For example, OT3 refers to totem pole output with a type 3 output
Table 15. Output drive characteristics
1 Output voltage
2 Output voltage
3 Output voltage
5 Command interface
Table 19, Table 20, Table 21 and Table 22 show the read and write timing parameters. maximum value can be determined from the card information structure. Figure 2. Attribute memory Read timing diagram
- D OUT signifies data provided by the CompactFlash memory card to the system. The -CE signal or both the -OE signal and
the -WE signal must be de-asserted between consecutive cycle operations. Table 16. Attribute memory Read timing
Figure 3. Configuration register (att ribute memory) Write timing diagram
- D IN signifies data provided by the system to the CompactFlash card.
Table 17. Configuration register (attribute memory) Write timing
Figure 4. Common memory Read timing diagram
- D OUT means data provided by the CompactFlash memory card to the system.
Table 18. Common memory Read timing (1)
- ST CF does not assert the WAIT signal.
Figure 5. Common memory Write timing diagram
- D IN signifies data provided by the system to the CompactFlash memory card.
Table 19. Common memory Write timing (1)
- ST CF does not assert the WAIT signal.
Figure 6. I/O Read timing diagram
- D OUT signifies data provided by the CompactFlash memory card or to the system.
Table 20. I/O Read timing (1)
- ST CF does not assert the WAIT signal.
Figure 7. I/O Write timing diagram
- D IN signifies data provided by the system to the CompactFlash memory card or CF+ card.
Table 21. I/O Write timing (1)
- ST CF does not assert the WAIT signal.
asserted state as High regardless of whether the signal is actually negative or positive true. inverted from their electrical states on the bus. Figure 8. True IDE mode I/O timing diagram
- The device addresses consists of −CS0, −CS1, and A2-A0.
- The Data I/O consist of D15-D0 (16 bit) or D7-D0 (8 bit).
- −IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
Table 22. True IDE mode I/O Read/Write timing diagram
- The maximum load on -IOCS16 is 1 LSTTL with a 50 pF total load.
- t 0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time
card implementation should support any legal host implementation.
- This parameter specifies the time from the falling edge of -IORD to the moment when the data bus is no longer driven by
the CompactFlash memory card (tri-state).
- t 7 and t8 apply only to modes 0, 1 and 2. This signal is not valid for other modes.
6 Card configuration
(CIS). The card has four Configuration registers (Table 23 and Table 24).
- Configuration Option register
- Pin Replacement register
- Card Configuration and Status register
- Socket and Copy register They are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, in I/O Card mode these registers provide a method for accessing status information that would normally appear on dedicated pins in Memory Card mode. The location of the Card Configuration registers should always be read from the CIS.These registers cannot be used in True IDE mode. No writes should be performed to the attribute memory except to the Configuration register addresses. All other attribute memory locations are reserved. See Section 6.5: Attribute memory function.
Table 23. CompactFlash memory card registers and memory space decoding
6.1 Configuration Option regist er (base + 00h in attribute
decoding and interrupt to the card (see Table 25).
6.1.1 LevlREQ
mode is selected. Set to zero (0) after power-up.
6.1.2 Conf5 - Conf0 (configuration index)
is set to ‘0’ after power-up. Table 24. CompactFlash memory card configuration registers decoding Table 25. Configuration Option register (default value: 00h) Table 26. CompactFlash memory card configurations
000000 M e m o r y M e m o r y 0 h - F h , 4 0 0 h - 7 F F h
000001 Contiguous
000010 P r i m a r y I / OI / O 1 F 0 h - 1 F 7 h , 3 F 6 h - 3 F 7 h
000011 S e c o n d a r y I / O I / O 1 7 0 h - 1 7 7 h , 376h - 377h
6.2 Card Configuration and Stat us register (base + 02h in
6.2.1 Changed
the card is configured for the I/O interface.
6.2.2 SigChg
6.2.3 IOis8
always configured for both 8 and 16 bit I/O, so this bit is ignored.
6.2.4 PwrDwn
6.2.5 Int
Control register, this bit is ‘0’. Table 27. Card Configuration and Status register (default value: 00h)
6.3 Pin Replacement register (b ase + 04h in attribute memory)
memory mode and the IREQ signal in I/O mode. See Table 28 and Table 29.
6.3.1 CReady
6.3.2 CWProt
6.3.3 RReady
6.3.4 WProt
switch. When written, this bit acts as a mask for writing the corresponding CWProt bit.
6.3.5 MReady
This bit acts as a mask for writing the corresponding CReady bit.
6.3.6 MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit. Table 28. Pin Replacement register (default value: 0Ch) Table 29. Pin Replacement Changed bit/Mask bit values
0 X 0 0 Unchanged
1 X 0 1 Unchanged
6.4 Socket and Copy register (b ase + 06h in attribute memory)
Option register (see Table 30).
6.4.1 Drive #
This value can be used to address two different cards in the case of twin card configuration. The socket number is ignored by the card. Table 30. Socket and Copy register (default value: 00h)
6.5 Attribute memory function
are also located here, the base address of the configuration registers is 200h. attribute memory access. Refer to Table 31 for signal states and bus validity. Table 31. Attribute memory function (1)
- The –CE signal or both the –OE signal and the –WE signal must be de-asserted between consecutive cycle operations.
6.6 I/O transfer function
Table 32. I/O function
6.7 Common memory transfer function
common memory addresses. (see Table 33). Table 33. Common memory function
6.8 True IDE mode I/O function
the card to PC Card ATA mode. Table 34. True IDE mode I/O function
7 Software interface
7.1 CF-ATA Drive register set definition and protocol
- Standard PC-AT disk I/O address spaces – 1F0h-1F7h, 3F6h-3F7h (primary); – 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
- Any system decoded 16 byte I/O block using any available IRQ.
- Memory space. Communication to or from the card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four-register mapping methods. Table 35 is a detailed description of these methods:
7.2 Memory mapped addressing (conf = 0)
the Data register FIFO. It does not allow random access to the data buffer within the card. (read) or feature (write) register.
- Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if
consecutive (even then odd) bytes from the data buffer. Table 35. I/O configurations
0 Memory 0h-Fh, 400h-7FFh Memory mapped
1 I/O xx0h-xxFh I/O mapped 16 continuous registers
2 I/O 1F0-1F7h, 3F6h-3F7h Primary I/O mapped
3 I/O 170-177h, 376h-377h Secondary I/O mapped
embedded auto incrementing address logic. the data bus, along with odd data at offset 9 on the most significant byte of the data bus. Table 36. Memory mapped decoding
7.3 Contiguous I/O mapped addressing (conf = 1)
- Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if
consecutive (even then odd) bytes from the data buffer. Table 37. Contiguous I/O decoding
0 X 00000 h E v e n D a t a r e g i s t e r E v e n D a t a r e g i s t e r
0 X 00011 h E r r o r r e g i s t e r F e a t u r e r e g i s t e r
0 X 00102 h S e c t o r C o u n t r e g i s t e r S e c t o r C o u n t r e g i s t e r
0 X 00113 h S e c t o r N u m b e r r e g i s t e r S e c t o r N u m b e r r e g i s t e r
0 X 01004 h C y l i n d e r L o w r e g i s t e r C y l i n d e r L o w r e g i s t e r
0 X 01015 h C y l i nder High register Cylinder High register
0 X 01106 h S e l e c t C a r d / H e a d r e g i s t e r S e l e c t C a r d / H e a d r e g i s t e r
0 X 01117 h S t a t u s r e g i s t e r C o m m a n d r e g i s t e r
0 X 1110E h A l t e r n a t e S t a t u s r e g i s t e r D e v i c e C o n t r o l r e g i s t e r
0 X 1111F h D r i v e A d d r e s s r e g i s t e r R e s e r v e d
7.4 I/O primary and secondar y address configurations
are accessed in the block of I/O space as shown in Table 38. Table 38. Primary and secondary I/O decoding
7.5 True IDE mode addressing
When the card is configured in the True IDE mode, the I/O decoding is as shown in Table 39. Table 39. True IDE mode I/O decoding
8 CF-ATA registers
commands to the card. These registers are collectively referred to as the ‘task file’.
8.1 Data register (address 1F 0h [170h]; offset 0, 8, 9)
the operations that can be performed.
8.2 Error register (address 1F1h [171h]; offset 1, 0Dh read only)
8.2.1 Bit 7 (BBK)
This bit is set when a bad block is detected.
8.2.2 Bit 6 (UNC)
This bit is set when an uncorrectable error is encountered.
8.2.3 Bit 5
Table 40. Data register access
8.2.4 Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
8.2.5 Bit 3
8.2.6 Bit 2 (abort)
Ready, Write Fault, etc.) or when an invalid command has been issued.
8.2.7 Bit 1
8.2.8 Bit 0 (AMNF)
This bit is set when there is a general error.
8.3 Feature register (address 1F 1h [171h]; offset 1, 0Dh write
8.4 Sector Count register (a ddress 1F2h [172h]; offset 2)
transferred in order to complete the request. The default value is 01h.
8.5 Sector Number (L BA 7-0) register (address 1F3h [173h];
(LBA), for any data access for the subsequent sector transfer command. Table 41. Error register
8.6 Cylinder Low (LBA 15-8) re gister (address 1F4h [174h];
offset 4) This register contains the least significant 8 bits of the starting cylinder address or bits 15 to 8 of the logical block address.
8.7 Cylinder High (LBA 23-16) re gister (address 1F5h [175h];
offset 5) This register contains the most significant bits of the starting cylinder address or bits 23 to 16 of the logical block address.
8.8 Drive/Head (LBA 27-24) regist er (address 1F6h [176h]; offset
The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined in Table 42.
8.8.1 Bit 7
This bit is set to ‘1’.
8.8.2 Bit 6 (LBA)
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address mode (LBA). When LBA is set to ‘0’, Cylinder/Head/Sector mode is selected. When LBA is set to ’1’, Logical Block Address mode is selected. In Logical Block Address mode, the logical block address is interpreted as follows:
- LBA7-LBA0: Sector Number register D7 to D0.
- LBA15-LBA8: Cylinder Low register D7 to D0.
- LBA23-LBA16: Cylinder High register D7 to D0.
- LBA27-LBA24: Drive/Head register bits HS3 to HS0.
8.8.3 Bit 5
This bit is set to ‘1’.
8.8.4 Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (master). When DRV is ‘1’, drive/card 1 is selected (slave). The card is set to card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register.
8.8.5 Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit 27 in the Logical Block Address mode.
8.8.6 Bit 2 (HS2)
26 in the Logical Block Address mode.
8.8.7 Bit 1 (HS1)
25 in the Logical Block Address mode.
8.8.8 Bit 0 (HS0)
24 in the Logical Block Address mode. Table 42. Drive/Head register
1 LBA 1 DRV HS3 HS2 HS1 HS0
8.9 Status & alternate status re gisters (address 1F7h [177h] &
3F6h [376h]; offsets 7 & Eh) These registers return the card status when read by the host. Reading the status register clears a pending interrupt. Reading the auxiliary status register does not clear a pending interrupt. The status register should be accessed in Byte mode; in Word mode it is recommended that alternate status register is used. The status bits are described as follows
8.9.1 Bit 7 (BUSY)
The busy bit is set when only the card can access the command register and buffer. The host is denied access. No other bits in this register are valid when this bit is set to ‘1’.
8.9.2 Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash memory card operations. This bit is cleared at power-up and remains cleared until the card is ready to accept a command.
8.9.3 Bit 5 (DWF)
When set this bit indicates a write fault has occurred.
8.9.4 Bit 4 (DSC)
This bit is set when the card is ready.
8.9.5 Bit 3 (DRQ)
The data request is set when the card requires information be transferred either to or from the host through the data register. The bit is cleared by the next command.
8.9.6 Bit 2 (CORR)
This bit is set when a correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation.
8.9.7 Bit 1 (IDX)
This bit is always set to ‘0’.
8.9.8 Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in the error register contain additional information describing the error. In case of read or write access commands that end with an error, the address of the first sector with an error is in the command block registers. This bit is cleared by the next command.
8.10 Device control register (add ress 3F6h [376h]; offset Eh)
8.10.1 Bit 7 to 3
Don’t care. The host should reset this bit to ‘0’.
8.10.2 Bit 2 (SW Rst)
8.10.3 Bit 1 (–IEn)
configuration and status register. It is set to ‘0’ at power-on.
8.10.4 Bit 0
Table 43. Status & alternate status register Table 44. Device control register
8.11 Card (drive) address register (address 3f7h [377h]; offset Fh)
8.11.1 Bit 7
8.11.2 Bit 6 (–WTG)
This bit is ‘0’ when a write operation is in progress, otherwise, it is ‘1’.
8.11.3 Bit 5 (–HS3)
This bit is the negation of bit 3 in the drive/head register.
8.11.4 Bit 4 (–HS2)
This bit is the negation of bit 2 in the drive/head register.
8.11.5 Bit 3 (–HS1)
This bit is the negation of bit 1 in the drive/head register.
8.11.6 Bit 2 (–HS0)
This bit is the negation of bit 0 in the drive/head register.
8.11.7 Bit 1 (–nDS1)
This bit is ‘0’ when drive 1 is active and selected.
8.11.8 Bit 0 (–nDS0)
This bit is ‘0’ when the drive 0 is active and selected. Table 45. Card (drive) address register
9 CF-ATA command description
host not issuing commands unless the card is not busy (BSY is ‘0’).
- Class 1. Upon receipt of a class 1 command, the card sets BSY within 400 ns.
- Class 2. Upon receipt of a class 2 command, the card sets BSY within 400 ns, sets up the sector buffer for a write operation, sets DRQ within 700 µs, and clears BSY within 400 ns of setting DRQ.
- Class 3. Upon receipt of a class 3 command, the card sets BSY within 400 ns, sets up the sector buffer for a write operation, sets DRQ within 20 ms (assuming no re- assignments), and clears BSY within 400 ns of setting DRQ. For reasons of backward compatibility some commands are implemented as ‘no operation’ NOP . Table 46 summarizes the CF-ATA command set with the paragraphs that follow describing the individual commands and the task file for each.
Table 46. CF-ATA command set (1)
1 Check Power mode E5h or 98h D
1 Execute Drive Diagnostic 90h YD
1 Erase Sector(s) C0h Y Y Y Y Y
1 Identify Drive ECh D
1 Idle E3h or 97h Y D
1 Idle immediate E1h or 95h D
1 Initialize Drive Parameters 91h Y Y
1 NOP 00h D
1 Read Buffer E4h D
1 Read Multiple C4h Y Y Y Y Y
1 Read Sector(s) 20h or 21h Y Y Y Y Y
1 Read Verify Sector(s) 40h or 41h Y Y Y Y Y
1 Recalibrate 1Xh D
1 Request Sense 03h D
1 Set Features EFh Y D
1 Set Multiple mode C6h Y D
1 Set Sleep mode E6h or 99h D
1 Standby E2h or 96h D
9.1 Check Power mode command (98h or E5h)
This command checks the power mode. register to FFh, clear BSY and generate an interrupt. Table 47 defines the byte sequence of the Check Power mode command.
1 Standby immediate E0h or 94h D
1 Translate Sector 87h Y Y Y Y Y
1 Wear Level F5h Y
2 Write Buffer E8h D
3 Write Multiple C5h Y Y Y Y Y
3 Write Multiple w/o Erase CDh Y Y Y Y Y
2 Write Sector(s) 30h or 31h Y Y Y Y Y
2 Write Sector(s) w/o Erase 38h Y Y Y Y Y
3 Write Verify 3Ch Y Y Y Y Y
- FR = Features Register, SC = Sector Count Regi ster, SN = Sector Number Register, CY = Cylinder
Compact Flash memory card and head parameters are used. C - the register contains command specific data (see command descriptors for use). Table 46. CF-ATA command set (1) (continued) Table 47. Check Power mode
9.2 Execute Drive Diagnostic command (90h)
This command performs the internal diagnostic tests implemented by the card. does not allow for direct inter-drive communication. the master and the slave with the master responding with the status for both devices. codes shown in Table 49 are returned in the error register at the end of the command. Table 48. Execute Drive Diagnostic Table 49. Diagnostic codes
9.3 Erase Sector(s) command (C0h)
defines the byte sequence of the Erase Sector command.
9.4 Identify Drive command (ECh)
defines the Identify Drive command byte sequence. All reserved bits or words are zero. Table 52 shows the definition of each field in the identify drive information.
9.4.1 Word 0: general configuration
This field indicates that the device is a CompactFlash memory card.
9.4.2 Word 1: default number of cylinders
value will be the same as the number of cylinders.
9.4.3 Word 3: default number of heads
This field contains the number of translated heads in the default translation mode.
9.4.4 Word 6: default num ber of sectors per track
This field contains the number of sectors per track in the default translation mode.
9.4.5 Word 7-8: num ber of sectors per card
invalid address in LBA translation mode. Table 50. Erase Sector(s)
SMCxxxAF CF-ATA command description
9.4.6 Word 10-19: memo ry card serial number
The contents of this field are right justified and padded with spaces (20h).
9.4.7 Word 23-26: firmware revision
This field contains the revision of the firmware for this product.
9.4.8 Word 27-46: model number
This field contains the model number for this product and is left justified and padded with spaces (20h).
9.4.9 Word 47: read/write multiple sector count
This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands.
9.4.10 Word 49: capabilities
- Bit 13 Standby timer: it is set to ’0’ to indicate that the Standby timer operation is defined by the manufacturer.
- Bit 9 LBA support: CompactFlash memory cards support LBA mode addressing.
- Bit 8 DMA Support: DMA mode is not supported.
9.4.11 Word 51: PIO data transfer cycle timing mode
This field defines the mode for PIO data transfer. For backward compatibility with BIOSs written before word 64 was defined for advanced modes, a device reports in word 51, the highest original PIO mode it can support (PIO mode 0, 1 or 2). Bits 15-8: are set to 02H.
9.4.12 Word 53: transl ation parameter valid
- Bit 1: is set to '1' to indicate that words 64 to 70 are valid
- Bit 0: is set to '1' to indicate that words 54 to 58 are valid
9.4.13 Word 54-56: current number of cylinders, heads, sectors/track
These fields contains the current number of user addressable cylinders, heads, and sectors/track in the current translation mode.
9.4.14 Word 57- 58: current capacity
This field contains the product of the current cylinders, heads and sectors.
9.4.15 Word 59: mult iple sector setting
- Bits 15-9 are reserved and must be set to ‘0’.
- Bit 8 is set to ‘1’, to indicate that the multiple sector setting is valid.
- Bits 7-0 are the current setting for the number of sectors to be transferred for every interrupt, on Read/Write Multiple commands; the only values returned are 00h or 01h.
9.4.16 Word 60-61: total sect ors addressable in LBA mode
This field contains the number of sectors addressable for the card in LBA mode only.
9.4.17 Word 64: advance d PIO transfer modes supported
- Bits 7-2 are reserved for future advanced PIO modes.
- Bit 1 is set to ‘1’, indicates that the CompactFlash memory card supports PIO mode 4.
- Bit 0 is set to ‘1’ to indicate that the CompactFlash memory card supports PIO mode 3.
9.4.18 Word 67: minimu m PIO transfer cycle time without flow control
used. The value returned is 78h (for cycle time values refer to Table 22).
9.4.19 Word 68: mini mum PIO transfer cycle time with IORDY
cycle time values refer to Table 22). Table 51. Identify drive
Table 52. Identify drive information
1 XXXXh 2 Default number of cylinders
6 XXXXh 2 Default number of sectors per track
54 XXXXh 2 Current numbers of cylinders
55 XXXXh 2 Current numbers of heads
56 XXXXh 2 Current sectors per track
9.5 Idle command (97h or E3h)
the ATA specification. Table 53 defines the byte sequence of the Idle command. Table 53. Idle
9.6 Idle Immediate co mmand (95h or E1h)
interrupt. Table 54 defines the Idle Immediate command byte sequence.
9.7 Initialize Drive Parameters command (91h)
this command. Table 55 defines the Initialize Drive Parameters command byte sequence. Table 54. Idle Immediate Table 55. Initialize Drive Parameters
9.8 NOP command (00h)
aborted. Table 56 defines the byte sequence of the NOP command.
9.9 Read Buffer command (E4h)
defines the Read Buffer command byte sequence. Table 56. NOP Table 57. Read Buffer
9.10 Read Multiple command (C4h)
of sectors defined by a Set Multiple command. sectors defined by a Set Multiple command are transferred without intervening interrupts. n = (sector count) module (block count). Interrupts are generated when DRQ is set at the beginning of each block or partial block. 256 sectors. The transfer begins at the sector specified in the Sector Number register. the error occurred. The flawed data is pending in the sector buffer. Table 58 defines the Read Multiple command byte sequence. Table 58. Read Multiple
9.11 Read Sector(s) co mmand (20h or 21h)
bytes of data from the buffer. the Read Sector command byte sequence.
9.12 Read Verify Sector(s ) command (40h or 41h)
no data is transferred to the host. When the command is accepted, the card sets BSY . occurred. The Sector Count register contains the number of sectors not yet verified. Table 60 defines the Read Verify Sector command byte sequence. Table 59. Read Sector(s)
9.13 Recalibrate command (1Xh)
purposes. Table 61 defines the Recalibrate command byte sequence.
9.14 Request Sense command (03h)
error codes. The extended error code is returned to the host in the Error register. Table 60. Read Verify Sector(s) Table 61. Recalibrate
Table 62. Request Sense Table 63. Extended Error codes
9.15 Seek command (7Xh)
range. Table 64 shows the Seek command byte sequence.
9.16 Set Features command (EFh)
Set Features command byte sequence. Table 66 defines all features that are supported. D7D0 data bus and the –IOIS16 signal will not be asserted for data register accesses. times. The host may change the selected mode by issuing the Set Features command. and therefore the highest current mode. lowest power or highest performance as appropriate. Table 64. Seek
Table 65. Set Features Table 66. Features supported 01h Enable 8 bit data transfers. 03h Set transfer mode based on value in Sector Count register. 55h Disable Read Look Ahead. 69h NOP Accepted for backward compatibility. 81h Disable 8 bit data transfer. 96h NOP accepted for backward compatibility. 97h Accepted for backward compatibility. Use of this feature is not recommended. Table 67. Transfer mode values
- Mode = transfer mode number.
9.17 Set Multiple mo de command (C6h)
checks the Sector Count register. contains ‘0’ when the command is issued, Read and Write Multiple commands are disabled. Set Feature command. Table 68 defines the Set Multiple Mode command byte sequence.
9.18 Set Sleep mode co mmand (99h or E6h)
Table 68. Set Multiple mode Table 69. Set Sleep mode
9.19 Standby command (96h or E2)
9.20 Standby Immediate command (94h or E0h)
ATA Standby mode), clear BSY and return the interrupt immediately. the Standby Immediate byte sequence. Table 70. Standby Table 71. Standby Immediate
9.21 Translate Sect or command (87h)
command byte sequence. Table 73 represents the information in the buffer. Table 72. Translate Sector Table 73. Translate Sector information
9.22 Wear Level command (F5h)
Table 74 defines the Wear Level command byte sequence.
9.23 Write Buffer command (E8h)
command and transfers 512 bytes. Table 75 defines the Write Buffer command byte sequence. Table 74. Wear Level Table 75. Write Buffer
9.24 Write Multiple command (C5h)
Multiple command is transferred without intervening interrupts. n = (sector count) module (block count). will be rejected with an aborted command error. sector. The Sector Count register contains 6 and the address is that of the third sector. provided for compatibility with future products which may support a larger block count. Table 76 defines the Write Multiple command byte sequence. Table 76. Write Multiple
9.25 Write Multiple without Erase command (CDh)
Multiple without Erase command byte sequence.
9.26 Write Sector(s) co mmand (30h or 31h)
by the host until BSY has been cleared by the host. Table 77. Write Multiple without Erase Table 78. Write Sector(s)
9.27 Write Sector(s) with out Erase command (38h)
9.28 Write Verify command (3Ch)
command. Table 80 defines the Write Verify command byte sequence. Table 79. Write Sector(s) without Erase Table 80. Write Verify
CIS information (typical) SMCxxxAF
10 CIS information (typical)
0000: Code 01, link 04 DF 79 01 FF – Tuple CISTPL_DEVICE (01), length 4 (04) – Device type is FUNCSPEC – Extended speed byte used – Device speed is 80 ns – Write protect switch is not in control – Device size is 2 Kbytes 000C: Code 1C, link 05
02 DF 79 01 FF
– Tuple CISTPL_DEVICE_OC (1C), length 5 (05) – Device conditions: V CC = 3.3 V – Device type is FUNCSPEC – Extended speed byte used – Device speed is 80 ns – Write protect switch is not in control – Device size is 2 Kbytes 001A: Code 18, link 02 DF 01 – Tuple CISTPL_JEDEC_C (18), length 2 (02) – Device 0 JEDEC id: Manufacturer DF , ID 01 0022: Code 20, link 04 0A 00 00 00 – Tuple CISTPL_MANFID (20), length 4 (04) – Manufacturer # 0x000A hardware rev 0.00 002E: Code 15, link 12 04 01 53 54 4D 00 53 54 4D 2D x x x x 42 00 00 FF
SMCxxxAF CIS informa tion (typical) – Tuple CISTPL_VERS_1 (15), length 18 (12) – Major version 4, minor version 1 – Product Information: Manufacturer: "STM", – Product name: "STM-xxxxB" 0056: Code 21, link 02 04 01 – Tuple CISTPL_FUNCID (21), length 2 (02) – Function code 04 (Fix ed Disk), system init 01 005E: Code 22, link 02 01 01 – Tuple CISTPL_FUNCE (22), length 2 (02) – This is a PC Card ATA Disk 0066: Code 22, link 03 02 0C 0F – Tuple CISTPL_FUNCE (22), length 3 (03) PP is not required – This is a silicon device – Identify drive model/serial number is guaranteed unique – Low-power modes supported: Sleep Standby Idle – Drive automatically minimizes power – All modes include 3F7 or 377 – Index bit is not supported – -IOIS16 is unspecified in twin configurations 0070: Code 1A, link 05 01 03 00 02 0F
CIS information (typical) SMCxxxAF – Tuple CISTPL_CONFIG (1A), length 5 (05) – Last valid configuration index is 3 – Configuration register base address is 200 – Configuration registers present: configuration option register at 200 – Card configuration and Status register at 202 – Pin Replacement register at 204 – Socket and Copy register at 206 007E: Code 1B, link 08 C0 C0 A1 01 55 08 00 20 – Tuple CISTPL_CFTABLE_ENTRY (1B), length 8 (08) – Configuration table index is 00 (default) – Interface type is memory – BVDs not active, WP not active, RdyBsy active – Wait signal support required CC Power Description: Nom V = 5.0 V – map 2048 bytes of memory to card address 0 – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 0092: Code 1B, link 06 00 01 21 B5 1E 4D – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration table index is 00 CC power description: Nom V = 3.30 V, Peak I = 45.0 mA 00A2: Code 1B, link 0A C1 41 99 01 55 64 F0 FF FF 20 – Tuple CISTPL_CFTABLE_ENTR Y (1B), length 10 (0A) – Configuration table index is 01 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required CC power description: Nom V = 5.0 V – Decode 4 I/O lines, bus size 8 or 16 – IRQ may be shared, pulse and level mode interrupts are supported – Interrupts in mask FFFF are supported – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
SMCxxxAF CIS informa tion (typical) 00BA: Code 1B, link 06 01 01 21 B5 1E 4D – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration Table Index is 01 CC power description: Nom V = 3.30 V, – Peak I = 45.0 mA 00CA: Code 1B, link 0F C2 41 99 01 55 EA 61 F0 01 07 F6 03 01 EE 20 – Tuple CISTPL_CFTABLE_ENTR Y (1B), length 15 (0F) – Configuration Table Index is 02 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required CC power description: – Nom V = 5.0 V – Decode 10 I/O lines, bus size 8 or 16 – I/O block at 01F0, length 8 – I/O block at 03F6, length 2 – IRQ may be shared, pulse and level mode interrupts are supported – Only IRQ14 is supported – Miscellaneous features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 00EC: Code 1B, link 06 02 01 21 B5 1E 4D – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration table index is 02 CC power description: Nom V = 3.30 V, Peak I = 45.0 mA 00FC: Code 1B, link 0F C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20
CIS information (typical) SMCxxxAF – Tuple CISTPL_CFTABLE_ENTR Y (1B), length 15 (0F) – Configuration table index is 03 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required CC power description: Nom V = 5.0 V – Decode 10 I/O lines, bus size 8 or 16 – I/O block at 0170, length 8 – I/O block at 0376, length 2 – IRQ may be shared, pulse and level mode interrupts are supported – Only IRQ14 is supported – Miscellaneous features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 011E: Code 1B, link 06 03 01 21 B5 1E 4D – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration table index is 03 CC power description: Nom V = 3.30 V, Peak I = 45.0 mA 012E: Code 14, link 00 – Tuple CISTPL_NO_LINK (14), length 0 (00) 0134: Code FF – Tuple CISTPL_END (FF)
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 9. Type I CompactFlash memory card dimensions
Note: Other digits may be added to the ordering code for preprogrammed parts or other options. Devices are shipped from the factory with the memory content bits erased to ’1’. Table 81. Ordering information scheme
Table 82. Document revision history 22-Sep-2006 1 Initial release. 14-Nov-2007 2 ECOPACK text added in Section 11: Package mechanical. 12-Dec-2007 3 Applied Numonyx branding.