SM9403BM

SM9403BM NPC | Alldatasheet

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NIPPON PRECISION CIRCUITS—1 NIPPON PRECISION CIRCUITS INC. DVDRAM Servo-amplifier LSI OVERVIEW The SM9403BM is a DVDROM and DVDRAM servo preprocessor LSI, designed for double-speed format DVDROM and DVDRAM drives. The SM9403BM is fabricated using a BiCMOS process, and incorporates an analog signal processing circuit that generates signals needed by the digital servo processor, a DPD signal processing circuit (DVDROM), and a CAPA (Complementary Allocated Pit Address) detection circuit (DVDRAM) all in a single chip. It operates from a single 5 V supply, and is available in 36-pin plastic SSOP packages.

FEATURES

n DPD signal processor n Tracking error signal output n Focus error signal output n Tracking error signal sample-and-hold n Focus error signal sample-and-hold n CAPA detection function n Track count pulse generator n Off-track detection n 2V and 4V reference voltage generator n Serial interface for setting internal parameters n Sleep-mode function n Single 5 V supply n 36-pin plastic SSOP

APPLICATIONS

n Double-speed DVDROM drives n Double-speed DVDRAM drives

ORDERING INFORMATION

36-pin SSOP (Top View) Device Package SM9403BM 36-pin SSOP 1NC 2NC 3FER 4FHOLD 5FSUB 6ISET 7DPDD 8DPDC 9DPDB 10DPDA 11AGND 12MMTI 13CAPAN 14CAPAP 15CAPLFC 16TSUB 17THOLD 18TRE 19 VREF4

20 VREF2

21 TROFF

22 TRP

23 CAPAREA

24 CAPOUT

25 AVCC

26 CAPIN

27 CAPSEL

28 CAPSEEK

29 DVCC

30 SENB

31 SDATA

32 SCLK

33 DGND

34 DEFECT

35 DPDI

36 DPDG

NIPPON PRECISION CIRCUITS—2 PACKAGE DIMENSIONS (Unit: mm) BLOCK DIAGRAM 2.44 to 2.64 0.85 15.20 to 15.40 7.40 to 7.60 0.29 to 0.39 0.80 0.10 to 0.30 0.51 to 1.01 10.11 to 10.51 0.63 ± 0.10 0 to 8° 0.23 to 0.32 7°0.51 – 0.20 45° R0.63 to 0.89 Phase comparator LPF Voltage reference S / H LPF Serial interface S / H control DPDI DPDG ISET VREF2 VREF4 FER FHOLD FSUB TSUB THOLD CAPAP CAPAN CAPLFC CAPIN CAPOUT CAPAREA CAPSEL CAPSEEK TRP TROFF TRE SENB SDATA SCLK DGND DVCC AGND AVCC VREF2 DPDA DPDB DPDC DPDD Mono-multiviblator Equalizer Delay LPF Analog signal processor S / H MMTI SWB Track Pulse Generator SWA DEFECT

NIPPON PRECISION CIRCUITS—3 PIN DESCRIPTION Number Name I/O 1. I = input, Ipd = Input with b uilt-in pull-down resistor, I/O = input/output (N-channel open-drain when output), O = output Function

1 NC O No connection

2 NC O No connection

3 FER O Focus error signal output

4 FHOLD – F ocus error hold capacitor connection

5 FSUB I F ocus error signal input

6 ISET I DPD signal equalizer, ref erence current set resistor connection

7 DPDD I DPD signal input D

8 DPDC I DPD signal input C

9 DPDB I DPD signal input B

10 DPDA I DPD signal input A

11 AG N D – Analog circuit g round

12 MMTI I Mono-m ultivibr ator time-constant set resistor connection

13 C A PA N I ID data signal differential inverting input

14 C A PAP I ID data signal differential non-inverting input

15 CAPLFC – Slice-level detect capacitor connection

16 TSUB I T r ac king error signal input

17 THOLD – T r ac king error hold capacitor connection

18 TRE O Tracking error signal output

19 VREF4 O 4V ref erence v oltage output

20 VREF2 O 2V ref erence v oltage output

21 T RO F F O Off-track detect signal output. LOW when off-track. 22 TRP O Track count pulse output. HIGH-level pulse for land to outer tracking. 23 CAP AREA O I D interval detect signal output. ID interval detected when HIGH. 24 CAPOUT O Outer offset ID detect signal output. Outer offset ID interval detected when HIGH.

25 AVCC – Analog circuit power supply

26 CAPIN O Inner offset ID detect signal output. Inner offset ID interval detected when HIGH. 27 CAPSEL Ipd ID interval signal input. ID interval selected when HIGH. 28 CAPSEEK Ipd Seek oper ation signal input. Seek operation selected when HIGH.

29 DV C C – Logic circuit pow er supply

30 SENB I Ser ial interf ace enable input. Enabled when HIGH.

31 S DATA I/O Serial interf ace data input/ackno wledge output

32 SCLK I Ser ial interf ace clock input

33 DGND – Logic circuit g round

34 DEFECT Ipd Def ect position signal input. Def ect position indicated when HIGH.

35 DPDI I DPD signal hold delay set resistor connection

36 DPDG I DPD signal phase difference to voltage conver ter coefficient set resistor connection

NIPPON PRECISION CIRCUITS—4 SPECIFICATIONS Absolute Maximum Ratings GND = 0 V Recommended Operating Conditions GND = 0 V Recommended External Components Parameter Symbol Condition Rating Unit Supply v oltage r ange V CC 0.5 to 7.0 V Input voltage r ange V IN 0.5 to V CC + 0.5 V Oper ating temper ature r ange T opr 0 to 70 C Stor age temper ature r ange T stg 40 to 125 C Pow er dissipation P D 250 m W Soldering temperature T sld 260 C Solder ing time t sld 10 s Parameter Symbol Condition Rating Unit Specifi cations supply v oltage r ange V CC 4.75 to 5.25 V Oper ating supply voltage r ange V CC 4.5 to 5.5 V Oper ating temper ature r ange T opr 0 to 70 C Pin No. Pin name Component T olerance

4 FHOLD 1000pF capacitor K (±10%)

6 ISET

W resistor ±1% 0.01µF capacitor Z (+80% to 20%)

12 MMTI 120k

W resistor ±1% 15 CAPLFC 0.01µF capacitor Z (+80% to 20%)

17 THOLD 1000pF capacitor K (±10%)

19 VREF4 0.1µF capacitor Z (+80% to 20%) 20 VREF2 0.1µF capacitor Z (+80% to 20%)

35 DPDI 47k

W resistor ±1%

36 DPDG 33k

W resistor ±1%

NIPPON PRECISION CIRCUITS—5 V CC = 5V ± 5%, GND = 0V , T a = 0 to 70 C Parameter Symbol Condition Rating Unit min typ max Current consumption 1. 33k W resistor connected betw een DPDG and AGND 47k W resistor connected betw een DPDI and AGND 120k W resistor connected betw een MMTI and AGND 47k W resistor connected betw een ISET and AGND 1000pF capacitor connected betw een FHOLD and AGND 1000pF capacitor connected between THOLD and AGND 0.1µF capacitor connected between VREF4 and AGND 0.1µF capacitor connected between VREF2 and AGND 0.01µF capacitor connected betw een CAPLFC and AGND 0.01µF capacitor connected betw een ISET and AGND CAPAP , CAP AN, DPDA, DPDB, DPDC, DPDD, FSUB, TSUB connected to VREF2 or other 2V supply. SENB, SD A T A, SCLK connected to GND; All other pins (e xcluding supply and g round pins) open circuit. Sleep mode 1: DPD system only in sleep condition. Sleep mode 2: All blocks e xcept ref erence supply voltage gener ator in sleep condition. Sleep mode 3: All blocks in sleep condition. I CC1 Oper ating mode – 28 34 mA I CC2 Sleep mode 1 – 17 21 I CC3 Sleep mode 2 – 2.0 2.6 I CC4 Sleep mode 3 – – 1.0 D I CC I CC1 I CC2 9–– CAPSEEK, CAPSEL, DEFECT , SENB, SDATA, SCLK HIGH-level input v oltage V IH 0.8V CC ––V CAPSEEK, CAPSEL, DEFECT , SENB, SDATA, SCLK LOW-le vel input v oltage V IL – – 0.2V CC V CAPSEEK, CAPSEL, DEFECT HIGH-level input current I IH1 V IN = V CC 50 100 200 µA SENB, SD A T A, SCLK HIGH-level input current I IH2 V IN = V CC ––3 µ A CAPSEEK, CAPSEL, DEFECT , SENB, SDATA, SCLK LOW-le vel input current I IL V IN = GND 3– –µ A CAPAREA, CAPIN, CAPOUT , TRP , TROFF HIGH-level output v oltage V OH I OH 0.2mA V CC 0.2 – – V CAPAREA, CAPIN, CAPOUT , TRP , TROFF LOW -level output v oltage V OL1 I OL = 0.8mA – – 0.4 V S DATA LOW -level output v oltage V OL2 I OL = 7mA – – 1.0 V

NIPPON PRECISION CIRCUITS—6 Focus Sample-and-Hold, Low-pass Filter Characteristics (FSUB fi FER) V CC = 5V ± 5%, GND = 0V , T a = 0 to 70 C, FSUB and FER signals in phase Tracking Sample-and-Hold, Low-pass Filter Characteristics (TSUB fi TRE) V CC = 5V ± 5%, GND = 0V , T a = 0 to 70 C, TSUB and TRE signals in phase Parameter Condition Rating Unit min typ max FSUB input signal r ange VREF2 reference 1.25 0 +1.25 V FER output v oltage r ange VREF2 reference 1.25 0 +1.25 V FER output offset voltage VREF2 reference, V IN = V REF2 – – ±8.0 m V FER output offset voltage temper ature drift VREF2 reference – – ±45 µV/ C FER output signal slew rate LPF off 1 – – V/µs FER output load regulation I OUT = ±3mA, V IN = V REF2 – – ±10 mV FSUB input impedance 100 – – k W FER output signal gain 0.17 0 +0.17 dB FER output signal bandwidth 1. C L = 20pF , R L = 500 W V IN = 1.5Vp-p, 3dB from DC LPF off (FFE = HIGH) 500 – – kHz LPF on (FFE = LOW) 115 160 230 FER output gain peaking DC to 3dB frequency 3 – +0.5 dB Hold time FER output droop char acter istic V IN = 200mVp-p, C FHOLD S/H acquisition time D V IN = 200mV , target v alue ± 10% – – 1 µs FER output hold error With respect to the previous v alue – – ±4 m V Power-down state FER output impedance 1 – – M W Parameter Condition Rating Unit min typ max TSUB input signal r ange VREF2 reference 1.25 0 +1.25 V TRE output v oltage r ange VREF2 reference 1.25 0 +1.25 V TRE output offset voltage VREF2 reference, V IN = V REF2 – – ±8.0 m V TRE output offset voltage temper ature drift VREF2 reference – – ±45 µV/ C TRE output load regulation I OUT = ±3mA, V IN = V REF2 – – ±10 mV TSUB input impedance 100 – – k W TRE output signal gain 0.17 0 +0.17 dB TRE output signal bandwidth 1. C L = 20pF , R L = 500 W V IN = 1.5Vp-p, 3dB from DC TFE = HIGH 24 35 50 kHz TFE = LOW 115 160 230 TRE output gain peaking DC to 3dB frequency 3 – +0.5 dB Hold time TRE output droop char acter istic V IN = 200mVp-p, C THOLD S/H acquisition time D V IN = 200mV , target v alue ±10% – – 1 µs TRE output hold error With respect to the previous v alue – – ±4 m V Power-down state TRE output impedance 1 – – M W

NIPPON PRECISION CIRCUITS—7 DPD Error Signal Detector Characteristics (DPDA/DPDB/DPDC/DPDD fi TRP) V CC = 5V ± 5%, GND = 0V , Ta = 0 to 70°C Parameter 1 1. The tracking error signal TRE is positive with respect to VREF2 if the (DPDA + DPDC) signal phase diff erence is leading. The detected phase diff erence is the diff erence betw een the point when one inter nal comparator output changes (from CMA and CMB both HIGH or both LOW) until the second output changes before the first changes again. The phase difference is conver ted to a v oltage and sampled for output. Other signals are held constant in the output stage when a phase difference is detected. Condition Rating Unit min typ max DPDA/DPDB/DPDC/DPDD input v oltage range VREF2 reference -0.55 – +1 V DPDA/DPDB/DPDC/DPDD input impedance 1–– M W Signal gain relative accuracy Gain relative to DPDA, DPDB, DPDC, DPDD inputs – – ±0.17 dB Equalizer gain 1MHz setting DG2 =LOW 1.2 1.6 2.3 dB DG2 = HIGH 1.8 2.2 2.9 5MHz setting DG2 =LOW 5.5 6.1 6.6 DG2 = HIGH 6.1 6.7 7.2 Equalizer frequency response Peak gain frequency (EQE = HIGH) 3.75 5.0 6.25 MHz -3dB frequency (EQE = LOW) 11 22 33 Equalizer frequency response relative accuracy fpeak , (A + C) vs. (B + D) – – ±1.5 % AC coupling time circuit -3dB frequency Time constant 1 DG2 = LOW 56 84 109 kHz Time constant 2 DG2 = HIGH 17 24 32 AC coupling time constant relative accuracy -3dB frequency, (A + C) vs. (B + D) – – ±2 % Delay control r ange See table 4. See table 4. ns Phase diff erence detector minimum time DG1 = DG2 = LOW 2 – – ns Phase diff erence detector maximum time DG1 = DG2 = HIGH – – 1 µs Phase diff erence detector minimum repeat time Input pulse interval 120 – – ns Phase difference to voltage conv ersion coeffi cient DG1 = DG2 = LOW – See table 5. typ ± 20% mV/ns Phase difference to voltage conv ersion coefficient change accuracy – See table 8. ±1 dB Phase difference output offset voltage VREF2 reference – – ±0.1 V Phase difference output offset voltage temper ature drift VREF2 reference – – ±570 µV/ °C DEFECT signal response time – – 1 µs DPD enable response time DPE flag – – 2 µs Abnormal waveform TRP droop char acter istic V OUT = V REF2 ± 200mV , VREF2 reference – – 0.1 %/µs TRP output v oltage r ange VREF2 reference -1.25 0 +1.25 V TRP output signal frequency response -3dB frequency 500 – – kHz

NIPPON PRECISION CIRCUITS—8 Header Position Detector Characteristics (CAPAP/N fi CAPAREA, CAPIN, CAPOUT) V CC = 5V ± 5%, GND = 0V , Ta = 0 to 70°C Sample-and-Hold Control Signal Generator Characteristics V CC = 5V ± 5%, GND = 0V , Ta = 0 to 70°C Tracking Error Signal Switching Characteristics (SWA, SWB) V CC = 5V ± 5%, GND = 0V , Ta = 0 to 70°C Parameter Condition Rating Unit min typ max CAPAP/N input v oltage r ange 1 – 3 V Analog signal processor frequency response V IN = V REF2 ± 0.5V , -3dB from DC 13 – – MHz Analog signal quantization slice level – See table 9. typ ± 15% V Mono-m ultivibr ator time constant typ - 5% See table 10. typ + 45% µs Mono-m ultivibr ator time constant switching accuracy –– ± 5 % Mono-m ultivibr ator time-constant block interval accuracy – – ±2.5 % CAPIN, CAPOUT , CAP AREA output r ise time and f all time C L = 20pF – – 15 ns Parameter Condition Rating Unit min typ max FER, TRE output response time 1 1. FSHCNT and TSHCNT are the f ocus and tracking sample-and-hold inter nal control signals, respectively. Mono-m ultivibr ator/CAPSEL/CAPSEEK fi FSHCNT/TSHCNT – – 100 ns Serial interf ace (HRE, FHE, THE, HAE) fi FSHCNT/TSHCNT ––2 µ s Parameter Condition Rating Unit min typ max Switching response time Ser ial interf ace timing – – 1 µs

NIPPON PRECISION CIRCUITS—9 Track Count Pulse Generator Characteristics (TSUB fi TRP, TROFF) V CC = 5V ± 5%, GND = 0V , Ta = 0 to 70°C Reference Voltage Generator Characteristics (VREF2, VREF4) V CC = 5V ± 5%, GND = 0V , Ta = 0 to 70°C Parameter Condition Rating Unit min typ max TSUB input signal r ange VREF2 reference -1.25 – +1.25 V TSUB signal limiter voltage level VREF2 reference ±1.0 – – V TSUB signal amplifier gain f = 5kHz 5.83 6.0 6.17 dB Quantization level offset set v alue typ - 15% See table 15 typ + 15% mV TRP output compar ator hysteresis 1 1. TRP has the same polar ity as TRE (i.e. TRP is HIGH when TRE > VREF2). TROFF is HIGH when the input signal is inside the window, and LOW when outside the window. typ - 10% See table 16 typ + 10% mV TRP output compar ator hysteresis response time Minimum h ysteresis, target v alue ± 10% – – 600 ns TRP output compar ator hysteresis switching response time Minimum « maximum h ysteresis v alue – – 2 µs TROFF output compar ator window typ - 10% See table 17 typ + 10% mV TROFF output compar ator window switching response time Minimum « maximum window v alue – – 5 µs Parameter Condition Rating Unit min typ max VREF4 output v oltage V CC = 5V , Ta = 25 °C, IOUT = 0 3.84 4.0 4.16 V VREF2 output v oltage 1.92 2.0 2.08 V VREF4 output v oltage temper ature drift V CC = 5V , Ta = 0 to 70 °C, IOUT = 0 – – ±400 µV/ °C VREF2 output v oltage temper ature drift – – ±200 µV/ °C VREF4 output v oltage supply voltage dependency V CC = 5V ± 5%, T a = 25 °C, IOUT = 0 –– ± 6 m V VREF2 output v oltage supply voltage dependency –– ± 3 m V VREF4 output v oltage load regulation V CC = 5V , Ta = 25 °C IOUT = 0 to 8mA – – -20 mV VREF2 output v oltage load regulation I OUT = 0 to ±5mA – – ±10 m V Relative output voltage accuracy 1 1. Defined as (VREF2 - (VREF4 ÷ 2)). V CC = 5V , IOUT = 0 – – ±20 m V Relative output v oltage temper ature drift V CC = 5V , Ta = 0 to 70 °C, IOUT = 0 – – ±10 µV/ °C Relative output-voltage supply-voltage dependency V CC = 5V ± 5%, T a = 25 °C, IOUT = 0 – – ±1 m V VREF4 pow er-down output impedance 13 – – k W VREF2 pow er-down output impedance 1 – – M W

NIPPON PRECISION CIRCUITS—10 Serial Interface Characteristics (SCLK, SDATA, SENB) V CC = 5V ± 5%, GND = 0V , Ta = 0 to 70°C Parameter Symbol Condition Rating Unit min typ max SCLK pulse cycle t cySCK 100 – – ns SCLK HIGH-level pulse width t whSCK 40 – – ns SCLK LOW-le vel pulse width t wlSCK 40 – – ns SENB setup time t sSEN 20 – – ns SENB hold time t hSEN 40 – – ns SDATA setup time t sSDA 15 – – ns SDATA hold time t hSDA 15 – – ns ACK setup time 1 1. ACK is the acknowledge output (n-channel open-dr ain). LOW -level output when the data received is v alid. SDATA load capacitance is 15pF . tsACK 0– 2 0 n s ACK hold time 1 thACK –– 5 0 n s SENB interval t inSEN 100 – – ns SENB SCLOCK SDATA Controller SDATA Port tsSEN twhSCK twlCLK tcySCK tsSDA thSDA tsACK thACK tinSEN thSEN bit 0 bit 1 bit 15 LSB MSB ACK High Impedance

output goes LOW as an acknowledge signal. or OFF using the serial interface control bit FFE. Table 1. Port address and bit configuration1

1. · = don’t care, – = unassigned

Table 2. Focus low-pass filter ON/OFF control Table 3. Tracking low-pass filter cutoff frequency

NIPPON PRECISION CIRCUITS—12 DPD Error Signal Detector (DPDA/DPDB/DPDC/DPDD fi TRP) This stage compares the DPD signals, passes the comparator output through a low-pass filter to obtain the DPD tracking error signal. The DPD signals are first added, (DPDA + DPDC) and (DPDB + DPDD), then passed to an equalizer. A relative time delay is added for offset correction. The signals are then converted to a pulse waveform by comparators with hysteresis characteristics. The phase comparator then compares the phase of the pulse waveforms to obtain a time signal equiva- lent to the tracking error. The time signal is then con- verted to a voltage. The converted voltage is passed to the output stage, undergoes sampling timing compensation before being integrated to generate the tracking error signal output. The phase comparator incorporates a detector func- tion which prevents abnormal waveform signals get- ting to the output by holding the output constant. In addition, serial interface control bit DPE and input DEFECT can be used to force the tracking error sig- nal to the reference voltage VREF2. These controls can be used when powering up a system or to prevent output saturation from occurring during periods when the input signal is unstable. The relative time delay setting and time-to-voltage conversion coefficient can be controlled using serial interface control bits. Also, the equalizer used to compensate for the previous stage can be turned ON or OFF using serial interface control.

Table 4. DPD delay time settings

1. Default is 0 ns (DL4 = DL3 = DL2 = DL1 = LOW)

The DPD delay is positive when (A+C) leads (B+D). Table 4. DPD delay time settings (Continued)

Table 5. Phase difference to voltage converter Table 6. Equalizer control Table 7. DPD output control

• HIGH F orced to VREF2 HIGH LOW Active 1. Default is VREF2 (DPE = LOW)

Table 8. DPD delay time coefficient, phase difference to voltage converter coefficient, AC coupling time constant

1. Default is DG2 = DG1 = LOW

tized logic levels which are used as reference signals. ous signals to create a header area CAPAREA signal. trolled by serial interface control bits. Table 9. Slice level shift voltages Table 10. Mono-multivibrator time constants

1. Default is 4 µs and (8 + a ), where a » 6 · ln(2V LS /V H ), V H = input sig-

nal amplitude, V LS = slice level absolute v alue shown in table 9. Table 11. CAPOUT/CAPIN/CAPAREA logic

• = don’t care.
• = don’t care. Tracking Error Signal Switching (SWA, SWB) This stage performs tracking error signal switching during DVDRAM write/read and DVDROM and CD playback. Switching is controlled by serial interface control bits.

Table 12. Sample-and-hold logic

• HIGH · LOW HIGH HIGH LOW LOW · LOW · LOW HIGH ·· LOW LOW LOW
• HIGH · LOW LOW LOW
• · HIGH HIGH · HIGH
• · LOW HIGH · LOW 1. Default is LOW

Table 13. Sample-and-hold signal control logic

1. FSHCNT is the f ocus sample-and-hold control signal, and TSHCNT is

the trac king sample-and-hold control signal.

• LOW · LOW HIGH · SHCNT ·
• HIGH · SHCNT

Table 14. Tracking error signal select

width are controlled by serial interface bits. are controlled by serial interface bits. dence when writing to the port. Table 15. Offset voltage setting Table 16. TRP comparator hysteresis Table 17. TROFF comparator window Table 18. Sleep mode settings

1. Default is OFF (SL2 = SL1 = LOW)

NIPPON PRECISION CIRCUITS—18 NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infr ingement. Applications for any devices shown in this data sheet are for illustr ation only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing o r modification. The products described in this data sheet are not intended to use for the apparatus which infl uence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. Customers shall not e xport, directly or indirectly, any products without first obtaining required licenses and approv als from appropriate gover nment agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, J apan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9813AE 1999.09 NIPPON PRECISION CIRCUITS INC.