SM9103M

SM9103M NPC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

NIPPON PRECISION CIRCUITS—1 NIPPON PRECISION CIRCUITS INC. DVDRAM Head Amplifier LSI OVERVIEW The SM9103M is a photodiode photoelectric cur- rent-to-voltage conversion head amplifier LSI for optical disk pickups in DVDRAM/DVDROM equip- ment. It sums the photodiode current data signals and then converts the signals to a differential signal for output. The output tracking servo and focusing servo signals are derived from built-in sum and difference circuits, and the gain for these servo signals can be adjusted using serial interface controls. Each of the signals from the photodiodes, used to generate DPD (Differential Phase Detection) tracking servo signal, is current-to-voltage converted and then also output. It operates from a single 5 V supply, and is available in 36-pin plastic SSOP packages.

FEATURES

n RAM/ROM gain switching, low-noise RF signal generator (differential output) n ROM tracking DPD signal output n Variable-gain RAM tracking push-pull signal out- put n Address signal, high-speed push-pull signal output n Variable-gain focus error signal output n Tracking PD sum signal output n Focus PD sum signal output n Offset correction timing output (logic) n Temperature monitor function n Serial interface to control internal parameter set- tings n Sleep-mode function n Single 5 V supply n 36-pin plastic SSOP TYPICAL APPLICATIONS n Double-speed DVDROM equipment n Double-speed DVDRAM equipment

ORDERING INFORMATION

(Top view) Device Package SM9103M 36-pin SSOP 1MODE 2WRITE 3DGND 4DVCC 5TEMPO 6TEMPI 7T1 8T2 9T3 10T4 11F1 12F2 13AGND 14VREF 15FSUBB 16FSUB 17FADDB 18FADD 19 AGND

20 AVCC

21 DPDD

22 DPDC

23 DPDB

24 DPDA

25 DATAN

26 DATAP

27 TSUBB

28 TSUB

29 CAPAN

30 CAPAP

31 TADDB

32 TADD

33 CALREQ

34 SENB

35 SDATA

36 SCLK

NIPPON PRECISION CIRCUITS—2 PACKAGE DIMENSIONS (Unit: mm) BLOCK DIAGRAM 2.44 to 2.64 0.85 15.20 to 15.40 7.40 to 7.60 0.29 to 0.39 0.80 0.10 to 0.30 0.51 to 1.01 10.11 to 10.51 0.63 ± 0.10 0 to 8° 0.23 to 0.32 7°0.51 – 0.20 45° R0.63 to 0.89 A B C D A+B+C+D (A+B)-(C+D) DATAP DATAN TADDB TADD CAPAP CAPAN TSUBB TSUB DPDA DPDB DPDC DPDD CALREQ FSUB FSUBB FADDB FADD AGND AVCC TEMPO TEMPI WRITE MODE SDATA SENB SCLK VREF to each block Serial interface Gain switching amplifier (RAM read/write, ROM read) Analog Signal processor Offset canceller Thermal sensor Canceller control Offset canceller Gain switching amplifier Differential output buffer Amplifier Gain switch (2dB step) Buffer Buffer Buffer Buffer Differential output buffer Gain switch (2dB step) Amplifier Analog Signal processor +5V +5V DGND DVCC

NIPPON PRECISION CIRCUITS—3 PIN DESCRIPTION Number Name I/O 1. I = input, Ipd = Input with built-in pull-down resistor, I/O = input/output, O = output Function

1 MODE Ipd Mode switching/offset correction control input 1

2 WRITE Ipd Mode switching/offset correction control input 2

3 DGND – Logic circuit ground. Connect to the analog ground if there is no dedicated pickup or logic ground. 4 DVCC – Logic circuit supply. Connect to the analog supply if there is no dedicated pickup or logic supply. 5 TEMPO O Thermal sensor test output. Leave open for normal operation 6 TEMPI I Thermal sensor test input. Leave open for normal operation

7 T1 I Tracking PD input A

8 T2 I Tracking PD input B

9 T3 I Tracking PD input C

10 T4 I Tracking PD input D

11 F1 I Focus PD input E

12 F2 I Focus PD input F

13 AGND – Analog circuit g round

14 VREF I 2.0 V reference voltage input

15 FSUBB I F ocus error signal feedback input

16 FSUB O F ocus error signal output

17 FADDB I F ocus sum signal feedback input

18 FADD O Focus sum signal output

19 AGND – Analog circuit g round

20 AVCC – Analog circuit supply

21 DPDD O Buffered tracking signal output D for DPD servo

22 DPDC O Buffered tracking signal output C for DPD servo

23 DPDB O Buffered tracking signal output B for DPD servo

24 DPDA O Buffered tracking signal output A for DPD servo

25 DATAN O Phase-modulated data signal diff erential inverting output

26 DATAP O Phase-modulated data signal differential non-inverting output

27 TSUBB I Trac king push-pull signal feedback input

28 TSUB O Trac king push-pull signal output

29 CAPAN O ID data signal differential inverting output

30 CAPAP O ID data signal differential non-inverting output

31 T ADDB I T rac king PD sum signal feedback input

32 TADD O Tracking PD sum signal output

33 CALREQ O Offset correction status/request output

34 SENB I Ser ial interface enable input

35 SDATA I/O Serial interf ace data input/acknowledge output

36 SCLK I Ser ial interface clock input

NIPPON PRECISION CIRCUITS—4 SPECIFICATIONS Absolute Maximum Ratings GND = 0 V Recommended Operating Conditions GND = 0 V Parameter Symbol Condition Rating Unit Supply voltage range V CC 0.5 to 7.0 V Input voltage range V IN 0.5 to V CC + 0.5 V Input current range I IN 3.0 to +3.0 mA Operating temperature range T opr 0 to 70 C Storage temperature range T stg 40 to 125 C Power dissipation P D 250 mW Soldering temperature T sld 260 C Soldering time t sld 10 s Parameter Symbol Condition Rating Unit Specs-guaranteed supply voltage range V CC 4.75 to 5.25 V Operating supply voltage range V CC 4.5 to 5.5 V Reference voltage input V REF 1.89 to 2.11 V Operating temperature range T opr 0 to 70 C

NIPPON PRECISION CIRCUITS—5 V CC = 5 V ± 5%, GND = 0 V , T a = 0 to 70 C Tracking PD Input Characteristics (T1, T2, T3, T4) V CC = 5 V ± 5%, GND = 0 V , T a = 0 to 70 C Parameter Symbol Condition Rating Unit min typ max Current consumption 1. 18 k W resistor connected between TSUB and TSUBB 47 k W resistor connected between TADD and TADDB 22 k W resistor connected between FSUB and FSUBB 27 k W resistor connected between FADD and FADDB SENB, SDAT A, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit. I CC1 Operating mode – 24 30 mA I CC2 Sleep mode – – 1 MODE, WRITE, SENB, SDATA, SCLK HIGH-level input voltage V IH 0.8V CC ––V MODE, WRITE, SENB, SDATA, SCLK LOW-level input voltage V IL – – 0.2V CC V MODE, WRITE HIGH-level input current I IH1 V IN = V CC 50 100 200 µA SENB, SDAT A, SCLK HIGH-level input current I IH2 V IN = V CC ––3 µ A MODE, WRITE, SENB, SDATA, SCLK LOW-level input current I IL V IN = 0 V 3– –µ A CALREQ HIGH-level output voltage V OH I OH 0.2 mA V CC 0.2 – – V CALREQ LOW-level output voltage V OL1 I OL = 0.8 mA – – 0.4 V SDATA LOW-level output voltage V OL2 I OL = 7 mA – – 1.0 V VREF input current I REF V REF = 2.0 V – – 250 µA Parameter Condition Rating Unit min typ max Input impedance No signal – – 250 W Input conversion noise current 100 kHz to 10 MHz RAM read 1. DATAP DATAN output difference operation when 10 pF capacitors are connected to T1, T2, T3, T4 – 0.035 – µA rms ROM read – 0.27 – Pin voltage No signal – – 1.5 V

NIPPON PRECISION CIRCUITS—6 Data Signal Processor Characteristics V CC = 5 V ± 5%, GND = 0 V , T a = 0 to 70 C Parameter Condition Rating Unit min typ max DATAP DATAN current-to-voltage converter coefficient 1. [DATAP DATAN] = K + I + I + I RAM read 10.0 12.5 15.0 k W ROM read 2.50 3.12 3.74 CAPAP CAPAN current-to-voltage converter coefficient 2. [CAPAP CAPAN] = K {[I + I + I RAM read 11.3 14.1 16.9 k W DATAP , DATAN, CAPAP , CAPAN output impedance – – 100 W DATAP , DATAN, CAPAP , CAPAN output center voltage 3. 5 k W load connected to ground to prevent abnormal operation No signal 0.9V REF – 1.1V REF V CAPAP, CAPAN output center voltage difference No signal – – ±50 mV DATAP , DATAN, CAPAP , CAPAN output operating output voltage 10 k W load, output center voltage reference 0.7 – +0.7 V Variable coefficient switching time RAM ROM read – – 10 ms Saturation output reset time 4. Converging to within final v alue ± 10% RAM wr ite fi RAM read – – 500 ns DATAP , DATAN signal bandwidth 5. 10 pF input load capacitors connected to T1, T2, T3, T4. DATAP, DATAN, CAPAP , CAPAN output load conditions shown below. f = 100 kHz 3 dB frequency 19 – – MHz CAPAP , CAPAN signal bandwidth f = 100 kHz 3 dB frequency 20 – – MHz DATAP DATAN, CAPAP CAPAN gain peaking f = 100 kHz 3 dB frequency 3 – +0.5 dB DATAP DATAN, CAPAP CAPAN group delay time f = 1 to 10 MHz – – ±1.0 ns 0.01mF 0.01mF 5pF 5pF 5pF 5pF 10kW DATAP DATAN 0.01mF 0.01mF 10pF 5pF 10pF 5pF 10kW CAPAP CAPAN

NIPPON PRECISION CIRCUITS—7 Tracking Signal Processor Characteristics V CC = 5 V ± 5%, GND = 0 V , T a = 0 to 70 C Parameter Condition Rating Unit min typ max TSUB current-to-voltage converter coefficient RAM read R f = 18 k W V OUT = V REF ± 0.8 V 10.64 11.95 13.26 k W ROM read 2.67 2.99 9.92 RAM write 1.78 1.99 2.20 TADD current-to-voltage converter coefficient RAM read Rf = 47 kW 27.82 31.25 34.68 kWROM read 6.95 7.80 8.65 RAM write 4.63 5.20 5.77 DPDA, DPDB, DPDC, DPDD current-to-voltage converter coefficient3 RAM read 40.0 50.0 60.0 kW ROM read 10.0 12.5 15.0 T1, T2, T3, T4 converter coefficient relative error TSUB output, RAM/ROM read – – ±2 % TSUB, TADD, DPDA, DPDB, DPDC, DPDD output impedance – – 100 W TSUB oper ating output voltage 10 k W load connected to VREF 1 – 3 V TADD, DPDA, DPDB, DPDC, DPDD operating output voltage 10 kW load connected to VREF V REF –3V Converter coefficient switching time RAM read « ROM read – – 10 ms RAM wr ite « RAM read – – 3 µs TSUB, TADD signal bandwidth4 DC to -3 dB frequency 1 – – MHz DPDA, DPDB, DPDC, DPDD signal bandwidth4 f = 100 kHz to -3 dB frequency 5 – – MHz TSUB, TADD gain peaking 4 f = 10 kHz to -3 dB frequency -3 – +0.5 dB DPDA, DPDB, DPDC, DPDD gain peaking4 f = 100 kHz to -3 dB frequency -3 – +4.0 dB TSUB phase response 4 @ f = 100 kHz – – 10 ° DPDA, DPDB, DPDC, DPDD g roup delay4 f = 1 to 5 MHz group delay differential absolute value ––5 ns Relative error between 4 pins – – 1.0 TSUB offset voltage No input signal, VREF reference, post-correction, T a = 25°C, Rf = 18 kW RAM read/wr ite max gain – – ±10.0 mV RAM read, min to max gain – – ±26 RAM read/wr ite differential gain max. –– ± 4 ROM read, gain min/max – – ±100 TADD offset voltage No input signal, VREF reference RAM read – – ±30 mV ROM read – – ±300 DPDA, DPDB, DPDC, DPDD offset voltage No input signal, VREF reference RAM/ROM read -550 – +50 mV TSUB offset voltage temperature coefficient Rf = 18 kW – – ±0.4 mV/ °C TSUB variable gain range -16 – +14 dB TSUB variable gain step width – 2 – dB

NIPPON PRECISION CIRCUITS—8 Focus PD Input Characteristics (F1, F2) V CC = 5 V ± 5%, GND = 0 V , Ta = 0 to 70 °C Focus Signal Processor Characteristics V CC = 5 V ± 5%, GND = 0 V , Ta = 0 to 70 °C TSUB gain switching absolute accuracy VOUT = VREF ± 0.8 V dB 1. TSUB = K · {[IT1 + IT2] - [IT3 + IT4]}, gain = 0 dB 2. TADD = K · [IT1 + IT2 + IT3 + IT4] 3. DPDA = K · IT1, DPDB = K · IT2, DPDC = K · IT3, DPDD = K · IT4 4. T1, T2, T3, T4: 10 pF input load capacitance TSUB, TADD, DPDA, DPDB, DPDC, DPDD: 10 pF output load capacitance TSUB, TADD: 10 kW load resistance DPDA, DPDB, DPDC, DPDD: 100 kW load resistance Parameter Condition Rating Unit min typ max Input impedance No signal – – 250 W Input conversion noise current DC to 10 kHz RAM read 1 1. Conversion from FSUB output noise value when 14 pF capacitors connected to F1 and F2 –– 2 4 nArmsROM read 1 –– 9 6 RAM write1 – – 150 Pin voltage No signal, V REF reference – – ±50 mV Parameter Condition Rating Unit min typ max FSUB current-to-voltage converter coefficient1 RAM read Rf = 22 kW , VOUT = VREF ± 0.35 V 370 415 460 kWROM read 94 105 116 RAM write 58 65 72 FADD current-to-voltage converter coefficient2 RAM read Rf = 27 kW 223 250 277 kWROM read 56.1 63 69.9 RAM write 35.6 40 44.1 F1, F2 converter coefficient relative error FSUB output, RAM/ROM read – – ±2 % FSUB, FADD output impedance – – 100 W FSUB oper ating output voltage 10 k W load connected to VREF 1 – 3 V FADD operating output voltage 10 k W load connected to VREF V REF –3V Converter coefficient switching time RAM read « ROM read – – 10 ms RAM wr ite « RAM read – – 3 µs FSUB, FADD signal bandwidth3 DC to -3 dB frequency 200 – – kHz FSUB, FADD gain peaking 3 f = 10 kHz to -3 dB frequency -3 – +0.5 dB FSUB, FADD phase response 3 @ f = 10 kHz – – 5 ° Parameter Condition Rating Unit min typ max

NIPPON PRECISION CIRCUITS—9 Mode Control Logic Offset Correction Characteristics V CC = 5 V ± 5%, GND = 0 V , Ta = 0 to 70 °C FSUB offset voltage No input signal, VREF reference, post-correction, T a = 25°C RAM read/write, ROM read max gain – – ±7.0 mVRAM read, min to max gain – – ±21 RAM read/wr ite differential gain max. –– ± 4 FADD offset voltage No input signal, V REF reference – – ±50 mV FSUB offset voltage temperature coefficient – – ±0.22 mV/ °C FSUB variable gain range -16 – +14 dB FSUB variable gain step width – 2 – dB FSUB gain switching absolute accuracy VOUT = VREF ± 0.35 V dB 1. FSUB = K · [IF1 - IF2], gain = 0 dB 2. FADD = K · [IF1 + IF2] 3. F1, F2: 14 pF input load capacitance FSUB, FADD: 10 pF output load capacitance, 10 kW load resistance Control input Operating mode Offset correction WRITE MODE LOW or open LOW or open RAM read ActiveLOW or open HIGH ROM read HIGH LOW or open RAM write HIGH HIGH Inactive Parameter Symbol Condition Rating Unit min typ max TSUB offset residual V REF reference, Ta = 25 °C – – ±8.5 mV FSUB offset residual V REF reference, Ta = 25 °C – – ±5.5 mV Supply voltage droop detect level V 1 1.9 2.8 3.7 V Correction circuit startup supply voltage V 2 3.2 3.8 4.4 V V1 and V2 difference V 2 - V1 0.7 1.0 1.3 V Correction thermal sensor detect temperature 15 20 25 °C Offset correction time – – 150 ms Parameter Condition Rating Unit min typ max

NIPPON PRECISION CIRCUITS—10 Serial Interface Characteristics V CC = 5 V ± 5%, GND = 0 V , Ta = 0 to 70 °C Parameter Symbol Condition Rating Unit min typ max SCLK pulse cycle t cySCK 100 – – ns SCLK HIGH-level pulsewidth t whSCK 40 – – ns SCLK LOW-level pulsewidth t wlSCK 40 – – ns SENB setup time t sSEN 20 – – ns SENB hold time t hSEN 40 – – ns SDATA setup time t sSDA 15 – – ns SDATA hold time t hSDA 15 – – ns ACK setup time1 tsACK 0– 2 0 n s ACK hold time1 thACK –– 5 0 n s SENB interval t inSEN 100 – – ns 1. ACK is the acknowledge output (n-channel open-dr ain). LOW-level output when the data received is valid. SDATA load capacitance is 15 pF . SENB SCLOCK SDATA Controller SDATA Port tsSEN twhSCK twlSCK tcySCK tsSDA thSDA tsACK thACK tinSEN thSEN bit 0 bit 1 bit 15 LSB MSB ACK High Impedance

and bit configuration of each port is shown in table 1. (high-reflectivity disc) read. removed using output stage capacitive networks. PD to ensure the data read bandwidth. Table 1. Port address and bit configuration1

1. · = don’t care, – = unassigned

SL1: sleep mode set bit. Sleep mode when 1, normal operation when 0. Default = 0. CS1: offset correction control. Offset correction when 1, normal operation when 0. Default = 0.

as a push-pull sum signal used as an auxiliary signal. F2) and the sum signal (F1 + F2) are generated. Table 2. TSUB gain setting Table 3. FSUB gain setting

rises to above 3.8 ± 0.6 V . n When sleep mode operation is cancelled. SL1 is also 1, then SL1 has priority. until the supply recovers to above 3.8 ± 0.6 V . HIGH. CALREQ goes LOW after correction stops. trolled by serial interface bit SL1. serial interface flags are reset to their default values. their default values in sleep mode. Table 4. Offset correction setting

0 No correction

1 Correction

Table 5. Sleep mode settings

NIPPON PRECISION CIRCUITS—14 NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon P recision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failu re or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, dir ectly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9806AE 1998.12 NIPPON PRECISION CIRCUITS INC.