SM5950AM

SM5950AM NPC | Alldatasheet

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NIPPON PRECISION CIRCUITS INC.—1 Asynchronous Sample Rate Converter OVERVIEW The SM5950AM is a digital audio signal asynchronous sample rate converter LSI. It supports 16/20/24-bit word-length input/output interface data. It also features a built-in digital deemphasis filter and direct mute functions.

FEATURES

I L/R 2-channel (stereo) processing I Input sample rate range: 20kHz to 100kHz I Output sample rate range: 30kHz to 50kHz I Operating sample rate conversion ratio (fso/fsi) : 0.45 to 2.205 selectable : fsi = input sample rate fso = output sample rate I Asynchronous input and output clock timing I System clock input

• Input system clock: 1fsi (LRCI)
• Output system clock: 512fso (SCKO input) I Deemphasis filter function
• IIR-type filter
• fsi = 44.1kHz, 48kHz, 32kHz compatible I Direct mute function I Through mode operation
• Direct connection from input to output I Output data clocks (LRCO, BCKO)
• Slave mode: external inputs
• Master mode: derived from the output system clock (SCKO) I Computation round-off processing
• Normal round-off I 5V tolerant input pins for direct connection to 5V operation devices I 3.3V single supply I Package: 24-pin SSOP

ORDERING INFORMATION

(Top view) PACKAGE DIMENSIONS (Unit: mm) Weight: 0.23g Note: Dimensions without tolerance are reference values. Device Package SM5950AM 24-pin SSOP LRCI 1 BCKI 2 DI 3 TMOD0 4 RSTN 5 VDD 6 IISI 7 IMOD0 8 IMOD1 9 DEEM 10 FS0 11 FS1 12 LRCO BCKO DOUT SLAVE SCKO VSS IISO OMOD0 OMOD1 TMOD1 THROU DMUTE 10.20 ± 0.30 10.05 ± 0.20 5.40 ± 0.20 7.80 ± 0.30 0.36 ± 0.100.8 0.12 M 0.10 0.10 ± 0.10 1.80 1.90 − 0.10 + 0.20 0.50 ± 0.20 0 to 10 0.15 − 0.05 + 0.10

NIPPON PRECISION CIRCUITS INC.—2 I Input data format

• 2s-complement, MSB-first, L/R alternating serial data
• IIS/non-IIS formats L = Low input level, H = high input level I Output data format
• 2s-complement, MSB-first, L/R alternating serial data
• Bit clock continuous (64fso) L = Low input level, H = high input level Structure I Silicon-gate CMOS process

Applications

I Digital audio equipment-interface sample rate conversion

• A V amplifier, CD-R/RW, DAT, MD, DVC I Recording/editing equipment sample rate conver- sion Converter Performance I Internal data word length: 20 bits I Deemphasis filter characteristics (IIR filter) 0.03dB gain deviation from ideal filter char- acteristic I Anti-aliasing LPF characteristics (6 types of FIR filter)
• Output/input sample rate conversion ratio auto- matic filter select (6 FIR filters) 1. Up converter LPF 1.0 to 2.205 times 2. Down converter LPF I about 0.92 times: 48.0kHz to 44.1kHz 3. Down converter LPF II about 0.73 times: 44.1kHz to 32.0kHz 4. Down converter LPF III about 0.67 times: 48.0kHz to 32.0kHz 5. Down converter LPF IV about 0.50 times: 96.0kHz to 48.0kHz 6. Down converter LPF V about 0.45 times: 96.0kHz to 44.1kHz - Passband ripple: ± 0.0001dB - Stopband attenuation: > 98dB I Converter insertion quantization noise level
• Internal calculation (quantization) noise – 96dB
• Output round-off noise: - 16-bit output mode : – 98dB - 20-bit output mode : – 122dB - 24-bit output mode : – 146dB
• Output S/N ratio (theoretical values) Format IMOD0 IMOD1 IISI 16-bit MSB-first right-justified L L L 20-bit MSB-first right-justified H L L 24-bit MSB-first right-justified L H L MSB-first left-justified (leading 16 bits valid data) HHL IIS (leading 16 bits valid data) H or L H or L H Format OMOD0 OMOD1 IISO 16-bit MSB-first right-justified L L L 20-bit MSB-first right-justified H L L 24-bit MSB-first right-justified L H L MSB-first left-justified (16-bit output) H H L IIS (16-bit output) H or L H or L H Output signal word length S/N ratio 16-bit input 20-bit input 24-bit input 16 bits – 92.5dB – 94.0dB – 94.0dB 20 bits – 93.9dB – 96.2dB – 96.2dB 24 bits – 93.9dB – 96.2dB – 96.2dB

NIPPON PRECISION CIRCUITS INC.—3 BLOCK DIAGRAM Arithmetic operation block Interpolation filter operation Output operation LRCO BCKO DOUT SCKO LRCI BCKI Deemphasis filter operation Sequencer block Interpolation operation Output data operation RSTN Input data interface DI Conversion rate detector Filter type selector Output timing operation IMOD0 IMOD1 IISI DEEM FS0 FS1 Output data interface Though, mute, and slave mode control IISO OMOD0 OMOD1 THROU SLAVE DMUTE

NIPPON PRECISION CIRCUITS INC.—4 PIN DESCRIPTION Number Name I/O Description HIGH LOW

1 LRCI I Sample rate clock input (fsi) – –

2 BCKI I Bit clock input (32fsi to 64fsi) – –

3 DI I Data input – –

4 TMOD0 I IC test mode select pin (must be LOW for normal operation) Test Normal

5 RSTN I Reset pin – Reset

6 VDD – VDD supply (3.3V) – –

7 IISI I IIS input select pin – –

8 IMOD0 I Input format select pin 0 – –

9 IMOD1 I Input format select pin 1 – –

10 DEEM I Deemphasis select pin ON OFF

11 FS0 I Deemphasis frequency select pin 0 – –

12 FS1 I Deemphasis frequency select pin 1 – –

13 DMUTE I Direct mute select pin ON OFF

14 THROU I Through mode select pin Through SRC

15 TMOD1 I IC test mode select pin (must be LOW for normal operation) Test Normal

16 OMOD1 I Output format select pin 1 – –

17 OMOD0 I Output format select pin 0 – –

18 IISO I IIS output select pin – –

19 VSS – GND connection (0V) – –

20 SCKO I Output system clock input (512fso) – –

21 SLAVE I Slave select pin Slave Master

22 DOUT O Data output – –

23 BCKO I/O Bit clock input/output (64fso) – –

24 LRCO I/O Sample rate clock input/output (fso) – –

NIPPON PRECISION CIRCUITS INC.—5 SPECIFICATIONS Absolute Maximum Ratings V SS = 0V , VDD pin voltage = V DD Note: Ratings also apply at supply switch ON and OFF . Recommended Operating Conditions V SS = 0V , VDD pin voltage = V DD V SS = 0V , V DD = 3.0 to 3.6V , Ta = 40 to 85 C (*A) All output pins with no load, System Clock frequency: F SCKO = 24.576MHz, Input word clock frequency: F LRCI = 48kHz, Supply voltage: V DD = 3.3V Pin type Note: All inputs and input/output pins are 5V compatible. Consequently, input voltages up to 5.5V can be connected. However, wh ile input/output pins in input mode can have input voltage up to 5.5V, input/output pins in output mode have output voltages that do not rise above VDD level. Plus, in out- put mode, it is prohibited to use external pull-up to raise the voltage above VDD. Parameter Symbol Rating Unit Supply voltage range V DD 0.3 to 4.6 V Input voltage range V I 0.3 to 5.5 V Output voltage range V O – 0.3 to V DD + 0.3 V Storage temperature range T stg 55 to 125 C Power dissipation P D 400 mW Parameter Symbol Rating Unit min typ max Supply voltage V DD 3.0 3.3 3.6 V Operating temperature T opr – 40 25 85 C Parameter Pin Symbol Condition Rating Unit min typ max Current consumption VDD I DD HIGH-level input voltage (*1) (*3) V IH 2.0 – 5.5 V LOW-level input voltage V IL 0 – 0.7 V HIGH-level output voltage (*2) (*3) V OH I OH 2.0mA 2.4 – V DD V LOW-level output voltage V OL I OL = 2.0mA 0 – 0.4 V Input leakage current (*1) (*3) I LH V IN = V DD – 1.0 – 1.0 µA I LL V IN Note Type Names (*1) Inputs LRCI, BCKI, DI, TMOD0, RSTN, IISI, IMOD0, IMOD1, DEEM, FS0, FS1, DMUTE, THROU, TMOD1, OMOD1, OMOD0, IISO, SCKO, SLAVE (*2) Output DOUT (*3) Inputs/Outputs BCKO, LRCO

NIPPON PRECISION CIRCUITS INC.—6 Output system clock (SCKO input) Reset input (RSTN) Parameter Symbol Condition Rating Unit min typ max Clock pulse cycle time t CY 39.0 – 65.1 ns Clock pulsewidth (HIGH level) t CWH 15.6 – 39.1 ns Clock pulsewidth (LOW level) t CWL 15.6 – 39.1 ns Clock pulse duty 40 – 60 % Parameter Symbol Condition Rating Unit min typ max RSTN pulsewidth t RST 39 – – ns 0.5VDDSCKO tCWH tCWL tCY VIL VIH 0.5VDDRSTN VIL VIH tRST

NIPPON PRECISION CIRCUITS INC.—7 Serial inputs (LRCI, BCKI, DI) Parameter Symbol Condition Rating Unit min typ max LRCI cycle time t LICY 1 0–5 0 µ s BCKI pulse cycle time t BICY 156.25 – 1562.5 ns BCKI pulsewidth (HIGH level) t BICWH 60 – – ns BCKI pulsewidth (LOW level) t BICWL 60 – – ns DI setup time t DIS 30 – – ns DI hold time t DIH 30 – – ns Last BCKI rising edge to LRCI edge t BLI 30 – – ns LRCI edge to first BCKI rising edge t LBI 30 – – ns 0.5VDD 0.5VDD DI BCKI LRCI 0.5VDD tBLI tLBI tBICWH tBICWL tBICY tDIS tDIH VIL VIH VIL VIH VIL VIH

NIPPON PRECISION CIRCUITS INC.—8 Serial outputs (SLAVE = HIGH, LRCO, BCKO inputs, DOUT output) Parameter Symbol Condition Rating Unit min typ max LRCO cycle time t LOCY 20 – 33.34 µ s BCKO pulse cycle time t BOCY 312.5 – 1041.7 ns BCKO pulsewidth (HIGH level) t BOCWH 125 – – ns BCKO pulsewidth (LOW level) t BOCWL 125 – – ns Last BCKO rising edge to LRCO edge t BLO 30 – – ns LRCO edge to first BCKO rising edge t LBO 30 – – ns DOUT output delay t DODL C L = 15pF – – 30 ns 0.5VDD 0.5VDD DOUT BCKO LRCO 0.5VDD VIL VIH VIL VIH tBLO tLBO tBOCWH tBOCWL tBOCY tDODL VOH VOL

NIPPON PRECISION CIRCUITS INC.—9 Serial outputs (SLAVE = LOW, LRCO, BCKO, DOUT outputs) t CY = output system clock (SCKO input) cycle time Parameter Symbol Condition Rating Unit min typ max LRCO cycle time t LOCY – 512 – t CY LRCO pulsewidth (HIGH level) t LOCWH – 256 – t CY LRCO pulsewidth (LOW level) t LOCWL – 256 – t CY BCKO pulse cycle time t BOCY –8– t CY BCKO pulsewidth (HIGH level) t BOCWH –4– t CY BCKO pulsewidth (LOW level) t BOCWL –4– t CY BCKO output delay t BODL C L = 15pF – – 30 ns LRCO output delay t LODL C L = 15pF – – 30 ns DOUT output delay t DODL C L = 15pF – – 30 ns 0.5VDD 0.5VDD DOUT BCKO LRCO 0.5VDD tBOCWH tBOCWL tBOCY tDODL VOH VOL SCKO tLODL 0.5VDD VIL VIH VOH VOL VOH VOL tBODLtBODL

NIPPON PRECISION CIRCUITS INC.—10 FUNCTIONAL DESCRIPTION Input Interface Settings (IMOD0, IMOD1, IISI) Input data format 2s-complement, MSB-first, L/R alternating serial data Note: L = Low input level, H = high input level Input timing The input timing for each input format is shown in figures 4 to 8. Output System Clock (SCKO) A clock with frequency 512 times the output sampling frequency (fso) must be input on SCKO. In master mode, the LRCO and BCKO output clocks are derived from the input clock on SCKO. It also functions as the internal computation circuit system clock. Output Interface Settings (OMOD0, OMOD1, IISO, THROU, SLAVE) Output data format 2s-complement, MSB-first, L/R alternating serial Note: L = Low input level, H = high input level Output mode select Output timing The timing for each output format is shown in figures 9 to 13. In slave mode, the input timing of LRCO and BCKO for each output format is shown in figures 9 to 13. In through mode, the LRCI, BCKI, and DI inputs are fed through to the outputs regardless of the output data format settings. IMOD0 IMOD1 IISI Format L L L 16-bit MSB-first right-justified H L L 20-bit MSB-first right-justified L H L 24-bit MSB-first right-justified H H L MSB-first left-justified (leading 16 bits valid data) H or L H or L H IIS (leading 16 bits valid data) OMOD0 OMOD1 IISO Format L L L 16-bit MSB-first right-justified H L L 20-bit MSB-first right-justified L H L 24-bit MSB-first right-justified H H L MSB-first left-justified (16-bit output) H or L H or L H IIS (16-bit output) Pin setting Function THROU SLAVE Mode Description LRCO, BCKO L L Master LRCO and BCKO are derived form SCKO. Function as outputs H Slave LRCO and BCKO are supplied externally. Function as inputs H H or L Through LRCO, BCKO, and DOUT are connected directly to LRCI, BCKI, and DI inputs. Note: DMUTE is valid. Function as outputs

NIPPON PRECISION CIRCUITS INC.—11 System Reset (RSTN) The SM5950AM must be reset if any of the following conditions occur during normal operation. A reset pulse is a LOW-level pulse applied to RSTN, although the reset operation actually occurs on the rising edge of the LOW-level pulse. I When the power supply is applied A reset (RSTN = LOW to HIGH) is required when the power supply voltage is applied and after the LRCI, BCKI, SCKO (and LRCO, BCKO if in slave mode) clocks have stabilized. I When the LRCI and BCKI clocks are interrupted This occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage, when the LRCI, BCKI clocks are dynamically switched, or when otherwise the clocks are not continuous. A reset (RSTN = LOW to HIGH) is required after the LRCI, BCKI clocks have stabilized. I When the SCKO (and LRCO, BCKO if in slave mode) clocks are interrupted This occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage, when the SCKO, LRCO, BCKO clocks are dynamically switched, or when otherwise the clocks are not contin- uous. A reset (RSTN = LOW to HIGH) is required after the SCKO, LRCO, BCKO clocks have stabilized. A reset pulse is required under these conditions because the conversion ratio calculated based on such non-con- tinuous clocks will result in an incorrect conversion ratio, and hence the output data will have incorrect values. Output state during reset interval DOUT is tied LOW during the reset interval (refer to section "Direct Mute" for operation after the reset is released). In master mode, the LRCO and BCKO clocks are also tied LOW. Direct Mute (DMUTE) Direct mute ON/OFF Other mute operations Direct mute also occurs at system reset. DMUTE Function L Audio data output starts from the next output word. H 0 data is output from the next output word. RSTN Function L 0 data is output from the next output word. H Computed data output starts after 8 output word cycles.

NIPPON PRECISION CIRCUITS INC.—12 Sample Rate Conversion The input/output sample rate conversion ratio is variable over a range 0.45 to 2.205 times frequency. The input sample rate (fsi) range is 20kHz to 100kHz, while the output sample rate (fso) range is 30kHz to 50kHz. Note that the sample rate conversion ratio lower limit means that conversion from fsi = 96kHz to fso = 32kHz is not possible. Anti-aliasing filter selection The following 6 filters are provided to function as anti-aliasing filters during sample rate conversion, where the optimum anti-aliasing filter is automatically selected in response to the automatic measurement of the sample conversion ratio between the input sampling frequency (on LRCI) and the output sampling frequency (calcu- lated using SCKO as reference). If the selected anti-aliasing filter fs conversion ratio and the actual sample rate conversion ratio do not match, the following phenomena occur. If the fs conversion ratio is not fixed, the conversion will slowly follow the change in ratio, but in the process the possibility exists that noise may occur in the audio data output. Filter mode fs conversion ratio (fso/fsi) Selects range Conversion frequency (example) 1 1.0 to 2.205 times ≥ 0.969697 times Up conversion 6 0.459375 times ≤ 0.492308 times 96.0 → 44.1 Conversion condition Response generated Actual sample rate conversion ratio is lower than the selected filter conversion ratio. High-frequency aliasing noise occurs in the audio band. Actual sample rate conversion ratio is higher than the selected filter conversion ratio. Primarily cuts high-frequency components in the audio band.

• Passband ripple: ± 0.0001dB
• Stopband attenuation: > 98dB I Conversion insertion quantization noise level
• Internal computation noise: ≤ – 96dB
• Output round-off noise: 16-bit output: – 98dB 20-bit output: – 122dB 24-bit output: – 146dB Overall theoretical output S/N ratio Anti-aliasing filter characteristics Output signal word length S/N ratio 16-bit input 20-bit input 24-bit input 16 bits – 92.5dB – 94.0dB – 94.0dB 20 bits – 93.9dB – 96.2dB – 96.2dB 24 bits – 93.9dB – 96.2dB – 96.2dB

Figure 1. Anti-aliasing filter characteristics

NIPPON PRECISION CIRCUITS INC.—15 Group Delay Time If tINPUT and tOUTPUT are defined as: tINPUT : Serial input data (fsi rate) read end timing (LRCI clock rising edge) tOUTPUT : Serial output data (fso rate) output start timing (LRCO clock rising edge) the group delay is given by: t OUTPUT – tINPUT = (48.41 ± 8.41)/fsi Response Time The conversion rate detector stage requires a certain amount of time to calculate the sample rate conversion ratio with accuracy. The minimum response time, after the SM5950AM input sampling frequency (fsi: LRCI input) and output sampling frequency (fso: derived from SCKO) have stabilized sufficiently, is the time required to determine the sample rate conversion ratio to 16-bit accuracy after reset is cleared, and is given by: Response time = 16384/fso (371ms at fso = 44.1kHz) tOUTPUT (48.41 ± 8.41)/fsiSerial data input 1/fs tINPUT 1/fso Serial data output tOUTPUT INPUT– t tOUTPUT tINPUT Data waveform image

NIPPON PRECISION CIRCUITS INC.—18 TYPICAL APPLICATION CIRCUITS Input Interface Connection Example Connection with a digital audio interface receiver (DIR:CS8414) example Output Interface Connection Example Connection to a digital audio interface transceiver (DIT:CS8402A) DEEM IMOD0 LRCI IMOD1 BCKI DI SM5950AM MCU Co/F0 SEL FSYNC CS12/FCK SCK SDATA DIR CS8414 TMOD0 TMOD1 IISI FS0 FS1CU CBL FSYNC SCK SDATA DIT CS8402A Level Shifter (3.3V to 5V) 6.144MHz (128fso) OMOD0 LRCO OMOD1 BCKO DOUT IISO THROU SLAVE TMOD0 SM5950AM 24.576MHz (512fso) External Clock SCKO MCK TMOD1

NIPPON PRECISION CIRCUITS INC.—19 Connection to MOST Interface Transceiver (OS8104) FSY SCK-SRC_FL SR0-D3 MOST OS8104 OMOD0 LRCO OMOD1 BCKO DOUT IISO THROU SLAVE TMOD0 SM5950AM 24.576MHz (512fso) SCKO RMCK TMOD1 /RD /WR PAR_CP PAR_SRC ASYNC PAD0 PAD1

NIPPON PRECISION CIRCUITS INC.—20 NC0101CE 2002.08 Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customer are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this documents are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: sales @npc.co.jp