SM5813AP | DigiCamel IC Datasheet

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au} [? ( EIGHT-TIMES OVERSAMPLING DIGITAL NIPPON PRECISION CIRCUITS INC. FILTER FOR DIGITAL AUDIO m OVERVIEW ‘ The SMS5813AP/APT is a high-fidelity eight-times oversampling digital filter LSI for digital audio system, using the molibdenum gate C-MOS process developed solely by NPC. This LSI has a two-channel FIR filter and three types of output modes (16bit/18bit/20bit). Since it has four kinds of system clocks --- 512fs/256fs/384fs/192fs, it can be used for not only CD players but also other audio systems. m FEATURES + FILTER CHARACTERISTICS ITEMS CHARACTERISTICS Pass band 0 to 0.4535fs. Stop band 0.5465fs to 7.4535fs Pass band ripple Within £0.00005dB Stop band attenuation | More than 110dB — Linear phase (There is no group delay distortion.) + FILTER STRUCTURE + Free running mode (Jitter-free) — Eight-times oversampling. + INPUT/OUTPUT — Two-channel filters —16 bit serial data input — Cascaded three-stage linear phase. (2's complement code, MSB first) FIR filters (153+29+17 order) — 16/18/20bit serial data output — 20 x 22 bit multiplier (2's complement/Complemented offset binary, — 25bit accumulator MSB first) — Overflow limiter * SYSTEM CLOCK — Crystal oscillation circuit (512fs/256fs/384fs/192fs) + Power supply voltage: 5V +0.5V + PACKAGE * Molybdenam gate C-MOS process 28-pin DIP, 44-pin QFP m PIN OUT (TOP VIEW) + 28-pin DIP + 44-pin QFP 829899 2959.989 pw (Sah ket REReeioegeeE CKBV BCKO (Nc) wo ge BDO. FSCO owen LRCI COB XxTI XTO : ® Q i v0 (NC) vu PC (Nc) o-n axe) RST Vs 1 2 H) Vsse SM5813AF cKo | a > f] DG wo we i] (NC) (Nc) cot [oe Duy 0000 ae wot f) OWE BcKL arc ac) f 4 f ows ane) [By sf ac) RST (4 15]) COB none on BRRRSSeeesb a NIPPON PRECISION CIRCUITS 444

™ BLOCK DIAGRAM LRCI DIN BCKI CREE © . i To 8 SYSTEM CLOCK XTO 6 ! cKO o—] 16 : H FILTER CALCULATION — Fsco }- Do i SYN 6 5 owns RSTO TIMING CONTROL | 0)

7 OUTPUT INTERFACE © ow20

Voo Vss1 Vase DG BCKO WCKO DOL DoR m FILTER CHARACTERISTICS (THEORITICAL VALUE) | ___trems | GHaractanisties Pass band. 0 ~.0.4535fs Stop band 0.5465f5 ~ 7.4535¢s Pass band ripple Within 40.00005B Stop band attenuation | More than 110dB Group delay time Constant STOP BAND ATTENUATION z 40 | Teste rccnnncan nec cnnecaceccceeennescanessnesensceenecesanecenece EI 80 poo rreenenarenencncnencnnnencenctenseecerereneeneeneteneeseeneenees | 2 100 - ZAI 2 3 4 5 6 7 {8 (xfs) 0.4535 0.5465 7.4535 NR PRESB REE

i} i 2 3 4 { (x fs] 0.4535 THE DOMAIN BETWEEN PASS BAND AND STOP BAND 60dB 3 | s Ce a ee 0.45 05 0.5465 0.6 [x fs]

144 NIPPON PRECISION CIRCUITS

@ PIN DESCRIPTION 1} 42 |DIN |__| Serial data input _2| 43 [BCKI | 1 | Timing clock for serial input data : 3 1 |CKSL.|_ 1 | Selecting system clock *2 6|.3.|XTI 1 _ | Input for oscillator or external clock input (System clock) 7 4 |XTO 0 | Output for oscillator, No connect when using external clock 8] 6 | Vss1 = _|Ground 1 : 9| 10 |CKO Q__| Clock output (Same frequency as XTI input clock) 10) 11 [SYN I__| Hi: Free running mode L: Forced synchronizing mode 14| 17. |RST I _ | H: Normal operation _L: System reset 15 | 19 |COB I | Selecting output data format . H: 2's complement _L: Complemented offset binary (COB) 16.) 20 |OW20 | I _ | Selecting number of output data bits *3 . . 20 }..25 |DG 0. | Deglitch control clock . 22.|_28 | VDD - | Supply voltage (+5V) 23.|_31./DOR 0. | Rch serial data output (8fs rate) ; 26 | 35.]BCKO | 0. | Output timing control for serial data (Bit clock) 27,| 36. |FSCO_| 0 | Internal timing clock (fs rate) ce 28 | 37 {LRCI I | Multiplex clock for Lch/Rch input data (fs rate): H: Lch_ L: Rch *1) I Input terminal Ip: Input terminal with pull-up resistance O: Output terminal H | 4H 1928s H | 384fs L H_ | 256fs : | Si2fs 3) —— H H 16 bit L H | 18 bit H L 20 bit

m@ ABSOLUTE MAXIMUM RATINGS (Vss=OV) SYMBOL] LIMITS STORAGE TEMPERATURE Tsra | -40 to 125 °C POWER DISSIPATION Pw 250 mW SOLDERING TEMPERATURE Tsp 255 °C SOLDERING TIME Tso 10 Sec ™ =RECOMMENDATORY OPERATING CONDITIONS WVese(V" Ss= SYMBOL| LIMITS OPERATING TEMPERATURE Torro -20 to 70 °C @ ELECTRIC CHARACTERISTICS + DC CHARACTERISTICS (Ta = -20 to 70°C, Von = 4.75 to 5.25V, Vss = OV) ITEM TER- |SYMBOL| CONDITION | MIN | TYP | MAX |UNIT MINAL CURRENT CONSUMPTION | Voo Top ‘Von=5V fsys*3 45 mA INPUT VOLTAGE (1) XTI Vin 0.7Vo> Vv Vir . 03Vo0 | V INPUT VOLTAGE (2) (1) Vien eee Vv ; V2 05 v OUTPUT VOLTAGE (3) Vou | Ton =0.4mA | 25 | : Vv INPUT LEAK CURRENT (1) XTI . Tn {vis =VDD . 10 20 pA Ta Vix=0V _}0 20, | BA INPUT LEAK CURRENT (2) (1) Tun Vin=Vpp 1.0 pA INPUT CURRENT (#2) In Vin <0V “P10 "| 207 Pa < TERMINAL> LRCI, DIN, BCKI, CKSE, CKDY, SYN, RST, COB, OW20, OWI8 CKO, DG, DOL, DOR, WCKO, BCKO, FSCO When CKDV=L fXTI/2 When CKDV =H fXTI (fXTI: Frequency of XTI input clock)

146 NIPPON PRECISION CIRCUITS

(Ta = -20 to 70°C, Von = 4.75 to 5.25V, Vss = Ov) (1) XTI input clock 1. XTITERMINAL ‘MIN. 0.7Vpo a._In case of crystal oscillation ff 08Vo0 ? [un MAX, O.3V% rem |SYM-| min typ (Max |unrr | CONDITION..| Nore | i | ° BOL CKSL “CKDY| tor tow 107 935 H H | 192s $$ 1ter +} frequency 1.0 95 L H | 256fs 20 i90 L L | si2ts b. In case of terminal clock input -—trcr_—+ SYM- : | CONDITION Eetncweni=tpow-e| Width of "38 500 HH 1 192%) (2) | \\ | ars tow [15250 ages (HL | Bais oe oe er ee ee ed pulse 38 :,, 500 Lo: H | 256fs ary ( tone! i Cycle | 105 1000 _H H_ | 192fs mn ——f ff sv timeof | tey ["'52 500 |nSec | HL | Beats : clock 105 1000 L H_ | 256fs Fetousfe—tha pulse : 52: 500 L L[512fs ERC wnt L- nr 2. INPUT TIMING pote tix BCKI, DIN, LRCI terminal (cxver) sat} ff van? MiN TYP MAR] UNIT | =e | BCKI, Pulse width twew | 100: nec | i BCKI, Cycle time tacy._ | 200 H nSec es DIN, Set up time tos 75 | nSec | DIN, Hold time toy 35 Seg” | (3) CRDVEB) XT ww nrfnnf anne Vo072 Rising edge of last BCKI tee 75 nSec — Edge of LRCI ; | Edge of LRCI ts 75 nSec — Rising edge of first BCKI Falling edge of XTI ix 20 | nSec Rising edge of LRCI | Riding edge of LRCT tix | é nee xn [AP fem — Falling edge of XTI cenpvet) -— toa roa —— 3, OUPUT TIMING oe Sn ah ey | 4 ITEM SYMBOL] MIN © ‘TYP: MAXT UNIT] NOTE ] | tH a BCKO delay time| txbH 35 120 (CRDV=L RDVSID Toa ares from XTI tbL 35°: 120 || Sec ; tl | KbH 35 120 | nec [CEB BCKO — EE —| — f ~18V ; xbL 35 120° pat Output delay tbdL | -10 0 +10 | mSec |15pF a iba’ “] 10010 Load DoL ee sv DOR i DGL! ae thd DGR \\ eee NIPPON PRECISION CIRCUITS 147

(Ta = -20 to 70°C, Von = 4.75 to 5.25V, Vss = OV) . 1. XTI TERMINAL (1) XTI input clock a. Incase of crystal oScillation rem [SYM | yun typ :MAX Junrr | CONPITION. | Nore, ove BOL i CRS CRE fp 1.0: 13.0 HH | 192fs 1 H Alm MAX. 0:8Vo0 Oscillating! .,, | 2.0: 260 woe | Hb | 384ts en frequency 1.0 2130 La | 25666 - teri 2.0 260 ee Oe ie b. In case of external clock input SYM- CONDITION MIN :TYP J I 1 trey} Width of 35 500 _H H_ | 192fs | (2) i i i clock — | tow | 15.2. 250 Jasec | Hb | 3848s | | mule 350 S00 L He | 256fs BOAT fren fanfare 15 15 250 LL | si2ts ue ton | Cycle 76 ©1000 H H | 192fs 1 a timeof | tey | 38): 500 |nSec | HL) 384fs DIN wenn Ff SV clock 76) 1000 L H__ | 256fs Pulse 38 500 L L__|512fs titi) 2. INPUT TIMING A BCKI, DIN, LRCI terminal pie tex SYMBOL] MIN = TYP! MAX| UNIT. ATT ete es Vio /2 BCKI, Pulse width “leew | 100 nSec BCKI, Cycle time tecy | 2002 nSec DIN, Setup me ed PB edo | nsec DIN, Hod ime |g ‘nsec | @) Rising edge of last BCKI tor B nSec > EdgeofLRCL Pod. Edge of LRCI tus 78 nSec — Rising edge of first BCKI Falling edge of XTi io 20 7 nsec ~ Rising edge of LRCI NTT |e er eons V0 /2 Rising edge of LRCI tx 0 . nSec \\ \\ — Falling edge of XTI (CRDV=L) Te XT Teen fennrnnennnnnet\\ emmnnntnnntnnmmmnntionn 3. OUTPUT TIMING on ae Voor tb | {ITEM | syMpor] MIN! Typ MAX] UNIT] NOTE | =H on Le ITEM SYMBOL] MIN: TYP: MAX| UNIT] NOTE (CRDV=H) a at BCKO delay time] wbH [35 = 120 | aSee [EKDV=L mr aa from XTI txbL 35: 120 BCKO of (—— vas LEV xb] 35120 | nec” /CRBVA ne txbL | 35 3 120 ik thd Output delay tbl] 10 410 | nSec J1SpF d tia” | ie “ Heel pop | nor an

148 NIPPON PRECISION GIRGUITS

EIGHT-TIMES OVERSAMPLING In put of fs sampling rate to the SM5813 is output with 8fs sampling rate after calculating in the digital filter. : CONDITION | XTI Cycle time of inter-] This LSI has cascaded three-stage FIR filter as follows: H H 192fs 2. SYSTEM CLOCK BB B86 ha oll + SELECTION OF SYSTEM CLOCK ro pate ore The SM5813AP/APT/AF has an internal clock generator that may be used by connecting a crystal of the appropriate frequency between pins XTI and XTO. Alternatively, an externally Figure A. Input SIPO generated clock can be input on XTI. The clock frequency Fxi is selected by the CKDV and ' CKSL inputs from one of the four multiples of pvnO the sample frequency shown in the right table, scx! where the clock period txi=1/Fxi. For the 384fs T and 512fs clock frequencies, the clock is divided ae - ; by two for internal use. The system clock signal, ! of the same frequency as the signal on pin XTI, H os is available on the CKO output pin. LRCI o U 3. AUDIO DATA INPUT t Input data is processed MSB first and 2's comple- | ont ment. Each bit of serial data input on the DIN 1 oy, U pin is read into the SIPO register (serial to 1 FSCK parallel conversion register) at the rising-edge of BCKI bit clock and converted to parallel data. The SIPO output is transferred to the Lch/Rch Figure B. Input timing of audio data input register, respectively, at the rising-edge/ falling-edge of the LRCI clock. (See Figure A st , and B) DN The timing of the operation part and output part BCKI nh A sn are independent from the timing of the input part, ibiada so that it is not affected by jitter of the input part. ret came a 4, JITTER-FREE MODE AND FORCED SYN- Input register (R.) w @ CHRONIZATION MODE SELECTION (SYN, ree TL. - FSCO) (intemal clock) my e ny The timing of the internal operation and output Input mgisier (internal timing) are determined by the system clock (the XTI input), which is independent of the input clock timing (BCKI, LRCI). The internal timing is provided with 2 kinds of ‘jitter-free mode," and "forced synchronization mode" to cope with jitter on the LRCI clock input. The setting of SYN enables selection. NIPPON PRECISIONGIRCUTS. —SSOS~S~S«SQ

@ Jitter-free mode (SYN=H) When the phase difference between the LRCI clock and the internal timing is within +3/8 to -3/8 of the input sampling frequency (1/fs), the internal timing is not adjusted. Thus jitter on the LRCI clock does not affect the internal timing to prevent malfunctions and jitter transmission. If the phase difference exceeds the said range, the phase of internal timing is adjusted synchronously with the starting-side edge f the LRCI clock. When a reset is input, the phase is also adjusted. @ Forced synchronization mode (SYN=L) In this mode, the internal timing is always reset at the starting-edge of the LRCI input. In this case, malfunction occurs if a cycle which does not statisfy the required system clock cycle due to jitter onthe LRCI input exists. To the contrary, if a cycle which is longer than the specified clock cycle exists, the intervals of the output timing are not the same though operation is performed corrtectly. @ FSCO clock (output) The fs frequency clock obtained by dividing the XTI clock. 5. DATA AND DAC CONTROL SIGNAL OUTPUT (DOL, DOR, BCKO, WCKO, DG, COB, OWI8, OW20) Table B. Output timing M83 ft [me fer] eet (1) MSB first bol (2) 2's complement and COB (complemented offset nema vem nc] [teas | 2508 binary) switch COB format (COBH) COB foram COB-L) @ Bit number selection of output data (OW18, OW20) Tobi ~ sys is internal system clock cycle. Bit number of output data can be selected from among 16, 18 and 20, po ior 16-bit output (OWI8-H, OW20=H) DOR 18-bit output (OWI8=L, OW20=H) BCKO np 20-bit output (OW18=H, OW20=L) weKko > @ Output tining DGTP The timing of audio output part is determined correspond- ing to the system clock frequency of each part. (See Table C. Output timing Table B, Figure C) 6. SYSTEM RESET (RST) When a reset is input in the jitter-free mode, the internal operation timing is reset synchronously with the rising- SM5813 edge of the following LRCI clock input. Taking advan- tage of this, the output timing in the jitter-free mode can match to LRCI. Vp The reset pulse (L level) should be longer than 5Ons after Vop power-on. A reset is also unnecessary in the jitter-free Vssa mode if the output timing is not required to match with 100pF the LRCT input. ih In the case of performing the system reset at power-on, connect a 100pF or so capacitor to the RST pin. (See . Figure D). Table D. System reset circuit sample at power-on js0.. NIPPONPREGISIONGIRGUTS.——SOSOSOC~—~—S—SSSS

1, SERIAL INPUT TIMING L___ ts eycle rs! LRCI | ree IIIT i MSB Lch data LSB MSB Rch data LSB A ee | more than | | more than | | » Ocycle ¥ | Ocycle = 6 cycle 2. SERIAL OUTPUT TIMING ; vo [tera ee ‘1 i y H 1 i | i | | WCKO | | | | nn | nn BCKO i Torrens | nes H } i i ° NIPPON PRECISION CIRCUITS 151

INPUT 0 x tal betty Cassseanat > (SONY ) XTAL less [CQ xTT-xTO CXD1125 LRCK | came —_| iret CXD1135 DATA [anna | DIN SM5813 (2.1168MHz PSSL__SLOB C210 BCKI 16.9344MHz (MATSUSHITA) = -*CK rare xTr MN6617 RAL lo 44.1kH2 LCI SRDATA aa DN SM5813 SEL IPSEL SRCK | BCKI bv YM3623 LR s4.tiais _ BCO BCKI Jeo NIPPON PRECISION GRQUS

OUTPUT ia] X' tal bo ( 84872MHz ) 8.4872MEz XTI XTO M50421P a LRCI bo DIN SM5813 DASEL_DFPAS DSCK BCKI —nippON PRECISION CIRCUITS SSB

Product Information

SM5813AP specifications and overview.

Summary

EIGHT-TIMES OVERSAMPLING DIGITAL FILTER FOR DIGITAL AUDIO

Description

EIGHT-TIMES OVERSAMPLING DIGITAL FILTER FOR DIGITAL AUDIO

Source title SM5813AP Datasheet(PDF) - Nippon Precision Circuits Inc

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