SM5807FS

SM5807 NPC | Alldatasheet

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FROM 8&7 LiYay + xo 2003%12R 88 (A) 16: 29/@m1 6: 28/%B8S4804112164 P 1 URPG renyiNued SM5807 Oe Ree NIPPON PRECISION CIRCUITS UTD. 57} 4.2 aD \\ IG trou OVER SAMPLING DIGITAL FILTER FOR DIGITAL AUDIO MGENERAL DESCRIPTION SM5807 is a four fold over sampling digital filter for low end digital audio system, using the molybdenum gate C-MOS process developed solely by NPC. This LSI has two channel FIR filters, and the pass-band ripple is less than +40. 05dB, stop band attenuation is more than 50dB.The input and output datas are 18-bit serial. so the circuit system can be small. MFEATURES + FILTER STRUCTURE -Four fold over sampling -On chip overflow limitter -Tow channel filter -On chip quartz oscillation circuit ~Cascaded linear phase FIR filter (61st+13th order) -Buffer output for XT input clock + FILTER CHARACTERISTICS Pass band ripple(0~20kHz) Within 40. 05dB [Within 40. 05dB Stop band attenuation (24. 1kllz~)| ‘ore than 50dB Nore than 45dB | -Linear Phase (There is no group delay distortion.) + INPUT/OUTPUT MPIN CONFIGURATION 16 bit serial input/output , TOP VIEW (2's complement code, MSB first) ‘DE Type g E 8 5 ag B TTL compatible Poa id eA Be la -Interface for 2DACs(F type) : fe] fel fe BLS + Power supply voltage: 5V+0. 5V +16 pin plastic DIP/SOP SM5807 + Molybdenum gate C-MOS process Eye] ETE) J =] MPACKAGE TYPE Pe ° ia a pus207pP, ep, Fa| 16 Pin plastic DIP. sskeggak an Pin plastic SOP | (2) (21 (31 (2) (3111 (I fe) SM5807 ATES] [=] . IO 4 --) -1-

FROM B&7LYYay: Oey i 2003%12A 88 (A) 16:30/816: 28/xB8S4804112184 P 2 meackacee Wes 1 ON (UNIT: mn) - DIP + SOP ie) 16 i [e) rif AA FL x > | pil : so32Max 7.62TYP RAR i asf =a 22 i Fy Pa ms l . asstoz: isto2 (SS Eee i | pes osaro2 © re | este ous ROSA | a oe Ml ossstoad | | yertoag! O4t0ls. ce : MBLOCK DIAGRAM : . fa g ZEB S Vop imam ? TIMING CONTROL ODGR [| [|| [wurreuter7 CORFFTCTENT) ACCUMULATOR 8 Apa Boki & rom |] [4 = a} DIN G——_JINpur = Es } LRCI O—-hyrpp ETsmFT # = pour se PT FACE [| & = SosT & REGISTER] |me & = Owpco (D.B type) SHIT Py Be 5 REGISTER] Ee 5 dBcKo S OLRCO O =O: Vss SOMD i (F type) ! -2-

FROM B&7LiYay + t-x oi 2003%12R 88 (A) 16:30/@M16:28/xB8S48041121684 P 3 DISCONTINUED MFILTER aeeeeee PRODUC (THEORITICAL VALUE) 1. SM5807 DP, DS (frequency :0~88. 2kHz) ITEM CHARACTERISTICS PASS BAND O~ 20kHz STOP BAND More than 24. 1kHz PASS BAND RIPPLE Within 40. 054B STOP BAND ATTENUATION More than 50dB B 4, = gob errr —— S60 oN NTS ZB 80 se oe = eA Se a ———> FREQUENCY (kiiz) Fig. 1 Characteristics of frequency domain : S 000 a a eS = 02} NN SO 2 a a 006 er = 9.08 a ( 0 10 5.0 10.0 15.0 20.0 (The attenuation at LkHz~~~~~0. 0044dB) ~——~ FREQUENCY (kHz) Fig.2 Pass band —— ES ————= S20 ee = 100 20.0 22.05 24.1 ——> FREQUENCY (kHz) Fig.3 The domain between pass band and stop band -3-

FROM B&7LiYay + xo 2003%12R 88 (A) 16:30/eM16:28/xB8S4804112184 P 4 uPC SiSCONTINUED 1, SM5807 EP, BS, » PRODUC (frequency :0~ 88. 2kHz) ITEM CHARACTERISTICS PASS BAND 0~20kiz STOP BAND More than 24, 1kHz PASS BAND RIPPLE Within #0.05dB | STOP BAND 24. 1~40kHz] More than 45dB ATTENUATION, 40.0kHz~] More than 50dB Sa —— a 5 ol La] Vy AAV aS & 80 Ag <—— E100 a in A \\ > FREQUENCY (kHz) Pig. 4 Characteristics of frequency domain Se a ae | a aaa s {| \\ Z — | 2 004 PRA ee FSS & =

0.03 SMS oe

Oo 10 5.0 10.0 15.0 20.0 (The attenuation at 1kHz~~~~~0, 0365dB) —— FREQUENCY (kHz) Fig. 5 Pass Band = of 7] oy 0 — ae S ey a Ep = 99 C9 0 20.0 22.05 24.1 ——~ FREQUENCY (kltz) Fig.6 The domain between pass band and stop band ~4-

FROM 8&7 LiYay + xo 2003%12R 88 (A) 16:31/@M16:28/e88S48041121684 P 5 c \\NUED NPC piscont Wer MPIN DESCRIPTIO [ No] name | 1/0 DESCRIPTION 1] XxT I | Input for oscillator or external clock input a ee . ace a satpet tor : oscillator, Wo sonnest at aving eiteal , = se ~ [Lt nXT input clock is 8.4672MHz or 8. 6436MHz (P type~only 8.467 2MHz) “ aio Ta] Fiufter out of XT ‘ek — _ ne i “eta heheh ‘Syuchroni zing oloa” cnn : ee — | eel my ee mee omen : - : se — . rer aA Timing clock for serial lant Gale . ae ee aan ‘scound statment eine — a ~ ~ 1 oo ere a aerereeerera +777 as SOMD | Ep] “H’----Output interface for 1 DAC (Same as D,E type) of EDL LLY Output interface for 2 DACs nnn Trl taco "0 Towtwer ‘ining control clackaye any” = volgen T's Seine el sek for serial gatpue ann USD ee Wea a he jp Seis Sy NOTE) I :Input terminal Ip:Input terminal with pull-up resistance 0 :Output terminal -5-

FROM B&7LYYay: Oey i 2003%12A 88 (A) 16:31 /A@R16: 28/%B8S4804112184 P 6 uPC DISCONTINUED MABSOLUTE MAXIMUM eatinePR (Vss=0¥) SUPPLY VOLTAGE a Vop -0.3~ 7. 9 Vv MRECOMMENDATORY OPERATING CONDITION (Vss=0¥) SUPPLY VOLTAGE |_Yop 4.h~ 5.5 Vv MELECTRIC CHARACTERISTICS *DC CHARACTERISTICS (Ta=-20~ 10°C, Vop=4. 5~5. 5V, Veg=0¥) TT TN rd enerennennannnininnn — Viua | nef mmmenf 22 VDD | V | safle | nl oe! MA oe cee _ a ee ee ct en Cs FP <TERMINAL> #1 | CHSL, LRCI, DIN, BCK1. SCSL(D, E Type), SOMD(F Type) #2 | CKO, CRCO, BCKO, WDCO, DOUT, DGL,DGR

FROM B&7LiYay + t-x oi 2003%12R 88 (A) 16:31/@M16:28/eB8S48041121684 P 7 UPC pISCONTINUED “AC CHARACTERISTWA UC 1. XT TERMINAL PROD a. In case of crystal oscillation (Ta=-20~70°C, VDD=4. 5~5, 5V, VSS=0V)n Oscillating frequency fose 20|MHz _EXSL=t ee econ b. In case of clock input to XT terminal (Ta=-20~ 70°C, VDD=4. 5~5. 5V, VSS=0V) [imam [svn Joan [ovr [wax [unit [opin 50 1000 | nSec CKSL=L Width of clock pulse re a en Cycle time of clock pulsel tey fe ee ee 50 1000 | nSec | CKSL=H Input pulse to XT terminal ' 2. INPUT TIMING (DIN, BCKI, LRCI) om f\\ £ \\ A Xo (Ta=-20~ 10°C, Von=4. 5~5. 5V. Vss=0V) {suo ft : binugerteid dae Te Tae —— a 3. OUTPUT TIMING (Ta=~20~ 10°C. Vpp=4. 5~5. 5V, Ves OV) a enna fennel iin ard Parnr nt woo, bout Output delay tine en ee Jnnnnfamnoned DCL, DGR town 25 | nSee| (loner | tov | ueKo wf of fev TRCO a Tor ze Soe ay Dour po, | ~- ~~ ~~ eS SS SSS SSS Sy rR fa H tout _

FROM 8&7 Liar: -X oi 2003%12R 88 (A) 16:32/@M16:28/xB8S4804112184 P 8S exes pISCONTINUED MFUNCTION OD (1) SYSTEM CLOCK PR D,E type SCUSL=H or OPEN~~~-192fs(8. 4672MHz) STSL= Lenn 96 F 5 (8, esi Ftp frequency (44. 1kHz) F type wmommnonly 1928 (8, 4672MH2) * Generating clock~~~~~-Crystal oscillation or external clock D,E Type(SCSL=H or OPEN) — D,E Type (SCSL=L) a Teg ai a ae wl XT/XT input [384fs= | 192ts= | 992ts= | 1g6ts= frequency 16. 9344MHz / 8. 4672MHz an 2872MHz : 8. S436MHz oe See ~ = laos oe oe eer — Speen ITT — n(n system clock| 8,4572Miz) | 8eagemiz | tt (2)SERIAL INPUT(DATA & TIMING CLOCK) The seial data input timing is raising edge of BCKI. So the input serial data must be changed at falling edge of BCKI. And the input data is latched to the internal register by LRCI. BCKI DIN y y y y y (3) INPUT DATA FORMAT The input data format is 2°s complement and MSB first. (A) INTERNAL CALCULATION The internal calculation starts at raising edge of LRCI. (5)SERIAL OUTPUT(DATA & TIMING CLOCK) The Leh/Rch datas are out from DOUT terminal alternately. So the 1 DAC interface system can be available. (D,E type & SOMD=H of F type) And using F type(SOMD=L) and 2DACs, the in-phase conversion is posible. (Refer to 12 page.) The output timing clock is out from BCKO terminal and the output data changes at fall- ing edge of BCKO clock, so the data input timing to DAC is raising edge of BCKO. BCKO=8. 4672MHz(At SCSL=H or open of D,E type/F type) BCKO=8. 6436MHz(At SCSL=L of D,E type) -8-

FROM 8&7 LYYay: OXY i 2003%12A 88 (A) 16:32/e16: 28/xB8S4804112184 P 9 (6) OUTPUT DATA FORMAT . PRODI J I The output data format is 2's complement and MSB first. (1)DEGLITCH SIGNAL DGL~"Leh deglitch signal 176. 4kHz(Duty 25%) DGR~"Reh deglitch signal 176. 4kHz(Duty 25%)

FROM B&TLYYay: tx yi 2003%12R 88 (A) 16: 32/16: 28/xB8S4804112184 P 10 UPC SSCONTINUED MTIMING CH ROD 1. INPUT P (1) INPUT TIMING 1(D,E Type;SCSL=H or OPEN & F Type) (a) oe 5 10 1s 2 25 x0 as p Bae Beat |f] U Wu SULA YUU j a I a j ON Ses Fis [shai slgel eB Esha , tacit | | 1 cate: Af OL (b) wt 23 4 5 8 7 8 8 10 1) 2 Id 14 15 16 IF IM 18 20 21 22 29 at 28-26 7 De wy 30 41 we A pee PU t Leh i Reh bin (e¥sf2 SSeS 9 Toh EERERME OTe RTM ey oD RC : H rr (2) INPUT TIMING 2(D,E Type;SCSL=L) sex wo. 5 10 18 20 25 30 a5 10 19 mm UUAUUGORTAOAUGUANCUQA OpOREUOQONOGTRUQOOGQONT VGH) gHIURO Goa EAU UEaT EVES OODOONIA UUM DECQOnUE DIN CE S00 GG0 0002 01D as 9 COG DTEDIES r LRCL _[=-.77 Of i 2. OUTPUT (1)OUTPUT TIMING 1(D,B Type:SCSL=H or OPEN & F Type SOMD=H or OPEN) a eg se es SO en es your Ce os on a a cs es ac (2)OUTPUT TIMING 2(D,E Type;SCSL=L) BR a es eg I eg es SO ee Ys es es The output cycle of WDCO is not constant. But the DGL.DGR cycles are constant. (176. 4kHz, Duty 25%) : (3) OUTPUT TIMING 3(F Type;SOMD=L) a bs te see tes soso HRIMUMACORUNIg NC neRTnnRnERna me emma cc AE NO Fe eeereeey MOO cen Se eee ER pon =| poke -10-

FROM B&7LYYay: Oey i 2003%12A 88 (A) 16:33/@816: 28/xB8S4804112184 P 11 MTYPICAL APPLI aT ISCONT T DL, IX'TAL mH GesaaaMeia) Di 6( DATA) = DIN XT XT (SONY) D14(C210) 21168MHz~| BCKI OxD1125 . SM5807 OXD1130 LROK + TMs LROI GXD1135 Psst stop AE 16934¢MHz | “XO DOUT - DIN (Tosh iba} BOK : BOKI ) 14112 709200F ; MH M5807 CHOK ) >Omaaae—| LRer 417M0 16.9344 MHz UXT 7 X'TAL HH (16.9344 MHz) DO DIN XT XT Mitsubishd DSOK T6EME] BCKI M50421P LRC ERO SM5807 : . DASEL prpas. a467oMEz | BCKO B (Matsushita) SRCK BCKI ci aur set rpsm, *~°* 169344MH2 |X? - “tL

FROM B&7LYYay: Oey i 2003%12A 88 (A) 16:33/@816: 28/xB8S4804112184 P 12 (1)1DAC(D,E Type & F Type;SOMD=H or OPEN) BCKO DATA CLOCK SM5807 | DOUT DATA INPUT DGL (BURR -BROWN ) DGR | POM56 ~ Degliteh controt (2) 2DACs(P Type: SOMD=L) DATA GLOOK L.E DATA INPUT ch (BURR - BROWN) BCKO PCMS6 LRCO Sms807_ | woco HHI DOUT DGL - i DATA CLOCK r L.E DATA INPUT Bch (BURR- BROWN ) PCM56 Deglitch control -12-