SM5803AP

SM5803AP NPC | Alldatasheet

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al [> Cc SM5803AP/APT ‘NIPPON PRECISION CIRCUITS INC, Multi-function Digital Filter for Digital Audio @ OVERVIEW The SM5803AP/APT is a multi-function digital filter for digital audio fabricated using NPC's original molybdenum-gate CMOS technology. This LSI uses a variety of functions including 4- times/8-times oversampling, digital de-emphasis, digital attenuator, jitter-free mechanism and soft mute. The I/O interface allows 16- or 18-bit input data and 16-, 18- or 20-bit output data, so a wide range of system configurations can be realized. @ FEATURES + Filter configuration + Filter functions — Two-channel 4-times/8-times oversampling — Noise shaper (can be turned on or off) — Three-stage linear-phase FIR filter configuration Reduction of re-quantization noise compo- (153th order + 29th order + 17th order) nent in the audio band ~— 22-bit filter coefficient to reduce round-off error — Soft mute — 20 x 22-bit parallel multiplier Smooth changes of attenuation level — High-precision operation by 25-bit accumulator — Digital attenuation — Digital attenuation 0.188-dB step attenuation in the 0 to -96 dB — Built-in overflow limiter range ~ Built-in quartz oscillator circuitry Floating output prevents reduction of + Filter characteristics (fs: sampling frequency) dynamic range. —Passband ripple 0 to 0.4535 fs Floating output (0/1/2/3/4/S/6-bit selection) .+. Within 0.00005 dB Control possible with external analog — Stopband attenuation attenuator control output digital attenuator 0.5465 to 7.4535 fs (8 fs mode) setting 0.5465 to 3.4535 fs (4 fs mode) — Jitter-free mode — Linear phase (group delay distortion: zero) — Digital de-emphasis * Input/output ¢ Free running mode (Jitter-free) — 16/18-bit serial data input (2's complement, MSB_ * INPUT/OUTPUT first) — 16 bit serial data input — 16/18/20-bit serial data output (2's complement or _ (2's complement code, MSB first) COB, MSB first) — 16/18/20bit serial data output * Clock (2's complement/Complemented offset — System clock: 512 fs, 256 fs, 384 fs and 192 fs binary, MSB first) * Supply voltage 5V+0.25V + SYSTEM CLOCK * Package 28-pin plastic DIP (512fs/256fs/384fs/192fs) * Molybdenum-gate CMOS construction * PACKAGE 28-pin plastic DIP NIPPON PRECISION CIRCUITS 121

‘SM5803AP/APT @ PINOUT (TOP VIEW) @ PACKAGE DIMENSION (UNIT: mm) 23 3 ss "mQOO00 a AyEaA 36.6MAX. ST 2ab5S5 B2aGaans 8 e=nAOOOSO SPQ QO eas A . . 8 ARMEAAS> eA 4 2.5440.25 | tL ODRONTNAHOROEOM Paw aw aw aw av aw ow Yaw aT aU aT ot at a ea NAAAAAAAA Ate ets] i) » 3 sll || fwuPCc =| 7) | | SM5803AP/APT TTT USTT TS eal e zx b ramrmonraaQi ans + LATYP. zz z ou Gicieaae © (RWSL SBR REE 2822258 fo. 4840.1 z PS @ FILTER CHARACTERISTICS 1. Oversampling filter Parana Passband 010 0.4535fs Stopband 0.5465 to 7.4535fs Passband AppTe Grp dea tine 0 wenn nnn =< 8s MEE 5 100- {on snnasannenseneoneonenenneennennetneennnneneneennnenten neennennetee | < : von pagegyarennneeeepeenennenenteneenneapyntenenntnnrg gat is sent | 120- eee einer een a eae o ” \\ 4 2 3 4CxfsJ 0.45: 0.5465 3.4535 SM5803A Frequency Characteristic (4fs mode, de-emphasis OFF)

122 NIPPON PRECISION CIRCUITS

40 -_ || Ee ee = ee gs 80 aa “alga iso! meat a 8 eee aa errr nee SC) eS ——- < Se 5 eee

120 Lee ee neeeneeneneneneenne enescescrpeneeentsnsesntntneseneaf ern ena

f 0 1 2 3 4 5 6 7. 8(xis] 0.4535 0.5465 7.4535 SM5803A Frequency Characteristic (8fs mode, de-emphasis OFF) 3 -0.00005: stent tennant § Va\\ DR PX-PP pe ff AGA PPP 3 ° PLP DPAPLATAL OARS) s +0.00005 oe 2 ov 0 0.1 0.2 0.3 0.4 4 (Xfs) 0.4535 SM5803A Passband Characteristic (4fs mode, de-emphasis OFF) = 0.00005 pon S +0.00005: etn ed a nnnnnennenennnenntnnnnennsntctnenenetnnnenee feneene 0.4535 SM5803A Passband Characteristic (8fs mode, de-emphasis OFF) i a +: = 40: aoe ever erseenerepeitietmnensastnanivn .

8 Jossecectneeenernrcenrceneeneneneenenenee; one ntntestnmntneeentnetnenerareraee

= 604 eee & a eevenene\\eneneeneeenenttntntnenttnenenenestseneneneneneeneee EF ce seseenntentnenerettepenenesetmntnenennenetetnteenentetneteeteennenese 5 — wens ensenennnnnererenenneeennrtnenee enero 0.45 0.5 0.5465 0.6 (Xfs) SM5803A Transition-band Characteristics (4fs/8fs mode, de-emphasis OFF) NIPPON PRECISION CIRCUITS 123

™@ PIN DESCRIPTION NAME 1 DIN. Input data ceseeletececenenentiiiiee 2. BCKI Input data bit clock (data input on the risingedge) 3. CKSL | XTI pin input frequency selection (See 6: XTI pin.) oA. CRDY ; ; ; a 5 8x Output sampling rate selection ne . H: 4fs mode, L: 8fs mode

6 XTI Oscillator input (192fs: CKSL = H, CKDV = H)

(384fs: CKSL = H, CKDV = L) (256fs: CKSL = L, CKDV = H) ee te - (512fs: CKSE. = L, CRDV. =D). 7) XTO...f Oscillator output vessecetensteneeenee 9 CKO. Oscillator output clock (same frequency as XTI) 10] MSI Mode set control] 11 MS2. Mode set control 2

12 MS3 Mode set control 3 Set the digital attenuator and mode

13] MDT. | Mode set data | flag register. 14 MEN. Mode set enable 1S MUTE Mute ON/OFF selection _H: no sound output, L:_ normal output

16 DIEM De-emphasis ON/OFF selection

• oe H: de-emphasis ON, L: de-emphasis OFF selection

19 DGR 8fs LR parallel output mode: de-glitched negative output

4fs LR alternate output mode: Rch de-glitched output . cn 4fs LR parallel output mode: _de-glitched negative output

20 DGL 8fs LR parallel output mode: _de-glitched positive output

4fs LR alternate output mode: Lch de-glitched output 2)" vpp | Powersupply (SV) ae

23 DOR 8fs LR parallel output mode: Rch data output

4fs LR alternate output mode: LR clock output ce 4fs LR parallel output mode: _ Rch data output “24 DOL 8fs LR parallel output mode: Lch data output 4fs LR alternate output mode: Lch/Rch data output 4fs LR parallel output mode: _Lch data output . coe 26 | |. BCKO. Output bit clock geste 27 FSCO... fs-period internal operation and output timing clock cesses 28 | R Input data sampling rate (fs) clock (fs stands for the input data sampling frequency.) NIPPON PRECISION CIRCUITS 125

‘SM5803AP/APT @ BLOCK DIAGRAM ERC] DIN. BCKI oxpvé H oKSLO R 1 me | en Elf my ' Fs00d _ ed Srseui wea —| Tin mt op orem word 3 PE H HERO cm Volume feta H Ns10 8 processing [J ' S20 a : ” me Le A H <2 OND = = ee : WCPL ! Yoo! $4 ' ude ge gh hdd Vssl Vss2 DGL DGR WCKO BCKO DOR DOL @ ABSOLUTE MAXIMUM RATINGS m™ RECOMMENDATORY OPERATING (Vss-OV) CONDITIONS [tem | Symbo | Rating | (Wss-0v) Input voltage Vm |-03~Voo+03| v_| | Supply voltage Voo | 4,75~5.25..| Vv Storage temperature range| Tsrc_| -40~125 | °c || Operating temperature | Torr | -20~70 | °c Power dissipation pw | 250(AP) | mw Soldering temperature Tap 255(APT) | °C Silden ae Pn Pee @ DC ELECTRIC CHARACTERISTICS Voom4.75 to 5.25V, Tam-20 t070°C,Vss-OV unless otherwise specified. Symbal] Conon <P ype> [ MIN [Typ] MAX|unrr | |*1/LRCI, DIN, BCKI, CKSL CKDV (Current Voo | oo |Voo=SV,fsys*3 4 | mA MS1, MS2, MS3, MDT, MEN consumption = 10MHz (AP) MUTE, DIEM, FSEL1, FSEL2, 8X Voo=SV, fsys*3] 50 CKO, DGR, DGL, DOR, DOL, = 13MHz «pn, WCKO, BCKO, FSCO Input voltage XT | Vea Vm 'V_ | Internal pull-up resistors are attached to ica ee a Mint ping @lyeneemt XL Output voltage | (#2) | Var | low—0.4mA | 25°] | v Vou. | tou=i.6ma 04 £43) fey: sytem clock fequency Input leak current} X11} ha | VieeVoo 10 | 20 pA Shove u: ea qu. Ve OV dL 10.120, (EXTI is the XT1 input clock C1) | bx | VoeVoo 1.0 frequency.) Input current eb lb Ve=0V 10 | 20 pA

126 NIPPON PRECISION CIRCUITS

+ AC CHARACTERISTICS (Ta = -20 ~ 70°C, Vov = 4.75 ~ 5.25V, Vss = OV) (1) a,b 0.7xVoo or more ariel . low a. Quartz oscillation H i H = ‘town town SYM-]__ RATING CONDITION | Nore] tom ftom [ rem | BOL | as typ MAX|UNT | xs: ckpv| —— tr —4 : 10, 95 HH | 192s Oscillating) 5. | 20 19.0 HL | 384fs +— trer ——4 frequency 10 SOs LH | 2568) (2) a {troy _,tecw | 20 190 LL} si2ts oT a b. External clock input BCKI Poe FR [ mem foot [aan tye max ONT] xan exo] MIN | TYP MAX CKSL | CKDV) 1 tos |! toe ' Width of 38 500 HH | 192fs oo t clock 24 250 H L_ | 384fs t . L pulse 38 500 LH | 2568s DIN 1sv (H level) 24 250 LL [5128s ‘ Width of 48 500 H__H_| 192fs H i clock 24 © 250 HL | 384fs rg t t pulse 48 500 Lon | 256fs Sees L level 24 250 Lo sis Ys sv Cycle 105 1000 H_._H_| 192fs LRCI 1S time of 52 500 HO OL || 384fs b aN clock 105 1000 LH | 256fs . p 52 500 L L_|512¢5 Mer ‘ v 2. SERIAL INPUT TIMING at ws a. BCKI, DIN, LRCI terminal MS3 i t RATING -— twos ——++— tan [mem [sem sin av sai ON | BCKI Pulse width wav 1160 We nex ONE sv BCKI, Cycle time wwcr | 200 nSec vw nA DIN, Set up time tos 5 | nSec stew} te | DIN, Hold time nee ee : nSec | _ _— ben —4 Rising edge of last BCKI iat 15 nSec | (3) to Edge of LRCI sane “rz Edge of LRCI os 75 nSec Vpp/2 to Rising edge of first BCKI H (CRDV=L) I oO TN - { t b. MSI, MS2, MS3, MDT, MEN terminal bass 1 : : —t em eg me [NT] et MDT, MSI, MS2, MS3 ‘bes 20 nSec OKDV=1 Vpp/2 setup time ¢ =H) Ny is 1 tsbH ,)tsbL MDT, MSi, MS2, MS3 hold | "bao 20 nSec hoy pe time i tb bly MEN L-level period bew 20 Lee 1 Helevel peri pei | STs y ‘ mee sans poxo, — ff — Interval with next bene 6 i pulse (MCO, MC3-MC7) ey emeed (MC1, MC2) 4 DOL 1 sv OUPUT TIMIN poe m1 : 3. TIMING DOL Mel RATING " eo er, IBCKO =. CKDV|_ &xbH 35 95 ‘WCKO} . from XTI crpv fr 2 i 3 (#1) Tsys: System clock period CKDV = L: tax 2 sn. 3 CKDV=H: ta Ourput delay time) OT PIO OT asec {SPE Where tw is the period of the clock input on XTI. NIPPON PRECISION CIRCUITS

+ AC CHARACTERISTICS (Ta = -20 ~ 70°C, Voo = 4.75 ~ 5.25V, Vss = OV) (1) ab 0.7XVpp LE . 5 0.3 XV; a. Quartz oscillation Hi i ' po AF 1 tow town SYM- RATING _| CONDITION om om TTEM {pow Min: Typ: MAX|UNTT | csr: cxpy NOTE tg Oscillating) « 10. 130 ie Heed H Ree *1 The clock duty ratios on tcwu and tow. iv PO FD Let We hime (ie., teww/ta x 100) are as follows: 2.0 260 L L__|5i2fs XTI clock frequency :__ Duty ratio b. External clock input ISMHz, carne AS 3% 10 545%, J MIN TYP: MAX KSL | CKD Qa bE teri Width of 3571 500 HH. | 1926s. 7 {teow tecw | clock is *250'|nsec | HL | 384ts i ee pulse 35¢1, 500 L H | 2566s sox ff sv H level) is 2250) L L | 512fs f ‘ Width of 3551 500, H H_ | 192fs tps] tox 1 clock tow [15 250, on an Seat | i H i ' | pulse 3541 500 L H | 256ts t Cycle 76 1000 H_:_H__| 192s | + timeof gg [382500 HL | Beats sips clock 76 1000 LH | 256fs LRCI. 15v pulse 330 500 L L Sits mt 2. SERIAL INPUT TIMING | a. BCKI, DIN, LRCI terminal b xt Se oe Pp] ee MS1 DIN, Sét up tiie cen Bsa EET asec oaaienr natal btn: Boks time toe Bk. Sec i ing edge of last BCKI w Edge of LRCT te. 5 CBr ‘aSec WEN \\ f VF sy [Edge of LRCI to Rising edge of first BCKI us S: z Sec uu A CTI rising edge to Start edge of LRCT “ba | “20 re see stot em | (al fred ser a in cesedbes i wey — fired ncronssmaey EY bux | 1G) b._ MSI, MS2, MS3, MDT, MEN terminal APA (CRDVaLY ; MDT, MSI, MS2, MS3 ‘aos, 20 nSec xTr te T { setup time i ty Vpp/2 MDT, MS1, MS2, MS3 bold | ‘bax 20 : nSec Yeu | ineL Sime... es ar MEN: L-level period | MEW ce ee ba H-level period peat | STsys : ; : Interval with next ben 6 : Tt H pulse (MCO, MC3-MC7) L i @1 Dob Tyrrel (MCI, MC2) 34 Ni 15 Note) See the table on p.12 for MCO-MC7. DOR " 3. OUPUT TIMING DoL Sh thd RATING DGR f ; unIT| NOTE sv BCKO oxpyg |..MOR | 352 (*) Start edge of LRCI: delay tbl. 352 2.95 LRPL flag = L Rist time: tsbH 35, 95 lag ~ L_ Rising edge from XT: isbL 33°: St LRPL flag = H Falling edge jelay time | bale. 210720" 10 isgR | OD Tews: system clock period CKDV=L: ta x2, Output delay time iH 10°20 S410 ae CKDV=H: ta tox is the period of the clock input on XTI.

128 NIPPON PRECISION CIRCUITS

— SSMS803AP/APT FUNCTION DESRIPTION lowi ions: lowing equations: 1. Output mode selection (8X input, OMD flag) Attenuation (L) = attenuation setting (L) x 0.188 [ £x input [OMD flag [Output mode | 0B; Leh H L 4fs LR alternate dB; Rch : (#1) The test mode is the same as [8fS LR parallel Den ne Som mute mode is ON ¢ FT flag = output mode] except that the attenuation —_ When an attenuation value is set, attenuation change operation is accelerated in the soft changes gradually in 0.188 dB steps until it - reaches the level given i 2. Oversampiing fier function (Ser Figue 1) gi by the above equation. * 8fs oversampling ; When the soft mute mode is OFF (SOFT flag = Signal input at the sample rate fs is output as data H): at the oversampling rate 8fs. This filter elimi- When an attenuation value i . nates sampling noise of 0.5465fS to 7.45358. immediately changes to the level ziven by the * 4fs oversampling - above equation. Signal input at the sample rate fs is output as data. 5 Mute 1 at the oversampling rate 4fs. This filter eliminates The maximum attenuation value (511) is set in 3. Digital de-emphasis filter When the mute mode is reset, attenuation returns An IR filter is used to revive the gain and phase to the previous setting. (When the setting is characteristics of the de-emphasis filter. changed externally while in the mute mode, at- + De-emphasis mode selection (DIEM input) tenuation changes to the new value.) ° De-emphasis ON (DIEM input = H or open) * Mute mode selection (MUTE input) De-emphasis OFF (DIEM input = L) Mute mode ON (MUTE input = H or open) + Filter coefficient selection (FSEL1 input, FSEL2 Mute mode OFF (MUTE input = L) input) * Relation with soft mute mode When the soft mute mode is ON (SOFT flag = |__| by Sonne FSELI Ezieaew Gradual attenuation in 0.188 dB steps (See Fig- FSEL2 L ure 2.) « Features of the digital de-emphasis filter When the soft mute mode is OFF (SOFT flag = The IIR achieves almost ideal gain and phase 4): ; characteristics, so there is no distortion and varia-__ Direct attenuation to the specified level tion due to component parameters. The primary §- Soft mute objective of de-emphasis is to reduce quantization When the soft mute mode is ON, noise generated noise in the high-frequency band and widen the by the attenuator setting (MC4, MCS, MC6) or dynamic range. However, de-emphasis in the ™ute ON/OFF is prevented by gradual attenua- digital stage narrows the dynamic range. This 2- ; digital filter ensures a sufficiently wide dynamic * Soft mute mode selection (SOFT flag) range by minimizing the level of requantization Soft mute mode ON (SOFT flag ~ L) noise by the following measures: Soft mute mode OFF (SOFT flag - H) 1) 8fs or 4fs oversampling output ty f ai s 2) Noise shaper | | \\ | foes. _ 3) 18-bit or longer output word length \\ | WU Ak RAAAARAA ime 4. Digital attenuator WAAAY AV VV VV VY Attenuation is possible in 0.188 dB steps from0to- || || | \\ Tye _ . 96dB. Leh and Rch outputs can be attenuatedinde- |_| | [1 J“ pendently. The attenuation level is given by the fol- “Figure When the attenuator setting is changed NIPPON PRECISION CIRCUITS 129

flag) * Maximum shift bit (Las) selection * Outpat data format (LAS1, LAS2, LAS3 flag) MSB first . When the configuration of the analog attenuator Switching between 2's complement and COB is 1, 1/2, 1/4 ... 1/2 (KS 6), set the following: (complemented offset binary) (COB flag) las=kKo , ° 2's complement omar (COS fag =1) When Las is set from 1 to 6, bits 2 to 7 are output . Ie B format (COB flag = H) as the analog shift word. Each bit is output MSB oating output system first and weighed with 1, 1/2, 1/4... 1/2K. Only 1 n the oating our syste 6 ab step analog bit corresponding to the digital attenuator value is attenuator Is provi¢ after version an ti hile th t to 0 . controlled (switched) according to the digital at- yore. (HD while the rest are set to 0 (L). tenuator setting. Ordinary digital attenuators use When the CKSL input i d put is H (192fs/384fs clock only the low-order bits of the DA converter when node), the sum of DA word bits and analog shift a large attenuation value is set, which narrows the word bits must not ex 24 (Lda + Las < 23). dynamic range. The floating output system does not suffer this. sein a _] problem. The 6-dB step attenuator is switched | “me™ Sat Die emer ee org statically according to the digital attenuator set- | .-/ .o'uig us (6s, Bs ewe, ts mas woe SET ting, so errors in the analog attenuator stage do j--j---j--j-i-g {Me aes OP. not adversely affect sound quality. eae tO Oe OA SO In floating output, a word is configured from the op Re ae aa ae DA data and analog shift words. (See Figure 5.) [-Re obec kes $2222 MM MR AMO. M6 te —— acueamces Ramee) ai (*1) The DA data length is not limited when CKSL =L, so any +_— 16 18, 200 ———— 0~70ie + ‘combinations of 16, 18 and 20 bits are possible. hal [3]a] * Output timing i ad Output mode DA data word Analog shift word em Symbol : pasate atk pail Figure 5 Configuration of Output Word Bit clock period Tb Tovs Tsvs | 2xTsvs Data word length Tw CKSL =H 524 x Tsys '24 x Tsys 48 x Tsvs * DA data word CKSL=L :32 x Tsys 32 x Tsvs : 64 x Tsys This data word is input to the DA converter for - analog conversion. Data value Nda is expressed ws {ntemal system Clock Period (See 8. System clock.) as follows: . Tw: See the figure below. Nda = Nreal/Nas where Nreal is the true data value, and Nas is the * DA data word bit selection (LDAI flag, i Lia bits testi LDA2 flag) Data ouput SE Io Selection can be made from 16, 18 and 20 Sr 1 tt bits. seco ne nny DA output part, No. of bits : LDAI flag. : LUDA2 flag weKo ‘0.25tw—1——0.75Tw ———1 i PE | eee EE

20 L H H Sey ed

• Analog shift word on ee Word for controlling the analog attenuator stage Figure 6 Output word following the DA converter When the floating system is not in use (Las = 0: LAS1, LAS2, LAS3 flags = L) NIPPON PRECISION CIRCUITS: 131

(MC1) Increment the attenuation register by 1 (this increases the attenuation by 0.188 dB). Ratt (L) + 1 — Ratt (L) ae Ratt (R) + 1 > Ratt (R) Data output The register value will not change when it my 1 1 is the maximum value (511). BcKo Aan AN. tn, (MC2) Decrement the attenuation register by 1 | ' ' ‘ 1 (this decreases the attenuation by 0.188 woKo an a 25TW——— 075Tw 4B). aoe b 7 ' Ratt (L) - 1 — Ratt (L) St} Ratt (R) - 1 — Ratt (R) ' WCPL=H) t wo ene 2st b—-? The register value will not change when it — sr " A ‘ni is the minimum value (0). Figure 7 Output word (MC3) Reset the attenuation register (attenuation 0 When the floating system is in use (Las > 1) dB). 0- Ratt (L) 12. Attenuation register (RattL, RattR) and mode 0 Ratt (R) flag register (Rmod) setting Figure 8 and Figure 9 show examples of (MS1 to MS3 input, MDT input, MEN input) the attenuation register settings using MC1 to MC3. _ Mode set control input Operation (MC4) (MCS) Transfer MSIPO register contents to Mode: MS1 MS2MS3 MEN: se . the attenuation register. MO uae aa MSIPO — Ratt (L) (with MC4) : css. MSIPO by 1 bit (READ). MSIPO - Ratt (R) (with MCS) MCI: H L OL : Increment the attenuation The MSIPO register must be set with : Ren aay NS [MCO] prior to using MC4 or MCS. MOL AL Decrement the attenuation See Figure 10 and Figure 11. register (L, R) by | (DEC, (MC7) Reset the attenuation register. 2 cecesseesnseeee {Raul RantR) 0 Ratt (L) MG! HH OL Set the attenuation register (L, i “R) to0 (Reset RattL, RattR). 0 — Ratt (R) MC4; LO OL OH ‘Transfer the MSIPO contents This function also resets the mode flag reg- er the eemation er a) ister (Rmod) and the operation output tim- MCS. HLH. Transfer the MSIPO contents ing counter at the same time. to the attenuation register (R) cesses =(MSIPO to Ratt). Vee MC6 LH OH Transfer the MSIPO contents me. to the mode flag register ccssns snes (Rmod) (MSIPO 20 Rmod).. ° y Ba3 ania Mo WW Reet ge mt {If Fo | (set toL). So ——| : Rano’ (etal figs to). =F > >—| us 2 i Reset the operation output > f>— ns3 MSIPO; serial — parallel conversion register <3 LAS > MEN ; Tising edge oo ESE! fee + Attenuation register (Ratt(L) and Ratt(R)) setting v Zz Of all the functions listed in the table above, 6 z . functions have an effect on the attenuation Figure 8 Example of attenuation register setting Tegisters. circuit using MC1, MC2 and MC3

132 NIPPON PRECISION CIRCUITS

List of mode flag settings (*Note 1) ‘Start on the risi of LRCL i ees | a a LET el ot perc nD thon a Eo a = DA data length (68) iid? yii¢ LDA2 : 162 182 30 Hi t FLAG Maximum | hif ‘LAS3 +2xLAS2 (+) LAS3 Fiewe 13 Mode ag sting sing MO? and MC (circuit of Figure 10 is in use) eT eae ites cape ors WEKO clock Po fe eaters | clock Noise ‘ON RS [RE SS fp ne Be ares aa ee be fal m TIMING CHART Sse | TIMIN¢ (*Note 1) All flags are reset to "L" upon reset. 1. INPUT 1G (DIN, BCKI, LRC1) (*Note 2). The sum of Lda and Las values must be 23 or less when CKSL = H (192fs/384fs mode). INPUT WORD © 3.8 DIN D3 X p27 Xn SX ~DoCEsB) XX t t ! t LRCI Hi i ! i T : —— — a SIPO SIPO SIPO_ sypo SIPO SHIFT SHIFT SHIFT ==> SHIFT IN IN IN parcH IN Leh DATA _ Rech DATA H - H H DIN TET TTT TT bsibababapip| —--- = aaa BT LLU UU incr i i CRP wRor—] i —— i (LRPL=H); ee 1 ' Figure A Audio data input timing The 16 bits (when IW18 flag = L) or 18 bits (IW18 flag = H) immediately preceding the changing edge of the LRCI input clock are latched as input data. SS

134 NIPPON PRECISION CIRCUITS

Output timing (DOL, DOR, BCKO, WCKO, DGL, DGR) {20 OR ae { vor con {1 1 t fee | [asl BOKO-. PADD DP RD LLLP PDAS p01 cam) heey an - . BE BORO 1 EAD DPD DAY YP PLD LLY PL pon, (D0R) | gs ee DOL, (DOR) kg SSS i BE BOKO $F ADD DD ADDL PDP YIP PILI ; ' ’ ft f {P%-cpon» - Be - BCKO PPP PPP PLPPLPPDPDPLDPPLDDIN t ; mM Suita BE PO OOO TS BCKO PAP PP PPP PP PRP PP PLPPRPD PPS wexo | | H a wort nage. Ft i ' horot bd — (WOR fag =H FT i eS (0am) re as er a ee eee ~~ i a we ' t t at Figure B_ Unit output word timing (when CKSL = H) Lda: Number of DAC bits Las: Number of analog shift bits lo a { Pov.coom Ppooooood Sococoky + f = | fae| {mR a | 5 20| { rev. coon) | Popo po + | BCKO_ IDPDIIAV AAA oe t le lie} { rv. coon) H oooooocoooooo asso aan pt} LADADDDA DALI ARADAAD Ad H wlyol { ov,crom i berreeesterrershicieeee 6 { BCKO. + TVA CAAA CON COU COTTE aue woxo [YON ( WOPL fing =) Hi weg iF sues} PE DOI.,(DGR)—* coom_} * 1 ' . t Figure C Unit output word timing (when CKSL = L) Lda: Number of DAC bits Las: Number of analog shift bits NIPPON PRECISION CIRCUITS 135

DOR =. ee ee WCKO SS = DER Poona WORD) === ! none TE Fsco fo — i ' a bn -----n-- n= ffs --- Figure D Output timing in 8fs LR parallel output mode (8X = L, OMD flag = L or H) ' \\ soe DOR LL ee DOL pn teh g § i rr oe gE dia a9 i eB H 22328 Fsco —} g5858 : jf WORD ----—-+=--- T WORD ----—} a eee ! ne ga 3 por fp pp SG Hi ' ' ' ' ' ' ' H Figure F Output timing in 4fs LR alternate output mode (8X = H, OMD flag = L) DOL =p tage DOR Se WeKO | (WOPL=L)_} 7 t H FSCO sj ' aT }TWORD_----~ 1 DOL +f; . . yy H i : t 1 DGR eS Fsco 4S i t t i i i i $ H Pemersrrn ee nnnnn Uf fg wenn nn nana ay Figure G Output timing in 4fs LR parallel output mode (8X = H, OMD flag = H)

136 NIPPON PRECISION CIRCUITS

@ TYPICAL APPLICATION 1. Input connection examples X? tal(16.9344MHz) - o XTI XTO - LRCK}— LRCI 1130 papal | pn 8M5803 1135 ayzot 2268MH | Bor PSSL SLOB 1 CKDV MATSUSHITA XCK XTI | MN6617 R/L LRCI ~ SRDATA — DIN PL feet) SRCK Bok y_CRPE flag = SEL IPSEL CKDV YAMAHA OA pe eT YM3623 L/R LRCI DO DIN SM5803 pool ___-pcx1 CKDV NIPPON PRECISION CIRCUITS 137

Output connection examples (1) Example of using 16-bit 2DAC (8fs, 4fs LR parallel output mode) BURR- BROWN CLOCK ie LE PCMS6 O Rech BCKO DATA | | a a SM5803 DOR ry BURR- BROWN port —t-| DGL LH i” CLOCK cl LE PCM56 O Leh @ 8fs LR parallel output 8X input - L, OMD flag =L @ 4fs LR parallel output 8X input = H, OMD flag = H (2) Example of using 16-bit IDAC (4fs LR alternate output mode) BCKO BURR- BROWN woxol tL croc SM5803 pos} | LJ LE PCMS6 DOL DATA Bae @ 4fs LR parallel output 8X output = H, OMD flag = L NIPPON PRECISION CIRCUITS 139